2 * linux/drivers/video/omap2/dss/dpi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DPI"
25 #include <linux/kernel.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
30 #include <linux/platform_device.h>
31 #include <linux/regulator/consumer.h>
33 #include <video/omapdss.h>
39 struct regulator *vdds_dsi_reg;
40 struct platform_device *dsidev;
43 static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
47 dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
49 return dsi_get_dsidev_from_id(dsi_module);
52 static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
54 if (dssdev->clocks.dispc.dispc_fclk_src ==
55 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
56 dssdev->clocks.dispc.dispc_fclk_src ==
57 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
58 dssdev->clocks.dispc.channel.lcd_clk_src ==
59 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
60 dssdev->clocks.dispc.channel.lcd_clk_src ==
61 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
67 static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
68 unsigned long pck_req, unsigned long *fck, int *lck_div,
71 struct dsi_clock_info dsi_cinfo;
72 struct dispc_clock_info dispc_cinfo;
75 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
76 &dsi_cinfo, &dispc_cinfo);
80 r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
84 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
86 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
90 *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
91 *lck_div = dispc_cinfo.lck_div;
92 *pck_div = dispc_cinfo.pck_div;
97 static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
98 unsigned long pck_req, unsigned long *fck, int *lck_div,
101 struct dss_clock_info dss_cinfo;
102 struct dispc_clock_info dispc_cinfo;
105 r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
109 r = dss_set_clock_div(&dss_cinfo);
113 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
117 *fck = dss_cinfo.fck;
118 *lck_div = dispc_cinfo.lck_div;
119 *pck_div = dispc_cinfo.pck_div;
124 static int dpi_set_mode(struct omap_dss_device *dssdev)
126 struct omap_video_timings *t = &dssdev->panel.timings;
127 int lck_div = 0, pck_div = 0;
128 unsigned long fck = 0;
133 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
135 dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
136 dssdev->panel.acbi, dssdev->panel.acb);
138 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
140 if (dpi_use_dsi_pll(dssdev))
141 r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
142 &fck, &lck_div, &pck_div);
144 r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
145 &fck, &lck_div, &pck_div);
149 pck = fck / lck_div / pck_div / 1000;
151 if (pck != t->pixel_clock) {
152 DSSWARN("Could not find exact pixel clock. "
153 "Requested %d kHz, got %lu kHz\n",
154 t->pixel_clock, pck);
156 t->pixel_clock = pck;
159 dispc_set_lcd_timings(dssdev->manager->id, t);
162 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
166 static int dpi_basic_init(struct omap_dss_device *dssdev)
170 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
172 dispc_set_parallel_interface_mode(dssdev->manager->id,
173 OMAP_DSS_PARALLELMODE_BYPASS);
174 dispc_set_lcd_display_type(dssdev->manager->id, is_tft ?
175 OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
176 dispc_set_tft_data_lines(dssdev->manager->id,
177 dssdev->phy.dpi.data_lines);
182 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
186 r = omap_dss_start_device(dssdev);
188 DSSERR("failed to start device\n");
192 if (cpu_is_omap34xx()) {
193 r = regulator_enable(dpi.vdds_dsi_reg);
198 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
200 r = dpi_basic_init(dssdev);
204 if (dpi_use_dsi_pll(dssdev)) {
205 dss_clk_enable(DSS_CLK_SYSCK);
206 r = dsi_pll_init(dpi.dsidev, 0, 1);
211 r = dpi_set_mode(dssdev);
217 dssdev->manager->enable(dssdev->manager);
222 if (dpi_use_dsi_pll(dssdev))
223 dsi_pll_uninit(dpi.dsidev, true);
225 if (dpi_use_dsi_pll(dssdev))
226 dss_clk_disable(DSS_CLK_SYSCK);
228 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
229 if (cpu_is_omap34xx())
230 regulator_disable(dpi.vdds_dsi_reg);
232 omap_dss_stop_device(dssdev);
236 EXPORT_SYMBOL(omapdss_dpi_display_enable);
238 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
240 dssdev->manager->disable(dssdev->manager);
242 if (dpi_use_dsi_pll(dssdev)) {
243 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
244 dsi_pll_uninit(dpi.dsidev, true);
245 dss_clk_disable(DSS_CLK_SYSCK);
248 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
250 if (cpu_is_omap34xx())
251 regulator_disable(dpi.vdds_dsi_reg);
253 omap_dss_stop_device(dssdev);
255 EXPORT_SYMBOL(omapdss_dpi_display_disable);
257 void dpi_set_timings(struct omap_dss_device *dssdev,
258 struct omap_video_timings *timings)
260 DSSDBG("dpi_set_timings\n");
261 dssdev->panel.timings = *timings;
262 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
263 dpi_set_mode(dssdev);
264 dispc_go(dssdev->manager->id);
267 EXPORT_SYMBOL(dpi_set_timings);
269 int dpi_check_timings(struct omap_dss_device *dssdev,
270 struct omap_video_timings *timings)
274 int lck_div, pck_div;
277 struct dispc_clock_info dispc_cinfo;
279 if (!dispc_lcd_timings_ok(timings))
282 if (timings->pixel_clock == 0)
285 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
287 if (dpi_use_dsi_pll(dssdev)) {
288 struct dsi_clock_info dsi_cinfo;
289 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
290 timings->pixel_clock * 1000,
291 &dsi_cinfo, &dispc_cinfo);
296 fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
298 struct dss_clock_info dss_cinfo;
299 r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
300 &dss_cinfo, &dispc_cinfo);
308 lck_div = dispc_cinfo.lck_div;
309 pck_div = dispc_cinfo.pck_div;
311 pck = fck / lck_div / pck_div / 1000;
313 timings->pixel_clock = pck;
317 EXPORT_SYMBOL(dpi_check_timings);
319 int dpi_init_display(struct omap_dss_device *dssdev)
321 DSSDBG("init_display\n");
323 if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
324 struct regulator *vdds_dsi;
326 vdds_dsi = dss_get_vdds_dsi();
328 if (IS_ERR(vdds_dsi)) {
329 DSSERR("can't get VDDS_DSI regulator\n");
330 return PTR_ERR(vdds_dsi);
333 dpi.vdds_dsi_reg = vdds_dsi;
336 if (dpi_use_dsi_pll(dssdev)) {
337 enum omap_dss_clk_source dispc_fclk_src =
338 dssdev->clocks.dispc.dispc_fclk_src;
339 dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);