drivers/video/omap2/dss/dispc.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.h
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  * Author: Archit Taneja <archit@ti.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef __OMAP2_DISPC_REG_H
  22 #define __OMAP2_DISPC_REG_H
  23
  24 struct dispc_reg { u16 idx; };
  25
  26 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  27
  28 /*
  29  * DISPC common registers and
  30  * DISPC channel registers , ch = 0 for LCD, ch = 1 for
  31  * DIGIT, and ch = 2 for LCD2
  32  */
  33 #define DISPC_REVISION                  DISPC_REG(0x0000)
  34 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  35 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  36 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  37 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  38 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  39 #define DISPC_CONTROL2                  DISPC_REG(0x0238)
  40 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  41 #define DISPC_CONFIG2                   DISPC_REG(0x0620)
  42 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  43 #define DISPC_DEFAULT_COLOR(ch)         DISPC_REG(ch == 0 ? 0x004C : \
  44                                         (ch == 1 ? 0x0050 : 0x03AC))
  45 #define DISPC_TRANS_COLOR(ch)           DISPC_REG(ch == 0 ? 0x0054 : \
  46                                         (ch == 1 ? 0x0058 : 0x03B0))
  47 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  48 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  49 #define DISPC_TIMING_H(ch)              DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
  50 #define DISPC_TIMING_V(ch)              DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
  51 #define DISPC_POL_FREQ(ch)              DISPC_REG(ch != 2 ? 0x006C : 0x0408)
  52 #define DISPC_DIVISORo(ch)              DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
  53 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  54 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  55 #define DISPC_SIZE_LCD(ch)              DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
  56
  57 #define DISPC_DATA_CYCLE1(ch)           DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
  58 #define DISPC_DATA_CYCLE2(ch)           DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
  59 #define DISPC_DATA_CYCLE3(ch)           DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
  60 #define DISPC_CPR_COEF_R(ch)            DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
  61 #define DISPC_CPR_COEF_G(ch)            DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
  62 #define DISPC_CPR_COEF_B(ch)            DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
  63
  64 #define DISPC_DIVISOR                   DISPC_REG(0x0804)
  65
  66 /* DISPC overlay registers */
  67 #define DISPC_OVL_BA0(n)                DISPC_REG(DISPC_OVL_BASE(n) + \
  68                                         DISPC_BA0_OFFSET(n))
  69 #define DISPC_OVL_BA1(n)                DISPC_REG(DISPC_OVL_BASE(n) + \
  70                                         DISPC_BA1_OFFSET(n))
  71 #define DISPC_OVL_POSITION(n)           DISPC_REG(DISPC_OVL_BASE(n) + \
  72                                         DISPC_POS_OFFSET(n))
  73 #define DISPC_OVL_SIZE(n)               DISPC_REG(DISPC_OVL_BASE(n) + \
  74                                         DISPC_SIZE_OFFSET(n))
  75 #define DISPC_OVL_ATTRIBUTES(n)         DISPC_REG(DISPC_OVL_BASE(n) + \
  76                                         DISPC_ATTR_OFFSET(n))
  77 #define DISPC_OVL_FIFO_THRESHOLD(n)     DISPC_REG(DISPC_OVL_BASE(n) + \
  78                                         DISPC_FIFO_THRESH_OFFSET(n))
  79 #define DISPC_OVL_FIFO_SIZE_STATUS(n)   DISPC_REG(DISPC_OVL_BASE(n) + \
  80                                         DISPC_FIFO_SIZE_STATUS_OFFSET(n))
  81 #define DISPC_OVL_ROW_INC(n)            DISPC_REG(DISPC_OVL_BASE(n) + \
  82                                         DISPC_ROW_INC_OFFSET(n))
  83 #define DISPC_OVL_PIXEL_INC(n)          DISPC_REG(DISPC_OVL_BASE(n) + \
  84                                         DISPC_PIX_INC_OFFSET(n))
  85 #define DISPC_OVL_WINDOW_SKIP(n)        DISPC_REG(DISPC_OVL_BASE(n) + \
  86                                         DISPC_WINDOW_SKIP_OFFSET(n))
  87 #define DISPC_OVL_TABLE_BA(n)           DISPC_REG(DISPC_OVL_BASE(n) + \
  88                                         DISPC_TABLE_BA_OFFSET(n))
  89 #define DISPC_OVL_FIR(n)                DISPC_REG(DISPC_OVL_BASE(n) + \
  90                                         DISPC_FIR_OFFSET(n))
  91 #define DISPC_OVL_PICTURE_SIZE(n)       DISPC_REG(DISPC_OVL_BASE(n) + \
  92                                         DISPC_PIC_SIZE_OFFSET(n))
  93 #define DISPC_OVL_ACCU0(n)              DISPC_REG(DISPC_OVL_BASE(n) + \
  94                                         DISPC_ACCU0_OFFSET(n))
  95 #define DISPC_OVL_ACCU1(n)              DISPC_REG(DISPC_OVL_BASE(n) + \
  96                                         DISPC_ACCU1_OFFSET(n))
  97 #define DISPC_OVL_FIR_COEF_H(n, i)      DISPC_REG(DISPC_OVL_BASE(n) + \
  98                                         DISPC_FIR_COEF_H_OFFSET(n, i))
  99 #define DISPC_OVL_FIR_COEF_HV(n, i)     DISPC_REG(DISPC_OVL_BASE(n) + \
 100                                         DISPC_FIR_COEF_HV_OFFSET(n, i))
 101 #define DISPC_OVL_CONV_COEF(n, i)       DISPC_REG(DISPC_OVL_BASE(n) + \
 102                                         DISPC_CONV_COEF_OFFSET(n, i))
 103 #define DISPC_OVL_FIR_COEF_V(n, i)      DISPC_REG(DISPC_OVL_BASE(n) + \
 104                                         DISPC_FIR_COEF_V_OFFSET(n, i))
 105 #define DISPC_OVL_PRELOAD(n)            DISPC_REG(DISPC_OVL_BASE(n) + \
 106                                         DISPC_PRELOAD_OFFSET(n))
 107
 108 /* DISPC overlay register base addresses */
 109 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
 110 {
 111         switch (plane) {
 112         case OMAP_DSS_GFX:
 113                 return 0x0080;
 114         case OMAP_DSS_VIDEO1:
 115                 return 0x00BC;
 116         case OMAP_DSS_VIDEO2:
 117                 return 0x014C;
 118         default:
 119                 BUG();
 120         }
 121 }
 122
 123 /* DISPC overlay register offsets */
 124 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
 125 {
 126         switch (plane) {
 127         case OMAP_DSS_GFX:
 128         case OMAP_DSS_VIDEO1:
 129         case OMAP_DSS_VIDEO2:
 130                 return 0x0000;
 131         default:
 132                 BUG();
 133         }
 134 }
 135
 136 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
 137 {
 138         switch (plane) {
 139         case OMAP_DSS_GFX:
 140         case OMAP_DSS_VIDEO1:
 141         case OMAP_DSS_VIDEO2:
 142                 return 0x0004;
 143         default:
 144                 BUG();
 145         }
 146 }
 147
 148 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
 149 {
 150         switch (plane) {
 151         case OMAP_DSS_GFX:
 152         case OMAP_DSS_VIDEO1:
 153         case OMAP_DSS_VIDEO2:
 154                 return 0x0008;
 155         default:
 156                 BUG();
 157         }
 158 }
 159
 160 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
 161 {
 162         switch (plane) {
 163         case OMAP_DSS_GFX:
 164         case OMAP_DSS_VIDEO1:
 165         case OMAP_DSS_VIDEO2:
 166                 return 0x000C;
 167         default:
 168                 BUG();
 169         }
 170 }
 171
 172 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
 173 {
 174         switch (plane) {
 175         case OMAP_DSS_GFX:
 176                 return 0x0020;
 177         case OMAP_DSS_VIDEO1:
 178         case OMAP_DSS_VIDEO2:
 179                 return 0x0010;
 180         default:
 181                 BUG();
 182         }
 183 }
 184
 185 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
 186 {
 187         switch (plane) {
 188         case OMAP_DSS_GFX:
 189                 return 0x0024;
 190         case OMAP_DSS_VIDEO1:
 191         case OMAP_DSS_VIDEO2:
 192                 return 0x0014;
 193         default:
 194                 BUG();
 195         }
 196 }
 197
 198 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
 199 {
 200         switch (plane) {
 201         case OMAP_DSS_GFX:
 202                 return 0x0028;
 203         case OMAP_DSS_VIDEO1:
 204         case OMAP_DSS_VIDEO2:
 205                 return 0x0018;
 206         default:
 207                 BUG();
 208         }
 209 }
 210
 211 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
 212 {
 213         switch (plane) {
 214         case OMAP_DSS_GFX:
 215                 return 0x002C;
 216         case OMAP_DSS_VIDEO1:
 217         case OMAP_DSS_VIDEO2:
 218                 return 0x001C;
 219         default:
 220                 BUG();
 221         }
 222 }
 223
 224 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
 225 {
 226         switch (plane) {
 227         case OMAP_DSS_GFX:
 228                 return 0x0030;
 229         case OMAP_DSS_VIDEO1:
 230         case OMAP_DSS_VIDEO2:
 231                 return 0x0020;
 232         default:
 233                 BUG();
 234         }
 235 }
 236
 237 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
 238 {
 239         switch (plane) {
 240         case OMAP_DSS_GFX:
 241                 return 0x0034;
 242         case OMAP_DSS_VIDEO1:
 243         case OMAP_DSS_VIDEO2:
 244                 BUG();
 245         default:
 246                 BUG();
 247         }
 248 }
 249
 250 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
 251 {
 252         switch (plane) {
 253         case OMAP_DSS_GFX:
 254                 return 0x0038;
 255         case OMAP_DSS_VIDEO1:
 256         case OMAP_DSS_VIDEO2:
 257                 BUG();
 258         default:
 259                 BUG();
 260         }
 261 }
 262
 263 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
 264 {
 265         switch (plane) {
 266         case OMAP_DSS_GFX:
 267                 BUG();
 268         case OMAP_DSS_VIDEO1:
 269         case OMAP_DSS_VIDEO2:
 270                 return 0x0024;
 271         default:
 272                 BUG();
 273         }
 274 }
 275
 276 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
 277 {
 278         switch (plane) {
 279         case OMAP_DSS_GFX:
 280                 BUG();
 281         case OMAP_DSS_VIDEO1:
 282         case OMAP_DSS_VIDEO2:
 283                 return 0x0028;
 284         default:
 285                 BUG();
 286         }
 287 }
 288
 289
 290 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
 291 {
 292         switch (plane) {
 293         case OMAP_DSS_GFX:
 294                 BUG();
 295         case OMAP_DSS_VIDEO1:
 296         case OMAP_DSS_VIDEO2:
 297                 return 0x002C;
 298         default:
 299                 BUG();
 300         }
 301 }
 302
 303 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
 304 {
 305         switch (plane) {
 306         case OMAP_DSS_GFX:
 307                 BUG();
 308         case OMAP_DSS_VIDEO1:
 309         case OMAP_DSS_VIDEO2:
 310                 return 0x0030;
 311         default:
 312                 BUG();
 313         }
 314 }
 315
 316 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 317 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
 318 {
 319         switch (plane) {
 320         case OMAP_DSS_GFX:
 321                 BUG();
 322         case OMAP_DSS_VIDEO1:
 323         case OMAP_DSS_VIDEO2:
 324                 return 0x0034 + i * 0x8;
 325         default:
 326                 BUG();
 327         }
 328 }
 329
 330 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 331 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
 332 {
 333         switch (plane) {
 334         case OMAP_DSS_GFX:
 335                 BUG();
 336         case OMAP_DSS_VIDEO1:
 337         case OMAP_DSS_VIDEO2:
 338                 return 0x0038 + i * 0x8;
 339         default:
 340                 BUG();
 341         }
 342 }
 343
 344 /* coef index i = {0, 1, 2, 3, 4,} */
 345 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
 346 {
 347         switch (plane) {
 348         case OMAP_DSS_GFX:
 349                 BUG();
 350         case OMAP_DSS_VIDEO1:
 351         case OMAP_DSS_VIDEO2:
 352                 return 0x0074 + i * 0x4;
 353         default:
 354                 BUG();
 355         }
 356 }
 357
 358 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 359 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
 360 {
 361         switch (plane) {
 362         case OMAP_DSS_GFX:
 363                 BUG();
 364         case OMAP_DSS_VIDEO1:
 365                 return 0x0124 + i * 0x4;
 366         case OMAP_DSS_VIDEO2:
 367                 return 0x00B4 + i * 0x4;
 368         default:
 369                 BUG();
 370         }
 371 }
 372
 373 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
 374 {
 375         switch (plane) {
 376         case OMAP_DSS_GFX:
 377                 return 0x01AC;
 378         case OMAP_DSS_VIDEO1:
 379                 return 0x0174;
 380         case OMAP_DSS_VIDEO2:
 381                 return 0x00E8;
 382         default:
 383                 BUG();
 384         }
 385 }
 386 #endif