1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX23/i.MX28 LCDIF driver
5 * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
12 #include <asm/cache.h>
13 #include <dm/device_compat.h>
14 #include <linux/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/mach-imx/dma.h>
25 #include "videomodes.h"
27 #define PS2KHZ(ps) (1000000000UL / (ps))
28 #define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
33 struct mxs_dma_desc desc;
36 * mxsfb_system_setup() - Fine-tune LCDIF configuration
38 * This function is used to adjust the LCDIF configuration. This is usually
39 * needed when driving the controller in System-Mode to operate an 8080 or
40 * 6800 connected SmartLCD.
42 __weak void mxsfb_system_setup(void)
49 * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
50 * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
52 * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
54 * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
55 * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
58 static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
59 struct display_timing *timings, int bpp)
61 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
62 const enum display_flags flags = timings->flags;
63 uint32_t word_len = 0, bus_width = 0;
64 uint8_t valid_data = 0;
67 #if CONFIG_IS_ENABLED(CLK)
71 ret = clk_get_by_name(dev, "per", &per_clk);
73 dev_err(dev, "Failed to get mxs clk: %d\n", ret);
77 ret = clk_set_rate(&per_clk, timings->pixelclock.typ);
79 dev_err(dev, "Failed to set mxs clk: %d\n", ret);
83 ret = clk_enable(&per_clk);
85 dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
89 /* Kick in the LCDIF clock */
90 mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
93 /* Restart the LCDIF block */
94 mxs_reset_block(®s->hw_lcdif_ctrl_reg);
98 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
99 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
103 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
104 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
108 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
109 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
113 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
114 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
119 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
120 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
121 ®s->hw_lcdif_ctrl);
123 writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
124 ®s->hw_lcdif_ctrl1);
126 mxsfb_system_setup();
128 writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
129 timings->hactive.typ, ®s->hw_lcdif_transfer_count);
131 vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
132 LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
133 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
134 timings->vsync_len.typ;
136 if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
137 vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
138 if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
139 vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
140 if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
141 vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
142 if(flags & DISPLAY_FLAGS_DE_HIGH)
143 vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
145 writel(vdctrl0, ®s->hw_lcdif_vdctrl0);
146 writel(timings->vback_porch.typ + timings->vfront_porch.typ +
147 timings->vsync_len.typ + timings->vactive.typ,
148 ®s->hw_lcdif_vdctrl1);
149 writel((timings->hsync_len.typ << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
150 (timings->hback_porch.typ + timings->hfront_porch.typ +
151 timings->hsync_len.typ + timings->hactive.typ),
152 ®s->hw_lcdif_vdctrl2);
153 writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
154 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
155 (timings->vback_porch.typ + timings->vsync_len.typ),
156 ®s->hw_lcdif_vdctrl3);
157 writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | timings->hactive.typ,
158 ®s->hw_lcdif_vdctrl4);
160 writel(fb_addr, ®s->hw_lcdif_cur_buf);
161 writel(fb_addr, ®s->hw_lcdif_next_buf);
163 /* Flush FIFO first */
164 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set);
166 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
167 /* Sync signals ON */
168 setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
172 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr);
175 writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
178 static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
181 /* Start framebuffer */
182 mxs_lcd_init(dev, fb, timings, bpp);
184 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
186 * If the LCD runs in system mode, the LCD refresh has to be triggered
187 * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
188 * having to set this bit manually after every single change in the
189 * framebuffer memory, we set up specially crafted circular DMA, which
190 * sets the RUN bit, then waits until it gets cleared and repeats this
191 * infinitelly. This way, we get smooth continuous updates of the LCD.
193 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
195 memset(&desc, 0, sizeof(struct mxs_dma_desc));
196 desc.address = (dma_addr_t)&desc;
197 desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
198 MXS_DMA_DESC_WAIT4END |
199 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
200 desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
201 desc.cmd.next = (uint32_t)&desc.cmd;
203 /* Execute the DMA chain. */
204 mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
210 static int mxs_remove_common(u32 fb)
212 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
213 int timeout = 1000000;
218 writel(fb, ®s->hw_lcdif_cur_buf_reg);
219 writel(fb, ®s->hw_lcdif_next_buf_reg);
220 writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
222 if (readl(®s->hw_lcdif_ctrl1_reg) &
223 LCDIF_CTRL1_VSYNC_EDGE_IRQ)
227 mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg);
232 #ifndef CONFIG_DM_VIDEO
234 static GraphicDevice panel;
236 void lcdif_power_down(void)
238 mxs_remove_common(panel.frameAdrs);
241 void *video_hw_init(void)
247 struct ctfb_res_modes mode;
248 struct display_timing timings;
252 /* Suck display configuration from "videomode" variable */
253 penv = env_get("videomode");
255 puts("MXSFB: 'videomode' variable not set!\n");
259 bpp = video_get_params(&mode, penv);
261 /* fill in Graphic device struct */
262 sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
264 panel.winSizeX = mode.xres;
265 panel.winSizeY = mode.yres;
266 panel.plnSizeX = mode.xres;
267 panel.plnSizeY = mode.yres;
272 panel.gdfBytesPP = 4;
273 panel.gdfIndex = GDF_32BIT_X888RGB;
276 panel.gdfBytesPP = 2;
277 panel.gdfIndex = GDF_16BIT_565RGB;
280 panel.gdfBytesPP = 1;
281 panel.gdfIndex = GDF__8BIT_INDEX;
284 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
288 panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
290 /* Allocate framebuffer */
291 fb = memalign(ARCH_DMA_MINALIGN,
292 roundup(panel.memSize, ARCH_DMA_MINALIGN));
294 printf("MXSFB: Error allocating framebuffer!\n");
298 /* Wipe framebuffer */
299 memset(fb, 0, panel.memSize);
301 panel.frameAdrs = (u32)fb;
303 printf("%s\n", panel.modeIdent);
305 video_ctfb_mode_to_display_timing(&mode, &timings);
307 ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
311 return (void *)&panel;
318 #else /* ifndef CONFIG_DM_VIDEO */
320 static int mxs_of_get_timings(struct udevice *dev,
321 struct display_timing *timings,
328 ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
330 dev_err(dev, "required display property isn't provided\n");
334 display_node = ofnode_get_by_phandle(display_phandle);
335 if (!ofnode_valid(display_node)) {
336 dev_err(dev, "failed to find display subnode\n");
340 ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
343 "required bits-per-pixel property isn't provided\n");
347 ret = ofnode_decode_display_timing(display_node, 0, timings);
349 dev_err(dev, "failed to get any display timings\n");
356 static int mxs_video_probe(struct udevice *dev)
358 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
359 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
361 struct display_timing timings;
363 u32 fb_start, fb_end;
366 debug("%s() plat: base 0x%lx, size 0x%x\n",
367 __func__, plat->base, plat->size);
369 ret = mxs_of_get_timings(dev, &timings, &bpp);
373 ret = mxs_probe_common(dev, &timings, bpp, plat->base);
381 uc_priv->bpix = VIDEO_BPP32;
384 uc_priv->bpix = VIDEO_BPP16;
387 uc_priv->bpix = VIDEO_BPP8;
390 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
394 uc_priv->xsize = timings.hactive.typ;
395 uc_priv->ysize = timings.vactive.typ;
397 /* Enable dcache for the frame buffer */
398 fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
399 fb_end = plat->base + plat->size;
400 fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
401 mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
403 video_set_flush_dcache(dev, true);
404 gd->fb_base = plat->base;
409 static int mxs_video_bind(struct udevice *dev)
411 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
412 struct display_timing timings;
417 ret = mxs_of_get_timings(dev, &timings, &bpp);
434 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
438 plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
443 static int mxs_video_remove(struct udevice *dev)
445 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
447 mxs_remove_common(plat->base);
452 static const struct udevice_id mxs_video_ids[] = {
453 { .compatible = "fsl,imx23-lcdif" },
454 { .compatible = "fsl,imx28-lcdif" },
455 { .compatible = "fsl,imx7ulp-lcdif" },
456 { .compatible = "fsl,imxrt-lcdif" },
460 U_BOOT_DRIVER(mxs_video) = {
463 .of_match = mxs_video_ids,
464 .bind = mxs_video_bind,
465 .probe = mxs_video_probe,
466 .remove = mxs_video_remove,
467 .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
469 #endif /* ifndef CONFIG_DM_VIDEO */