1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016-2018 ARM Ltd.
4 * Author: Liviu Dudau <liviu.dudau@foss.arm.com>
18 #include <fdt_support.h>
20 #include <dm/device_compat.h>
21 #include <linux/delay.h>
22 #include <linux/sizes.h>
24 #define MALIDP_CORE_ID 0x0018
25 #define MALIDP_REG_BG_COLOR 0x0044
26 #define MALIDP_LAYER_LV1 0x0100
27 #define MALIDP_DC_STATUS 0xc000
28 #define MALIDP_DC_CONTROL 0xc010
29 #define MALIDP_DC_CFG_VALID 0xc014
31 /* offsets inside the modesetting register block */
32 #define MALIDP_H_INTERVALS 0x0000
33 #define MALIDP_V_INTERVALS 0x0004
34 #define MALIDP_SYNC_CONTROL 0x0008
35 #define MALIDP_HV_ACTIVESIZE 0x000c
36 #define MALIDP_OUTPUT_DEPTH 0x001c
38 /* offsets inside the layer register block */
39 #define MALIDP_LAYER_FORMAT 0x0000
40 #define MALIDP_LAYER_CONTROL 0x0004
41 #define MALIDP_LAYER_IN_SIZE 0x000c
42 #define MALIDP_LAYER_CMP_SIZE 0x0010
43 #define MALIDP_LAYER_STRIDE 0x0018
44 #define MALIDP_LAYER_PTR_LOW 0x0024
45 #define MALIDP_LAYER_PTR_HIGH 0x0028
47 /* offsets inside the IRQ control blocks */
48 #define MALIDP_REG_MASKIRQ 0x0008
49 #define MALIDP_REG_CLEARIRQ 0x000c
55 #define M10BITS 0x03ff
56 #define M12BITS 0x0fff
57 #define M13BITS 0x1fff
58 #define M16BITS 0xffff
59 #define M17BITS 0x1ffff
61 #define MALIDP_H_FRONTPORCH(x) (((x) & M12BITS) << 0)
62 #define MALIDP_H_BACKPORCH(x) (((x) & M10BITS) << 16)
63 #define MALIDP_V_FRONTPORCH(x) (((x) & M12BITS) << 0)
64 #define MALIDP_V_BACKPORCH(x) (((x) & M8BITS) << 16)
65 #define MALIDP_H_SYNCWIDTH(x) (((x) & M10BITS) << 0)
66 #define MALIDP_V_SYNCWIDTH(x) (((x) & M8BITS) << 16)
67 #define MALIDP_H_ACTIVE(x) (((x) & M13BITS) << 0)
68 #define MALIDP_V_ACTIVE(x) (((x) & M13BITS) << 16)
70 #define MALIDP_CMP_V_SIZE(x) (((x) & M13BITS) << 16)
71 #define MALIDP_CMP_H_SIZE(x) (((x) & M13BITS) << 0)
73 #define MALIDP_IN_V_SIZE(x) (((x) & M13BITS) << 16)
74 #define MALIDP_IN_H_SIZE(x) (((x) & M13BITS) << 0)
76 #define MALIDP_DC_CM_CONTROL(x) ((x) & M1BITS) << 16, 1 << 16
77 #define MALIDP_DC_STATUS_GET_CM(reg) (((reg) >> 16) & M1BITS)
79 #define MALIDP_FORMAT_ARGB8888 0x08
80 #define MALIDP_DEFAULT_BG_R 0x0
81 #define MALIDP_DEFAULT_BG_G 0x0
82 #define MALIDP_DEFAULT_BG_B 0x0
84 #define MALIDP_PRODUCT_ID(core_id) ((u32)(core_id) >> 16)
86 #define MALIDP500 0x500
88 DECLARE_GLOBAL_DATA_PTR;
91 phys_addr_t base_addr;
92 phys_addr_t dc_status_addr;
93 phys_addr_t dc_control_addr;
94 phys_addr_t cval_addr;
95 struct udevice *display; /* display device attached */
98 u16 modeset_regs_offset;
100 u8 clear_irq; /* offset for IRQ clear register */
103 static const struct video_ops malidp_ops = {
106 static int malidp_get_hwid(phys_addr_t base_addr)
111 * reading from the old CORE_ID offset will always
112 * return 0x5000000 on DP500
114 hwid = readl(base_addr + MALIDP_CORE_ID);
115 if (MALIDP_PRODUCT_ID(hwid) == MALIDP500)
117 /* otherwise try the other gen CORE_ID offset */
118 hwid = readl(base_addr + MALIDP_DC_STATUS + MALIDP_CORE_ID);
124 * wait for config mode bit setup to be acted upon by the hardware
126 static int malidp_wait_configdone(struct malidp_priv *malidp)
128 u32 status, tries = 300;
131 status = readl(malidp->dc_status_addr);
132 if ((status >> malidp->config_bit_shift) & 1)
144 * signal the hardware to enter configuration mode
146 static int malidp_enter_config(struct malidp_priv *malidp)
148 setbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
149 return malidp_wait_configdone(malidp);
153 * signal the hardware to exit configuration mode
155 static int malidp_leave_config(struct malidp_priv *malidp)
157 clrbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
158 return malidp_wait_configdone(malidp);
161 static void malidp_setup_timings(struct malidp_priv *malidp,
162 struct display_timing *timings)
164 u32 val = MALIDP_H_SYNCWIDTH(timings->hsync_len.typ) |
165 MALIDP_V_SYNCWIDTH(timings->vsync_len.typ);
166 writel(val, malidp->base_addr + malidp->modeset_regs_offset +
167 MALIDP_SYNC_CONTROL);
168 val = MALIDP_H_BACKPORCH(timings->hback_porch.typ) |
169 MALIDP_H_FRONTPORCH(timings->hfront_porch.typ);
170 writel(val, malidp->base_addr + malidp->modeset_regs_offset +
172 val = MALIDP_V_BACKPORCH(timings->vback_porch.typ) |
173 MALIDP_V_FRONTPORCH(timings->vfront_porch.typ);
174 writel(val, malidp->base_addr + malidp->modeset_regs_offset +
176 val = MALIDP_H_ACTIVE(timings->hactive.typ) |
177 MALIDP_V_ACTIVE(timings->vactive.typ);
178 writel(val, malidp->base_addr + malidp->modeset_regs_offset +
179 MALIDP_HV_ACTIVESIZE);
180 /* default output bit-depth per colour is 8 bits */
181 writel(0x080808, malidp->base_addr + malidp->modeset_regs_offset +
182 MALIDP_OUTPUT_DEPTH);
185 static int malidp_setup_mode(struct malidp_priv *malidp,
186 struct display_timing *timings)
190 if (clk_set_rate(&malidp->pxlclk, timings->pixelclock.typ) == 0)
193 malidp_setup_timings(malidp, timings);
195 err = display_enable(malidp->display, 8, timings);
197 printf("display_enable failed with %d\n", err);
202 static void malidp_setup_layer(struct malidp_priv *malidp,
203 struct display_timing *timings,
204 u32 layer_offset, phys_addr_t fb_addr)
208 /* setup the base layer's pixel format to A8R8G8B8 */
209 writel(MALIDP_FORMAT_ARGB8888, malidp->base_addr + layer_offset +
210 MALIDP_LAYER_FORMAT);
211 /* setup layer composition size */
212 val = MALIDP_CMP_V_SIZE(timings->vactive.typ) |
213 MALIDP_CMP_H_SIZE(timings->hactive.typ);
214 writel(val, malidp->base_addr + layer_offset +
215 MALIDP_LAYER_CMP_SIZE);
216 /* setup layer input size */
217 val = MALIDP_IN_V_SIZE(timings->vactive.typ) |
218 MALIDP_IN_H_SIZE(timings->hactive.typ);
219 writel(val, malidp->base_addr + layer_offset + MALIDP_LAYER_IN_SIZE);
220 /* setup layer stride in bytes */
221 writel(timings->hactive.typ << 2, malidp->base_addr + layer_offset +
222 MALIDP_LAYER_STRIDE);
223 /* set framebuffer address */
224 writel(lower_32_bits(fb_addr), malidp->base_addr + layer_offset +
225 MALIDP_LAYER_PTR_LOW);
226 writel(upper_32_bits(fb_addr), malidp->base_addr + layer_offset +
227 MALIDP_LAYER_PTR_HIGH);
229 setbits_le32(malidp->base_addr + layer_offset +
230 MALIDP_LAYER_CONTROL, 1);
233 static void malidp_set_configvalid(struct malidp_priv *malidp)
235 setbits_le32(malidp->cval_addr, 1);
238 static int malidp_update_timings_from_edid(struct udevice *dev,
239 struct display_timing *timings)
241 #ifdef CONFIG_DISPLAY
242 struct malidp_priv *priv = dev_get_priv(dev);
243 struct udevice *disp_dev;
246 err = uclass_first_device(UCLASS_DISPLAY, &disp_dev);
250 priv->display = disp_dev;
252 err = display_read_timing(disp_dev, timings);
260 static int malidp_probe(struct udevice *dev)
262 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
263 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
264 ofnode framebuffer = ofnode_find_subnode(dev_ofnode(dev), "framebuffer");
265 struct malidp_priv *priv = dev_get_priv(dev);
266 struct display_timing timings;
267 phys_addr_t fb_base, fb_size;
272 if (!ofnode_valid(framebuffer))
275 err = clk_get_by_name(dev, "pxlclk", &priv->pxlclk);
277 dev_err(dev, "failed to get pixel clock\n");
280 err = clk_get_by_name(dev, "aclk", &priv->aclk);
282 dev_err(dev, "failed to get AXI clock\n");
286 err = ofnode_decode_display_timing(dev_ofnode(dev), 1, &timings);
288 dev_err(dev, "failed to get any display timings\n");
292 err = malidp_update_timings_from_edid(dev, &timings);
294 printf("malidp_update_timings_from_edid failed: %d\n", err);
298 fb_base = ofnode_get_addr_size(framebuffer, "reg", &fb_size);
299 if (fb_base != FDT_ADDR_T_NONE) {
300 uc_plat->base = fb_base;
301 uc_plat->size = fb_size;
303 printf("cannot get address size for framebuffer\n");
306 err = ofnode_read_u32(framebuffer, "width", &value);
309 uc_priv->xsize = (ushort)value;
311 err = ofnode_read_u32(framebuffer, "height", &value);
314 uc_priv->ysize = (ushort)value;
316 format = ofnode_read_string(framebuffer, "format");
320 } else if (!strncmp(format, "a8r8g8b8", 8)) {
321 uc_priv->bpix = VIDEO_BPP32;
325 priv->base_addr = (phys_addr_t)dev_read_addr(dev);
327 clk_enable(&priv->pxlclk);
328 clk_enable(&priv->aclk);
330 value = malidp_get_hwid(priv->base_addr);
331 printf("Display: Arm Mali DP%3x r%dp%d\n", MALIDP_PRODUCT_ID(value),
332 (value >> 12) & 0xf, (value >> 8) & 0xf);
334 if (MALIDP_PRODUCT_ID(value) == MALIDP500) {
335 /* DP500 is special */
336 priv->modeset_regs_offset = 0x28;
337 priv->dc_status_addr = priv->base_addr;
338 priv->dc_control_addr = priv->base_addr + 0xc;
339 priv->cval_addr = priv->base_addr + 0xf00;
340 priv->config_bit_shift = 17;
343 priv->modeset_regs_offset = 0x30;
344 priv->dc_status_addr = priv->base_addr + MALIDP_DC_STATUS;
345 priv->dc_control_addr = priv->base_addr + MALIDP_DC_CONTROL;
346 priv->cval_addr = priv->base_addr + MALIDP_DC_CFG_VALID;
347 priv->config_bit_shift = 16;
348 priv->clear_irq = MALIDP_REG_CLEARIRQ;
351 /* enter config mode */
352 err = malidp_enter_config(priv);
356 /* disable interrupts */
357 writel(0, priv->dc_status_addr + MALIDP_REG_MASKIRQ);
358 writel(0xffffffff, priv->dc_status_addr + priv->clear_irq);
360 err = malidp_setup_mode(priv, &timings);
364 malidp_setup_layer(priv, &timings, MALIDP_LAYER_LV1,
365 (phys_addr_t)uc_plat->base);
367 err = malidp_leave_config(priv);
371 malidp_set_configvalid(priv);
376 clk_free(&priv->aclk);
378 clk_free(&priv->pxlclk);
383 static int malidp_bind(struct udevice *dev)
385 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
387 /* choose max possible size: 2K x 2K, XRGB888 framebuffer */
388 uc_plat->size = 4 * 2048 * 2048;
393 static const struct udevice_id malidp_ids[] = {
394 { .compatible = "arm,mali-dp500" },
395 { .compatible = "arm,mali-dp550" },
396 { .compatible = "arm,mali-dp650" },
400 U_BOOT_DRIVER(mali_dp) = {
403 .of_match = malidp_ids,
405 .probe = malidp_probe,
406 .priv_auto_alloc_size = sizeof(struct malidp_priv),