drivers/video/fbdev/omap2/dss/hdmi_pll.c

   1 /*
   2  * HDMI PLL
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #define DSS_SUBSYS_NAME "HDMIPLL"
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17 #include <linux/platform_device.h>
  18 #include <video/omapdss.h>
  19
  20 #include "dss.h"
  21 #include "hdmi.h"
  22
  23 #define HDMI_DEFAULT_REGN 16
  24 #define HDMI_DEFAULT_REGM2 1
  25
  26 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
  27 {
  28 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
  29                 hdmi_read_reg(pll->base, r))
  30
  31         DUMPPLL(PLLCTRL_PLL_CONTROL);
  32         DUMPPLL(PLLCTRL_PLL_STATUS);
  33         DUMPPLL(PLLCTRL_PLL_GO);
  34         DUMPPLL(PLLCTRL_CFG1);
  35         DUMPPLL(PLLCTRL_CFG2);
  36         DUMPPLL(PLLCTRL_CFG3);
  37         DUMPPLL(PLLCTRL_SSC_CFG1);
  38         DUMPPLL(PLLCTRL_SSC_CFG2);
  39         DUMPPLL(PLLCTRL_CFG4);
  40 }
  41
  42 void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy)
  43 {
  44         struct hdmi_pll_info *pi = &pll->info;
  45         unsigned long refclk;
  46         u32 mf;
  47
  48         /* use our funky units */
  49         clkin /= 10000;
  50
  51         /*
  52          * Input clock is predivided by N + 1
  53          * out put of which is reference clk
  54          */
  55
  56         pi->regn = HDMI_DEFAULT_REGN;
  57
  58         refclk = clkin / pi->regn;
  59
  60         pi->regm2 = HDMI_DEFAULT_REGM2;
  61
  62         /*
  63          * multiplier is pixel_clk/ref_clk
  64          * Multiplying by 100 to avoid fractional part removal
  65          */
  66         pi->regm = phy * pi->regm2 / refclk;
  67
  68         /*
  69          * fractional multiplier is remainder of the difference between
  70          * multiplier and actual phy(required pixel clock thus should be
  71          * multiplied by 2^18(262144) divided by the reference clock
  72          */
  73         mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
  74         pi->regmf = pi->regm2 * mf / refclk;
  75
  76         /*
  77          * Dcofreq should be set to 1 if required pixel clock
  78          * is greater than 1000MHz
  79          */
  80         pi->dcofreq = phy > 1000 * 100;
  81         pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
  82
  83         /* Set the reference clock to sysclk reference */
  84         pi->refsel = HDMI_REFSEL_SYSCLK;
  85
  86         DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
  87         DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
  88 }
  89
  90
  91 static int hdmi_pll_config(struct hdmi_pll_data *pll)
  92 {
  93         u32 r;
  94         struct hdmi_pll_info *fmt = &pll->info;
  95
  96         /* PLL start always use manual mode */
  97         REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
  98
  99         r = hdmi_read_reg(pll->base, PLLCTRL_CFG1);
 100         r = FLD_MOD(r, fmt->regm, 20, 9);       /* CFG1_PLL_REGM */
 101         r = FLD_MOD(r, fmt->regn - 1, 8, 1);    /* CFG1_PLL_REGN */
 102         hdmi_write_reg(pll->base, PLLCTRL_CFG1, r);
 103
 104         r = hdmi_read_reg(pll->base, PLLCTRL_CFG2);
 105
 106         r = FLD_MOD(r, 0x0, 12, 12);    /* PLL_HIGHFREQ divide by 2 */
 107         r = FLD_MOD(r, 0x1, 13, 13);    /* PLL_REFEN */
 108         r = FLD_MOD(r, 0x0, 14, 14);    /* PHY_CLKINEN de-assert during locking */
 109         r = FLD_MOD(r, fmt->refsel, 22, 21);    /* REFSEL */
 110
 111         if (fmt->dcofreq) {
 112                 /* divider programming for frequency beyond 1000Mhz */
 113                 REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
 114                 r = FLD_MOD(r, 0x4, 3, 1);      /* 1000MHz and 2000MHz */
 115         } else {
 116                 r = FLD_MOD(r, 0x2, 3, 1);      /* 500MHz and 1000MHz */
 117         }
 118
 119         hdmi_write_reg(pll->base, PLLCTRL_CFG2, r);
 120
 121         r = hdmi_read_reg(pll->base, PLLCTRL_CFG4);
 122         r = FLD_MOD(r, fmt->regm2, 24, 18);
 123         r = FLD_MOD(r, fmt->regmf, 17, 0);
 124         hdmi_write_reg(pll->base, PLLCTRL_CFG4, r);
 125
 126         /* go now */
 127         REG_FLD_MOD(pll->base, PLLCTRL_PLL_GO, 0x1, 0, 0);
 128
 129         /* wait for bit change */
 130         if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_GO,
 131                         0, 0, 1) != 1) {
 132                 DSSERR("PLL GO bit not set\n");
 133                 return -ETIMEDOUT;
 134         }
 135
 136         /* Wait till the lock bit is set in PLL status */
 137         if (hdmi_wait_for_bit_change(pll->base,
 138                         PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
 139                 DSSERR("cannot lock PLL\n");
 140                 DSSERR("CFG1 0x%x\n",
 141                         hdmi_read_reg(pll->base, PLLCTRL_CFG1));
 142                 DSSERR("CFG2 0x%x\n",
 143                         hdmi_read_reg(pll->base, PLLCTRL_CFG2));
 144                 DSSERR("CFG4 0x%x\n",
 145                         hdmi_read_reg(pll->base, PLLCTRL_CFG4));
 146                 return -ETIMEDOUT;
 147         }
 148
 149         DSSDBG("PLL locked!\n");
 150
 151         return 0;
 152 }
 153
 154 static int hdmi_pll_reset(struct hdmi_pll_data *pll)
 155 {
 156         /* SYSRESET  controlled by power FSM */
 157         REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
 158
 159         /* READ 0x0 reset is in progress */
 160         if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_STATUS, 0, 0, 1)
 161                         != 1) {
 162                 DSSERR("Failed to sysreset PLL\n");
 163                 return -ETIMEDOUT;
 164         }
 165
 166         return 0;
 167 }
 168
 169 int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
 170 {
 171         u16 r = 0;
 172
 173         r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
 174         if (r)
 175                 return r;
 176
 177         r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
 178         if (r)
 179                 return r;
 180
 181         r = hdmi_pll_reset(pll);
 182         if (r)
 183                 return r;
 184
 185         r = hdmi_pll_config(pll);
 186         if (r)
 187                 return r;
 188
 189         return 0;
 190 }
 191
 192 void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
 193 {
 194         hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
 195 }
 196
 197 #define PLL_OFFSET      0x200
 198 #define PLL_SIZE        0x100
 199
 200 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll)
 201 {
 202         struct resource *res;
 203         struct resource temp_res;
 204
 205         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
 206         if (!res) {
 207                 DSSDBG("can't get PLL mem resource by name\n");
 208                 /*
 209                  * if hwmod/DT doesn't have the memory resource information
 210                  * split into HDMI sub blocks by name, we try again by getting
 211                  * the platform's first resource. this code will be removed when
 212                  * the driver can get the mem resources by name
 213                  */
 214                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 215                 if (!res) {
 216                         DSSERR("can't get PLL mem resource\n");
 217                         return -EINVAL;
 218                 }
 219
 220                 temp_res.start = res->start + PLL_OFFSET;
 221                 temp_res.end = temp_res.start + PLL_SIZE - 1;
 222                 res = &temp_res;
 223         }
 224
 225         pll->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 226         if (!pll->base) {
 227                 DSSERR("can't ioremap PLLCTRL\n");
 228                 return -ENOMEM;
 229         }
 230
 231         return 0;
 232 }