2 * linux/drivers/video/cyber2000fb.c
4 * Copyright (C) 1998-2002 Russell King
6 * MIPS and 50xx clock support
7 * Copyright (C) 2001 Bradley D. LaRonde <brad@ltc.com>
9 * 32 bit support, text color and panning fixes for modes != 8 bit
10 * Copyright (C) 2002 Denis Oliver Kropp <dok@directfb.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
16 * Integraphics CyberPro 2000, 2010 and 5000 frame buffer device
20 * Note that we now use the new fbcon fix, var and cmap scheme. We do
21 * still have to check which console is the currently displayed one
22 * however, especially for the colourmap stuff.
24 * We also use the new hotplug PCI subsystem. I'm not sure if there
25 * are any such cards, but I'm erring on the side of caution. We don't
26 * want to go pop just because someone does have one.
28 * Note that this doesn't work fully in the case of multiple CyberPro
29 * cards with grabbers. We currently can only attach to the first
30 * CyberPro card found.
32 * When we're in truecolour mode, we power down the LUT RAM as a power
33 * saving feature. Also, when we enter any of the powersaving modes
34 * (except soft blanking) we power down the RAMDACs. This saves about
35 * 1W, which is roughly 8% of the power consumption of a NetWinder
36 * (which, incidentally, is about the same saving as a 2.5in hard disk
37 * entering standby mode.)
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/errno.h>
42 #include <linux/string.h>
44 #include <linux/slab.h>
45 #include <linux/delay.h>
47 #include <linux/pci.h>
48 #include <linux/init.h>
50 #include <linux/i2c.h>
51 #include <linux/i2c-algo-bit.h>
53 #include <asm/pgtable.h>
54 #include <asm/system.h>
57 #include <asm/mach-types.h>
60 #include "cyber2000fb.h"
64 struct display_switch *dispsw;
65 struct display *display;
66 unsigned char __iomem *region;
67 unsigned char __iomem *regs;
80 } palette[NR_PALETTE];
87 * RAMDAC control register is both of these or'ed together
90 u_char ramdac_powerdown;
92 u32 pseudo_palette[16];
94 spinlock_t reg_b0_lock;
96 #ifdef CONFIG_FB_CYBER2000_DDC
98 struct i2c_adapter ddc_adapter;
99 struct i2c_algo_bit_data ddc_algo;
102 #ifdef CONFIG_FB_CYBER2000_I2C
103 struct i2c_adapter i2c_adapter;
104 struct i2c_algo_bit_data i2c_algo;
108 static char *default_font = "Acorn8x8";
109 module_param(default_font, charp, 0);
110 MODULE_PARM_DESC(default_font, "Default font name");
113 * Our access methods.
115 #define cyber2000fb_writel(val, reg, cfb) writel(val, (cfb)->regs + (reg))
116 #define cyber2000fb_writew(val, reg, cfb) writew(val, (cfb)->regs + (reg))
117 #define cyber2000fb_writeb(val, reg, cfb) writeb(val, (cfb)->regs + (reg))
119 #define cyber2000fb_readb(reg, cfb) readb((cfb)->regs + (reg))
122 cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
124 cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb);
128 cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
130 cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb);
133 static inline unsigned int
134 cyber2000_grphr(unsigned int reg, struct cfb_info *cfb)
136 cyber2000fb_writeb(reg, 0x3ce, cfb);
137 return cyber2000fb_readb(0x3cf, cfb);
141 cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
143 cyber2000fb_readb(0x3da, cfb);
144 cyber2000fb_writeb(reg, 0x3c0, cfb);
145 cyber2000fb_readb(0x3c1, cfb);
146 cyber2000fb_writeb(val, 0x3c0, cfb);
150 cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
152 cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb);
155 /* -------------------- Hardware specific routines ------------------------- */
158 * Hardware Cyber2000 Acceleration
161 cyber2000fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
163 struct cfb_info *cfb = (struct cfb_info *)info;
164 unsigned long dst, col;
166 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
167 cfb_fillrect(info, rect);
171 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
172 cyber2000fb_writew(rect->width - 1, CO_REG_PIXWIDTH, cfb);
173 cyber2000fb_writew(rect->height - 1, CO_REG_PIXHEIGHT, cfb);
176 if (cfb->fb.var.bits_per_pixel > 8)
177 col = ((u32 *)cfb->fb.pseudo_palette)[col];
178 cyber2000fb_writel(col, CO_REG_FGCOLOUR, cfb);
180 dst = rect->dx + rect->dy * cfb->fb.var.xres_virtual;
181 if (cfb->fb.var.bits_per_pixel == 24) {
182 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
186 cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
187 cyber2000fb_writeb(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
188 cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L, cfb);
189 cyber2000fb_writew(CO_CMD_H_BLITTER, CO_REG_CMD_H, cfb);
193 cyber2000fb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
195 struct cfb_info *cfb = (struct cfb_info *)info;
196 unsigned int cmd = CO_CMD_L_PATTERN_FGCOL;
197 unsigned long src, dst;
199 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
200 cfb_copyarea(info, region);
204 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
205 cyber2000fb_writew(region->width - 1, CO_REG_PIXWIDTH, cfb);
206 cyber2000fb_writew(region->height - 1, CO_REG_PIXHEIGHT, cfb);
208 src = region->sx + region->sy * cfb->fb.var.xres_virtual;
209 dst = region->dx + region->dy * cfb->fb.var.xres_virtual;
211 if (region->sx < region->dx) {
212 src += region->width - 1;
213 dst += region->width - 1;
214 cmd |= CO_CMD_L_INC_LEFT;
217 if (region->sy < region->dy) {
218 src += (region->height - 1) * cfb->fb.var.xres_virtual;
219 dst += (region->height - 1) * cfb->fb.var.xres_virtual;
220 cmd |= CO_CMD_L_INC_UP;
223 if (cfb->fb.var.bits_per_pixel == 24) {
224 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
228 cyber2000fb_writel(src, CO_REG_SRC1_PTR, cfb);
229 cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
230 cyber2000fb_writew(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
231 cyber2000fb_writew(cmd, CO_REG_CMD_L, cfb);
232 cyber2000fb_writew(CO_CMD_H_FGSRCMAP | CO_CMD_H_BLITTER,
237 cyber2000fb_imageblit(struct fb_info *info, const struct fb_image *image)
239 cfb_imageblit(info, image);
243 static int cyber2000fb_sync(struct fb_info *info)
245 struct cfb_info *cfb = (struct cfb_info *)info;
248 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT))
251 while (cyber2000fb_readb(CO_REG_CONTROL, cfb) & CO_CTRL_BUSY) {
253 debug_printf("accel_wait timed out\n");
254 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
263 * ===========================================================================
266 static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf)
268 u_int mask = (1 << bf->length) - 1;
270 return (val >> (16 - bf->length) & mask) << bf->offset;
274 * Set a single color register. Return != 0 for invalid regno.
277 cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
278 u_int transp, struct fb_info *info)
280 struct cfb_info *cfb = (struct cfb_info *)info;
281 struct fb_var_screeninfo *var = &cfb->fb.var;
285 switch (cfb->fb.fix.visual) {
292 * pixel --/--+--/--> red lut --> red dac
294 * +--/--> green lut --> green dac
296 * +--/--> blue lut --> blue dac
298 case FB_VISUAL_PSEUDOCOLOR:
299 if (regno >= NR_PALETTE)
306 cfb->palette[regno].red = red;
307 cfb->palette[regno].green = green;
308 cfb->palette[regno].blue = blue;
310 cyber2000fb_writeb(regno, 0x3c8, cfb);
311 cyber2000fb_writeb(red, 0x3c9, cfb);
312 cyber2000fb_writeb(green, 0x3c9, cfb);
313 cyber2000fb_writeb(blue, 0x3c9, cfb);
319 * pixel --/--+--/--> red lut --> red dac
321 * +--/--> green lut --> green dac
323 * +--/--> blue lut --> blue dac
324 * n = bpp, rl = red length, gl = green length, bl = blue length
326 case FB_VISUAL_DIRECTCOLOR:
331 if (var->green.length == 6 && regno < 64) {
332 cfb->palette[regno << 2].green = green;
335 * The 6 bits of the green component are applied
336 * to the high 6 bits of the LUT.
338 cyber2000fb_writeb(regno << 2, 0x3c8, cfb);
339 cyber2000fb_writeb(cfb->palette[regno >> 1].red,
341 cyber2000fb_writeb(green, 0x3c9, cfb);
342 cyber2000fb_writeb(cfb->palette[regno >> 1].blue,
345 green = cfb->palette[regno << 3].green;
350 if (var->green.length >= 5 && regno < 32) {
351 cfb->palette[regno << 3].red = red;
352 cfb->palette[regno << 3].green = green;
353 cfb->palette[regno << 3].blue = blue;
356 * The 5 bits of each colour component are
357 * applied to the high 5 bits of the LUT.
359 cyber2000fb_writeb(regno << 3, 0x3c8, cfb);
360 cyber2000fb_writeb(red, 0x3c9, cfb);
361 cyber2000fb_writeb(green, 0x3c9, cfb);
362 cyber2000fb_writeb(blue, 0x3c9, cfb);
366 if (var->green.length == 4 && regno < 16) {
367 cfb->palette[regno << 4].red = red;
368 cfb->palette[regno << 4].green = green;
369 cfb->palette[regno << 4].blue = blue;
372 * The 5 bits of each colour component are
373 * applied to the high 5 bits of the LUT.
375 cyber2000fb_writeb(regno << 4, 0x3c8, cfb);
376 cyber2000fb_writeb(red, 0x3c9, cfb);
377 cyber2000fb_writeb(green, 0x3c9, cfb);
378 cyber2000fb_writeb(blue, 0x3c9, cfb);
383 * Since this is only used for the first 16 colours, we
384 * don't have to care about overflowing for regno >= 32
386 pseudo_val = regno << var->red.offset |
387 regno << var->green.offset |
388 regno << var->blue.offset;
394 * pixel --/--+--/--> red dac
399 * n = bpp, rl = red length, gl = green length, bl = blue length
401 case FB_VISUAL_TRUECOLOR:
402 pseudo_val = convert_bitfield(transp ^ 0xffff, &var->transp);
403 pseudo_val |= convert_bitfield(red, &var->red);
404 pseudo_val |= convert_bitfield(green, &var->green);
405 pseudo_val |= convert_bitfield(blue, &var->blue);
411 * Now set our pseudo palette for the CFB16/24/32 drivers.
414 ((u32 *)cfb->fb.pseudo_palette)[regno] = pseudo_val;
439 static const u_char crtc_idx[] = {
440 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
442 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18
445 static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb)
448 unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown;
450 cyber2000fb_writeb(0x56, 0x3ce, cfb);
451 i = cyber2000fb_readb(0x3cf, cfb);
452 cyber2000fb_writeb(i | 4, 0x3cf, cfb);
453 cyber2000fb_writeb(val, 0x3c6, cfb);
454 cyber2000fb_writeb(i, 0x3cf, cfb);
455 /* prevent card lock-up observed on x86 with CyberPro 2000 */
456 cyber2000fb_readb(0x3cf, cfb);
459 static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw)
466 for (i = 0; i < NR_PALETTE; i++) {
467 cyber2000fb_writeb(i, 0x3c8, cfb);
468 cyber2000fb_writeb(0, 0x3c9, cfb);
469 cyber2000fb_writeb(0, 0x3c9, cfb);
470 cyber2000fb_writeb(0, 0x3c9, cfb);
473 cyber2000fb_writeb(0xef, 0x3c2, cfb);
474 cyber2000_crtcw(0x11, 0x0b, cfb);
475 cyber2000_attrw(0x11, 0x00, cfb);
477 cyber2000_seqw(0x00, 0x01, cfb);
478 cyber2000_seqw(0x01, 0x01, cfb);
479 cyber2000_seqw(0x02, 0x0f, cfb);
480 cyber2000_seqw(0x03, 0x00, cfb);
481 cyber2000_seqw(0x04, 0x0e, cfb);
482 cyber2000_seqw(0x00, 0x03, cfb);
484 for (i = 0; i < sizeof(crtc_idx); i++)
485 cyber2000_crtcw(crtc_idx[i], hw->crtc[i], cfb);
487 for (i = 0x0a; i < 0x10; i++)
488 cyber2000_crtcw(i, 0, cfb);
490 cyber2000_grphw(EXT_CRT_VRTOFL, hw->crtc_ofl, cfb);
491 cyber2000_grphw(0x00, 0x00, cfb);
492 cyber2000_grphw(0x01, 0x00, cfb);
493 cyber2000_grphw(0x02, 0x00, cfb);
494 cyber2000_grphw(0x03, 0x00, cfb);
495 cyber2000_grphw(0x04, 0x00, cfb);
496 cyber2000_grphw(0x05, 0x60, cfb);
497 cyber2000_grphw(0x06, 0x05, cfb);
498 cyber2000_grphw(0x07, 0x0f, cfb);
499 cyber2000_grphw(0x08, 0xff, cfb);
501 /* Attribute controller registers */
502 for (i = 0; i < 16; i++)
503 cyber2000_attrw(i, i, cfb);
505 cyber2000_attrw(0x10, 0x01, cfb);
506 cyber2000_attrw(0x11, 0x00, cfb);
507 cyber2000_attrw(0x12, 0x0f, cfb);
508 cyber2000_attrw(0x13, 0x00, cfb);
509 cyber2000_attrw(0x14, 0x00, cfb);
512 spin_lock(&cfb->reg_b0_lock);
513 cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb);
514 cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb);
515 cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb);
516 cyber2000_grphw(EXT_MCLK_DIV, cfb->mclk_div, cfb);
517 cyber2000_grphw(0x90, 0x01, cfb);
518 cyber2000_grphw(0xb9, 0x80, cfb);
519 cyber2000_grphw(0xb9, 0x00, cfb);
520 spin_unlock(&cfb->reg_b0_lock);
522 cfb->ramdac_ctrl = hw->ramdac;
523 cyber2000fb_write_ramdac_ctrl(cfb);
525 cyber2000fb_writeb(0x20, 0x3c0, cfb);
526 cyber2000fb_writeb(0xff, 0x3c6, cfb);
528 cyber2000_grphw(0x14, hw->fetch, cfb);
529 cyber2000_grphw(0x15, ((hw->fetch >> 8) & 0x03) |
530 ((hw->pitch >> 4) & 0x30), cfb);
531 cyber2000_grphw(EXT_SEQ_MISC, hw->extseqmisc, cfb);
534 * Set up accelerator registers
536 cyber2000fb_writew(hw->width, CO_REG_SRC_WIDTH, cfb);
537 cyber2000fb_writew(hw->width, CO_REG_DEST_WIDTH, cfb);
538 cyber2000fb_writeb(hw->co_pixfmt, CO_REG_PIXFMT, cfb);
542 cyber2000fb_update_start(struct cfb_info *cfb, struct fb_var_screeninfo *var)
544 u_int base = var->yoffset * var->xres_virtual + var->xoffset;
546 base *= var->bits_per_pixel;
549 * Convert to bytes and shift two extra bits because DAC
550 * can only start on 4 byte aligned data.
557 cyber2000_grphw(0x10, base >> 16 | 0x10, cfb);
558 cyber2000_crtcw(0x0c, base >> 8, cfb);
559 cyber2000_crtcw(0x0d, base, cfb);
565 cyber2000fb_decode_crtc(struct par_info *hw, struct cfb_info *cfb,
566 struct fb_var_screeninfo *var)
568 u_int Htotal, Hblankend, Hsyncend;
569 u_int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend;
570 #define ENCODE_BIT(v, b1, m, b2) ((((v) >> (b1)) & (m)) << (b2))
572 hw->crtc[13] = hw->pitch;
577 Htotal = var->xres + var->right_margin +
578 var->hsync_len + var->left_margin;
583 hw->crtc[0] = (Htotal >> 3) - 5;
584 hw->crtc[1] = (var->xres >> 3) - 1;
585 hw->crtc[2] = var->xres >> 3;
586 hw->crtc[4] = (var->xres + var->right_margin) >> 3;
588 Hblankend = (Htotal - 4 * 8) >> 3;
590 hw->crtc[3] = ENCODE_BIT(Hblankend, 0, 0x1f, 0) |
591 ENCODE_BIT(1, 0, 0x01, 7);
593 Hsyncend = (var->xres + var->right_margin + var->hsync_len) >> 3;
595 hw->crtc[5] = ENCODE_BIT(Hsyncend, 0, 0x1f, 0) |
596 ENCODE_BIT(Hblankend, 5, 0x01, 7);
598 Vdispend = var->yres - 1;
599 Vsyncstart = var->yres + var->lower_margin;
600 Vsyncend = var->yres + var->lower_margin + var->vsync_len;
601 Vtotal = var->yres + var->lower_margin + var->vsync_len +
602 var->upper_margin - 2;
607 Vblankstart = var->yres + 6;
608 Vblankend = Vtotal - 10;
610 hw->crtc[6] = Vtotal;
611 hw->crtc[7] = ENCODE_BIT(Vtotal, 8, 0x01, 0) |
612 ENCODE_BIT(Vdispend, 8, 0x01, 1) |
613 ENCODE_BIT(Vsyncstart, 8, 0x01, 2) |
614 ENCODE_BIT(Vblankstart, 8, 0x01, 3) |
615 ENCODE_BIT(1, 0, 0x01, 4) |
616 ENCODE_BIT(Vtotal, 9, 0x01, 5) |
617 ENCODE_BIT(Vdispend, 9, 0x01, 6) |
618 ENCODE_BIT(Vsyncstart, 9, 0x01, 7);
619 hw->crtc[9] = ENCODE_BIT(0, 0, 0x1f, 0) |
620 ENCODE_BIT(Vblankstart, 9, 0x01, 5) |
621 ENCODE_BIT(1, 0, 0x01, 6);
622 hw->crtc[10] = Vsyncstart;
623 hw->crtc[11] = ENCODE_BIT(Vsyncend, 0, 0x0f, 0) |
624 ENCODE_BIT(1, 0, 0x01, 7);
625 hw->crtc[12] = Vdispend;
626 hw->crtc[15] = Vblankstart;
627 hw->crtc[16] = Vblankend;
631 * overflow - graphics reg 0x11
632 * 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10
633 * 4=LINECOMP:10 5-IVIDEO 6=FIXCNT
636 ENCODE_BIT(Vtotal, 10, 0x01, 0) |
637 ENCODE_BIT(Vdispend, 10, 0x01, 1) |
638 ENCODE_BIT(Vsyncstart, 10, 0x01, 2) |
639 ENCODE_BIT(Vblankstart, 10, 0x01, 3) |
640 EXT_CRT_VRTOFL_LINECOMP10;
642 /* woody: set the interlaced bit... */
643 /* FIXME: what about doublescan? */
644 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
645 hw->crtc_ofl |= EXT_CRT_VRTOFL_INTERLACE;
651 * The following was discovered by a good monitor, bit twiddling, theorising
652 * and but mostly luck. Strangely, it looks like everyone elses' PLL!
655 * fclock = fpll / div2
656 * fpll = fref * mult / div1
658 * fref = 14.318MHz (69842ps)
660 * div1 = (reg0xb1.5:0 + 1)
661 * div2 = 2^(reg0xb1.7:6)
662 * fpll should be between 115 and 260 MHz
663 * (8696ps and 3846ps)
666 cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb,
667 struct fb_var_screeninfo *var)
669 u_long pll_ps = var->pixclock;
670 const u_long ref_ps = cfb->ref_ps;
671 u_int div2, t_div1, best_div1, best_mult;
677 * find div2 such that 115MHz < fpll < 260MHz
680 for (div2 = 0; div2 < 4; div2++) {
683 new_pll = pll_ps / cfb->divisors[div2];
684 if (8696 > new_pll && new_pll > 3846) {
695 * Given pll_ps and ref_ps, find:
696 * pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005
697 * where { 1 < best_div1 < 32, 1 < best_mult < 256 }
698 * pll_ps_calc = best_div1 / (ref_ps * best_mult)
700 best_diff = 0x7fffffff;
703 for (t_div1 = 2; t_div1 < 32; t_div1 += 1) {
704 u_int rr, t_mult, t_pll_ps;
708 * Find the multiplier for this divisor
710 rr = ref_ps * t_div1;
711 t_mult = (rr + pll_ps / 2) / pll_ps;
714 * Is the multiplier within the correct range?
716 if (t_mult > 256 || t_mult < 2)
720 * Calculate the actual clock period from this multiplier
721 * and divisor, and estimate the error.
723 t_pll_ps = (rr + t_mult / 2) / t_mult;
724 diff = pll_ps - t_pll_ps;
728 if (diff < best_diff) {
735 * If we hit an exact value, there is no point in continuing.
745 hw->clock_mult = best_mult - 1;
746 hw->clock_div = div2 << 6 | (best_div1 - 1);
748 vco = ref_ps * best_div1 / best_mult;
749 if ((ref_ps == 40690) && (vco < 5556))
750 /* Set VFSEL when VCO > 180MHz (5.556 ps). */
751 hw->clock_div |= EXT_DCLK_DIV_VFSEL;
757 * Set the User Defined Part of the Display
760 cyber2000fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
762 struct cfb_info *cfb = (struct cfb_info *)info;
767 var->transp.msb_right = 0;
768 var->red.msb_right = 0;
769 var->green.msb_right = 0;
770 var->blue.msb_right = 0;
771 var->transp.offset = 0;
772 var->transp.length = 0;
774 switch (var->bits_per_pixel) {
775 case 8: /* PSEUDOCOLOUR, 256 */
778 var->green.offset = 0;
779 var->green.length = 8;
780 var->blue.offset = 0;
781 var->blue.length = 8;
784 case 16:/* DIRECTCOLOUR, 64k or 32k */
785 switch (var->green.length) {
786 case 6: /* RGB565, 64k */
787 var->red.offset = 11;
789 var->green.offset = 5;
790 var->green.length = 6;
791 var->blue.offset = 0;
792 var->blue.length = 5;
796 case 5: /* RGB555, 32k */
797 var->red.offset = 10;
799 var->green.offset = 5;
800 var->green.length = 5;
801 var->blue.offset = 0;
802 var->blue.length = 5;
805 case 4: /* RGB444, 4k + transparency? */
806 var->transp.offset = 12;
807 var->transp.length = 4;
810 var->green.offset = 4;
811 var->green.length = 4;
812 var->blue.offset = 0;
813 var->blue.length = 4;
818 case 24:/* TRUECOLOUR, 16m */
819 var->red.offset = 16;
821 var->green.offset = 8;
822 var->green.length = 8;
823 var->blue.offset = 0;
824 var->blue.length = 8;
827 case 32:/* TRUECOLOUR, 16m */
828 var->transp.offset = 24;
829 var->transp.length = 8;
830 var->red.offset = 16;
832 var->green.offset = 8;
833 var->green.length = 8;
834 var->blue.offset = 0;
835 var->blue.length = 8;
842 mem = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8);
843 if (mem > cfb->fb.fix.smem_len)
844 var->yres_virtual = cfb->fb.fix.smem_len * 8 /
845 (var->bits_per_pixel * var->xres_virtual);
847 if (var->yres > var->yres_virtual)
848 var->yres = var->yres_virtual;
849 if (var->xres > var->xres_virtual)
850 var->xres = var->xres_virtual;
852 err = cyber2000fb_decode_clock(&hw, cfb, var);
856 err = cyber2000fb_decode_crtc(&hw, cfb, var);
863 static int cyber2000fb_set_par(struct fb_info *info)
865 struct cfb_info *cfb = (struct cfb_info *)info;
866 struct fb_var_screeninfo *var = &cfb->fb.var;
870 hw.width = var->xres_virtual;
871 hw.ramdac = RAMDAC_VREFEN | RAMDAC_DAC8BIT;
873 switch (var->bits_per_pixel) {
875 hw.co_pixfmt = CO_PIXFMT_8BPP;
876 hw.pitch = hw.width >> 3;
877 hw.extseqmisc = EXT_SEQ_MISC_8;
881 hw.co_pixfmt = CO_PIXFMT_16BPP;
882 hw.pitch = hw.width >> 2;
884 switch (var->green.length) {
885 case 6: /* RGB565, 64k */
886 hw.extseqmisc = EXT_SEQ_MISC_16_RGB565;
888 case 5: /* RGB555, 32k */
889 hw.extseqmisc = EXT_SEQ_MISC_16_RGB555;
891 case 4: /* RGB444, 4k + transparency? */
892 hw.extseqmisc = EXT_SEQ_MISC_16_RGB444;
899 case 24:/* TRUECOLOUR, 16m */
900 hw.co_pixfmt = CO_PIXFMT_24BPP;
902 hw.pitch = hw.width >> 3;
903 hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
904 hw.extseqmisc = EXT_SEQ_MISC_24_RGB888;
907 case 32:/* TRUECOLOUR, 16m */
908 hw.co_pixfmt = CO_PIXFMT_32BPP;
909 hw.pitch = hw.width >> 1;
910 hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
911 hw.extseqmisc = EXT_SEQ_MISC_32;
919 * Sigh, this is absolutely disgusting, but caused by
920 * the way the fbcon developers want to separate out
921 * the "checking" and the "setting" of the video mode.
923 * If the mode is not suitable for the hardware here,
924 * we can't prevent it being set by returning an error.
926 * In theory, since NetWinders contain just one VGA card,
927 * we should never end up hitting this problem.
929 BUG_ON(cyber2000fb_decode_clock(&hw, cfb, var) != 0);
930 BUG_ON(cyber2000fb_decode_crtc(&hw, cfb, var) != 0);
934 if (!(cfb->mem_ctl2 & MEM_CTL2_64BIT))
938 cfb->fb.fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
941 * Same here - if the size of the video mode exceeds the
942 * available RAM, we can't prevent this mode being set.
944 * In theory, since NetWinders contain just one VGA card,
945 * we should never end up hitting this problem.
947 mem = cfb->fb.fix.line_length * var->yres_virtual;
948 BUG_ON(mem > cfb->fb.fix.smem_len);
951 * 8bpp displays are always pseudo colour. 16bpp and above
952 * are direct colour or true colour, depending on whether
953 * the RAMDAC palettes are bypassed. (Direct colour has
954 * palettes, true colour does not.)
956 if (var->bits_per_pixel == 8)
957 cfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
958 else if (hw.ramdac & RAMDAC_BYPASS)
959 cfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
961 cfb->fb.fix.visual = FB_VISUAL_DIRECTCOLOR;
963 cyber2000fb_set_timing(cfb, &hw);
964 cyber2000fb_update_start(cfb, var);
970 * Pan or Wrap the Display
973 cyber2000fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
975 struct cfb_info *cfb = (struct cfb_info *)info;
977 if (cyber2000fb_update_start(cfb, var))
980 cfb->fb.var.xoffset = var->xoffset;
981 cfb->fb.var.yoffset = var->yoffset;
983 if (var->vmode & FB_VMODE_YWRAP) {
984 cfb->fb.var.vmode |= FB_VMODE_YWRAP;
986 cfb->fb.var.vmode &= ~FB_VMODE_YWRAP;
993 * (Un)Blank the display.
995 * Blank the screen if blank_mode != 0, else unblank. If
996 * blank == NULL then the caller blanks by setting the CLUT
997 * (Color Look Up Table) to all black. Return 0 if blanking
998 * succeeded, != 0 if un-/blanking failed due to e.g. a
999 * video mode which doesn't support it. Implements VESA
1000 * suspend and powerdown modes on hardware that supports
1001 * disabling hsync/vsync:
1002 * blank_mode == 2: suspend vsync
1003 * blank_mode == 3: suspend hsync
1004 * blank_mode == 4: powerdown
1006 * wms...Enable VESA DMPS compatible powerdown mode
1007 * run "setterm -powersave powerdown" to take advantage
1009 static int cyber2000fb_blank(int blank, struct fb_info *info)
1011 struct cfb_info *cfb = (struct cfb_info *)info;
1012 unsigned int sync = 0;
1016 case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */
1017 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_0;
1019 case FB_BLANK_HSYNC_SUSPEND: /* hsync off */
1020 sync = EXT_SYNC_CTL_VS_NORMAL | EXT_SYNC_CTL_HS_0;
1022 case FB_BLANK_VSYNC_SUSPEND: /* vsync off */
1023 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_NORMAL;
1025 case FB_BLANK_NORMAL: /* soft blank */
1026 default: /* unblank */
1030 cyber2000_grphw(EXT_SYNC_CTL, sync, cfb);
1033 /* turn on ramdacs */
1034 cfb->ramdac_powerdown &= ~(RAMDAC_DACPWRDN | RAMDAC_BYPASS |
1036 cyber2000fb_write_ramdac_ctrl(cfb);
1040 * Soft blank/unblank the display.
1042 if (blank) { /* soft blank */
1043 for (i = 0; i < NR_PALETTE; i++) {
1044 cyber2000fb_writeb(i, 0x3c8, cfb);
1045 cyber2000fb_writeb(0, 0x3c9, cfb);
1046 cyber2000fb_writeb(0, 0x3c9, cfb);
1047 cyber2000fb_writeb(0, 0x3c9, cfb);
1049 } else { /* unblank */
1050 for (i = 0; i < NR_PALETTE; i++) {
1051 cyber2000fb_writeb(i, 0x3c8, cfb);
1052 cyber2000fb_writeb(cfb->palette[i].red, 0x3c9, cfb);
1053 cyber2000fb_writeb(cfb->palette[i].green, 0x3c9, cfb);
1054 cyber2000fb_writeb(cfb->palette[i].blue, 0x3c9, cfb);
1059 /* turn off ramdacs */
1060 cfb->ramdac_powerdown |= RAMDAC_DACPWRDN | RAMDAC_BYPASS |
1062 cyber2000fb_write_ramdac_ctrl(cfb);
1068 static struct fb_ops cyber2000fb_ops = {
1069 .owner = THIS_MODULE,
1070 .fb_check_var = cyber2000fb_check_var,
1071 .fb_set_par = cyber2000fb_set_par,
1072 .fb_setcolreg = cyber2000fb_setcolreg,
1073 .fb_blank = cyber2000fb_blank,
1074 .fb_pan_display = cyber2000fb_pan_display,
1075 .fb_fillrect = cyber2000fb_fillrect,
1076 .fb_copyarea = cyber2000fb_copyarea,
1077 .fb_imageblit = cyber2000fb_imageblit,
1078 .fb_sync = cyber2000fb_sync,
1082 * This is the only "static" reference to the internal data structures
1083 * of this driver. It is here solely at the moment to support the other
1084 * CyberPro modules external to this driver.
1086 static struct cfb_info *int_cfb_info;
1089 * Enable access to the extended registers
1091 void cyber2000fb_enable_extregs(struct cfb_info *cfb)
1093 cfb->func_use_count += 1;
1095 if (cfb->func_use_count == 1) {
1098 old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
1099 old |= EXT_FUNC_CTL_EXTREGENBL;
1100 cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
1103 EXPORT_SYMBOL(cyber2000fb_enable_extregs);
1106 * Disable access to the extended registers
1108 void cyber2000fb_disable_extregs(struct cfb_info *cfb)
1110 if (cfb->func_use_count == 1) {
1113 old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
1114 old &= ~EXT_FUNC_CTL_EXTREGENBL;
1115 cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
1118 if (cfb->func_use_count == 0)
1119 printk(KERN_ERR "disable_extregs: count = 0\n");
1121 cfb->func_use_count -= 1;
1123 EXPORT_SYMBOL(cyber2000fb_disable_extregs);
1126 * Attach a capture/tv driver to the core CyberX0X0 driver.
1128 int cyber2000fb_attach(struct cyberpro_info *info, int idx)
1130 if (int_cfb_info != NULL) {
1131 info->dev = int_cfb_info->fb.device;
1132 #ifdef CONFIG_FB_CYBER2000_I2C
1133 info->i2c = &int_cfb_info->i2c_adapter;
1137 info->regs = int_cfb_info->regs;
1138 info->irq = int_cfb_info->irq;
1139 info->fb = int_cfb_info->fb.screen_base;
1140 info->fb_size = int_cfb_info->fb.fix.smem_len;
1141 info->info = int_cfb_info;
1143 strlcpy(info->dev_name, int_cfb_info->fb.fix.id,
1144 sizeof(info->dev_name));
1147 return int_cfb_info != NULL;
1149 EXPORT_SYMBOL(cyber2000fb_attach);
1152 * Detach a capture/tv driver from the core CyberX0X0 driver.
1154 void cyber2000fb_detach(int idx)
1157 EXPORT_SYMBOL(cyber2000fb_detach);
1159 #ifdef CONFIG_FB_CYBER2000_DDC
1161 #define DDC_REG 0xb0
1162 #define DDC_SCL_OUT (1 << 0)
1163 #define DDC_SDA_OUT (1 << 4)
1164 #define DDC_SCL_IN (1 << 2)
1165 #define DDC_SDA_IN (1 << 6)
1167 static void cyber2000fb_enable_ddc(struct cfb_info *cfb)
1169 spin_lock(&cfb->reg_b0_lock);
1170 cyber2000fb_writew(0x1bf, 0x3ce, cfb);
1173 static void cyber2000fb_disable_ddc(struct cfb_info *cfb)
1175 cyber2000fb_writew(0x0bf, 0x3ce, cfb);
1176 spin_unlock(&cfb->reg_b0_lock);
1180 static void cyber2000fb_ddc_setscl(void *data, int val)
1182 struct cfb_info *cfb = data;
1185 cyber2000fb_enable_ddc(cfb);
1186 reg = cyber2000_grphr(DDC_REG, cfb);
1187 if (!val) /* bit is inverted */
1190 reg &= ~DDC_SCL_OUT;
1191 cyber2000_grphw(DDC_REG, reg, cfb);
1192 cyber2000fb_disable_ddc(cfb);
1195 static void cyber2000fb_ddc_setsda(void *data, int val)
1197 struct cfb_info *cfb = data;
1200 cyber2000fb_enable_ddc(cfb);
1201 reg = cyber2000_grphr(DDC_REG, cfb);
1202 if (!val) /* bit is inverted */
1205 reg &= ~DDC_SDA_OUT;
1206 cyber2000_grphw(DDC_REG, reg, cfb);
1207 cyber2000fb_disable_ddc(cfb);
1210 static int cyber2000fb_ddc_getscl(void *data)
1212 struct cfb_info *cfb = data;
1215 cyber2000fb_enable_ddc(cfb);
1216 retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SCL_IN);
1217 cyber2000fb_disable_ddc(cfb);
1222 static int cyber2000fb_ddc_getsda(void *data)
1224 struct cfb_info *cfb = data;
1227 cyber2000fb_enable_ddc(cfb);
1228 retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SDA_IN);
1229 cyber2000fb_disable_ddc(cfb);
1234 static int __devinit cyber2000fb_setup_ddc_bus(struct cfb_info *cfb)
1236 strlcpy(cfb->ddc_adapter.name, cfb->fb.fix.id,
1237 sizeof(cfb->ddc_adapter.name));
1238 cfb->ddc_adapter.owner = THIS_MODULE;
1239 cfb->ddc_adapter.class = I2C_CLASS_DDC;
1240 cfb->ddc_adapter.algo_data = &cfb->ddc_algo;
1241 cfb->ddc_adapter.dev.parent = cfb->fb.device;
1242 cfb->ddc_algo.setsda = cyber2000fb_ddc_setsda;
1243 cfb->ddc_algo.setscl = cyber2000fb_ddc_setscl;
1244 cfb->ddc_algo.getsda = cyber2000fb_ddc_getsda;
1245 cfb->ddc_algo.getscl = cyber2000fb_ddc_getscl;
1246 cfb->ddc_algo.udelay = 10;
1247 cfb->ddc_algo.timeout = 20;
1248 cfb->ddc_algo.data = cfb;
1250 i2c_set_adapdata(&cfb->ddc_adapter, cfb);
1252 return i2c_bit_add_bus(&cfb->ddc_adapter);
1254 #endif /* CONFIG_FB_CYBER2000_DDC */
1256 #ifdef CONFIG_FB_CYBER2000_I2C
1257 static void cyber2000fb_i2c_setsda(void *data, int state)
1259 struct cfb_info *cfb = data;
1260 unsigned int latch2;
1262 spin_lock(&cfb->reg_b0_lock);
1263 latch2 = cyber2000_grphr(EXT_LATCH2, cfb);
1264 latch2 &= EXT_LATCH2_I2C_CLKEN;
1266 latch2 |= EXT_LATCH2_I2C_DATEN;
1267 cyber2000_grphw(EXT_LATCH2, latch2, cfb);
1268 spin_unlock(&cfb->reg_b0_lock);
1271 static void cyber2000fb_i2c_setscl(void *data, int state)
1273 struct cfb_info *cfb = data;
1274 unsigned int latch2;
1276 spin_lock(&cfb->reg_b0_lock);
1277 latch2 = cyber2000_grphr(EXT_LATCH2, cfb);
1278 latch2 &= EXT_LATCH2_I2C_DATEN;
1280 latch2 |= EXT_LATCH2_I2C_CLKEN;
1281 cyber2000_grphw(EXT_LATCH2, latch2, cfb);
1282 spin_unlock(&cfb->reg_b0_lock);
1285 static int cyber2000fb_i2c_getsda(void *data)
1287 struct cfb_info *cfb = data;
1290 spin_lock(&cfb->reg_b0_lock);
1291 ret = !!(cyber2000_grphr(EXT_LATCH2, cfb) & EXT_LATCH2_I2C_DAT);
1292 spin_unlock(&cfb->reg_b0_lock);
1297 static int cyber2000fb_i2c_getscl(void *data)
1299 struct cfb_info *cfb = data;
1302 spin_lock(&cfb->reg_b0_lock);
1303 ret = !!(cyber2000_grphr(EXT_LATCH2, cfb) & EXT_LATCH2_I2C_CLK);
1304 spin_unlock(&cfb->reg_b0_lock);
1309 static int __devinit cyber2000fb_i2c_register(struct cfb_info *cfb)
1311 strlcpy(cfb->i2c_adapter.name, cfb->fb.fix.id,
1312 sizeof(cfb->i2c_adapter.name));
1313 cfb->i2c_adapter.owner = THIS_MODULE;
1314 cfb->i2c_adapter.algo_data = &cfb->i2c_algo;
1315 cfb->i2c_adapter.dev.parent = cfb->fb.device;
1316 cfb->i2c_algo.setsda = cyber2000fb_i2c_setsda;
1317 cfb->i2c_algo.setscl = cyber2000fb_i2c_setscl;
1318 cfb->i2c_algo.getsda = cyber2000fb_i2c_getsda;
1319 cfb->i2c_algo.getscl = cyber2000fb_i2c_getscl;
1320 cfb->i2c_algo.udelay = 5;
1321 cfb->i2c_algo.timeout = msecs_to_jiffies(100);
1322 cfb->i2c_algo.data = cfb;
1324 return i2c_bit_add_bus(&cfb->i2c_adapter);
1327 static void cyber2000fb_i2c_unregister(struct cfb_info *cfb)
1329 i2c_del_adapter(&cfb->i2c_adapter);
1332 #define cyber2000fb_i2c_register(cfb) (0)
1333 #define cyber2000fb_i2c_unregister(cfb) do { } while (0)
1337 * These parameters give
1338 * 640x480, hsync 31.5kHz, vsync 60Hz
1340 static struct fb_videomode __devinitdata cyber2000fb_default_mode = {
1351 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1352 .vmode = FB_VMODE_NONINTERLACED
1355 static char igs_regs[] = {
1359 EXT_SEG_WRITE_PTR, 0,
1360 EXT_SEG_READ_PTR, 0,
1361 EXT_BIU_MISC, EXT_BIU_MISC_LIN_ENABLE |
1362 EXT_BIU_MISC_COP_ENABLE |
1363 EXT_BIU_MISC_COP_BFC,
1366 CURS_H_START + 1, 0,
1369 CURS_V_START + 1, 0,
1372 EXT_ATTRIB_CTL, EXT_ATTRIB_CTL_EXT,
1373 EXT_OVERSCAN_RED, 0,
1374 EXT_OVERSCAN_GREEN, 0,
1375 EXT_OVERSCAN_BLUE, 0,
1377 /* some of these are questionable when we have a BIOS */
1378 EXT_MEM_CTL0, EXT_MEM_CTL0_7CLK |
1379 EXT_MEM_CTL0_RAS_1 |
1380 EXT_MEM_CTL0_MULTCAS,
1381 EXT_HIDDEN_CTL1, 0x30,
1383 EXT_FIFO_CTL + 1, 0x17,
1385 EXT_HIDDEN_CTL4, 0xc8
1389 * Initialise the CyberPro hardware. On the CyberPro5XXXX,
1390 * ensure that we're using the correct PLL (5XXX's may be
1391 * programmed to use an additional set of PLLs.)
1393 static void cyberpro_init_hw(struct cfb_info *cfb)
1397 for (i = 0; i < sizeof(igs_regs); i += 2)
1398 cyber2000_grphw(igs_regs[i], igs_regs[i + 1], cfb);
1400 if (cfb->id == ID_CYBERPRO_5000) {
1402 cyber2000fb_writeb(0xba, 0x3ce, cfb);
1403 val = cyber2000fb_readb(0x3cf, cfb) & 0x80;
1404 cyber2000fb_writeb(val, 0x3cf, cfb);
1408 static struct cfb_info __devinit *cyberpro_alloc_fb_info(unsigned int id,
1411 struct cfb_info *cfb;
1413 cfb = kzalloc(sizeof(struct cfb_info), GFP_KERNEL);
1420 if (id == ID_CYBERPRO_5000)
1421 cfb->ref_ps = 40690; /* 24.576 MHz */
1423 cfb->ref_ps = 69842; /* 14.31818 MHz (69841?) */
1425 cfb->divisors[0] = 1;
1426 cfb->divisors[1] = 2;
1427 cfb->divisors[2] = 4;
1429 if (id == ID_CYBERPRO_2000)
1430 cfb->divisors[3] = 8;
1432 cfb->divisors[3] = 6;
1434 strcpy(cfb->fb.fix.id, name);
1436 cfb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1437 cfb->fb.fix.type_aux = 0;
1438 cfb->fb.fix.xpanstep = 0;
1439 cfb->fb.fix.ypanstep = 1;
1440 cfb->fb.fix.ywrapstep = 0;
1444 cfb->fb.fix.accel = 0;
1447 case ID_CYBERPRO_2000:
1448 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2000;
1451 case ID_CYBERPRO_2010:
1452 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2010;
1455 case ID_CYBERPRO_5000:
1456 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER5000;
1460 cfb->fb.var.nonstd = 0;
1461 cfb->fb.var.activate = FB_ACTIVATE_NOW;
1462 cfb->fb.var.height = -1;
1463 cfb->fb.var.width = -1;
1464 cfb->fb.var.accel_flags = FB_ACCELF_TEXT;
1466 cfb->fb.fbops = &cyber2000fb_ops;
1467 cfb->fb.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1468 cfb->fb.pseudo_palette = cfb->pseudo_palette;
1470 spin_lock_init(&cfb->reg_b0_lock);
1472 fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0);
1477 static void cyberpro_free_fb_info(struct cfb_info *cfb)
1481 * Free the colourmap
1483 fb_alloc_cmap(&cfb->fb.cmap, 0, 0);
1490 * Parse Cyber2000fb options. Usage:
1491 * video=cyber2000:font:fontname
1494 static int cyber2000fb_setup(char *options)
1498 if (!options || !*options)
1501 while ((opt = strsep(&options, ",")) != NULL) {
1505 if (strncmp(opt, "font:", 5) == 0) {
1506 static char default_font_storage[40];
1508 strlcpy(default_font_storage, opt + 5,
1509 sizeof(default_font_storage));
1510 default_font = default_font_storage;
1514 printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", opt);
1521 * The CyberPro chips can be placed on many different bus types.
1522 * This probe function is common to all bus types. The bus-specific
1523 * probe function is expected to have:
1524 * - enabled access to the linear memory region
1525 * - memory mapped access to the registers
1526 * - initialised mem_ctl1 and mem_ctl2 appropriately.
1528 static int __devinit cyberpro_common_probe(struct cfb_info *cfb)
1531 u_int h_sync, v_sync;
1534 cyberpro_init_hw(cfb);
1537 * Get the video RAM size and width from the VGA register.
1538 * This should have been already initialised by the BIOS,
1539 * but if it's garbage, claim default 1MB VRAM (woody)
1541 cfb->mem_ctl1 = cyber2000_grphr(EXT_MEM_CTL1, cfb);
1542 cfb->mem_ctl2 = cyber2000_grphr(EXT_MEM_CTL2, cfb);
1545 * Determine the size of the memory.
1547 switch (cfb->mem_ctl2 & MEM_CTL2_SIZE_MASK) {
1548 case MEM_CTL2_SIZE_4MB:
1549 smem_size = 0x00400000;
1551 case MEM_CTL2_SIZE_2MB:
1552 smem_size = 0x00200000;
1554 case MEM_CTL2_SIZE_1MB:
1555 smem_size = 0x00100000;
1558 smem_size = 0x00100000;
1562 cfb->fb.fix.smem_len = smem_size;
1563 cfb->fb.fix.mmio_len = MMIO_SIZE;
1564 cfb->fb.screen_base = cfb->region;
1566 #ifdef CONFIG_FB_CYBER2000_DDC
1567 if (cyber2000fb_setup_ddc_bus(cfb) == 0)
1568 cfb->ddc_registered = true;
1572 if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0,
1573 &cyber2000fb_default_mode, 8)) {
1574 printk(KERN_ERR "%s: no valid mode found\n", cfb->fb.fix.id);
1578 cfb->fb.var.yres_virtual = cfb->fb.fix.smem_len * 8 /
1579 (cfb->fb.var.bits_per_pixel * cfb->fb.var.xres_virtual);
1581 if (cfb->fb.var.yres_virtual < cfb->fb.var.yres)
1582 cfb->fb.var.yres_virtual = cfb->fb.var.yres;
1584 /* fb_set_var(&cfb->fb.var, -1, &cfb->fb); */
1587 * Calculate the hsync and vsync frequencies. Note that
1588 * we split the 1e12 constant up so that we can preserve
1589 * the precision and fit the results into 32-bit registers.
1590 * (1953125000 * 512 = 1e12)
1592 h_sync = 1953125000 / cfb->fb.var.pixclock;
1593 h_sync = h_sync * 512 / (cfb->fb.var.xres + cfb->fb.var.left_margin +
1594 cfb->fb.var.right_margin + cfb->fb.var.hsync_len);
1595 v_sync = h_sync / (cfb->fb.var.yres + cfb->fb.var.upper_margin +
1596 cfb->fb.var.lower_margin + cfb->fb.var.vsync_len);
1598 printk(KERN_INFO "%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
1599 cfb->fb.fix.id, cfb->fb.fix.smem_len >> 10,
1600 cfb->fb.var.xres, cfb->fb.var.yres,
1601 h_sync / 1000, h_sync % 1000, v_sync);
1603 err = cyber2000fb_i2c_register(cfb);
1607 err = register_framebuffer(&cfb->fb);
1609 cyber2000fb_i2c_unregister(cfb);
1612 #ifdef CONFIG_FB_CYBER2000_DDC
1613 if (err && cfb->ddc_registered)
1614 i2c_del_adapter(&cfb->ddc_adapter);
1619 static void __devexit cyberpro_common_remove(struct cfb_info *cfb)
1621 unregister_framebuffer(&cfb->fb);
1622 #ifdef CONFIG_FB_CYBER2000_DDC
1623 if (cfb->ddc_registered)
1624 i2c_del_adapter(&cfb->ddc_adapter);
1626 cyber2000fb_i2c_unregister(cfb);
1629 static void cyberpro_common_resume(struct cfb_info *cfb)
1631 cyberpro_init_hw(cfb);
1634 * Reprogram the MEM_CTL1 and MEM_CTL2 registers
1636 cyber2000_grphw(EXT_MEM_CTL1, cfb->mem_ctl1, cfb);
1637 cyber2000_grphw(EXT_MEM_CTL2, cfb->mem_ctl2, cfb);
1640 * Restore the old video mode and the palette.
1641 * We also need to tell fbcon to redraw the console.
1643 cyber2000fb_set_par(&cfb->fb);
1646 #ifdef CONFIG_ARCH_SHARK
1648 #include <mach/framebuffer.h>
1650 static int __devinit cyberpro_vl_probe(void)
1652 struct cfb_info *cfb;
1655 if (!request_mem_region(FB_START, FB_SIZE, "CyberPro2010"))
1658 cfb = cyberpro_alloc_fb_info(ID_CYBERPRO_2010, "CyberPro2010");
1660 goto failed_release;
1663 cfb->region = ioremap(FB_START, FB_SIZE);
1665 goto failed_ioremap;
1667 cfb->regs = cfb->region + MMIO_OFFSET;
1668 cfb->fb.device = NULL;
1669 cfb->fb.fix.mmio_start = FB_START + MMIO_OFFSET;
1670 cfb->fb.fix.smem_start = FB_START;
1673 * Bring up the hardware. This is expected to enable access
1674 * to the linear memory region, and allow access to the memory
1675 * mapped registers. Also, mem_ctl1 and mem_ctl2 must be
1678 cyber2000fb_writeb(0x18, 0x46e8, cfb);
1679 cyber2000fb_writeb(0x01, 0x102, cfb);
1680 cyber2000fb_writeb(0x08, 0x46e8, cfb);
1681 cyber2000fb_writeb(EXT_BIU_MISC, 0x3ce, cfb);
1682 cyber2000fb_writeb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf, cfb);
1684 cfb->mclk_mult = 0xdb;
1685 cfb->mclk_div = 0x54;
1687 err = cyberpro_common_probe(cfb);
1691 if (int_cfb_info == NULL)
1697 iounmap(cfb->region);
1699 cyberpro_free_fb_info(cfb);
1701 release_mem_region(FB_START, FB_SIZE);
1705 #endif /* CONFIG_ARCH_SHARK */
1708 * PCI specific support.
1712 * We need to wake up the CyberPro, and make sure its in linear memory
1713 * mode. Unfortunately, this is specific to the platform and card that
1714 * we are running on.
1716 * On x86 and ARM, should we be initialising the CyberPro first via the
1717 * IO registers, and then the MMIO registers to catch all cases? Can we
1718 * end up in the situation where the chip is in MMIO mode, but not awake
1721 static int cyberpro_pci_enable_mmio(struct cfb_info *cfb)
1725 #if defined(__sparc_v9__)
1726 #error "You lose, consult DaveM."
1727 #elif defined(__sparc__)
1729 * SPARC does not have an "outb" instruction, so we generate
1730 * I/O cycles storing into a reserved memory space at
1731 * physical address 0x3000000
1733 unsigned char __iomem *iop;
1735 iop = ioremap(0x3000000, 0x5000);
1737 printk(KERN_ERR "iga5000: cannot map I/O\n");
1741 writeb(0x18, iop + 0x46e8);
1742 writeb(0x01, iop + 0x102);
1743 writeb(0x08, iop + 0x46e8);
1744 writeb(EXT_BIU_MISC, iop + 0x3ce);
1745 writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf);
1750 * Most other machine types are "normal", so
1751 * we use the standard IO-based wakeup.
1756 outb(EXT_BIU_MISC, 0x3ce);
1757 outb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf);
1761 * Allow the CyberPro to accept PCI burst accesses
1763 if (cfb->id == ID_CYBERPRO_2010) {
1764 printk(KERN_INFO "%s: NOT enabling PCI bursts\n",
1767 val = cyber2000_grphr(EXT_BUS_CTL, cfb);
1768 if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) {
1769 printk(KERN_INFO "%s: enabling PCI bursts\n",
1772 val |= EXT_BUS_CTL_PCIBURST_WRITE;
1774 if (cfb->id == ID_CYBERPRO_5000)
1775 val |= EXT_BUS_CTL_PCIBURST_READ;
1777 cyber2000_grphw(EXT_BUS_CTL, val, cfb);
1784 static int __devinit
1785 cyberpro_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1787 struct cfb_info *cfb;
1791 sprintf(name, "CyberPro%4X", id->device);
1793 err = pci_enable_device(dev);
1798 cfb = cyberpro_alloc_fb_info(id->driver_data, name);
1800 goto failed_release;
1802 err = pci_request_regions(dev, cfb->fb.fix.id);
1804 goto failed_regions;
1806 cfb->irq = dev->irq;
1807 cfb->region = pci_ioremap_bar(dev, 0);
1809 goto failed_ioremap;
1811 cfb->regs = cfb->region + MMIO_OFFSET;
1812 cfb->fb.device = &dev->dev;
1813 cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET;
1814 cfb->fb.fix.smem_start = pci_resource_start(dev, 0);
1817 * Bring up the hardware. This is expected to enable access
1818 * to the linear memory region, and allow access to the memory
1819 * mapped registers. Also, mem_ctl1 and mem_ctl2 must be
1822 err = cyberpro_pci_enable_mmio(cfb);
1827 * Use MCLK from BIOS. FIXME: what about hotplug?
1829 cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb);
1830 cfb->mclk_div = cyber2000_grphr(EXT_MCLK_DIV, cfb);
1834 * MCLK on the NetWinder and the Shark is fixed at 75MHz
1836 if (machine_is_netwinder()) {
1837 cfb->mclk_mult = 0xdb;
1838 cfb->mclk_div = 0x54;
1842 err = cyberpro_common_probe(cfb);
1849 pci_set_drvdata(dev, cfb);
1850 if (int_cfb_info == NULL)
1856 iounmap(cfb->region);
1858 pci_release_regions(dev);
1860 cyberpro_free_fb_info(cfb);
1865 static void __devexit cyberpro_pci_remove(struct pci_dev *dev)
1867 struct cfb_info *cfb = pci_get_drvdata(dev);
1870 cyberpro_common_remove(cfb);
1871 iounmap(cfb->region);
1872 cyberpro_free_fb_info(cfb);
1875 * Ensure that the driver data is no longer
1878 pci_set_drvdata(dev, NULL);
1879 if (cfb == int_cfb_info)
1880 int_cfb_info = NULL;
1882 pci_release_regions(dev);
1886 static int cyberpro_pci_suspend(struct pci_dev *dev, pm_message_t state)
1892 * Re-initialise the CyberPro hardware
1894 static int cyberpro_pci_resume(struct pci_dev *dev)
1896 struct cfb_info *cfb = pci_get_drvdata(dev);
1899 cyberpro_pci_enable_mmio(cfb);
1900 cyberpro_common_resume(cfb);
1906 static struct pci_device_id cyberpro_pci_table[] = {
1908 * { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682,
1909 * PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 },
1911 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000,
1912 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2000 },
1913 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010,
1914 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2010 },
1915 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000,
1916 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_5000 },
1920 MODULE_DEVICE_TABLE(pci, cyberpro_pci_table);
1922 static struct pci_driver cyberpro_driver = {
1924 .probe = cyberpro_pci_probe,
1925 .remove = __devexit_p(cyberpro_pci_remove),
1926 .suspend = cyberpro_pci_suspend,
1927 .resume = cyberpro_pci_resume,
1928 .id_table = cyberpro_pci_table
1933 * I don't think we can use the "module_init" stuff here because
1934 * the fbcon stuff may not be initialised yet. Hence the #ifdef
1935 * around module_init.
1937 * Tony: "module_init" is now required
1939 static int __init cyber2000fb_init(void)
1944 char *option = NULL;
1946 if (fb_get_options("cyber2000fb", &option))
1948 cyber2000fb_setup(option);
1951 #ifdef CONFIG_ARCH_SHARK
1952 err = cyberpro_vl_probe();
1957 err = pci_register_driver(&cyberpro_driver);
1962 return ret ? err : 0;
1964 module_init(cyber2000fb_init);
1966 #ifndef CONFIG_ARCH_SHARK
1967 static void __exit cyberpro_exit(void)
1969 pci_unregister_driver(&cyberpro_driver);
1971 module_exit(cyberpro_exit);
1974 MODULE_AUTHOR("Russell King");
1975 MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver");
1976 MODULE_LICENSE("GPL");