drivers/video/atmel_hlcdfb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for AT91/AT32 MULTI LAYER LCD Controller
   4  *
   5  * Copyright (C) 2012 Atmel Corporation
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <log.h>
  11 #include <malloc.h>
  12 #include <part.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/gpio.h>
  15 #include <asm/arch/clk.h>
  16 #include <clk.h>
  17 #include <dm.h>
  18 #include <fdtdec.h>
  19 #include <lcd.h>
  20 #include <video.h>
  21 #include <wait_bit.h>
  22 #include <atmel_hlcdc.h>
  23
  24 #if defined(CONFIG_LCD_LOGO)
  25 #include <bmp_logo.h>
  26 #endif
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #ifndef CONFIG_DM_VIDEO
  31
  32 /* configurable parameters */
  33 #define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  34 #define ATMEL_LCDC_DMA_BURST_LEN        8
  35 #ifndef ATMEL_LCDC_GUARD_TIME
  36 #define ATMEL_LCDC_GUARD_TIME           1
  37 #endif
  38
  39 #define ATMEL_LCDC_FIFO_SIZE            512
  40
  41 /*
  42  * the CLUT register map as following
  43  * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
  44  */
  45 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  46 {
  47         writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
  48                ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
  49                | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
  50                | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
  51 }
  52
  53 ushort *configuration_get_cmap(void)
  54 {
  55 #if defined(CONFIG_LCD_LOGO)
  56         return bmp_logo_palette;
  57 #else
  58         return NULL;
  59 #endif
  60 }
  61
  62 void lcd_ctrl_init(void *lcdbase)
  63 {
  64         unsigned long value;
  65         struct lcd_dma_desc *desc;
  66         struct atmel_hlcd_regs *regs;
  67         int ret;
  68
  69         if (!has_lcdc())
  70                 return;     /* No lcdc */
  71
  72         regs = (struct atmel_hlcd_regs *)panel_info.mmio;
  73
  74         /* Disable DISP signal */
  75         writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
  76         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  77                                 false, 1000, false);
  78         if (ret)
  79                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
  80         /* Disable synchronization */
  81         writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
  82         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  83                                 false, 1000, false);
  84         if (ret)
  85                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
  86         /* Disable pixel clock */
  87         writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
  88         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  89                                 false, 1000, false);
  90         if (ret)
  91                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
  92         /* Disable PWM */
  93         writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
  94         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  95                                 false, 1000, false);
  96         if (ret)
  97                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
  98
  99         /* Set pixel clock */
 100         value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
 101         if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
 102                 value++;
 103
 104         if (value < 1) {
 105                 /* Using system clock as pixel clock */
 106                 writel(LCDC_LCDCFG0_CLKDIV(0)
 107                         | LCDC_LCDCFG0_CGDISHCR
 108                         | LCDC_LCDCFG0_CGDISHEO
 109                         | LCDC_LCDCFG0_CGDISOVR1
 110                         | LCDC_LCDCFG0_CGDISBASE
 111                         | panel_info.vl_clk_pol
 112                         | LCDC_LCDCFG0_CLKSEL,
 113                         &regs->lcdc_lcdcfg0);
 114
 115         } else {
 116                 writel(LCDC_LCDCFG0_CLKDIV(value - 2)
 117                         | LCDC_LCDCFG0_CGDISHCR
 118                         | LCDC_LCDCFG0_CGDISHEO
 119                         | LCDC_LCDCFG0_CGDISOVR1
 120                         | LCDC_LCDCFG0_CGDISBASE
 121                         | panel_info.vl_clk_pol,
 122                         &regs->lcdc_lcdcfg0);
 123         }
 124
 125         /* Initialize control register 5 */
 126         value = 0;
 127
 128         value |= panel_info.vl_sync;
 129
 130 #ifndef LCD_OUTPUT_BPP
 131         /* Output is 24bpp */
 132         value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 133 #else
 134         switch (LCD_OUTPUT_BPP) {
 135         case 12:
 136                 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
 137                 break;
 138         case 16:
 139                 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
 140                 break;
 141         case 18:
 142                 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
 143                 break;
 144         case 24:
 145                 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 146                 break;
 147         default:
 148                 BUG();
 149                 break;
 150         }
 151 #endif
 152
 153         value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
 154         value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
 155         writel(value, &regs->lcdc_lcdcfg5);
 156
 157         /* Vertical & Horizontal Timing */
 158         value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
 159         value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
 160         writel(value, &regs->lcdc_lcdcfg1);
 161
 162         value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
 163         value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
 164         writel(value, &regs->lcdc_lcdcfg2);
 165
 166         value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
 167         value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
 168         writel(value, &regs->lcdc_lcdcfg3);
 169
 170         /* Display size */
 171         value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
 172         value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
 173         writel(value, &regs->lcdc_lcdcfg4);
 174
 175         writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
 176                &regs->lcdc_basecfg0);
 177
 178         switch (NBITS(panel_info.vl_bpix)) {
 179         case 16:
 180                 writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
 181                        &regs->lcdc_basecfg1);
 182                 break;
 183         case 32:
 184                 writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
 185                        &regs->lcdc_basecfg1);
 186                 break;
 187         default:
 188                 BUG();
 189                 break;
 190         }
 191
 192         writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
 193         writel(0, &regs->lcdc_basecfg3);
 194         writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
 195
 196         /* Disable all interrupts */
 197         writel(~0UL, &regs->lcdc_lcdidr);
 198         writel(~0UL, &regs->lcdc_baseidr);
 199
 200         /* Setup the DMA descriptor, this descriptor will loop to itself */
 201         desc = (struct lcd_dma_desc *)(lcdbase - 16);
 202
 203         desc->address = (u32)lcdbase;
 204         /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
 205         desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
 206                         | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
 207         desc->next = (u32)desc;
 208
 209         /* Flush the DMA descriptor if we enabled dcache */
 210         flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
 211
 212         writel(desc->address, &regs->lcdc_baseaddr);
 213         writel(desc->control, &regs->lcdc_basectrl);
 214         writel(desc->next, &regs->lcdc_basenext);
 215         writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
 216                &regs->lcdc_basecher);
 217
 218         /* Enable LCD */
 219         value = readl(&regs->lcdc_lcden);
 220         writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
 221         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
 222                                 true, 1000, false);
 223         if (ret)
 224                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 225         value = readl(&regs->lcdc_lcden);
 226         writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
 227         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
 228                                 true, 1000, false);
 229         if (ret)
 230                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 231         value = readl(&regs->lcdc_lcden);
 232         writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
 233         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
 234                                 true, 1000, false);
 235         if (ret)
 236                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 237         value = readl(&regs->lcdc_lcden);
 238         writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
 239         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
 240                                 true, 1000, false);
 241         if (ret)
 242                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 243
 244         /* Enable flushing if we enabled dcache */
 245         lcd_set_flush_dcache(1);
 246 }
 247
 248 #else
 249
 250 enum {
 251         LCD_MAX_WIDTH           = 1024,
 252         LCD_MAX_HEIGHT          = 768,
 253         LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
 254 };
 255
 256 struct atmel_hlcdc_priv {
 257         struct atmel_hlcd_regs *regs;
 258         struct display_timing timing;
 259         unsigned int vl_bpix;
 260         unsigned int output_mode;
 261         unsigned int guard_time;
 262         ulong clk_rate;
 263 };
 264
 265 static int at91_hlcdc_enable_clk(struct udevice *dev)
 266 {
 267         struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
 268         struct clk clk;
 269         ulong clk_rate;
 270         int ret;
 271
 272         ret = clk_get_by_index(dev, 0, &clk);
 273         if (ret)
 274                 return -EINVAL;
 275
 276         ret = clk_enable(&clk);
 277         if (ret)
 278                 return ret;
 279
 280         clk_rate = clk_get_rate(&clk);
 281         if (!clk_rate) {
 282                 clk_disable(&clk);
 283                 return -ENODEV;
 284         }
 285
 286         priv->clk_rate = clk_rate;
 287
 288         clk_free(&clk);
 289
 290         return 0;
 291 }
 292
 293 static void atmel_hlcdc_init(struct udevice *dev)
 294 {
 295         struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
 296         struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
 297         struct atmel_hlcd_regs *regs = priv->regs;
 298         struct display_timing *timing = &priv->timing;
 299         struct lcd_dma_desc *desc;
 300         unsigned long value, vl_clk_pol;
 301         int ret;
 302
 303         /* Disable DISP signal */
 304         writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
 305         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
 306                                 false, 1000, false);
 307         if (ret)
 308                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 309         /* Disable synchronization */
 310         writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
 311         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
 312                                 false, 1000, false);
 313         if (ret)
 314                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 315         /* Disable pixel clock */
 316         writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
 317         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
 318                                 false, 1000, false);
 319         if (ret)
 320                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 321         /* Disable PWM */
 322         writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
 323         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
 324                                 false, 1000, false);
 325         if (ret)
 326                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 327
 328         /* Set pixel clock */
 329         value = priv->clk_rate / timing->pixelclock.typ;
 330         if (priv->clk_rate % timing->pixelclock.typ)
 331                 value++;
 332
 333         vl_clk_pol = 0;
 334         if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 335                 vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
 336
 337         if (value < 1) {
 338                 /* Using system clock as pixel clock */
 339                 writel(LCDC_LCDCFG0_CLKDIV(0)
 340                         | LCDC_LCDCFG0_CGDISHCR
 341                         | LCDC_LCDCFG0_CGDISHEO
 342                         | LCDC_LCDCFG0_CGDISOVR1
 343                         | LCDC_LCDCFG0_CGDISBASE
 344                         | vl_clk_pol
 345                         | LCDC_LCDCFG0_CLKSEL,
 346                         &regs->lcdc_lcdcfg0);
 347
 348         } else {
 349                 writel(LCDC_LCDCFG0_CLKDIV(value - 2)
 350                         | LCDC_LCDCFG0_CGDISHCR
 351                         | LCDC_LCDCFG0_CGDISHEO
 352                         | LCDC_LCDCFG0_CGDISOVR1
 353                         | LCDC_LCDCFG0_CGDISBASE
 354                         | vl_clk_pol,
 355                         &regs->lcdc_lcdcfg0);
 356         }
 357
 358         /* Initialize control register 5 */
 359         value = 0;
 360
 361         if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
 362                 value |= LCDC_LCDCFG5_HSPOL;
 363         if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
 364                 value |= LCDC_LCDCFG5_VSPOL;
 365
 366         switch (priv->output_mode) {
 367         case 12:
 368                 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
 369                 break;
 370         case 16:
 371                 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
 372                 break;
 373         case 18:
 374                 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
 375                 break;
 376         case 24:
 377                 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 378                 break;
 379         default:
 380                 BUG();
 381                 break;
 382         }
 383
 384         value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
 385         value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
 386         writel(value, &regs->lcdc_lcdcfg5);
 387
 388         /* Vertical & Horizontal Timing */
 389         value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
 390         value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
 391         writel(value, &regs->lcdc_lcdcfg1);
 392
 393         value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
 394         value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
 395         writel(value, &regs->lcdc_lcdcfg2);
 396
 397         value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
 398         value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
 399         writel(value, &regs->lcdc_lcdcfg3);
 400
 401         /* Display size */
 402         value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
 403         value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
 404         writel(value, &regs->lcdc_lcdcfg4);
 405
 406         writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
 407                &regs->lcdc_basecfg0);
 408
 409         switch (VNBITS(priv->vl_bpix)) {
 410         case 16:
 411                 writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
 412                        &regs->lcdc_basecfg1);
 413                 break;
 414         case 32:
 415                 writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
 416                        &regs->lcdc_basecfg1);
 417                 break;
 418         default:
 419                 BUG();
 420                 break;
 421         }
 422
 423         writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
 424         writel(0, &regs->lcdc_basecfg3);
 425         writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
 426
 427         /* Disable all interrupts */
 428         writel(~0UL, &regs->lcdc_lcdidr);
 429         writel(~0UL, &regs->lcdc_baseidr);
 430
 431         /* Setup the DMA descriptor, this descriptor will loop to itself */
 432         desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
 433         if (!desc)
 434                 return;
 435
 436         desc->address = (u32)uc_plat->base;
 437
 438         /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
 439         desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
 440                         | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
 441         desc->next = (u32)desc;
 442
 443         /* Flush the DMA descriptor if we enabled dcache */
 444         flush_dcache_range((u32)desc,
 445                            ALIGN(((u32)desc + sizeof(*desc)),
 446                            CONFIG_SYS_CACHELINE_SIZE));
 447
 448         writel(desc->address, &regs->lcdc_baseaddr);
 449         writel(desc->control, &regs->lcdc_basectrl);
 450         writel(desc->next, &regs->lcdc_basenext);
 451         writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
 452                &regs->lcdc_basecher);
 453
 454         /* Enable LCD */
 455         value = readl(&regs->lcdc_lcden);
 456         writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
 457         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
 458                                 true, 1000, false);
 459         if (ret)
 460                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 461         value = readl(&regs->lcdc_lcden);
 462         writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
 463         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
 464                                 true, 1000, false);
 465         if (ret)
 466                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 467         value = readl(&regs->lcdc_lcden);
 468         writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
 469         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
 470                                 true, 1000, false);
 471         if (ret)
 472                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 473         value = readl(&regs->lcdc_lcden);
 474         writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
 475         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
 476                                 true, 1000, false);
 477         if (ret)
 478                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 479 }
 480
 481 static int atmel_hlcdc_probe(struct udevice *dev)
 482 {
 483         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 484         struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
 485         int ret;
 486
 487         ret = at91_hlcdc_enable_clk(dev);
 488         if (ret)
 489                 return ret;
 490
 491         atmel_hlcdc_init(dev);
 492
 493         uc_priv->xsize = priv->timing.hactive.typ;
 494         uc_priv->ysize = priv->timing.vactive.typ;
 495         uc_priv->bpix = priv->vl_bpix;
 496
 497         /* Enable flushing if we enabled dcache */
 498         video_set_flush_dcache(dev, true);
 499
 500         return 0;
 501 }
 502
 503 static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev)
 504 {
 505         struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
 506         const void *blob = gd->fdt_blob;
 507         int node = dev_of_offset(dev);
 508
 509         priv->regs = (struct atmel_hlcd_regs *)devfdt_get_addr(dev);
 510         if (!priv->regs) {
 511                 debug("%s: No display controller address\n", __func__);
 512                 return -EINVAL;
 513         }
 514
 515         if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
 516                                          0, &priv->timing)) {
 517                 debug("%s: Failed to decode display timing\n", __func__);
 518                 return -EINVAL;
 519         }
 520
 521         if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
 522                 priv->timing.hactive.typ = LCD_MAX_WIDTH;
 523
 524         if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
 525                 priv->timing.vactive.typ = LCD_MAX_HEIGHT;
 526
 527         priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
 528         if (!priv->vl_bpix) {
 529                 debug("%s: Failed to get bits per pixel\n", __func__);
 530                 return -EINVAL;
 531         }
 532
 533         priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
 534         priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
 535
 536         return 0;
 537 }
 538
 539 static int atmel_hlcdc_bind(struct udevice *dev)
 540 {
 541         struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
 542
 543         uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 544                                 (1 << LCD_MAX_LOG2_BPP) / 8;
 545
 546         debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
 547
 548         return 0;
 549 }
 550
 551 static const struct udevice_id atmel_hlcdc_ids[] = {
 552         { .compatible = "atmel,sama5d2-hlcdc" },
 553         { .compatible = "atmel,at91sam9x5-hlcdc" },
 554         { }
 555 };
 556
 557 U_BOOT_DRIVER(atmel_hlcdfb) = {
 558         .name   = "atmel_hlcdfb",
 559         .id     = UCLASS_VIDEO,
 560         .of_match = atmel_hlcdc_ids,
 561         .bind   = atmel_hlcdc_bind,
 562         .probe  = atmel_hlcdc_probe,
 563         .ofdata_to_platdata = atmel_hlcdc_ofdata_to_platdata,
 564         .priv_auto_alloc_size = sizeof(struct atmel_hlcdc_priv),
 565 };
 566
 567 #endif