drivers/video/am335x-fb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at>
   4  * B&R Industrial Automation GmbH - http://www.br-automation.com
   5  *
   6  * minimal framebuffer driver for TI's AM335x SoC to be compatible with
   7  * Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
   8  *
   9  * - supporting 16/24/32bit RGB/TFT raster Mode (not using palette)
  10  * - sets up LCD controller as in 'am335x_lcdpanel' struct given
  11  * - starts output DMA from gd->fb_base buffer
  12  */
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/omap.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <linux/err.h>
  20 #include <lcd.h>
  21 #include "am335x-fb.h"
  22
  23 #if !defined(LCD_CNTL_BASE)
  24 #error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
  25 #endif
  26
  27 #define LCDC_FMAX                               200000000
  28
  29 /* LCD Control Register */
  30 #define LCDC_CTRL_CLK_DIVISOR_MASK              GENMASK(15, 8)
  31 #define LCDC_CTRL_RASTER_MODE                   BIT(0)
  32 #define LCDC_CTRL_CLK_DIVISOR(x)                (((x) & GENMASK(7, 0)) << 8)
  33 /* LCD Clock Enable Register */
  34 #define LCDC_CLKC_ENABLE_CORECLKEN              BIT(0)
  35 #define LCDC_CLKC_ENABLE_LIDDCLKEN              BIT(1)
  36 #define LCDC_CLKC_ENABLE_DMACLKEN               BIT(2)
  37 /* LCD DMA Control Register */
  38 #define LCDC_DMA_CTRL_BURST_SIZE(x)             (((x) & GENMASK(2, 0)) << 4)
  39 #define LCDC_DMA_CTRL_BURST_1                   0x0
  40 #define LCDC_DMA_CTRL_BURST_2                   0x1
  41 #define LCDC_DMA_CTRL_BURST_4                   0x2
  42 #define LCDC_DMA_CTRL_BURST_8                   0x3
  43 #define LCDC_DMA_CTRL_BURST_16                  0x4
  44 /* LCD Timing_0 Register */
  45 #define LCDC_RASTER_TIMING_0_HORMSB(x)          (((((x) >> 4) - 1) & 0x40) >> 4)
  46 #define LCDC_RASTER_TIMING_0_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4)
  47 #define LCDC_RASTER_TIMING_0_HSWLSB(x)  ((((x) - 1) & GENMASK(5, 0)) << 10)
  48 #define LCDC_RASTER_TIMING_0_HFPLSB(x)  ((((x) - 1) & GENMASK(7, 0)) << 16)
  49 #define LCDC_RASTER_TIMING_0_HBPLSB(x)  ((((x) - 1) & GENMASK(7, 0)) << 24)
  50 /* LCD Timing_1 Register */
  51 #define LCDC_RASTER_TIMING_1_VERLSB(x)          (((x) - 1) & GENMASK(9, 0))
  52 #define LCDC_RASTER_TIMING_1_VSW(x)     ((((x) - 1) & GENMASK(5, 0)) << 10)
  53 #define LCDC_RASTER_TIMING_1_VFP(x)             (((x) & GENMASK(7, 0)) << 16)
  54 #define LCDC_RASTER_TIMING_1_VBP(x)             (((x) & GENMASK(7, 0)) << 24)
  55 /* LCD Timing_2 Register */
  56 #define LCDC_RASTER_TIMING_2_HFPMSB(x)  ((((x) - 1) & GENMASK(9, 8)) >> 8)
  57 #define LCDC_RASTER_TIMING_2_HBPMSB(x)  ((((x) - 1) & GENMASK(9, 8)) >> 4)
  58 #define LCDC_RASTER_TIMING_2_INVMASK(x)         ((x) & GENMASK(25, 20))
  59 #define LCDC_RASTER_TIMING_2_VERMSB(x)          ((((x) - 1) & BIT(10)) << 16)
  60 #define LCDC_RASTER_TIMING_2_HSWMSB(x)  ((((x) - 1) & GENMASK(9, 6)) << 21)
  61 /* LCD Raster Ctrl Register */
  62 #define LCDC_RASTER_CTRL_ENABLE                 BIT(0)
  63 #define LCDC_RASTER_CTRL_TFT_MODE               BIT(7)
  64 #define LCDC_RASTER_CTRL_PALMODE_RAWDATA        (0x02 << 20)
  65 #define LCDC_RASTER_CTRL_TFT_24BPP_MODE         BIT(25)
  66 #define LCDC_RASTER_CTRL_TFT_24BPP_UNPACK       BIT(26)
  67
  68 /* Macro definitions */
  69 #define FBSIZE(x)       ((x->hactive * x->vactive * x->bpp) >> 3)
  70
  71 struct am335x_lcdhw {
  72         unsigned int            pid;                    /* 0x00 */
  73         unsigned int            ctrl;                   /* 0x04 */
  74         unsigned int            gap0;                   /* 0x08 */
  75         unsigned int            lidd_ctrl;              /* 0x0C */
  76         unsigned int            lidd_cs0_conf;          /* 0x10 */
  77         unsigned int            lidd_cs0_addr;          /* 0x14 */
  78         unsigned int            lidd_cs0_data;          /* 0x18 */
  79         unsigned int            lidd_cs1_conf;          /* 0x1C */
  80         unsigned int            lidd_cs1_addr;          /* 0x20 */
  81         unsigned int            lidd_cs1_data;          /* 0x24 */
  82         unsigned int            raster_ctrl;            /* 0x28 */
  83         unsigned int            raster_timing0;         /* 0x2C */
  84         unsigned int            raster_timing1;         /* 0x30 */
  85         unsigned int            raster_timing2;         /* 0x34 */
  86         unsigned int            raster_subpanel;        /* 0x38 */
  87         unsigned int            raster_subpanel2;       /* 0x3C */
  88         unsigned int            lcddma_ctrl;            /* 0x40 */
  89         unsigned int            lcddma_fb0_base;        /* 0x44 */
  90         unsigned int            lcddma_fb0_ceiling;     /* 0x48 */
  91         unsigned int            lcddma_fb1_base;        /* 0x4C */
  92         unsigned int            lcddma_fb1_ceiling;     /* 0x50 */
  93         unsigned int            sysconfig;              /* 0x54 */
  94         unsigned int            irqstatus_raw;          /* 0x58 */
  95         unsigned int            irqstatus;              /* 0x5C */
  96         unsigned int            irqenable_set;          /* 0x60 */
  97         unsigned int            irqenable_clear;        /* 0x64 */
  98         unsigned int            gap1;                   /* 0x68 */
  99         unsigned int            clkc_enable;            /* 0x6C */
 100         unsigned int            clkc_reset;             /* 0x70 */
 101 };
 102
 103 struct dpll_data {
 104         unsigned long rounded_rate;
 105         u16 rounded_m;
 106         u8 rounded_n;
 107         u8 rounded_div;
 108 };
 109
 110 static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
 111
 112 DECLARE_GLOBAL_DATA_PTR;
 113
 114 /**
 115  * am335x_dpll_round_rate() - Round a target rate for an OMAP DPLL
 116  *
 117  * @dpll_data: struct dpll_data pointer for the DPLL
 118  * @rate:      New DPLL clock rate
 119  * @return rounded rate and the computed m, n and div values in the dpll_data
 120  *         structure, or -ve error code.
 121  */
 122 static ulong am335x_dpll_round_rate(struct dpll_data *dd, ulong rate)
 123 {
 124         unsigned int m, n, d;
 125         unsigned long rounded_rate;
 126         int err, err_r;
 127
 128         dd->rounded_rate = -EFAULT;
 129         err = rate;
 130         err_r = err;
 131
 132         for (d = 2; err && d < 255; d++) {
 133                 for (m = 2; m < 2047; m++) {
 134                         if ((V_OSCK * m) < (rate * d))
 135                                 continue;
 136
 137                         n = (V_OSCK * m) / (rate * d);
 138                         if (n > 127)
 139                                 break;
 140
 141                         if (((V_OSCK * m) / n) > LCDC_FMAX)
 142                                 break;
 143
 144                         rounded_rate = (V_OSCK * m) / n / d;
 145                         err = abs(rounded_rate - rate);
 146                         if (err < err_r) {
 147                                 err_r = err;
 148                                 dd->rounded_rate = rounded_rate;
 149                                 dd->rounded_m = m;
 150                                 dd->rounded_n = n;
 151                                 dd->rounded_div = d;
 152                                 if (err == 0)
 153                                         break;
 154                         }
 155                 }
 156         }
 157
 158         debug("DPLL display: best error %d Hz (M %d, N %d, DIV %d)\n",
 159               err_r, dd->rounded_m, dd->rounded_n, dd->rounded_div);
 160
 161         return dd->rounded_rate;
 162 }
 163
 164 /**
 165  * am335x_fb_set_pixel_clk_rate() - Set pixel clock rate.
 166  *
 167  * @am335x_lcdhw: Base address of the LCD controller registers.
 168  * @rate:         New clock rate in Hz.
 169  * @return new rate, or -ve error code.
 170  */
 171 static ulong am335x_fb_set_pixel_clk_rate(struct am335x_lcdhw *regs, ulong rate)
 172 {
 173         struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
 174         struct dpll_data dd;
 175         ulong round_rate;
 176         u32 reg;
 177
 178         round_rate = am335x_dpll_round_rate(&dd, rate);
 179         if (IS_ERR_VALUE(round_rate))
 180                 return round_rate;
 181
 182         dpll_disp.m = dd.rounded_m;
 183         dpll_disp.n = dd.rounded_n;
 184         do_setup_dpll(&dpll_disp_regs, &dpll_disp);
 185
 186         reg = readl(&regs->ctrl) & ~LCDC_CTRL_CLK_DIVISOR_MASK;
 187         reg |= LCDC_CTRL_CLK_DIVISOR(dd.rounded_div);
 188         writel(reg, &regs->ctrl);
 189         return round_rate;
 190 }
 191
 192 int lcd_get_size(int *line_length)
 193 {
 194         *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
 195         return *line_length * panel_info.vl_row + 0x20;
 196 }
 197
 198 int am335xfb_init(struct am335x_lcdpanel *panel)
 199 {
 200         u32 raster_ctrl = 0;
 201         struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
 202         ulong rate;
 203         u32 reg;
 204
 205         if (gd->fb_base == 0) {
 206                 printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
 207                 return -1;
 208         }
 209         if (panel == NULL) {
 210                 printf("ERROR: missing ptr to am335x_lcdpanel!\n");
 211                 return -1;
 212         }
 213
 214         /* We can already set the bits for the raster_ctrl in this check */
 215         switch (panel->bpp) {
 216         case 16:
 217                 break;
 218         case 32:
 219                 raster_ctrl |= LCDC_RASTER_CTRL_TFT_24BPP_UNPACK;
 220                 /* fallthrough */
 221         case 24:
 222                 raster_ctrl |= LCDC_RASTER_CTRL_TFT_24BPP_MODE;
 223                 break;
 224         default:
 225                 pr_err("am335x-fb: invalid bpp value: %d\n", panel->bpp);
 226                 return -1;
 227         }
 228
 229         /* check given clock-frequency */
 230         if (panel->pxl_clk > (LCDC_FMAX / 2)) {
 231                 pr_err("am335x-fb: requested pxl-clk: %d not supported!\n",
 232                        panel->pxl_clk);
 233                 return -1;
 234         }
 235
 236         debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
 237               panel->hactive, panel->vactive, panel->bpp,
 238               panel->hfp, panel->hbp, panel->hsw);
 239         debug("vfp=%d,vbp=%d,vsw=%d / clk=%d)\n",
 240               panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk);
 241         debug("using frambuffer at 0x%08x with size %d.\n",
 242               (unsigned int)gd->fb_base, FBSIZE(panel));
 243
 244         rate = am335x_fb_set_pixel_clk_rate(lcdhw, panel->pxl_clk);
 245         if (IS_ERR_VALUE(rate))
 246                 return rate;
 247
 248         /* clock source for LCDC from dispPLL M2 */
 249         writel(0x0, &cmdpll->clklcdcpixelclk);
 250
 251         /* palette default entry */
 252         memset((void *)gd->fb_base, 0, 0x20);
 253         *(unsigned int *)gd->fb_base = 0x4000;
 254         /* point fb behind palette */
 255         gd->fb_base += 0x20;
 256
 257         /* turn ON display through powercontrol function if accessible */
 258         if (panel->panel_power_ctrl != NULL)
 259                 panel->panel_power_ctrl(1);
 260
 261         debug("am335x-fb: wait for stable power ...\n");
 262         mdelay(panel->pup_delay);
 263         lcdhw->clkc_enable = LCDC_CLKC_ENABLE_CORECLKEN |
 264                 LCDC_CLKC_ENABLE_LIDDCLKEN | LCDC_CLKC_ENABLE_DMACLKEN;
 265         lcdhw->raster_ctrl = 0;
 266
 267         reg = lcdhw->ctrl & LCDC_CTRL_CLK_DIVISOR_MASK;
 268         reg |= LCDC_CTRL_RASTER_MODE;
 269         lcdhw->ctrl = reg;
 270
 271         lcdhw->lcddma_fb0_base = gd->fb_base;
 272         lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
 273         lcdhw->lcddma_fb1_base = gd->fb_base;
 274         lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel);
 275         lcdhw->lcddma_ctrl = LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_16);
 276
 277         lcdhw->raster_timing0 = LCDC_RASTER_TIMING_0_HORLSB(panel->hactive) |
 278                                 LCDC_RASTER_TIMING_0_HORMSB(panel->hactive) |
 279                                 LCDC_RASTER_TIMING_0_HFPLSB(panel->hfp) |
 280                                 LCDC_RASTER_TIMING_0_HBPLSB(panel->hbp) |
 281                                 LCDC_RASTER_TIMING_0_HSWLSB(panel->hsw);
 282         lcdhw->raster_timing1 = LCDC_RASTER_TIMING_1_VBP(panel->vbp) |
 283                                 LCDC_RASTER_TIMING_1_VFP(panel->vfp) |
 284                                 LCDC_RASTER_TIMING_1_VSW(panel->vsw) |
 285                                 LCDC_RASTER_TIMING_1_VERLSB(panel->vactive);
 286         lcdhw->raster_timing2 = LCDC_RASTER_TIMING_2_HSWMSB(panel->hsw) |
 287                                 LCDC_RASTER_TIMING_2_VERMSB(panel->vactive) |
 288                                 LCDC_RASTER_TIMING_2_INVMASK(panel->pol) |
 289                                 LCDC_RASTER_TIMING_2_HBPMSB(panel->hbp) |
 290                                 LCDC_RASTER_TIMING_2_HFPMSB(panel->hfp) |
 291                                 0x0000FF00;     /* clk cycles for ac-bias */
 292         lcdhw->raster_ctrl =    raster_ctrl |
 293                                 LCDC_RASTER_CTRL_PALMODE_RAWDATA |
 294                                 LCDC_RASTER_CTRL_TFT_MODE |
 295                                 LCDC_RASTER_CTRL_ENABLE;
 296
 297         debug("am335x-fb: waiting picture to be stable.\n.");
 298         mdelay(panel->pon_delay);
 299
 300         return 0;
 301 }