drivers/video/am335x-fb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at>
   4  * B&R Industrial Automation GmbH - http://www.br-automation.com
   5  *
   6  * minimal framebuffer driver for TI's AM335x SoC to be compatible with
   7  * Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
   8  *
   9  * - supporting 16/24/32bit RGB/TFT raster Mode (not using palette)
  10  * - sets up LCD controller as in 'am335x_lcdpanel' struct given
  11  * - starts output DMA from gd->fb_base buffer
  12  */
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/omap.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <lcd.h>
  20 #include "am335x-fb.h"
  21
  22 #if !defined(LCD_CNTL_BASE)
  23 #error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
  24 #endif
  25
  26 #define LCDC_FMAX                               200000000
  27
  28 /* LCD Control Register */
  29 #define LCDC_CTRL_RASTER_MODE                   BIT(0)
  30 #define LCDC_CTRL_CLK_DIVISOR(x)                (((x) & GENMASK(7, 0)) << 8)
  31 /* LCD Clock Enable Register */
  32 #define LCDC_CLKC_ENABLE_CORECLKEN              BIT(0)
  33 #define LCDC_CLKC_ENABLE_LIDDCLKEN              BIT(1)
  34 #define LCDC_CLKC_ENABLE_DMACLKEN               BIT(2)
  35 /* LCD DMA Control Register */
  36 #define LCDC_DMA_CTRL_BURST_SIZE(x)             (((x) & GENMASK(2, 0)) << 4)
  37 #define LCDC_DMA_CTRL_BURST_1                   0x0
  38 #define LCDC_DMA_CTRL_BURST_2                   0x1
  39 #define LCDC_DMA_CTRL_BURST_4                   0x2
  40 #define LCDC_DMA_CTRL_BURST_8                   0x3
  41 #define LCDC_DMA_CTRL_BURST_16                  0x4
  42 /* LCD Timing_0 Register */
  43 #define LCDC_RASTER_TIMING_0_HORMSB(x)          (((((x) >> 4) - 1) & 0x40) >> 4)
  44 #define LCDC_RASTER_TIMING_0_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4)
  45 #define LCDC_RASTER_TIMING_0_HSWLSB(x)  ((((x) - 1) & GENMASK(5, 0)) << 10)
  46 #define LCDC_RASTER_TIMING_0_HFPLSB(x)  ((((x) - 1) & GENMASK(7, 0)) << 16)
  47 #define LCDC_RASTER_TIMING_0_HBPLSB(x)  ((((x) - 1) & GENMASK(7, 0)) << 24)
  48 /* LCD Timing_1 Register */
  49 #define LCDC_RASTER_TIMING_1_VERLSB(x)          (((x) - 1) & GENMASK(9, 0))
  50 #define LCDC_RASTER_TIMING_1_VSW(x)     ((((x) - 1) & GENMASK(5, 0)) << 10)
  51 #define LCDC_RASTER_TIMING_1_VFP(x)             (((x) & GENMASK(7, 0)) << 16)
  52 #define LCDC_RASTER_TIMING_1_VBP(x)             (((x) & GENMASK(7, 0)) << 24)
  53 /* LCD Timing_2 Register */
  54 #define LCDC_RASTER_TIMING_2_HFPMSB(x)  ((((x) - 1) & GENMASK(9, 8)) >> 8)
  55 #define LCDC_RASTER_TIMING_2_HBPMSB(x)  ((((x) - 1) & GENMASK(9, 8)) >> 4)
  56 #define LCDC_RASTER_TIMING_2_INVMASK(x)         ((x) & GENMASK(25, 20))
  57 #define LCDC_RASTER_TIMING_2_VERMSB(x)          ((((x) - 1) & BIT(10)) << 16)
  58 #define LCDC_RASTER_TIMING_2_HSWMSB(x)  ((((x) - 1) & GENMASK(9, 6)) << 21)
  59 /* LCD Raster Ctrl Register */
  60 #define LCDC_RASTER_CTRL_ENABLE                 BIT(0)
  61 #define LCDC_RASTER_CTRL_TFT_MODE               BIT(7)
  62 #define LCDC_RASTER_CTRL_PALMODE_RAWDATA        (0x02 << 20)
  63 #define LCDC_RASTER_CTRL_TFT_24BPP_MODE         BIT(25)
  64 #define LCDC_RASTER_CTRL_TFT_24BPP_UNPACK       BIT(26)
  65
  66 /* Macro definitions */
  67 #define FBSIZE(x)       ((x->hactive * x->vactive * x->bpp) >> 3)
  68
  69 struct am335x_lcdhw {
  70         unsigned int            pid;                    /* 0x00 */
  71         unsigned int            ctrl;                   /* 0x04 */
  72         unsigned int            gap0;                   /* 0x08 */
  73         unsigned int            lidd_ctrl;              /* 0x0C */
  74         unsigned int            lidd_cs0_conf;          /* 0x10 */
  75         unsigned int            lidd_cs0_addr;          /* 0x14 */
  76         unsigned int            lidd_cs0_data;          /* 0x18 */
  77         unsigned int            lidd_cs1_conf;          /* 0x1C */
  78         unsigned int            lidd_cs1_addr;          /* 0x20 */
  79         unsigned int            lidd_cs1_data;          /* 0x24 */
  80         unsigned int            raster_ctrl;            /* 0x28 */
  81         unsigned int            raster_timing0;         /* 0x2C */
  82         unsigned int            raster_timing1;         /* 0x30 */
  83         unsigned int            raster_timing2;         /* 0x34 */
  84         unsigned int            raster_subpanel;        /* 0x38 */
  85         unsigned int            raster_subpanel2;       /* 0x3C */
  86         unsigned int            lcddma_ctrl;            /* 0x40 */
  87         unsigned int            lcddma_fb0_base;        /* 0x44 */
  88         unsigned int            lcddma_fb0_ceiling;     /* 0x48 */
  89         unsigned int            lcddma_fb1_base;        /* 0x4C */
  90         unsigned int            lcddma_fb1_ceiling;     /* 0x50 */
  91         unsigned int            sysconfig;              /* 0x54 */
  92         unsigned int            irqstatus_raw;          /* 0x58 */
  93         unsigned int            irqstatus;              /* 0x5C */
  94         unsigned int            irqenable_set;          /* 0x60 */
  95         unsigned int            irqenable_clear;        /* 0x64 */
  96         unsigned int            gap1;                   /* 0x68 */
  97         unsigned int            clkc_enable;            /* 0x6C */
  98         unsigned int            clkc_reset;             /* 0x70 */
  99 };
 100
 101 static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
 102
 103 DECLARE_GLOBAL_DATA_PTR;
 104
 105 int lcd_get_size(int *line_length)
 106 {
 107         *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
 108         return *line_length * panel_info.vl_row + 0x20;
 109 }
 110
 111 int am335xfb_init(struct am335x_lcdpanel *panel)
 112 {
 113         u32 raster_ctrl = 0;
 114
 115         struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
 116         struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
 117         unsigned int m, n, d, best_d = 2;
 118         int err = 0, err_r = 0;
 119
 120         if (gd->fb_base == 0) {
 121                 printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
 122                 return -1;
 123         }
 124         if (panel == NULL) {
 125                 printf("ERROR: missing ptr to am335x_lcdpanel!\n");
 126                 return -1;
 127         }
 128
 129         /* We can already set the bits for the raster_ctrl in this check */
 130         switch (panel->bpp) {
 131         case 16:
 132                 break;
 133         case 32:
 134                 raster_ctrl |= LCDC_RASTER_CTRL_TFT_24BPP_UNPACK;
 135                 /* fallthrough */
 136         case 24:
 137                 raster_ctrl |= LCDC_RASTER_CTRL_TFT_24BPP_MODE;
 138                 break;
 139         default:
 140                 pr_err("am335x-fb: invalid bpp value: %d\n", panel->bpp);
 141                 return -1;
 142         }
 143
 144         /* check given clock-frequency */
 145         if (panel->pxl_clk > (LCDC_FMAX / 2)) {
 146                 pr_err("am335x-fb: requested pxl-clk: %d not supported!\n",
 147                        panel->pxl_clk);
 148                 return -1;
 149         }
 150
 151         debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
 152               panel->hactive, panel->vactive, panel->bpp,
 153               panel->hfp, panel->hbp, panel->hsw);
 154         debug("vfp=%d,vbp=%d,vsw=%d / clk=%d)\n",
 155               panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk);
 156         debug("using frambuffer at 0x%08x with size %d.\n",
 157               (unsigned int)gd->fb_base, FBSIZE(panel));
 158
 159         /* setup display pll for requested clock frequency */
 160         err = panel->pxl_clk;
 161         err_r = err;
 162
 163         for (d = 2; err_r && d < 255; d++) {
 164                 for (m = 2; m < 2047; m++) {
 165                         if ((V_OSCK * m) < (panel->pxl_clk * d))
 166                                 continue;
 167                         n = (V_OSCK * m) / (panel->pxl_clk * d);
 168                         if (n > 127)
 169                                 break;
 170                         if (((V_OSCK * m) / n) > LCDC_FMAX)
 171                                 break;
 172
 173                         err = abs((V_OSCK * m) / n / d - panel->pxl_clk);
 174                         if (err < err_r) {
 175                                 err_r = err;
 176                                 dpll_disp.m = m;
 177                                 dpll_disp.n = n;
 178                                 best_d = d;
 179                                 if (err_r == 0)
 180                                         break;
 181                         }
 182                 }
 183         }
 184         debug("%s: PLL: best error %d Hz (M %d, N %d, DIV %d)\n",
 185               __func__, err_r, dpll_disp.m, dpll_disp.n, best_d);
 186         do_setup_dpll(&dpll_disp_regs, &dpll_disp);
 187
 188         /* clock source for LCDC from dispPLL M2 */
 189         writel(0x0, &cmdpll->clklcdcpixelclk);
 190
 191         /* palette default entry */
 192         memset((void *)gd->fb_base, 0, 0x20);
 193         *(unsigned int *)gd->fb_base = 0x4000;
 194         /* point fb behind palette */
 195         gd->fb_base += 0x20;
 196
 197         /* turn ON display through powercontrol function if accessible */
 198         if (panel->panel_power_ctrl != NULL)
 199                 panel->panel_power_ctrl(1);
 200
 201         debug("am335x-fb: wait for stable power ...\n");
 202         mdelay(panel->pup_delay);
 203         lcdhw->clkc_enable = LCDC_CLKC_ENABLE_CORECLKEN |
 204                 LCDC_CLKC_ENABLE_LIDDCLKEN | LCDC_CLKC_ENABLE_DMACLKEN;
 205         lcdhw->raster_ctrl = 0;
 206         lcdhw->ctrl = LCDC_CTRL_CLK_DIVISOR(best_d) | LCDC_CTRL_RASTER_MODE;
 207         lcdhw->lcddma_fb0_base = gd->fb_base;
 208         lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
 209         lcdhw->lcddma_fb1_base = gd->fb_base;
 210         lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel);
 211         lcdhw->lcddma_ctrl = LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_16);
 212
 213         lcdhw->raster_timing0 = LCDC_RASTER_TIMING_0_HORLSB(panel->hactive) |
 214                                 LCDC_RASTER_TIMING_0_HORMSB(panel->hactive) |
 215                                 LCDC_RASTER_TIMING_0_HFPLSB(panel->hfp) |
 216                                 LCDC_RASTER_TIMING_0_HBPLSB(panel->hbp) |
 217                                 LCDC_RASTER_TIMING_0_HSWLSB(panel->hsw);
 218         lcdhw->raster_timing1 = LCDC_RASTER_TIMING_1_VBP(panel->vbp) |
 219                                 LCDC_RASTER_TIMING_1_VFP(panel->vfp) |
 220                                 LCDC_RASTER_TIMING_1_VSW(panel->vsw) |
 221                                 LCDC_RASTER_TIMING_1_VERLSB(panel->vactive);
 222         lcdhw->raster_timing2 = LCDC_RASTER_TIMING_2_HSWMSB(panel->hsw) |
 223                                 LCDC_RASTER_TIMING_2_VERMSB(panel->vactive) |
 224                                 LCDC_RASTER_TIMING_2_INVMASK(panel->pol) |
 225                                 LCDC_RASTER_TIMING_2_HBPMSB(panel->hbp) |
 226                                 LCDC_RASTER_TIMING_2_HFPMSB(panel->hfp) |
 227                                 0x0000FF00;     /* clk cycles for ac-bias */
 228         lcdhw->raster_ctrl =    raster_ctrl |
 229                                 LCDC_RASTER_CTRL_PALMODE_RAWDATA |
 230                                 LCDC_RASTER_CTRL_TFT_MODE |
 231                                 LCDC_RASTER_CTRL_ENABLE;
 232
 233         debug("am335x-fb: waiting picture to be stable.\n.");
 234         mdelay(panel->pon_delay);
 235
 236         return 0;
 237 }