drivers/usb/phy/phy-samsung-usb3.c

   1 /* linux/drivers/usb/phy/phy-samsung-usb3.c
   2  *
   3  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Author: Vivek Gautam <gautam.vivek@samsung.com>
   7  *
   8  * Samsung USB 3.0 PHY transceiver; talks to DWC3 controller.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/delay.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/of.h>
  27 #include <linux/usb/samsung_usb_phy.h>
  28 #include <linux/platform_data/samsung-usbphy.h>
  29
  30 #include "phy-samsung-usb.h"
  31
  32 /*
  33  * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock core.
  34  */
  35 static u32 samsung_usb3phy_set_refclk(struct samsung_usbphy *sphy)
  36 {
  37         u32 reg;
  38         u32 refclk;
  39
  40         refclk = sphy->ref_clk_freq;
  41
  42         reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
  43                 PHYCLKRST_FSEL(refclk);
  44
  45         switch (refclk) {
  46         case FSEL_CLKSEL_50M:
  47                 reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
  48                         PHYCLKRST_SSC_REFCLKSEL(0x00));
  49                 break;
  50         case FSEL_CLKSEL_20M:
  51                 reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
  52                         PHYCLKRST_SSC_REFCLKSEL(0x00));
  53                 break;
  54         case FSEL_CLKSEL_19200K:
  55                 reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
  56                         PHYCLKRST_SSC_REFCLKSEL(0x88));
  57                 break;
  58         case FSEL_CLKSEL_24M:
  59         default:
  60                 reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
  61                         PHYCLKRST_SSC_REFCLKSEL(0x88));
  62                 break;
  63         }
  64
  65         return reg;
  66 }
  67
  68 static int samsung_exynos5_usb3phy_enable(struct samsung_usbphy *sphy)
  69 {
  70         void __iomem *regs = sphy->regs;
  71         u32 phyparam0;
  72         u32 phyparam1;
  73         u32 linksystem;
  74         u32 phybatchg;
  75         u32 phytest;
  76         u32 phyclkrst;
  77
  78         /* Reset USB 3.0 PHY */
  79         writel(0x0, regs + EXYNOS5_DRD_PHYREG0);
  80
  81         phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0);
  82         /* Select PHY CLK source */
  83         phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
  84         /* Set Loss-of-Signal Detector sensitivity */
  85         phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
  86         phyparam0 |= PHYPARAM0_REF_LOSLEVEL;
  87         writel(phyparam0, regs + EXYNOS5_DRD_PHYPARAM0);
  88
  89         writel(0x0, regs + EXYNOS5_DRD_PHYRESUME);
  90
  91         /*
  92          * Setting the Frame length Adj value[6:1] to default 0x20
  93          * See xHCI 1.0 spec, 5.2.4
  94          */
  95         linksystem = LINKSYSTEM_XHCI_VERSION_CONTROL |
  96                         LINKSYSTEM_FLADJ(0x20);
  97         writel(linksystem, regs + EXYNOS5_DRD_LINKSYSTEM);
  98
  99         phyparam1 = readl(regs + EXYNOS5_DRD_PHYPARAM1);
 100         /* Set Tx De-Emphasis level */
 101         phyparam1 &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
 102         phyparam1 |= PHYPARAM1_PCS_TXDEEMPH;
 103         writel(phyparam1, regs + EXYNOS5_DRD_PHYPARAM1);
 104
 105         phybatchg = readl(regs + EXYNOS5_DRD_PHYBATCHG);
 106         phybatchg |= PHYBATCHG_UTMI_CLKSEL;
 107         writel(phybatchg, regs + EXYNOS5_DRD_PHYBATCHG);
 108
 109         /* PHYTEST POWERDOWN Control */
 110         phytest = readl(regs + EXYNOS5_DRD_PHYTEST);
 111         phytest &= ~(PHYTEST_POWERDOWN_SSP |
 112                         PHYTEST_POWERDOWN_HSP);
 113         writel(phytest, regs + EXYNOS5_DRD_PHYTEST);
 114
 115         /* UTMI Power Control */
 116         writel(PHYUTMI_OTGDISABLE, regs + EXYNOS5_DRD_PHYUTMI);
 117
 118         phyclkrst = samsung_usb3phy_set_refclk(sphy);
 119
 120         phyclkrst |= PHYCLKRST_PORTRESET |
 121                         /* Digital power supply in normal operating mode */
 122                         PHYCLKRST_RETENABLEN |
 123                         /* Enable ref clock for SS function */
 124                         PHYCLKRST_REF_SSP_EN |
 125                         /* Enable spread spectrum */
 126                         PHYCLKRST_SSC_EN |
 127                         /* Power down HS Bias and PLL blocks in suspend mode */
 128                         PHYCLKRST_COMMONONN;
 129
 130         writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST);
 131
 132         udelay(10);
 133
 134         phyclkrst &= ~(PHYCLKRST_PORTRESET);
 135         writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST);
 136
 137         return 0;
 138 }
 139
 140 static void samsung_exynos5_usb3phy_disable(struct samsung_usbphy *sphy)
 141 {
 142         u32 phyutmi;
 143         u32 phyclkrst;
 144         u32 phytest;
 145         void __iomem *regs = sphy->regs;
 146
 147         phyutmi = PHYUTMI_OTGDISABLE |
 148                         PHYUTMI_FORCESUSPEND |
 149                         PHYUTMI_FORCESLEEP;
 150         writel(phyutmi, regs + EXYNOS5_DRD_PHYUTMI);
 151
 152         /* Resetting the PHYCLKRST enable bits to reduce leakage current */
 153         phyclkrst = readl(regs + EXYNOS5_DRD_PHYCLKRST);
 154         phyclkrst &= ~(PHYCLKRST_REF_SSP_EN |
 155                         PHYCLKRST_SSC_EN |
 156                         PHYCLKRST_COMMONONN);
 157         writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST);
 158
 159         /* Control PHYTEST to remove leakage current */
 160         phytest = readl(regs + EXYNOS5_DRD_PHYTEST);
 161         phytest |= (PHYTEST_POWERDOWN_SSP |
 162                         PHYTEST_POWERDOWN_HSP);
 163         writel(phytest, regs + EXYNOS5_DRD_PHYTEST);
 164 }
 165
 166 static int samsung_usb3phy_init(struct usb_phy *phy)
 167 {
 168         struct samsung_usbphy *sphy;
 169         unsigned long flags;
 170         int ret = 0;
 171
 172         sphy = phy_to_sphy(phy);
 173
 174         /* Enable the phy clock */
 175         ret = clk_prepare_enable(sphy->clk);
 176         if (ret) {
 177                 dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
 178                 return ret;
 179         }
 180
 181         spin_lock_irqsave(&sphy->lock, flags);
 182
 183         /* setting default phy-type for USB 3.0 */
 184         samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
 185
 186         /* Disable phy isolation */
 187         samsung_usbphy_set_isolation(sphy, false);
 188
 189         /* Initialize usb phy registers */
 190         samsung_exynos5_usb3phy_enable(sphy);
 191
 192         spin_unlock_irqrestore(&sphy->lock, flags);
 193
 194         /* Disable the phy clock */
 195         clk_disable_unprepare(sphy->clk);
 196
 197         return ret;
 198 }
 199
 200 /*
 201  * The function passed to the usb driver for phy shutdown
 202  */
 203 static void samsung_usb3phy_shutdown(struct usb_phy *phy)
 204 {
 205         struct samsung_usbphy *sphy;
 206         unsigned long flags;
 207
 208         sphy = phy_to_sphy(phy);
 209
 210         if (clk_prepare_enable(sphy->clk)) {
 211                 dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
 212                 return;
 213         }
 214
 215         spin_lock_irqsave(&sphy->lock, flags);
 216
 217         /* setting default phy-type for USB 3.0 */
 218         samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
 219
 220         /* De-initialize usb phy registers */
 221         samsung_exynos5_usb3phy_disable(sphy);
 222
 223         /* Enable phy isolation */
 224         samsung_usbphy_set_isolation(sphy, true);
 225
 226         spin_unlock_irqrestore(&sphy->lock, flags);
 227
 228         clk_disable_unprepare(sphy->clk);
 229 }
 230
 231 static int samsung_usb3phy_probe(struct platform_device *pdev)
 232 {
 233         struct samsung_usbphy *sphy;
 234         struct samsung_usbphy_data *pdata = pdev->dev.platform_data;
 235         struct device *dev = &pdev->dev;
 236         struct resource *phy_mem;
 237         void __iomem    *phy_base;
 238         struct clk *clk;
 239         int ret;
 240
 241         phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 242         if (!phy_mem) {
 243                 dev_err(dev, "%s: missing mem resource\n", __func__);
 244                 return -ENODEV;
 245         }
 246
 247         phy_base = devm_ioremap_resource(dev, phy_mem);
 248         if (IS_ERR(phy_base))
 249                 return PTR_ERR(phy_base);
 250
 251         sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
 252         if (!sphy)
 253                 return -ENOMEM;
 254
 255         clk = devm_clk_get(dev, "usbdrd30");
 256         if (IS_ERR(clk)) {
 257                 dev_err(dev, "Failed to get device clock\n");
 258                 return PTR_ERR(clk);
 259         }
 260
 261         sphy->dev = dev;
 262
 263         if (dev->of_node) {
 264                 ret = samsung_usbphy_parse_dt(sphy);
 265                 if (ret < 0)
 266                         return ret;
 267         } else {
 268                 if (!pdata) {
 269                         dev_err(dev, "no platform data specified\n");
 270                         return -EINVAL;
 271                 }
 272         }
 273
 274         sphy->plat              = pdata;
 275         sphy->regs              = phy_base;
 276         sphy->clk               = clk;
 277         sphy->phy.dev           = sphy->dev;
 278         sphy->phy.label         = "samsung-usb3phy";
 279         sphy->phy.init          = samsung_usb3phy_init;
 280         sphy->phy.shutdown      = samsung_usb3phy_shutdown;
 281         sphy->drv_data          = samsung_usbphy_get_driver_data(pdev);
 282         sphy->ref_clk_freq      = samsung_usbphy_get_refclk_freq(sphy);
 283
 284         spin_lock_init(&sphy->lock);
 285
 286         platform_set_drvdata(pdev, sphy);
 287
 288         return usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB3);
 289 }
 290
 291 static int samsung_usb3phy_remove(struct platform_device *pdev)
 292 {
 293         struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
 294
 295         usb_remove_phy(&sphy->phy);
 296
 297         if (sphy->pmuregs)
 298                 iounmap(sphy->pmuregs);
 299         if (sphy->sysreg)
 300                 iounmap(sphy->sysreg);
 301
 302         return 0;
 303 }
 304
 305 static struct samsung_usbphy_drvdata usb3phy_exynos5 = {
 306         .cpu_type               = TYPE_EXYNOS5250,
 307         .devphy_en_mask         = EXYNOS_USBPHY_ENABLE,
 308 };
 309
 310 #ifdef CONFIG_OF
 311 static const struct of_device_id samsung_usbphy_dt_match[] = {
 312         {
 313                 .compatible = "samsung,exynos5250-usb3phy",
 314                 .data = &usb3phy_exynos5
 315         },
 316         {},
 317 };
 318 MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
 319 #endif
 320
 321 static struct platform_device_id samsung_usbphy_driver_ids[] = {
 322         {
 323                 .name           = "exynos5250-usb3phy",
 324                 .driver_data    = (unsigned long)&usb3phy_exynos5,
 325         },
 326         {},
 327 };
 328
 329 MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
 330
 331 static struct platform_driver samsung_usb3phy_driver = {
 332         .probe          = samsung_usb3phy_probe,
 333         .remove         = samsung_usb3phy_remove,
 334         .id_table       = samsung_usbphy_driver_ids,
 335         .driver         = {
 336                 .name   = "samsung-usb3phy",
 337                 .owner  = THIS_MODULE,
 338                 .of_match_table = of_match_ptr(samsung_usbphy_dt_match),
 339         },
 340 };
 341
 342 module_platform_driver(samsung_usb3phy_driver);
 343
 344 MODULE_DESCRIPTION("Samsung USB 3.0 phy controller");
 345 MODULE_AUTHOR("Vivek Gautam <gautam.vivek@samsung.com>");
 346 MODULE_LICENSE("GPL");
 347 MODULE_ALIAS("platform:samsung-usb3phy");