drivers/usb/phy/phy-msm-usb.c

   1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15  * 02110-1301, USA.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/slab.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/err.h>
  26 #include <linux/delay.h>
  27 #include <linux/io.h>
  28 #include <linux/ioport.h>
  29 #include <linux/uaccess.h>
  30 #include <linux/debugfs.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include <linux/usb.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/usb/ulpi.h>
  37 #include <linux/usb/gadget.h>
  38 #include <linux/usb/hcd.h>
  39 #include <linux/usb/msm_hsusb.h>
  40 #include <linux/usb/msm_hsusb_hw.h>
  41 #include <linux/regulator/consumer.h>
  42
  43 #define MSM_USB_BASE    (motg->regs)
  44 #define DRIVER_NAME     "msm_otg"
  45
  46 #define ULPI_IO_TIMEOUT_USEC    (10 * 1000)
  47
  48 #define USB_PHY_3P3_VOL_MIN     3050000 /* uV */
  49 #define USB_PHY_3P3_VOL_MAX     3300000 /* uV */
  50 #define USB_PHY_3P3_HPM_LOAD    50000   /* uA */
  51 #define USB_PHY_3P3_LPM_LOAD    4000    /* uA */
  52
  53 #define USB_PHY_1P8_VOL_MIN     1800000 /* uV */
  54 #define USB_PHY_1P8_VOL_MAX     1800000 /* uV */
  55 #define USB_PHY_1P8_HPM_LOAD    50000   /* uA */
  56 #define USB_PHY_1P8_LPM_LOAD    4000    /* uA */
  57
  58 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
  59 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
  60
  61 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
  62 {
  63         int ret = 0;
  64
  65         if (init) {
  66                 ret = regulator_set_voltage(motg->vddcx,
  67                                 USB_PHY_VDD_DIG_VOL_MIN,
  68                                 USB_PHY_VDD_DIG_VOL_MAX);
  69                 if (ret) {
  70                         dev_err(motg->phy.dev, "unable to set the voltage "
  71                                         "for hsusb vddcx\n");
  72                         return ret;
  73                 }
  74
  75                 ret = regulator_enable(motg->vddcx);
  76                 if (ret)
  77                         dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
  78         } else {
  79                 ret = regulator_set_voltage(motg->vddcx, 0,
  80                         USB_PHY_VDD_DIG_VOL_MAX);
  81                 if (ret)
  82                         dev_err(motg->phy.dev, "unable to set the voltage "
  83                                         "for hsusb vddcx\n");
  84                 ret = regulator_disable(motg->vddcx);
  85                 if (ret)
  86                         dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
  87         }
  88
  89         return ret;
  90 }
  91
  92 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
  93 {
  94         int rc = 0;
  95
  96         if (init) {
  97                 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
  98                                 USB_PHY_3P3_VOL_MAX);
  99                 if (rc) {
 100                         dev_err(motg->phy.dev, "unable to set voltage level "
 101                                         "for hsusb 3p3\n");
 102                         goto exit;
 103                 }
 104                 rc = regulator_enable(motg->v3p3);
 105                 if (rc) {
 106                         dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
 107                         goto exit;
 108                 }
 109                 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
 110                                 USB_PHY_1P8_VOL_MAX);
 111                 if (rc) {
 112                         dev_err(motg->phy.dev, "unable to set voltage level "
 113                                         "for hsusb 1p8\n");
 114                         goto disable_3p3;
 115                 }
 116                 rc = regulator_enable(motg->v1p8);
 117                 if (rc) {
 118                         dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
 119                         goto disable_3p3;
 120                 }
 121
 122                 return 0;
 123         }
 124
 125         regulator_disable(motg->v1p8);
 126 disable_3p3:
 127         regulator_disable(motg->v3p3);
 128 exit:
 129         return rc;
 130 }
 131
 132 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
 133 {
 134         int ret = 0;
 135
 136         if (!motg->v1p8 || IS_ERR(motg->v1p8)) {
 137                 pr_err("%s: HSUSB_1p8 is not initialized\n", __func__);
 138                 return -ENODEV;
 139         }
 140
 141         if (!motg->v3p3 || IS_ERR(motg->v3p3)) {
 142                 pr_err("%s: HSUSB_3p3 is not initialized\n", __func__);
 143                 return -ENODEV;
 144         }
 145
 146         if (on) {
 147                 ret = regulator_set_optimum_mode(motg->v1p8,
 148                                 USB_PHY_1P8_HPM_LOAD);
 149                 if (ret < 0) {
 150                         pr_err("%s: Unable to set HPM of the regulator "
 151                                 "HSUSB_1p8\n", __func__);
 152                         return ret;
 153                 }
 154                 ret = regulator_set_optimum_mode(motg->v3p3,
 155                                 USB_PHY_3P3_HPM_LOAD);
 156                 if (ret < 0) {
 157                         pr_err("%s: Unable to set HPM of the regulator "
 158                                 "HSUSB_3p3\n", __func__);
 159                         regulator_set_optimum_mode(motg->v1p8,
 160                                 USB_PHY_1P8_LPM_LOAD);
 161                         return ret;
 162                 }
 163         } else {
 164                 ret = regulator_set_optimum_mode(motg->v1p8,
 165                                 USB_PHY_1P8_LPM_LOAD);
 166                 if (ret < 0)
 167                         pr_err("%s: Unable to set LPM of the regulator "
 168                                 "HSUSB_1p8\n", __func__);
 169                 ret = regulator_set_optimum_mode(motg->v3p3,
 170                                 USB_PHY_3P3_LPM_LOAD);
 171                 if (ret < 0)
 172                         pr_err("%s: Unable to set LPM of the regulator "
 173                                 "HSUSB_3p3\n", __func__);
 174         }
 175
 176         pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
 177         return ret < 0 ? ret : 0;
 178 }
 179
 180 static int ulpi_read(struct usb_phy *phy, u32 reg)
 181 {
 182         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 183         int cnt = 0;
 184
 185         /* initiate read operation */
 186         writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
 187                USB_ULPI_VIEWPORT);
 188
 189         /* wait for completion */
 190         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 191                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 192                         break;
 193                 udelay(1);
 194                 cnt++;
 195         }
 196
 197         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 198                 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
 199                         readl(USB_ULPI_VIEWPORT));
 200                 return -ETIMEDOUT;
 201         }
 202         return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
 203 }
 204
 205 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
 206 {
 207         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 208         int cnt = 0;
 209
 210         /* initiate write operation */
 211         writel(ULPI_RUN | ULPI_WRITE |
 212                ULPI_ADDR(reg) | ULPI_DATA(val),
 213                USB_ULPI_VIEWPORT);
 214
 215         /* wait for completion */
 216         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 217                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 218                         break;
 219                 udelay(1);
 220                 cnt++;
 221         }
 222
 223         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 224                 dev_err(phy->dev, "ulpi_write: timeout\n");
 225                 return -ETIMEDOUT;
 226         }
 227         return 0;
 228 }
 229
 230 static struct usb_phy_io_ops msm_otg_io_ops = {
 231         .read = ulpi_read,
 232         .write = ulpi_write,
 233 };
 234
 235 static void ulpi_init(struct msm_otg *motg)
 236 {
 237         struct msm_otg_platform_data *pdata = motg->pdata;
 238         int *seq = pdata->phy_init_seq;
 239
 240         if (!seq)
 241                 return;
 242
 243         while (seq[0] >= 0) {
 244                 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
 245                                 seq[0], seq[1]);
 246                 ulpi_write(&motg->phy, seq[0], seq[1]);
 247                 seq += 2;
 248         }
 249 }
 250
 251 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
 252 {
 253         int ret = 0;
 254
 255         if (!motg->pdata->link_clk_reset)
 256                 return ret;
 257
 258         ret = motg->pdata->link_clk_reset(motg->clk, assert);
 259         if (ret)
 260                 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
 261                         assert ? "assert" : "deassert");
 262
 263         return ret;
 264 }
 265
 266 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
 267 {
 268         int ret = 0;
 269
 270         if (!motg->pdata->phy_clk_reset)
 271                 return ret;
 272
 273         ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk);
 274         if (ret)
 275                 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
 276
 277         return ret;
 278 }
 279
 280 static int msm_otg_phy_reset(struct msm_otg *motg)
 281 {
 282         u32 val;
 283         int ret;
 284         int retries;
 285
 286         ret = msm_otg_link_clk_reset(motg, 1);
 287         if (ret)
 288                 return ret;
 289         ret = msm_otg_phy_clk_reset(motg);
 290         if (ret)
 291                 return ret;
 292         ret = msm_otg_link_clk_reset(motg, 0);
 293         if (ret)
 294                 return ret;
 295
 296         val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
 297         writel(val | PORTSC_PTS_ULPI, USB_PORTSC);
 298
 299         for (retries = 3; retries > 0; retries--) {
 300                 ret = ulpi_write(&motg->phy, ULPI_FUNC_CTRL_SUSPENDM,
 301                                 ULPI_CLR(ULPI_FUNC_CTRL));
 302                 if (!ret)
 303                         break;
 304                 ret = msm_otg_phy_clk_reset(motg);
 305                 if (ret)
 306                         return ret;
 307         }
 308         if (!retries)
 309                 return -ETIMEDOUT;
 310
 311         /* This reset calibrates the phy, if the above write succeeded */
 312         ret = msm_otg_phy_clk_reset(motg);
 313         if (ret)
 314                 return ret;
 315
 316         for (retries = 3; retries > 0; retries--) {
 317                 ret = ulpi_read(&motg->phy, ULPI_DEBUG);
 318                 if (ret != -ETIMEDOUT)
 319                         break;
 320                 ret = msm_otg_phy_clk_reset(motg);
 321                 if (ret)
 322                         return ret;
 323         }
 324         if (!retries)
 325                 return -ETIMEDOUT;
 326
 327         dev_info(motg->phy.dev, "phy_reset: success\n");
 328         return 0;
 329 }
 330
 331 #define LINK_RESET_TIMEOUT_USEC         (250 * 1000)
 332 static int msm_otg_reset(struct usb_phy *phy)
 333 {
 334         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 335         struct msm_otg_platform_data *pdata = motg->pdata;
 336         int cnt = 0;
 337         int ret;
 338         u32 val = 0;
 339         u32 ulpi_val = 0;
 340
 341         ret = msm_otg_phy_reset(motg);
 342         if (ret) {
 343                 dev_err(phy->dev, "phy_reset failed\n");
 344                 return ret;
 345         }
 346
 347         ulpi_init(motg);
 348
 349         writel(USBCMD_RESET, USB_USBCMD);
 350         while (cnt < LINK_RESET_TIMEOUT_USEC) {
 351                 if (!(readl(USB_USBCMD) & USBCMD_RESET))
 352                         break;
 353                 udelay(1);
 354                 cnt++;
 355         }
 356         if (cnt >= LINK_RESET_TIMEOUT_USEC)
 357                 return -ETIMEDOUT;
 358
 359         /* select ULPI phy */
 360         writel(0x80000000, USB_PORTSC);
 361
 362         msleep(100);
 363
 364         writel(0x0, USB_AHBBURST);
 365         writel(0x00, USB_AHBMODE);
 366
 367         if (pdata->otg_control == OTG_PHY_CONTROL) {
 368                 val = readl(USB_OTGSC);
 369                 if (pdata->mode == USB_OTG) {
 370                         ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
 371                         val |= OTGSC_IDIE | OTGSC_BSVIE;
 372                 } else if (pdata->mode == USB_PERIPHERAL) {
 373                         ulpi_val = ULPI_INT_SESS_VALID;
 374                         val |= OTGSC_BSVIE;
 375                 }
 376                 writel(val, USB_OTGSC);
 377                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
 378                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
 379         }
 380
 381         return 0;
 382 }
 383
 384 #define PHY_SUSPEND_TIMEOUT_USEC        (500 * 1000)
 385 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
 386
 387 #ifdef CONFIG_PM
 388
 389 #define USB_PHY_SUSP_DIG_VOL  500000
 390 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
 391 {
 392         int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
 393         int min_vol;
 394         int ret;
 395
 396         if (high)
 397                 min_vol = USB_PHY_VDD_DIG_VOL_MIN;
 398         else
 399                 min_vol = USB_PHY_SUSP_DIG_VOL;
 400
 401         ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
 402         if (ret) {
 403                 pr_err("%s: unable to set the voltage for regulator "
 404                         "HSUSB_VDDCX\n", __func__);
 405                 return ret;
 406         }
 407
 408         pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
 409
 410         return ret;
 411 }
 412
 413 static int msm_otg_suspend(struct msm_otg *motg)
 414 {
 415         struct usb_phy *phy = &motg->phy;
 416         struct usb_bus *bus = phy->otg->host;
 417         struct msm_otg_platform_data *pdata = motg->pdata;
 418         int cnt = 0;
 419
 420         if (atomic_read(&motg->in_lpm))
 421                 return 0;
 422
 423         disable_irq(motg->irq);
 424         /*
 425          * Chipidea 45-nm PHY suspend sequence:
 426          *
 427          * Interrupt Latch Register auto-clear feature is not present
 428          * in all PHY versions. Latch register is clear on read type.
 429          * Clear latch register to avoid spurious wakeup from
 430          * low power mode (LPM).
 431          *
 432          * PHY comparators are disabled when PHY enters into low power
 433          * mode (LPM). Keep PHY comparators ON in LPM only when we expect
 434          * VBUS/Id notifications from USB PHY. Otherwise turn off USB
 435          * PHY comparators. This save significant amount of power.
 436          *
 437          * PLL is not turned off when PHY enters into low power mode (LPM).
 438          * Disable PLL for maximum power savings.
 439          */
 440
 441         if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
 442                 ulpi_read(phy, 0x14);
 443                 if (pdata->otg_control == OTG_PHY_CONTROL)
 444                         ulpi_write(phy, 0x01, 0x30);
 445                 ulpi_write(phy, 0x08, 0x09);
 446         }
 447
 448         /*
 449          * PHY may take some time or even fail to enter into low power
 450          * mode (LPM). Hence poll for 500 msec and reset the PHY and link
 451          * in failure case.
 452          */
 453         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
 454         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
 455                 if (readl(USB_PORTSC) & PORTSC_PHCD)
 456                         break;
 457                 udelay(1);
 458                 cnt++;
 459         }
 460
 461         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
 462                 dev_err(phy->dev, "Unable to suspend PHY\n");
 463                 msm_otg_reset(phy);
 464                 enable_irq(motg->irq);
 465                 return -ETIMEDOUT;
 466         }
 467
 468         /*
 469          * PHY has capability to generate interrupt asynchronously in low
 470          * power mode (LPM). This interrupt is level triggered. So USB IRQ
 471          * line must be disabled till async interrupt enable bit is cleared
 472          * in USBCMD register. Assert STP (ULPI interface STOP signal) to
 473          * block data communication from PHY.
 474          */
 475         writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
 476
 477         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 478                         motg->pdata->otg_control == OTG_PMIC_CONTROL)
 479                 writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
 480
 481         clk_disable_unprepare(motg->pclk);
 482         clk_disable_unprepare(motg->clk);
 483         if (!IS_ERR(motg->core_clk))
 484                 clk_disable_unprepare(motg->core_clk);
 485
 486         if (!IS_ERR(motg->pclk_src))
 487                 clk_disable_unprepare(motg->pclk_src);
 488
 489         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 490                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 491                 msm_hsusb_ldo_set_mode(motg, 0);
 492                 msm_hsusb_config_vddcx(motg, 0);
 493         }
 494
 495         if (device_may_wakeup(phy->dev))
 496                 enable_irq_wake(motg->irq);
 497         if (bus)
 498                 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 499
 500         atomic_set(&motg->in_lpm, 1);
 501         enable_irq(motg->irq);
 502
 503         dev_info(phy->dev, "USB in low power mode\n");
 504
 505         return 0;
 506 }
 507
 508 static int msm_otg_resume(struct msm_otg *motg)
 509 {
 510         struct usb_phy *phy = &motg->phy;
 511         struct usb_bus *bus = phy->otg->host;
 512         int cnt = 0;
 513         unsigned temp;
 514
 515         if (!atomic_read(&motg->in_lpm))
 516                 return 0;
 517
 518         if (!IS_ERR(motg->pclk_src))
 519                 clk_prepare_enable(motg->pclk_src);
 520
 521         clk_prepare_enable(motg->pclk);
 522         clk_prepare_enable(motg->clk);
 523         if (!IS_ERR(motg->core_clk))
 524                 clk_prepare_enable(motg->core_clk);
 525
 526         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 527                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 528                 msm_hsusb_ldo_set_mode(motg, 1);
 529                 msm_hsusb_config_vddcx(motg, 1);
 530                 writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL);
 531         }
 532
 533         temp = readl(USB_USBCMD);
 534         temp &= ~ASYNC_INTR_CTRL;
 535         temp &= ~ULPI_STP_CTRL;
 536         writel(temp, USB_USBCMD);
 537
 538         /*
 539          * PHY comes out of low power mode (LPM) in case of wakeup
 540          * from asynchronous interrupt.
 541          */
 542         if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 543                 goto skip_phy_resume;
 544
 545         writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
 546         while (cnt < PHY_RESUME_TIMEOUT_USEC) {
 547                 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 548                         break;
 549                 udelay(1);
 550                 cnt++;
 551         }
 552
 553         if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
 554                 /*
 555                  * This is a fatal error. Reset the link and
 556                  * PHY. USB state can not be restored. Re-insertion
 557                  * of USB cable is the only way to get USB working.
 558                  */
 559                 dev_err(phy->dev, "Unable to resume USB."
 560                                 "Re-plugin the cable\n");
 561                 msm_otg_reset(phy);
 562         }
 563
 564 skip_phy_resume:
 565         if (device_may_wakeup(phy->dev))
 566                 disable_irq_wake(motg->irq);
 567         if (bus)
 568                 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 569
 570         atomic_set(&motg->in_lpm, 0);
 571
 572         if (motg->async_int) {
 573                 motg->async_int = 0;
 574                 pm_runtime_put(phy->dev);
 575                 enable_irq(motg->irq);
 576         }
 577
 578         dev_info(phy->dev, "USB exited from low power mode\n");
 579
 580         return 0;
 581 }
 582 #endif
 583
 584 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
 585 {
 586         if (motg->cur_power == mA)
 587                 return;
 588
 589         /* TODO: Notify PMIC about available current */
 590         dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
 591         motg->cur_power = mA;
 592 }
 593
 594 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
 595 {
 596         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 597
 598         /*
 599          * Gadget driver uses set_power method to notify about the
 600          * available current based on suspend/configured states.
 601          *
 602          * IDEV_CHG can be drawn irrespective of suspend/un-configured
 603          * states when CDP/ACA is connected.
 604          */
 605         if (motg->chg_type == USB_SDP_CHARGER)
 606                 msm_otg_notify_charger(motg, mA);
 607
 608         return 0;
 609 }
 610
 611 static void msm_otg_start_host(struct usb_phy *phy, int on)
 612 {
 613         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 614         struct msm_otg_platform_data *pdata = motg->pdata;
 615         struct usb_hcd *hcd;
 616
 617         if (!phy->otg->host)
 618                 return;
 619
 620         hcd = bus_to_hcd(phy->otg->host);
 621
 622         if (on) {
 623                 dev_dbg(phy->dev, "host on\n");
 624
 625                 if (pdata->vbus_power)
 626                         pdata->vbus_power(1);
 627                 /*
 628                  * Some boards have a switch cotrolled by gpio
 629                  * to enable/disable internal HUB. Enable internal
 630                  * HUB before kicking the host.
 631                  */
 632                 if (pdata->setup_gpio)
 633                         pdata->setup_gpio(OTG_STATE_A_HOST);
 634 #ifdef CONFIG_USB
 635                 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 636                 device_wakeup_enable(hcd->self.controller);
 637 #endif
 638         } else {
 639                 dev_dbg(phy->dev, "host off\n");
 640
 641 #ifdef CONFIG_USB
 642                 usb_remove_hcd(hcd);
 643 #endif
 644                 if (pdata->setup_gpio)
 645                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 646                 if (pdata->vbus_power)
 647                         pdata->vbus_power(0);
 648         }
 649 }
 650
 651 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
 652 {
 653         struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
 654         struct usb_hcd *hcd;
 655
 656         /*
 657          * Fail host registration if this board can support
 658          * only peripheral configuration.
 659          */
 660         if (motg->pdata->mode == USB_PERIPHERAL) {
 661                 dev_info(otg->phy->dev, "Host mode is not supported\n");
 662                 return -ENODEV;
 663         }
 664
 665         if (!host) {
 666                 if (otg->phy->state == OTG_STATE_A_HOST) {
 667                         pm_runtime_get_sync(otg->phy->dev);
 668                         msm_otg_start_host(otg->phy, 0);
 669                         otg->host = NULL;
 670                         otg->phy->state = OTG_STATE_UNDEFINED;
 671                         schedule_work(&motg->sm_work);
 672                 } else {
 673                         otg->host = NULL;
 674                 }
 675
 676                 return 0;
 677         }
 678
 679         hcd = bus_to_hcd(host);
 680         hcd->power_budget = motg->pdata->power_budget;
 681
 682         otg->host = host;
 683         dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n");
 684
 685         /*
 686          * Kick the state machine work, if peripheral is not supported
 687          * or peripheral is already registered with us.
 688          */
 689         if (motg->pdata->mode == USB_HOST || otg->gadget) {
 690                 pm_runtime_get_sync(otg->phy->dev);
 691                 schedule_work(&motg->sm_work);
 692         }
 693
 694         return 0;
 695 }
 696
 697 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
 698 {
 699         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 700         struct msm_otg_platform_data *pdata = motg->pdata;
 701
 702         if (!phy->otg->gadget)
 703                 return;
 704
 705         if (on) {
 706                 dev_dbg(phy->dev, "gadget on\n");
 707                 /*
 708                  * Some boards have a switch cotrolled by gpio
 709                  * to enable/disable internal HUB. Disable internal
 710                  * HUB before kicking the gadget.
 711                  */
 712                 if (pdata->setup_gpio)
 713                         pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
 714                 usb_gadget_vbus_connect(phy->otg->gadget);
 715         } else {
 716                 dev_dbg(phy->dev, "gadget off\n");
 717                 usb_gadget_vbus_disconnect(phy->otg->gadget);
 718                 if (pdata->setup_gpio)
 719                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 720         }
 721
 722 }
 723
 724 static int msm_otg_set_peripheral(struct usb_otg *otg,
 725                                         struct usb_gadget *gadget)
 726 {
 727         struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
 728
 729         /*
 730          * Fail peripheral registration if this board can support
 731          * only host configuration.
 732          */
 733         if (motg->pdata->mode == USB_HOST) {
 734                 dev_info(otg->phy->dev, "Peripheral mode is not supported\n");
 735                 return -ENODEV;
 736         }
 737
 738         if (!gadget) {
 739                 if (otg->phy->state == OTG_STATE_B_PERIPHERAL) {
 740                         pm_runtime_get_sync(otg->phy->dev);
 741                         msm_otg_start_peripheral(otg->phy, 0);
 742                         otg->gadget = NULL;
 743                         otg->phy->state = OTG_STATE_UNDEFINED;
 744                         schedule_work(&motg->sm_work);
 745                 } else {
 746                         otg->gadget = NULL;
 747                 }
 748
 749                 return 0;
 750         }
 751         otg->gadget = gadget;
 752         dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n");
 753
 754         /*
 755          * Kick the state machine work, if host is not supported
 756          * or host is already registered with us.
 757          */
 758         if (motg->pdata->mode == USB_PERIPHERAL || otg->host) {
 759                 pm_runtime_get_sync(otg->phy->dev);
 760                 schedule_work(&motg->sm_work);
 761         }
 762
 763         return 0;
 764 }
 765
 766 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
 767 {
 768         struct usb_phy *phy = &motg->phy;
 769         u32 chg_det;
 770         bool ret = false;
 771
 772         switch (motg->pdata->phy_type) {
 773         case CI_45NM_INTEGRATED_PHY:
 774                 chg_det = ulpi_read(phy, 0x34);
 775                 ret = chg_det & (1 << 4);
 776                 break;
 777         case SNPS_28NM_INTEGRATED_PHY:
 778                 chg_det = ulpi_read(phy, 0x87);
 779                 ret = chg_det & 1;
 780                 break;
 781         default:
 782                 break;
 783         }
 784         return ret;
 785 }
 786
 787 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
 788 {
 789         struct usb_phy *phy = &motg->phy;
 790         u32 chg_det;
 791
 792         switch (motg->pdata->phy_type) {
 793         case CI_45NM_INTEGRATED_PHY:
 794                 chg_det = ulpi_read(phy, 0x34);
 795                 /* Turn off charger block */
 796                 chg_det |= ~(1 << 1);
 797                 ulpi_write(phy, chg_det, 0x34);
 798                 udelay(20);
 799                 /* control chg block via ULPI */
 800                 chg_det &= ~(1 << 3);
 801                 ulpi_write(phy, chg_det, 0x34);
 802                 /* put it in host mode for enabling D- source */
 803                 chg_det &= ~(1 << 2);
 804                 ulpi_write(phy, chg_det, 0x34);
 805                 /* Turn on chg detect block */
 806                 chg_det &= ~(1 << 1);
 807                 ulpi_write(phy, chg_det, 0x34);
 808                 udelay(20);
 809                 /* enable chg detection */
 810                 chg_det &= ~(1 << 0);
 811                 ulpi_write(phy, chg_det, 0x34);
 812                 break;
 813         case SNPS_28NM_INTEGRATED_PHY:
 814                 /*
 815                  * Configure DM as current source, DP as current sink
 816                  * and enable battery charging comparators.
 817                  */
 818                 ulpi_write(phy, 0x8, 0x85);
 819                 ulpi_write(phy, 0x2, 0x85);
 820                 ulpi_write(phy, 0x1, 0x85);
 821                 break;
 822         default:
 823                 break;
 824         }
 825 }
 826
 827 static bool msm_chg_check_primary_det(struct msm_otg *motg)
 828 {
 829         struct usb_phy *phy = &motg->phy;
 830         u32 chg_det;
 831         bool ret = false;
 832
 833         switch (motg->pdata->phy_type) {
 834         case CI_45NM_INTEGRATED_PHY:
 835                 chg_det = ulpi_read(phy, 0x34);
 836                 ret = chg_det & (1 << 4);
 837                 break;
 838         case SNPS_28NM_INTEGRATED_PHY:
 839                 chg_det = ulpi_read(phy, 0x87);
 840                 ret = chg_det & 1;
 841                 break;
 842         default:
 843                 break;
 844         }
 845         return ret;
 846 }
 847
 848 static void msm_chg_enable_primary_det(struct msm_otg *motg)
 849 {
 850         struct usb_phy *phy = &motg->phy;
 851         u32 chg_det;
 852
 853         switch (motg->pdata->phy_type) {
 854         case CI_45NM_INTEGRATED_PHY:
 855                 chg_det = ulpi_read(phy, 0x34);
 856                 /* enable chg detection */
 857                 chg_det &= ~(1 << 0);
 858                 ulpi_write(phy, chg_det, 0x34);
 859                 break;
 860         case SNPS_28NM_INTEGRATED_PHY:
 861                 /*
 862                  * Configure DP as current source, DM as current sink
 863                  * and enable battery charging comparators.
 864                  */
 865                 ulpi_write(phy, 0x2, 0x85);
 866                 ulpi_write(phy, 0x1, 0x85);
 867                 break;
 868         default:
 869                 break;
 870         }
 871 }
 872
 873 static bool msm_chg_check_dcd(struct msm_otg *motg)
 874 {
 875         struct usb_phy *phy = &motg->phy;
 876         u32 line_state;
 877         bool ret = false;
 878
 879         switch (motg->pdata->phy_type) {
 880         case CI_45NM_INTEGRATED_PHY:
 881                 line_state = ulpi_read(phy, 0x15);
 882                 ret = !(line_state & 1);
 883                 break;
 884         case SNPS_28NM_INTEGRATED_PHY:
 885                 line_state = ulpi_read(phy, 0x87);
 886                 ret = line_state & 2;
 887                 break;
 888         default:
 889                 break;
 890         }
 891         return ret;
 892 }
 893
 894 static void msm_chg_disable_dcd(struct msm_otg *motg)
 895 {
 896         struct usb_phy *phy = &motg->phy;
 897         u32 chg_det;
 898
 899         switch (motg->pdata->phy_type) {
 900         case CI_45NM_INTEGRATED_PHY:
 901                 chg_det = ulpi_read(phy, 0x34);
 902                 chg_det &= ~(1 << 5);
 903                 ulpi_write(phy, chg_det, 0x34);
 904                 break;
 905         case SNPS_28NM_INTEGRATED_PHY:
 906                 ulpi_write(phy, 0x10, 0x86);
 907                 break;
 908         default:
 909                 break;
 910         }
 911 }
 912
 913 static void msm_chg_enable_dcd(struct msm_otg *motg)
 914 {
 915         struct usb_phy *phy = &motg->phy;
 916         u32 chg_det;
 917
 918         switch (motg->pdata->phy_type) {
 919         case CI_45NM_INTEGRATED_PHY:
 920                 chg_det = ulpi_read(phy, 0x34);
 921                 /* Turn on D+ current source */
 922                 chg_det |= (1 << 5);
 923                 ulpi_write(phy, chg_det, 0x34);
 924                 break;
 925         case SNPS_28NM_INTEGRATED_PHY:
 926                 /* Data contact detection enable */
 927                 ulpi_write(phy, 0x10, 0x85);
 928                 break;
 929         default:
 930                 break;
 931         }
 932 }
 933
 934 static void msm_chg_block_on(struct msm_otg *motg)
 935 {
 936         struct usb_phy *phy = &motg->phy;
 937         u32 func_ctrl, chg_det;
 938
 939         /* put the controller in non-driving mode */
 940         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
 941         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 942         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
 943         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
 944
 945         switch (motg->pdata->phy_type) {
 946         case CI_45NM_INTEGRATED_PHY:
 947                 chg_det = ulpi_read(phy, 0x34);
 948                 /* control chg block via ULPI */
 949                 chg_det &= ~(1 << 3);
 950                 ulpi_write(phy, chg_det, 0x34);
 951                 /* Turn on chg detect block */
 952                 chg_det &= ~(1 << 1);
 953                 ulpi_write(phy, chg_det, 0x34);
 954                 udelay(20);
 955                 break;
 956         case SNPS_28NM_INTEGRATED_PHY:
 957                 /* Clear charger detecting control bits */
 958                 ulpi_write(phy, 0x3F, 0x86);
 959                 /* Clear alt interrupt latch and enable bits */
 960                 ulpi_write(phy, 0x1F, 0x92);
 961                 ulpi_write(phy, 0x1F, 0x95);
 962                 udelay(100);
 963                 break;
 964         default:
 965                 break;
 966         }
 967 }
 968
 969 static void msm_chg_block_off(struct msm_otg *motg)
 970 {
 971         struct usb_phy *phy = &motg->phy;
 972         u32 func_ctrl, chg_det;
 973
 974         switch (motg->pdata->phy_type) {
 975         case CI_45NM_INTEGRATED_PHY:
 976                 chg_det = ulpi_read(phy, 0x34);
 977                 /* Turn off charger block */
 978                 chg_det |= ~(1 << 1);
 979                 ulpi_write(phy, chg_det, 0x34);
 980                 break;
 981         case SNPS_28NM_INTEGRATED_PHY:
 982                 /* Clear charger detecting control bits */
 983                 ulpi_write(phy, 0x3F, 0x86);
 984                 /* Clear alt interrupt latch and enable bits */
 985                 ulpi_write(phy, 0x1F, 0x92);
 986                 ulpi_write(phy, 0x1F, 0x95);
 987                 break;
 988         default:
 989                 break;
 990         }
 991
 992         /* put the controller in normal mode */
 993         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
 994         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 995         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
 996         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
 997 }
 998
 999 #define MSM_CHG_DCD_POLL_TIME           (100 * HZ/1000) /* 100 msec */
1000 #define MSM_CHG_DCD_MAX_RETRIES         6 /* Tdcd_tmout = 6 * 100 msec */
1001 #define MSM_CHG_PRIMARY_DET_TIME        (40 * HZ/1000) /* TVDPSRC_ON */
1002 #define MSM_CHG_SECONDARY_DET_TIME      (40 * HZ/1000) /* TVDMSRC_ON */
1003 static void msm_chg_detect_work(struct work_struct *w)
1004 {
1005         struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1006         struct usb_phy *phy = &motg->phy;
1007         bool is_dcd, tmout, vout;
1008         unsigned long delay;
1009
1010         dev_dbg(phy->dev, "chg detection work\n");
1011         switch (motg->chg_state) {
1012         case USB_CHG_STATE_UNDEFINED:
1013                 pm_runtime_get_sync(phy->dev);
1014                 msm_chg_block_on(motg);
1015                 msm_chg_enable_dcd(motg);
1016                 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1017                 motg->dcd_retries = 0;
1018                 delay = MSM_CHG_DCD_POLL_TIME;
1019                 break;
1020         case USB_CHG_STATE_WAIT_FOR_DCD:
1021                 is_dcd = msm_chg_check_dcd(motg);
1022                 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1023                 if (is_dcd || tmout) {
1024                         msm_chg_disable_dcd(motg);
1025                         msm_chg_enable_primary_det(motg);
1026                         delay = MSM_CHG_PRIMARY_DET_TIME;
1027                         motg->chg_state = USB_CHG_STATE_DCD_DONE;
1028                 } else {
1029                         delay = MSM_CHG_DCD_POLL_TIME;
1030                 }
1031                 break;
1032         case USB_CHG_STATE_DCD_DONE:
1033                 vout = msm_chg_check_primary_det(motg);
1034                 if (vout) {
1035                         msm_chg_enable_secondary_det(motg);
1036                         delay = MSM_CHG_SECONDARY_DET_TIME;
1037                         motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1038                 } else {
1039                         motg->chg_type = USB_SDP_CHARGER;
1040                         motg->chg_state = USB_CHG_STATE_DETECTED;
1041                         delay = 0;
1042                 }
1043                 break;
1044         case USB_CHG_STATE_PRIMARY_DONE:
1045                 vout = msm_chg_check_secondary_det(motg);
1046                 if (vout)
1047                         motg->chg_type = USB_DCP_CHARGER;
1048                 else
1049                         motg->chg_type = USB_CDP_CHARGER;
1050                 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1051                 /* fall through */
1052         case USB_CHG_STATE_SECONDARY_DONE:
1053                 motg->chg_state = USB_CHG_STATE_DETECTED;
1054         case USB_CHG_STATE_DETECTED:
1055                 msm_chg_block_off(motg);
1056                 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1057                 schedule_work(&motg->sm_work);
1058                 return;
1059         default:
1060                 return;
1061         }
1062
1063         schedule_delayed_work(&motg->chg_work, delay);
1064 }
1065
1066 /*
1067  * We support OTG, Peripheral only and Host only configurations. In case
1068  * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1069  * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1070  * enabled when switch is controlled by user and default mode is supplied
1071  * by board file, which can be changed by userspace later.
1072  */
1073 static void msm_otg_init_sm(struct msm_otg *motg)
1074 {
1075         struct msm_otg_platform_data *pdata = motg->pdata;
1076         u32 otgsc = readl(USB_OTGSC);
1077
1078         switch (pdata->mode) {
1079         case USB_OTG:
1080                 if (pdata->otg_control == OTG_PHY_CONTROL) {
1081                         if (otgsc & OTGSC_ID)
1082                                 set_bit(ID, &motg->inputs);
1083                         else
1084                                 clear_bit(ID, &motg->inputs);
1085
1086                         if (otgsc & OTGSC_BSV)
1087                                 set_bit(B_SESS_VLD, &motg->inputs);
1088                         else
1089                                 clear_bit(B_SESS_VLD, &motg->inputs);
1090                 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1091                         if (pdata->default_mode == USB_HOST) {
1092                                 clear_bit(ID, &motg->inputs);
1093                         } else if (pdata->default_mode == USB_PERIPHERAL) {
1094                                 set_bit(ID, &motg->inputs);
1095                                 set_bit(B_SESS_VLD, &motg->inputs);
1096                         } else {
1097                                 set_bit(ID, &motg->inputs);
1098                                 clear_bit(B_SESS_VLD, &motg->inputs);
1099                         }
1100                 }
1101                 break;
1102         case USB_HOST:
1103                 clear_bit(ID, &motg->inputs);
1104                 break;
1105         case USB_PERIPHERAL:
1106                 set_bit(ID, &motg->inputs);
1107                 if (otgsc & OTGSC_BSV)
1108                         set_bit(B_SESS_VLD, &motg->inputs);
1109                 else
1110                         clear_bit(B_SESS_VLD, &motg->inputs);
1111                 break;
1112         default:
1113                 break;
1114         }
1115 }
1116
1117 static void msm_otg_sm_work(struct work_struct *w)
1118 {
1119         struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1120         struct usb_otg *otg = motg->phy.otg;
1121
1122         switch (otg->phy->state) {
1123         case OTG_STATE_UNDEFINED:
1124                 dev_dbg(otg->phy->dev, "OTG_STATE_UNDEFINED state\n");
1125                 msm_otg_reset(otg->phy);
1126                 msm_otg_init_sm(motg);
1127                 otg->phy->state = OTG_STATE_B_IDLE;
1128                 /* FALL THROUGH */
1129         case OTG_STATE_B_IDLE:
1130                 dev_dbg(otg->phy->dev, "OTG_STATE_B_IDLE state\n");
1131                 if (!test_bit(ID, &motg->inputs) && otg->host) {
1132                         /* disable BSV bit */
1133                         writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1134                         msm_otg_start_host(otg->phy, 1);
1135                         otg->phy->state = OTG_STATE_A_HOST;
1136                 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1137                         switch (motg->chg_state) {
1138                         case USB_CHG_STATE_UNDEFINED:
1139                                 msm_chg_detect_work(&motg->chg_work.work);
1140                                 break;
1141                         case USB_CHG_STATE_DETECTED:
1142                                 switch (motg->chg_type) {
1143                                 case USB_DCP_CHARGER:
1144                                         msm_otg_notify_charger(motg,
1145                                                         IDEV_CHG_MAX);
1146                                         break;
1147                                 case USB_CDP_CHARGER:
1148                                         msm_otg_notify_charger(motg,
1149                                                         IDEV_CHG_MAX);
1150                                         msm_otg_start_peripheral(otg->phy, 1);
1151                                         otg->phy->state
1152                                                 = OTG_STATE_B_PERIPHERAL;
1153                                         break;
1154                                 case USB_SDP_CHARGER:
1155                                         msm_otg_notify_charger(motg, IUNIT);
1156                                         msm_otg_start_peripheral(otg->phy, 1);
1157                                         otg->phy->state
1158                                                 = OTG_STATE_B_PERIPHERAL;
1159                                         break;
1160                                 default:
1161                                         break;
1162                                 }
1163                                 break;
1164                         default:
1165                                 break;
1166                         }
1167                 } else {
1168                         /*
1169                          * If charger detection work is pending, decrement
1170                          * the pm usage counter to balance with the one that
1171                          * is incremented in charger detection work.
1172                          */
1173                         if (cancel_delayed_work_sync(&motg->chg_work)) {
1174                                 pm_runtime_put_sync(otg->phy->dev);
1175                                 msm_otg_reset(otg->phy);
1176                         }
1177                         msm_otg_notify_charger(motg, 0);
1178                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1179                         motg->chg_type = USB_INVALID_CHARGER;
1180                 }
1181                 pm_runtime_put_sync(otg->phy->dev);
1182                 break;
1183         case OTG_STATE_B_PERIPHERAL:
1184                 dev_dbg(otg->phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1185                 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1186                                 !test_bit(ID, &motg->inputs)) {
1187                         msm_otg_notify_charger(motg, 0);
1188                         msm_otg_start_peripheral(otg->phy, 0);
1189                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1190                         motg->chg_type = USB_INVALID_CHARGER;
1191                         otg->phy->state = OTG_STATE_B_IDLE;
1192                         msm_otg_reset(otg->phy);
1193                         schedule_work(w);
1194                 }
1195                 break;
1196         case OTG_STATE_A_HOST:
1197                 dev_dbg(otg->phy->dev, "OTG_STATE_A_HOST state\n");
1198                 if (test_bit(ID, &motg->inputs)) {
1199                         msm_otg_start_host(otg->phy, 0);
1200                         otg->phy->state = OTG_STATE_B_IDLE;
1201                         msm_otg_reset(otg->phy);
1202                         schedule_work(w);
1203                 }
1204                 break;
1205         default:
1206                 break;
1207         }
1208 }
1209
1210 static irqreturn_t msm_otg_irq(int irq, void *data)
1211 {
1212         struct msm_otg *motg = data;
1213         struct usb_phy *phy = &motg->phy;
1214         u32 otgsc = 0;
1215
1216         if (atomic_read(&motg->in_lpm)) {
1217                 disable_irq_nosync(irq);
1218                 motg->async_int = 1;
1219                 pm_runtime_get(phy->dev);
1220                 return IRQ_HANDLED;
1221         }
1222
1223         otgsc = readl(USB_OTGSC);
1224         if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1225                 return IRQ_NONE;
1226
1227         if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1228                 if (otgsc & OTGSC_ID)
1229                         set_bit(ID, &motg->inputs);
1230                 else
1231                         clear_bit(ID, &motg->inputs);
1232                 dev_dbg(phy->dev, "ID set/clear\n");
1233                 pm_runtime_get_noresume(phy->dev);
1234         } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1235                 if (otgsc & OTGSC_BSV)
1236                         set_bit(B_SESS_VLD, &motg->inputs);
1237                 else
1238                         clear_bit(B_SESS_VLD, &motg->inputs);
1239                 dev_dbg(phy->dev, "BSV set/clear\n");
1240                 pm_runtime_get_noresume(phy->dev);
1241         }
1242
1243         writel(otgsc, USB_OTGSC);
1244         schedule_work(&motg->sm_work);
1245         return IRQ_HANDLED;
1246 }
1247
1248 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1249 {
1250         struct msm_otg *motg = s->private;
1251         struct usb_otg *otg = motg->phy.otg;
1252
1253         switch (otg->phy->state) {
1254         case OTG_STATE_A_HOST:
1255                 seq_printf(s, "host\n");
1256                 break;
1257         case OTG_STATE_B_PERIPHERAL:
1258                 seq_printf(s, "peripheral\n");
1259                 break;
1260         default:
1261                 seq_printf(s, "none\n");
1262                 break;
1263         }
1264
1265         return 0;
1266 }
1267
1268 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1269 {
1270         return single_open(file, msm_otg_mode_show, inode->i_private);
1271 }
1272
1273 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1274                                 size_t count, loff_t *ppos)
1275 {
1276         struct seq_file *s = file->private_data;
1277         struct msm_otg *motg = s->private;
1278         char buf[16];
1279         struct usb_otg *otg = motg->phy.otg;
1280         int status = count;
1281         enum usb_mode_type req_mode;
1282
1283         memset(buf, 0x00, sizeof(buf));
1284
1285         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1286                 status = -EFAULT;
1287                 goto out;
1288         }
1289
1290         if (!strncmp(buf, "host", 4)) {
1291                 req_mode = USB_HOST;
1292         } else if (!strncmp(buf, "peripheral", 10)) {
1293                 req_mode = USB_PERIPHERAL;
1294         } else if (!strncmp(buf, "none", 4)) {
1295                 req_mode = USB_NONE;
1296         } else {
1297                 status = -EINVAL;
1298                 goto out;
1299         }
1300
1301         switch (req_mode) {
1302         case USB_NONE:
1303                 switch (otg->phy->state) {
1304                 case OTG_STATE_A_HOST:
1305                 case OTG_STATE_B_PERIPHERAL:
1306                         set_bit(ID, &motg->inputs);
1307                         clear_bit(B_SESS_VLD, &motg->inputs);
1308                         break;
1309                 default:
1310                         goto out;
1311                 }
1312                 break;
1313         case USB_PERIPHERAL:
1314                 switch (otg->phy->state) {
1315                 case OTG_STATE_B_IDLE:
1316                 case OTG_STATE_A_HOST:
1317                         set_bit(ID, &motg->inputs);
1318                         set_bit(B_SESS_VLD, &motg->inputs);
1319                         break;
1320                 default:
1321                         goto out;
1322                 }
1323                 break;
1324         case USB_HOST:
1325                 switch (otg->phy->state) {
1326                 case OTG_STATE_B_IDLE:
1327                 case OTG_STATE_B_PERIPHERAL:
1328                         clear_bit(ID, &motg->inputs);
1329                         break;
1330                 default:
1331                         goto out;
1332                 }
1333                 break;
1334         default:
1335                 goto out;
1336         }
1337
1338         pm_runtime_get_sync(otg->phy->dev);
1339         schedule_work(&motg->sm_work);
1340 out:
1341         return status;
1342 }
1343
1344 const struct file_operations msm_otg_mode_fops = {
1345         .open = msm_otg_mode_open,
1346         .read = seq_read,
1347         .write = msm_otg_mode_write,
1348         .llseek = seq_lseek,
1349         .release = single_release,
1350 };
1351
1352 static struct dentry *msm_otg_dbg_root;
1353 static struct dentry *msm_otg_dbg_mode;
1354
1355 static int msm_otg_debugfs_init(struct msm_otg *motg)
1356 {
1357         msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1358
1359         if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1360                 return -ENODEV;
1361
1362         msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1363                                 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1364         if (!msm_otg_dbg_mode) {
1365                 debugfs_remove(msm_otg_dbg_root);
1366                 msm_otg_dbg_root = NULL;
1367                 return -ENODEV;
1368         }
1369
1370         return 0;
1371 }
1372
1373 static void msm_otg_debugfs_cleanup(void)
1374 {
1375         debugfs_remove(msm_otg_dbg_mode);
1376         debugfs_remove(msm_otg_dbg_root);
1377 }
1378
1379 static int msm_otg_probe(struct platform_device *pdev)
1380 {
1381         struct regulator_bulk_data regs[3];
1382         int ret = 0;
1383         struct resource *res;
1384         struct msm_otg *motg;
1385         struct usb_phy *phy;
1386
1387         dev_info(&pdev->dev, "msm_otg probe\n");
1388         if (!dev_get_platdata(&pdev->dev)) {
1389                 dev_err(&pdev->dev, "No platform data given. Bailing out\n");
1390                 return -ENODEV;
1391         }
1392
1393         motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1394         if (!motg) {
1395                 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1396                 return -ENOMEM;
1397         }
1398
1399         motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1400                                      GFP_KERNEL);
1401         if (!motg->phy.otg) {
1402                 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1403                 return -ENOMEM;
1404         }
1405
1406         motg->pdata = dev_get_platdata(&pdev->dev);
1407         phy = &motg->phy;
1408         phy->dev = &pdev->dev;
1409
1410         motg->phy_reset_clk = devm_clk_get(&pdev->dev, "usb_phy_clk");
1411         if (IS_ERR(motg->phy_reset_clk)) {
1412                 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
1413                 return PTR_ERR(motg->phy_reset_clk);
1414         }
1415
1416         motg->clk = devm_clk_get(&pdev->dev, "usb_hs_clk");
1417         if (IS_ERR(motg->clk)) {
1418                 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1419                 return PTR_ERR(motg->clk);
1420         }
1421
1422         /*
1423          * If USB Core is running its protocol engine based on CORE CLK,
1424          * CORE CLK  must be running at >55Mhz for correct HSUSB
1425          * operation and USB core cannot tolerate frequency changes on
1426          * CORE CLK. For such USB cores, vote for maximum clk frequency
1427          * on pclk source
1428          */
1429          motg->pclk_src = ERR_PTR(-ENOENT);
1430          if (motg->pdata->pclk_src_name) {
1431                 motg->pclk_src = devm_clk_get(&pdev->dev,
1432                                         motg->pdata->pclk_src_name);
1433                 if (IS_ERR(motg->pclk_src))
1434                         return PTR_ERR(motg->pclk_src);
1435         }
1436
1437         motg->pclk = devm_clk_get(&pdev->dev, "usb_hs_pclk");
1438         if (IS_ERR(motg->pclk)) {
1439                 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1440                 return PTR_ERR(motg->pclk);
1441         }
1442
1443         /*
1444          * USB core clock is not present on all MSM chips. This
1445          * clock is introduced to remove the dependency on AXI
1446          * bus frequency.
1447          */
1448         motg->core_clk = devm_clk_get(&pdev->dev, "usb_hs_core_clk");
1449
1450         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1451         motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1452         if (IS_ERR(motg->regs))
1453                 return PTR_ERR(motg->regs);
1454
1455         dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1456
1457         motg->irq = platform_get_irq(pdev, 0);
1458         if (!motg->irq) {
1459                 dev_err(&pdev->dev, "platform_get_irq failed\n");
1460                 return motg->irq;
1461         }
1462
1463         regs[0].supply = "HSUSB_VDDCX";
1464         regs[1].supply = "HSUSB_3p3";
1465         regs[2].supply = "HSUSB_1p8";
1466
1467         ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1468         if (ret)
1469                 return ret;
1470
1471         motg->vddcx = regs[0].consumer;
1472         motg->v3p3  = regs[1].consumer;
1473         motg->v1p8  = regs[2].consumer;
1474
1475         clk_set_rate(motg->clk, 60000000);
1476         if (!IS_ERR(motg->pclk_src)) {
1477                 clk_set_rate(motg->pclk_src, INT_MAX);
1478                 clk_prepare_enable(motg->pclk_src);
1479         }
1480
1481         clk_prepare_enable(motg->clk);
1482         clk_prepare_enable(motg->pclk);
1483
1484         if (!IS_ERR(motg->core_clk))
1485                 clk_prepare_enable(motg->core_clk);
1486
1487         ret = msm_hsusb_init_vddcx(motg, 1);
1488         if (ret) {
1489                 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1490                 goto disable_clks;
1491         }
1492
1493         ret = msm_hsusb_ldo_init(motg, 1);
1494         if (ret) {
1495                 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1496                 goto disable_vddcx;
1497         }
1498         ret = msm_hsusb_ldo_set_mode(motg, 1);
1499         if (ret) {
1500                 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1501                 goto disable_ldo;
1502         }
1503
1504         writel(0, USB_USBINTR);
1505         writel(0, USB_OTGSC);
1506
1507         INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1508         INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1509         ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1510                                         "msm_otg", motg);
1511         if (ret) {
1512                 dev_err(&pdev->dev, "request irq failed\n");
1513                 goto disable_ldo;
1514         }
1515
1516         phy->init = msm_otg_reset;
1517         phy->set_power = msm_otg_set_power;
1518
1519         phy->io_ops = &msm_otg_io_ops;
1520
1521         phy->otg->phy = &motg->phy;
1522         phy->otg->set_host = msm_otg_set_host;
1523         phy->otg->set_peripheral = msm_otg_set_peripheral;
1524
1525         ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2);
1526         if (ret) {
1527                 dev_err(&pdev->dev, "usb_add_phy failed\n");
1528                 goto disable_ldo;
1529         }
1530
1531         platform_set_drvdata(pdev, motg);
1532         device_init_wakeup(&pdev->dev, 1);
1533
1534         if (motg->pdata->mode == USB_OTG &&
1535                         motg->pdata->otg_control == OTG_USER_CONTROL) {
1536                 ret = msm_otg_debugfs_init(motg);
1537                 if (ret)
1538                         dev_dbg(&pdev->dev, "mode debugfs file is"
1539                                         "not available\n");
1540         }
1541
1542         pm_runtime_set_active(&pdev->dev);
1543         pm_runtime_enable(&pdev->dev);
1544
1545         return 0;
1546
1547 disable_ldo:
1548         msm_hsusb_ldo_init(motg, 0);
1549 disable_vddcx:
1550         msm_hsusb_init_vddcx(motg, 0);
1551 disable_clks:
1552         clk_disable_unprepare(motg->pclk);
1553         clk_disable_unprepare(motg->clk);
1554         if (!IS_ERR(motg->core_clk))
1555                 clk_disable_unprepare(motg->core_clk);
1556         if (!IS_ERR(motg->pclk_src))
1557                 clk_disable_unprepare(motg->pclk_src);
1558         return ret;
1559 }
1560
1561 static int msm_otg_remove(struct platform_device *pdev)
1562 {
1563         struct msm_otg *motg = platform_get_drvdata(pdev);
1564         struct usb_phy *phy = &motg->phy;
1565         int cnt = 0;
1566
1567         if (phy->otg->host || phy->otg->gadget)
1568                 return -EBUSY;
1569
1570         msm_otg_debugfs_cleanup();
1571         cancel_delayed_work_sync(&motg->chg_work);
1572         cancel_work_sync(&motg->sm_work);
1573
1574         pm_runtime_resume(&pdev->dev);
1575
1576         device_init_wakeup(&pdev->dev, 0);
1577         pm_runtime_disable(&pdev->dev);
1578
1579         usb_remove_phy(phy);
1580         disable_irq(motg->irq);
1581
1582         /*
1583          * Put PHY in low power mode.
1584          */
1585         ulpi_read(phy, 0x14);
1586         ulpi_write(phy, 0x08, 0x09);
1587
1588         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1589         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1590                 if (readl(USB_PORTSC) & PORTSC_PHCD)
1591                         break;
1592                 udelay(1);
1593                 cnt++;
1594         }
1595         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1596                 dev_err(phy->dev, "Unable to suspend PHY\n");
1597
1598         clk_disable_unprepare(motg->pclk);
1599         clk_disable_unprepare(motg->clk);
1600         if (!IS_ERR(motg->core_clk))
1601                 clk_disable_unprepare(motg->core_clk);
1602         if (!IS_ERR(motg->pclk_src))
1603                 clk_disable_unprepare(motg->pclk_src);
1604
1605         msm_hsusb_ldo_init(motg, 0);
1606
1607         pm_runtime_set_suspended(&pdev->dev);
1608
1609         return 0;
1610 }
1611
1612 #ifdef CONFIG_PM_RUNTIME
1613 static int msm_otg_runtime_idle(struct device *dev)
1614 {
1615         struct msm_otg *motg = dev_get_drvdata(dev);
1616         struct usb_otg *otg = motg->phy.otg;
1617
1618         dev_dbg(dev, "OTG runtime idle\n");
1619
1620         /*
1621          * It is observed some times that a spurious interrupt
1622          * comes when PHY is put into LPM immediately after PHY reset.
1623          * This 1 sec delay also prevents entering into LPM immediately
1624          * after asynchronous interrupt.
1625          */
1626         if (otg->phy->state != OTG_STATE_UNDEFINED)
1627                 pm_schedule_suspend(dev, 1000);
1628
1629         return -EAGAIN;
1630 }
1631
1632 static int msm_otg_runtime_suspend(struct device *dev)
1633 {
1634         struct msm_otg *motg = dev_get_drvdata(dev);
1635
1636         dev_dbg(dev, "OTG runtime suspend\n");
1637         return msm_otg_suspend(motg);
1638 }
1639
1640 static int msm_otg_runtime_resume(struct device *dev)
1641 {
1642         struct msm_otg *motg = dev_get_drvdata(dev);
1643
1644         dev_dbg(dev, "OTG runtime resume\n");
1645         return msm_otg_resume(motg);
1646 }
1647 #endif
1648
1649 #ifdef CONFIG_PM_SLEEP
1650 static int msm_otg_pm_suspend(struct device *dev)
1651 {
1652         struct msm_otg *motg = dev_get_drvdata(dev);
1653
1654         dev_dbg(dev, "OTG PM suspend\n");
1655         return msm_otg_suspend(motg);
1656 }
1657
1658 static int msm_otg_pm_resume(struct device *dev)
1659 {
1660         struct msm_otg *motg = dev_get_drvdata(dev);
1661         int ret;
1662
1663         dev_dbg(dev, "OTG PM resume\n");
1664
1665         ret = msm_otg_resume(motg);
1666         if (ret)
1667                 return ret;
1668
1669         /*
1670          * Runtime PM Documentation recommends bringing the
1671          * device to full powered state upon resume.
1672          */
1673         pm_runtime_disable(dev);
1674         pm_runtime_set_active(dev);
1675         pm_runtime_enable(dev);
1676
1677         return 0;
1678 }
1679 #endif
1680
1681 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1682         SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1683         SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1684                                 msm_otg_runtime_idle)
1685 };
1686
1687 static struct platform_driver msm_otg_driver = {
1688         .probe = msm_otg_probe,
1689         .remove = msm_otg_remove,
1690         .driver = {
1691                 .name = DRIVER_NAME,
1692                 .owner = THIS_MODULE,
1693                 .pm = &msm_otg_dev_pm_ops,
1694         },
1695 };
1696
1697 module_platform_driver(msm_otg_driver);
1698
1699 MODULE_LICENSE("GPL v2");
1700 MODULE_DESCRIPTION("MSM USB transceiver driver");