drivers/usb/otg/msm_otg.c

   1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15  * 02110-1301, USA.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/slab.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/err.h>
  26 #include <linux/delay.h>
  27 #include <linux/io.h>
  28 #include <linux/ioport.h>
  29 #include <linux/uaccess.h>
  30 #include <linux/debugfs.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include <linux/usb.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/usb/ulpi.h>
  37 #include <linux/usb/gadget.h>
  38 #include <linux/usb/hcd.h>
  39 #include <linux/usb/msm_hsusb.h>
  40 #include <linux/usb/msm_hsusb_hw.h>
  41 #include <linux/regulator/consumer.h>
  42
  43 #include <mach/clk.h>
  44
  45 #define MSM_USB_BASE    (motg->regs)
  46 #define DRIVER_NAME     "msm_otg"
  47
  48 #define ULPI_IO_TIMEOUT_USEC    (10 * 1000)
  49
  50 #define USB_PHY_3P3_VOL_MIN     3050000 /* uV */
  51 #define USB_PHY_3P3_VOL_MAX     3300000 /* uV */
  52 #define USB_PHY_3P3_HPM_LOAD    50000   /* uA */
  53 #define USB_PHY_3P3_LPM_LOAD    4000    /* uA */
  54
  55 #define USB_PHY_1P8_VOL_MIN     1800000 /* uV */
  56 #define USB_PHY_1P8_VOL_MAX     1800000 /* uV */
  57 #define USB_PHY_1P8_HPM_LOAD    50000   /* uA */
  58 #define USB_PHY_1P8_LPM_LOAD    4000    /* uA */
  59
  60 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
  61 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
  62
  63 static struct regulator *hsusb_3p3;
  64 static struct regulator *hsusb_1p8;
  65 static struct regulator *hsusb_vddcx;
  66
  67 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
  68 {
  69         int ret = 0;
  70
  71         if (init) {
  72                 hsusb_vddcx = regulator_get(motg->otg.dev, "HSUSB_VDDCX");
  73                 if (IS_ERR(hsusb_vddcx)) {
  74                         dev_err(motg->otg.dev, "unable to get hsusb vddcx\n");
  75                         return PTR_ERR(hsusb_vddcx);
  76                 }
  77
  78                 ret = regulator_set_voltage(hsusb_vddcx,
  79                                 USB_PHY_VDD_DIG_VOL_MIN,
  80                                 USB_PHY_VDD_DIG_VOL_MAX);
  81                 if (ret) {
  82                         dev_err(motg->otg.dev, "unable to set the voltage "
  83                                         "for hsusb vddcx\n");
  84                         regulator_put(hsusb_vddcx);
  85                         return ret;
  86                 }
  87
  88                 ret = regulator_enable(hsusb_vddcx);
  89                 if (ret) {
  90                         dev_err(motg->otg.dev, "unable to enable hsusb vddcx\n");
  91                         regulator_put(hsusb_vddcx);
  92                 }
  93         } else {
  94                 ret = regulator_set_voltage(hsusb_vddcx, 0,
  95                         USB_PHY_VDD_DIG_VOL_MIN);
  96                 if (ret) {
  97                         dev_err(motg->otg.dev, "unable to set the voltage "
  98                                         "for hsusb vddcx\n");
  99                         return ret;
 100                 }
 101                 ret = regulator_disable(hsusb_vddcx);
 102                 if (ret)
 103                         dev_err(motg->otg.dev, "unable to disable hsusb vddcx\n");
 104
 105                 regulator_put(hsusb_vddcx);
 106         }
 107
 108         return ret;
 109 }
 110
 111 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
 112 {
 113         int rc = 0;
 114
 115         if (init) {
 116                 hsusb_3p3 = regulator_get(motg->otg.dev, "HSUSB_3p3");
 117                 if (IS_ERR(hsusb_3p3)) {
 118                         dev_err(motg->otg.dev, "unable to get hsusb 3p3\n");
 119                         return PTR_ERR(hsusb_3p3);
 120                 }
 121
 122                 rc = regulator_set_voltage(hsusb_3p3, USB_PHY_3P3_VOL_MIN,
 123                                 USB_PHY_3P3_VOL_MAX);
 124                 if (rc) {
 125                         dev_err(motg->otg.dev, "unable to set voltage level "
 126                                         "for hsusb 3p3\n");
 127                         goto put_3p3;
 128                 }
 129                 rc = regulator_enable(hsusb_3p3);
 130                 if (rc) {
 131                         dev_err(motg->otg.dev, "unable to enable the hsusb 3p3\n");
 132                         goto put_3p3;
 133                 }
 134                 hsusb_1p8 = regulator_get(motg->otg.dev, "HSUSB_1p8");
 135                 if (IS_ERR(hsusb_1p8)) {
 136                         dev_err(motg->otg.dev, "unable to get hsusb 1p8\n");
 137                         rc = PTR_ERR(hsusb_1p8);
 138                         goto disable_3p3;
 139                 }
 140                 rc = regulator_set_voltage(hsusb_1p8, USB_PHY_1P8_VOL_MIN,
 141                                 USB_PHY_1P8_VOL_MAX);
 142                 if (rc) {
 143                         dev_err(motg->otg.dev, "unable to set voltage level "
 144                                         "for hsusb 1p8\n");
 145                         goto put_1p8;
 146                 }
 147                 rc = regulator_enable(hsusb_1p8);
 148                 if (rc) {
 149                         dev_err(motg->otg.dev, "unable to enable the hsusb 1p8\n");
 150                         goto put_1p8;
 151                 }
 152
 153                 return 0;
 154         }
 155
 156         regulator_disable(hsusb_1p8);
 157 put_1p8:
 158         regulator_put(hsusb_1p8);
 159 disable_3p3:
 160         regulator_disable(hsusb_3p3);
 161 put_3p3:
 162         regulator_put(hsusb_3p3);
 163         return rc;
 164 }
 165
 166 #ifdef CONFIG_PM_SLEEP
 167 #define USB_PHY_SUSP_DIG_VOL  500000
 168 static int msm_hsusb_config_vddcx(int high)
 169 {
 170         int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
 171         int min_vol;
 172         int ret;
 173
 174         if (high)
 175                 min_vol = USB_PHY_VDD_DIG_VOL_MIN;
 176         else
 177                 min_vol = USB_PHY_SUSP_DIG_VOL;
 178
 179         ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
 180         if (ret) {
 181                 pr_err("%s: unable to set the voltage for regulator "
 182                         "HSUSB_VDDCX\n", __func__);
 183                 return ret;
 184         }
 185
 186         pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
 187
 188         return ret;
 189 }
 190 #endif
 191
 192 static int msm_hsusb_ldo_set_mode(int on)
 193 {
 194         int ret = 0;
 195
 196         if (!hsusb_1p8 || IS_ERR(hsusb_1p8)) {
 197                 pr_err("%s: HSUSB_1p8 is not initialized\n", __func__);
 198                 return -ENODEV;
 199         }
 200
 201         if (!hsusb_3p3 || IS_ERR(hsusb_3p3)) {
 202                 pr_err("%s: HSUSB_3p3 is not initialized\n", __func__);
 203                 return -ENODEV;
 204         }
 205
 206         if (on) {
 207                 ret = regulator_set_optimum_mode(hsusb_1p8,
 208                                 USB_PHY_1P8_HPM_LOAD);
 209                 if (ret < 0) {
 210                         pr_err("%s: Unable to set HPM of the regulator "
 211                                 "HSUSB_1p8\n", __func__);
 212                         return ret;
 213                 }
 214                 ret = regulator_set_optimum_mode(hsusb_3p3,
 215                                 USB_PHY_3P3_HPM_LOAD);
 216                 if (ret < 0) {
 217                         pr_err("%s: Unable to set HPM of the regulator "
 218                                 "HSUSB_3p3\n", __func__);
 219                         regulator_set_optimum_mode(hsusb_1p8,
 220                                 USB_PHY_1P8_LPM_LOAD);
 221                         return ret;
 222                 }
 223         } else {
 224                 ret = regulator_set_optimum_mode(hsusb_1p8,
 225                                 USB_PHY_1P8_LPM_LOAD);
 226                 if (ret < 0)
 227                         pr_err("%s: Unable to set LPM of the regulator "
 228                                 "HSUSB_1p8\n", __func__);
 229                 ret = regulator_set_optimum_mode(hsusb_3p3,
 230                                 USB_PHY_3P3_LPM_LOAD);
 231                 if (ret < 0)
 232                         pr_err("%s: Unable to set LPM of the regulator "
 233                                 "HSUSB_3p3\n", __func__);
 234         }
 235
 236         pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
 237         return ret < 0 ? ret : 0;
 238 }
 239
 240 static int ulpi_read(struct otg_transceiver *otg, u32 reg)
 241 {
 242         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 243         int cnt = 0;
 244
 245         /* initiate read operation */
 246         writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
 247                USB_ULPI_VIEWPORT);
 248
 249         /* wait for completion */
 250         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 251                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 252                         break;
 253                 udelay(1);
 254                 cnt++;
 255         }
 256
 257         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 258                 dev_err(otg->dev, "ulpi_read: timeout %08x\n",
 259                         readl(USB_ULPI_VIEWPORT));
 260                 return -ETIMEDOUT;
 261         }
 262         return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
 263 }
 264
 265 static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
 266 {
 267         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 268         int cnt = 0;
 269
 270         /* initiate write operation */
 271         writel(ULPI_RUN | ULPI_WRITE |
 272                ULPI_ADDR(reg) | ULPI_DATA(val),
 273                USB_ULPI_VIEWPORT);
 274
 275         /* wait for completion */
 276         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 277                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 278                         break;
 279                 udelay(1);
 280                 cnt++;
 281         }
 282
 283         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 284                 dev_err(otg->dev, "ulpi_write: timeout\n");
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 static struct otg_io_access_ops msm_otg_io_ops = {
 291         .read = ulpi_read,
 292         .write = ulpi_write,
 293 };
 294
 295 static void ulpi_init(struct msm_otg *motg)
 296 {
 297         struct msm_otg_platform_data *pdata = motg->pdata;
 298         int *seq = pdata->phy_init_seq;
 299
 300         if (!seq)
 301                 return;
 302
 303         while (seq[0] >= 0) {
 304                 dev_vdbg(motg->otg.dev, "ulpi: write 0x%02x to 0x%02x\n",
 305                                 seq[0], seq[1]);
 306                 ulpi_write(&motg->otg, seq[0], seq[1]);
 307                 seq += 2;
 308         }
 309 }
 310
 311 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
 312 {
 313         int ret;
 314
 315         if (assert) {
 316                 ret = clk_reset(motg->clk, CLK_RESET_ASSERT);
 317                 if (ret)
 318                         dev_err(motg->otg.dev, "usb hs_clk assert failed\n");
 319         } else {
 320                 ret = clk_reset(motg->clk, CLK_RESET_DEASSERT);
 321                 if (ret)
 322                         dev_err(motg->otg.dev, "usb hs_clk deassert failed\n");
 323         }
 324         return ret;
 325 }
 326
 327 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
 328 {
 329         int ret;
 330
 331         ret = clk_reset(motg->phy_reset_clk, CLK_RESET_ASSERT);
 332         if (ret) {
 333                 dev_err(motg->otg.dev, "usb phy clk assert failed\n");
 334                 return ret;
 335         }
 336         usleep_range(10000, 12000);
 337         ret = clk_reset(motg->phy_reset_clk, CLK_RESET_DEASSERT);
 338         if (ret)
 339                 dev_err(motg->otg.dev, "usb phy clk deassert failed\n");
 340         return ret;
 341 }
 342
 343 static int msm_otg_phy_reset(struct msm_otg *motg)
 344 {
 345         u32 val;
 346         int ret;
 347         int retries;
 348
 349         ret = msm_otg_link_clk_reset(motg, 1);
 350         if (ret)
 351                 return ret;
 352         ret = msm_otg_phy_clk_reset(motg);
 353         if (ret)
 354                 return ret;
 355         ret = msm_otg_link_clk_reset(motg, 0);
 356         if (ret)
 357                 return ret;
 358
 359         val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
 360         writel(val | PORTSC_PTS_ULPI, USB_PORTSC);
 361
 362         for (retries = 3; retries > 0; retries--) {
 363                 ret = ulpi_write(&motg->otg, ULPI_FUNC_CTRL_SUSPENDM,
 364                                 ULPI_CLR(ULPI_FUNC_CTRL));
 365                 if (!ret)
 366                         break;
 367                 ret = msm_otg_phy_clk_reset(motg);
 368                 if (ret)
 369                         return ret;
 370         }
 371         if (!retries)
 372                 return -ETIMEDOUT;
 373
 374         /* This reset calibrates the phy, if the above write succeeded */
 375         ret = msm_otg_phy_clk_reset(motg);
 376         if (ret)
 377                 return ret;
 378
 379         for (retries = 3; retries > 0; retries--) {
 380                 ret = ulpi_read(&motg->otg, ULPI_DEBUG);
 381                 if (ret != -ETIMEDOUT)
 382                         break;
 383                 ret = msm_otg_phy_clk_reset(motg);
 384                 if (ret)
 385                         return ret;
 386         }
 387         if (!retries)
 388                 return -ETIMEDOUT;
 389
 390         dev_info(motg->otg.dev, "phy_reset: success\n");
 391         return 0;
 392 }
 393
 394 #define LINK_RESET_TIMEOUT_USEC         (250 * 1000)
 395 static int msm_otg_reset(struct otg_transceiver *otg)
 396 {
 397         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 398         struct msm_otg_platform_data *pdata = motg->pdata;
 399         int cnt = 0;
 400         int ret;
 401         u32 val = 0;
 402         u32 ulpi_val = 0;
 403
 404         ret = msm_otg_phy_reset(motg);
 405         if (ret) {
 406                 dev_err(otg->dev, "phy_reset failed\n");
 407                 return ret;
 408         }
 409
 410         ulpi_init(motg);
 411
 412         writel(USBCMD_RESET, USB_USBCMD);
 413         while (cnt < LINK_RESET_TIMEOUT_USEC) {
 414                 if (!(readl(USB_USBCMD) & USBCMD_RESET))
 415                         break;
 416                 udelay(1);
 417                 cnt++;
 418         }
 419         if (cnt >= LINK_RESET_TIMEOUT_USEC)
 420                 return -ETIMEDOUT;
 421
 422         /* select ULPI phy */
 423         writel(0x80000000, USB_PORTSC);
 424
 425         msleep(100);
 426
 427         writel(0x0, USB_AHBBURST);
 428         writel(0x00, USB_AHBMODE);
 429
 430         if (pdata->otg_control == OTG_PHY_CONTROL) {
 431                 val = readl(USB_OTGSC);
 432                 if (pdata->mode == USB_OTG) {
 433                         ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
 434                         val |= OTGSC_IDIE | OTGSC_BSVIE;
 435                 } else if (pdata->mode == USB_PERIPHERAL) {
 436                         ulpi_val = ULPI_INT_SESS_VALID;
 437                         val |= OTGSC_BSVIE;
 438                 }
 439                 writel(val, USB_OTGSC);
 440                 ulpi_write(otg, ulpi_val, ULPI_USB_INT_EN_RISE);
 441                 ulpi_write(otg, ulpi_val, ULPI_USB_INT_EN_FALL);
 442         }
 443
 444         return 0;
 445 }
 446
 447 #define PHY_SUSPEND_TIMEOUT_USEC        (500 * 1000)
 448 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
 449
 450 #ifdef CONFIG_PM_SLEEP
 451 static int msm_otg_suspend(struct msm_otg *motg)
 452 {
 453         struct otg_transceiver *otg = &motg->otg;
 454         struct usb_bus *bus = otg->host;
 455         struct msm_otg_platform_data *pdata = motg->pdata;
 456         int cnt = 0;
 457
 458         if (atomic_read(&motg->in_lpm))
 459                 return 0;
 460
 461         disable_irq(motg->irq);
 462         /*
 463          * Chipidea 45-nm PHY suspend sequence:
 464          *
 465          * Interrupt Latch Register auto-clear feature is not present
 466          * in all PHY versions. Latch register is clear on read type.
 467          * Clear latch register to avoid spurious wakeup from
 468          * low power mode (LPM).
 469          *
 470          * PHY comparators are disabled when PHY enters into low power
 471          * mode (LPM). Keep PHY comparators ON in LPM only when we expect
 472          * VBUS/Id notifications from USB PHY. Otherwise turn off USB
 473          * PHY comparators. This save significant amount of power.
 474          *
 475          * PLL is not turned off when PHY enters into low power mode (LPM).
 476          * Disable PLL for maximum power savings.
 477          */
 478
 479         if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
 480                 ulpi_read(otg, 0x14);
 481                 if (pdata->otg_control == OTG_PHY_CONTROL)
 482                         ulpi_write(otg, 0x01, 0x30);
 483                 ulpi_write(otg, 0x08, 0x09);
 484         }
 485
 486         /*
 487          * PHY may take some time or even fail to enter into low power
 488          * mode (LPM). Hence poll for 500 msec and reset the PHY and link
 489          * in failure case.
 490          */
 491         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
 492         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
 493                 if (readl(USB_PORTSC) & PORTSC_PHCD)
 494                         break;
 495                 udelay(1);
 496                 cnt++;
 497         }
 498
 499         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
 500                 dev_err(otg->dev, "Unable to suspend PHY\n");
 501                 msm_otg_reset(otg);
 502                 enable_irq(motg->irq);
 503                 return -ETIMEDOUT;
 504         }
 505
 506         /*
 507          * PHY has capability to generate interrupt asynchronously in low
 508          * power mode (LPM). This interrupt is level triggered. So USB IRQ
 509          * line must be disabled till async interrupt enable bit is cleared
 510          * in USBCMD register. Assert STP (ULPI interface STOP signal) to
 511          * block data communication from PHY.
 512          */
 513         writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
 514
 515         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 516                         motg->pdata->otg_control == OTG_PMIC_CONTROL)
 517                 writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
 518
 519         clk_disable(motg->pclk);
 520         clk_disable(motg->clk);
 521         if (motg->core_clk)
 522                 clk_disable(motg->core_clk);
 523
 524         if (!IS_ERR(motg->pclk_src))
 525                 clk_disable(motg->pclk_src);
 526
 527         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 528                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 529                 msm_hsusb_ldo_set_mode(0);
 530                 msm_hsusb_config_vddcx(0);
 531         }
 532
 533         if (device_may_wakeup(otg->dev))
 534                 enable_irq_wake(motg->irq);
 535         if (bus)
 536                 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 537
 538         atomic_set(&motg->in_lpm, 1);
 539         enable_irq(motg->irq);
 540
 541         dev_info(otg->dev, "USB in low power mode\n");
 542
 543         return 0;
 544 }
 545
 546 static int msm_otg_resume(struct msm_otg *motg)
 547 {
 548         struct otg_transceiver *otg = &motg->otg;
 549         struct usb_bus *bus = otg->host;
 550         int cnt = 0;
 551         unsigned temp;
 552
 553         if (!atomic_read(&motg->in_lpm))
 554                 return 0;
 555
 556         if (!IS_ERR(motg->pclk_src))
 557                 clk_enable(motg->pclk_src);
 558
 559         clk_enable(motg->pclk);
 560         clk_enable(motg->clk);
 561         if (motg->core_clk)
 562                 clk_enable(motg->core_clk);
 563
 564         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 565                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 566                 msm_hsusb_ldo_set_mode(1);
 567                 msm_hsusb_config_vddcx(1);
 568                 writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL);
 569         }
 570
 571         temp = readl(USB_USBCMD);
 572         temp &= ~ASYNC_INTR_CTRL;
 573         temp &= ~ULPI_STP_CTRL;
 574         writel(temp, USB_USBCMD);
 575
 576         /*
 577          * PHY comes out of low power mode (LPM) in case of wakeup
 578          * from asynchronous interrupt.
 579          */
 580         if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 581                 goto skip_phy_resume;
 582
 583         writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
 584         while (cnt < PHY_RESUME_TIMEOUT_USEC) {
 585                 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 586                         break;
 587                 udelay(1);
 588                 cnt++;
 589         }
 590
 591         if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
 592                 /*
 593                  * This is a fatal error. Reset the link and
 594                  * PHY. USB state can not be restored. Re-insertion
 595                  * of USB cable is the only way to get USB working.
 596                  */
 597                 dev_err(otg->dev, "Unable to resume USB."
 598                                 "Re-plugin the cable\n");
 599                 msm_otg_reset(otg);
 600         }
 601
 602 skip_phy_resume:
 603         if (device_may_wakeup(otg->dev))
 604                 disable_irq_wake(motg->irq);
 605         if (bus)
 606                 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 607
 608         atomic_set(&motg->in_lpm, 0);
 609
 610         if (motg->async_int) {
 611                 motg->async_int = 0;
 612                 pm_runtime_put(otg->dev);
 613                 enable_irq(motg->irq);
 614         }
 615
 616         dev_info(otg->dev, "USB exited from low power mode\n");
 617
 618         return 0;
 619 }
 620 #endif
 621
 622 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
 623 {
 624         if (motg->cur_power == mA)
 625                 return;
 626
 627         /* TODO: Notify PMIC about available current */
 628         dev_info(motg->otg.dev, "Avail curr from USB = %u\n", mA);
 629         motg->cur_power = mA;
 630 }
 631
 632 static int msm_otg_set_power(struct otg_transceiver *otg, unsigned mA)
 633 {
 634         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 635
 636         /*
 637          * Gadget driver uses set_power method to notify about the
 638          * available current based on suspend/configured states.
 639          *
 640          * IDEV_CHG can be drawn irrespective of suspend/un-configured
 641          * states when CDP/ACA is connected.
 642          */
 643         if (motg->chg_type == USB_SDP_CHARGER)
 644                 msm_otg_notify_charger(motg, mA);
 645
 646         return 0;
 647 }
 648
 649 static void msm_otg_start_host(struct otg_transceiver *otg, int on)
 650 {
 651         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 652         struct msm_otg_platform_data *pdata = motg->pdata;
 653         struct usb_hcd *hcd;
 654
 655         if (!otg->host)
 656                 return;
 657
 658         hcd = bus_to_hcd(otg->host);
 659
 660         if (on) {
 661                 dev_dbg(otg->dev, "host on\n");
 662
 663                 if (pdata->vbus_power)
 664                         pdata->vbus_power(1);
 665                 /*
 666                  * Some boards have a switch cotrolled by gpio
 667                  * to enable/disable internal HUB. Enable internal
 668                  * HUB before kicking the host.
 669                  */
 670                 if (pdata->setup_gpio)
 671                         pdata->setup_gpio(OTG_STATE_A_HOST);
 672 #ifdef CONFIG_USB
 673                 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 674 #endif
 675         } else {
 676                 dev_dbg(otg->dev, "host off\n");
 677
 678 #ifdef CONFIG_USB
 679                 usb_remove_hcd(hcd);
 680 #endif
 681                 if (pdata->setup_gpio)
 682                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 683                 if (pdata->vbus_power)
 684                         pdata->vbus_power(0);
 685         }
 686 }
 687
 688 static int msm_otg_set_host(struct otg_transceiver *otg, struct usb_bus *host)
 689 {
 690         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 691         struct usb_hcd *hcd;
 692
 693         /*
 694          * Fail host registration if this board can support
 695          * only peripheral configuration.
 696          */
 697         if (motg->pdata->mode == USB_PERIPHERAL) {
 698                 dev_info(otg->dev, "Host mode is not supported\n");
 699                 return -ENODEV;
 700         }
 701
 702         if (!host) {
 703                 if (otg->state == OTG_STATE_A_HOST) {
 704                         pm_runtime_get_sync(otg->dev);
 705                         msm_otg_start_host(otg, 0);
 706                         otg->host = NULL;
 707                         otg->state = OTG_STATE_UNDEFINED;
 708                         schedule_work(&motg->sm_work);
 709                 } else {
 710                         otg->host = NULL;
 711                 }
 712
 713                 return 0;
 714         }
 715
 716         hcd = bus_to_hcd(host);
 717         hcd->power_budget = motg->pdata->power_budget;
 718
 719         otg->host = host;
 720         dev_dbg(otg->dev, "host driver registered w/ tranceiver\n");
 721
 722         /*
 723          * Kick the state machine work, if peripheral is not supported
 724          * or peripheral is already registered with us.
 725          */
 726         if (motg->pdata->mode == USB_HOST || otg->gadget) {
 727                 pm_runtime_get_sync(otg->dev);
 728                 schedule_work(&motg->sm_work);
 729         }
 730
 731         return 0;
 732 }
 733
 734 static void msm_otg_start_peripheral(struct otg_transceiver *otg, int on)
 735 {
 736         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 737         struct msm_otg_platform_data *pdata = motg->pdata;
 738
 739         if (!otg->gadget)
 740                 return;
 741
 742         if (on) {
 743                 dev_dbg(otg->dev, "gadget on\n");
 744                 /*
 745                  * Some boards have a switch cotrolled by gpio
 746                  * to enable/disable internal HUB. Disable internal
 747                  * HUB before kicking the gadget.
 748                  */
 749                 if (pdata->setup_gpio)
 750                         pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
 751                 usb_gadget_vbus_connect(otg->gadget);
 752         } else {
 753                 dev_dbg(otg->dev, "gadget off\n");
 754                 usb_gadget_vbus_disconnect(otg->gadget);
 755                 if (pdata->setup_gpio)
 756                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 757         }
 758
 759 }
 760
 761 static int msm_otg_set_peripheral(struct otg_transceiver *otg,
 762                         struct usb_gadget *gadget)
 763 {
 764         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 765
 766         /*
 767          * Fail peripheral registration if this board can support
 768          * only host configuration.
 769          */
 770         if (motg->pdata->mode == USB_HOST) {
 771                 dev_info(otg->dev, "Peripheral mode is not supported\n");
 772                 return -ENODEV;
 773         }
 774
 775         if (!gadget) {
 776                 if (otg->state == OTG_STATE_B_PERIPHERAL) {
 777                         pm_runtime_get_sync(otg->dev);
 778                         msm_otg_start_peripheral(otg, 0);
 779                         otg->gadget = NULL;
 780                         otg->state = OTG_STATE_UNDEFINED;
 781                         schedule_work(&motg->sm_work);
 782                 } else {
 783                         otg->gadget = NULL;
 784                 }
 785
 786                 return 0;
 787         }
 788         otg->gadget = gadget;
 789         dev_dbg(otg->dev, "peripheral driver registered w/ tranceiver\n");
 790
 791         /*
 792          * Kick the state machine work, if host is not supported
 793          * or host is already registered with us.
 794          */
 795         if (motg->pdata->mode == USB_PERIPHERAL || otg->host) {
 796                 pm_runtime_get_sync(otg->dev);
 797                 schedule_work(&motg->sm_work);
 798         }
 799
 800         return 0;
 801 }
 802
 803 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
 804 {
 805         struct otg_transceiver *otg = &motg->otg;
 806         u32 chg_det;
 807         bool ret = false;
 808
 809         switch (motg->pdata->phy_type) {
 810         case CI_45NM_INTEGRATED_PHY:
 811                 chg_det = ulpi_read(otg, 0x34);
 812                 ret = chg_det & (1 << 4);
 813                 break;
 814         case SNPS_28NM_INTEGRATED_PHY:
 815                 chg_det = ulpi_read(otg, 0x87);
 816                 ret = chg_det & 1;
 817                 break;
 818         default:
 819                 break;
 820         }
 821         return ret;
 822 }
 823
 824 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
 825 {
 826         struct otg_transceiver *otg = &motg->otg;
 827         u32 chg_det;
 828
 829         switch (motg->pdata->phy_type) {
 830         case CI_45NM_INTEGRATED_PHY:
 831                 chg_det = ulpi_read(otg, 0x34);
 832                 /* Turn off charger block */
 833                 chg_det |= ~(1 << 1);
 834                 ulpi_write(otg, chg_det, 0x34);
 835                 udelay(20);
 836                 /* control chg block via ULPI */
 837                 chg_det &= ~(1 << 3);
 838                 ulpi_write(otg, chg_det, 0x34);
 839                 /* put it in host mode for enabling D- source */
 840                 chg_det &= ~(1 << 2);
 841                 ulpi_write(otg, chg_det, 0x34);
 842                 /* Turn on chg detect block */
 843                 chg_det &= ~(1 << 1);
 844                 ulpi_write(otg, chg_det, 0x34);
 845                 udelay(20);
 846                 /* enable chg detection */
 847                 chg_det &= ~(1 << 0);
 848                 ulpi_write(otg, chg_det, 0x34);
 849                 break;
 850         case SNPS_28NM_INTEGRATED_PHY:
 851                 /*
 852                  * Configure DM as current source, DP as current sink
 853                  * and enable battery charging comparators.
 854                  */
 855                 ulpi_write(otg, 0x8, 0x85);
 856                 ulpi_write(otg, 0x2, 0x85);
 857                 ulpi_write(otg, 0x1, 0x85);
 858                 break;
 859         default:
 860                 break;
 861         }
 862 }
 863
 864 static bool msm_chg_check_primary_det(struct msm_otg *motg)
 865 {
 866         struct otg_transceiver *otg = &motg->otg;
 867         u32 chg_det;
 868         bool ret = false;
 869
 870         switch (motg->pdata->phy_type) {
 871         case CI_45NM_INTEGRATED_PHY:
 872                 chg_det = ulpi_read(otg, 0x34);
 873                 ret = chg_det & (1 << 4);
 874                 break;
 875         case SNPS_28NM_INTEGRATED_PHY:
 876                 chg_det = ulpi_read(otg, 0x87);
 877                 ret = chg_det & 1;
 878                 break;
 879         default:
 880                 break;
 881         }
 882         return ret;
 883 }
 884
 885 static void msm_chg_enable_primary_det(struct msm_otg *motg)
 886 {
 887         struct otg_transceiver *otg = &motg->otg;
 888         u32 chg_det;
 889
 890         switch (motg->pdata->phy_type) {
 891         case CI_45NM_INTEGRATED_PHY:
 892                 chg_det = ulpi_read(otg, 0x34);
 893                 /* enable chg detection */
 894                 chg_det &= ~(1 << 0);
 895                 ulpi_write(otg, chg_det, 0x34);
 896                 break;
 897         case SNPS_28NM_INTEGRATED_PHY:
 898                 /*
 899                  * Configure DP as current source, DM as current sink
 900                  * and enable battery charging comparators.
 901                  */
 902                 ulpi_write(otg, 0x2, 0x85);
 903                 ulpi_write(otg, 0x1, 0x85);
 904                 break;
 905         default:
 906                 break;
 907         }
 908 }
 909
 910 static bool msm_chg_check_dcd(struct msm_otg *motg)
 911 {
 912         struct otg_transceiver *otg = &motg->otg;
 913         u32 line_state;
 914         bool ret = false;
 915
 916         switch (motg->pdata->phy_type) {
 917         case CI_45NM_INTEGRATED_PHY:
 918                 line_state = ulpi_read(otg, 0x15);
 919                 ret = !(line_state & 1);
 920                 break;
 921         case SNPS_28NM_INTEGRATED_PHY:
 922                 line_state = ulpi_read(otg, 0x87);
 923                 ret = line_state & 2;
 924                 break;
 925         default:
 926                 break;
 927         }
 928         return ret;
 929 }
 930
 931 static void msm_chg_disable_dcd(struct msm_otg *motg)
 932 {
 933         struct otg_transceiver *otg = &motg->otg;
 934         u32 chg_det;
 935
 936         switch (motg->pdata->phy_type) {
 937         case CI_45NM_INTEGRATED_PHY:
 938                 chg_det = ulpi_read(otg, 0x34);
 939                 chg_det &= ~(1 << 5);
 940                 ulpi_write(otg, chg_det, 0x34);
 941                 break;
 942         case SNPS_28NM_INTEGRATED_PHY:
 943                 ulpi_write(otg, 0x10, 0x86);
 944                 break;
 945         default:
 946                 break;
 947         }
 948 }
 949
 950 static void msm_chg_enable_dcd(struct msm_otg *motg)
 951 {
 952         struct otg_transceiver *otg = &motg->otg;
 953         u32 chg_det;
 954
 955         switch (motg->pdata->phy_type) {
 956         case CI_45NM_INTEGRATED_PHY:
 957                 chg_det = ulpi_read(otg, 0x34);
 958                 /* Turn on D+ current source */
 959                 chg_det |= (1 << 5);
 960                 ulpi_write(otg, chg_det, 0x34);
 961                 break;
 962         case SNPS_28NM_INTEGRATED_PHY:
 963                 /* Data contact detection enable */
 964                 ulpi_write(otg, 0x10, 0x85);
 965                 break;
 966         default:
 967                 break;
 968         }
 969 }
 970
 971 static void msm_chg_block_on(struct msm_otg *motg)
 972 {
 973         struct otg_transceiver *otg = &motg->otg;
 974         u32 func_ctrl, chg_det;
 975
 976         /* put the controller in non-driving mode */
 977         func_ctrl = ulpi_read(otg, ULPI_FUNC_CTRL);
 978         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 979         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
 980         ulpi_write(otg, func_ctrl, ULPI_FUNC_CTRL);
 981
 982         switch (motg->pdata->phy_type) {
 983         case CI_45NM_INTEGRATED_PHY:
 984                 chg_det = ulpi_read(otg, 0x34);
 985                 /* control chg block via ULPI */
 986                 chg_det &= ~(1 << 3);
 987                 ulpi_write(otg, chg_det, 0x34);
 988                 /* Turn on chg detect block */
 989                 chg_det &= ~(1 << 1);
 990                 ulpi_write(otg, chg_det, 0x34);
 991                 udelay(20);
 992                 break;
 993         case SNPS_28NM_INTEGRATED_PHY:
 994                 /* Clear charger detecting control bits */
 995                 ulpi_write(otg, 0x3F, 0x86);
 996                 /* Clear alt interrupt latch and enable bits */
 997                 ulpi_write(otg, 0x1F, 0x92);
 998                 ulpi_write(otg, 0x1F, 0x95);
 999                 udelay(100);
1000                 break;
1001         default:
1002                 break;
1003         }
1004 }
1005
1006 static void msm_chg_block_off(struct msm_otg *motg)
1007 {
1008         struct otg_transceiver *otg = &motg->otg;
1009         u32 func_ctrl, chg_det;
1010
1011         switch (motg->pdata->phy_type) {
1012         case CI_45NM_INTEGRATED_PHY:
1013                 chg_det = ulpi_read(otg, 0x34);
1014                 /* Turn off charger block */
1015                 chg_det |= ~(1 << 1);
1016                 ulpi_write(otg, chg_det, 0x34);
1017                 break;
1018         case SNPS_28NM_INTEGRATED_PHY:
1019                 /* Clear charger detecting control bits */
1020                 ulpi_write(otg, 0x3F, 0x86);
1021                 /* Clear alt interrupt latch and enable bits */
1022                 ulpi_write(otg, 0x1F, 0x92);
1023                 ulpi_write(otg, 0x1F, 0x95);
1024                 break;
1025         default:
1026                 break;
1027         }
1028
1029         /* put the controller in normal mode */
1030         func_ctrl = ulpi_read(otg, ULPI_FUNC_CTRL);
1031         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1032         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1033         ulpi_write(otg, func_ctrl, ULPI_FUNC_CTRL);
1034 }
1035
1036 #define MSM_CHG_DCD_POLL_TIME           (100 * HZ/1000) /* 100 msec */
1037 #define MSM_CHG_DCD_MAX_RETRIES         6 /* Tdcd_tmout = 6 * 100 msec */
1038 #define MSM_CHG_PRIMARY_DET_TIME        (40 * HZ/1000) /* TVDPSRC_ON */
1039 #define MSM_CHG_SECONDARY_DET_TIME      (40 * HZ/1000) /* TVDMSRC_ON */
1040 static void msm_chg_detect_work(struct work_struct *w)
1041 {
1042         struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1043         struct otg_transceiver *otg = &motg->otg;
1044         bool is_dcd, tmout, vout;
1045         unsigned long delay;
1046
1047         dev_dbg(otg->dev, "chg detection work\n");
1048         switch (motg->chg_state) {
1049         case USB_CHG_STATE_UNDEFINED:
1050                 pm_runtime_get_sync(otg->dev);
1051                 msm_chg_block_on(motg);
1052                 msm_chg_enable_dcd(motg);
1053                 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1054                 motg->dcd_retries = 0;
1055                 delay = MSM_CHG_DCD_POLL_TIME;
1056                 break;
1057         case USB_CHG_STATE_WAIT_FOR_DCD:
1058                 is_dcd = msm_chg_check_dcd(motg);
1059                 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1060                 if (is_dcd || tmout) {
1061                         msm_chg_disable_dcd(motg);
1062                         msm_chg_enable_primary_det(motg);
1063                         delay = MSM_CHG_PRIMARY_DET_TIME;
1064                         motg->chg_state = USB_CHG_STATE_DCD_DONE;
1065                 } else {
1066                         delay = MSM_CHG_DCD_POLL_TIME;
1067                 }
1068                 break;
1069         case USB_CHG_STATE_DCD_DONE:
1070                 vout = msm_chg_check_primary_det(motg);
1071                 if (vout) {
1072                         msm_chg_enable_secondary_det(motg);
1073                         delay = MSM_CHG_SECONDARY_DET_TIME;
1074                         motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1075                 } else {
1076                         motg->chg_type = USB_SDP_CHARGER;
1077                         motg->chg_state = USB_CHG_STATE_DETECTED;
1078                         delay = 0;
1079                 }
1080                 break;
1081         case USB_CHG_STATE_PRIMARY_DONE:
1082                 vout = msm_chg_check_secondary_det(motg);
1083                 if (vout)
1084                         motg->chg_type = USB_DCP_CHARGER;
1085                 else
1086                         motg->chg_type = USB_CDP_CHARGER;
1087                 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1088                 /* fall through */
1089         case USB_CHG_STATE_SECONDARY_DONE:
1090                 motg->chg_state = USB_CHG_STATE_DETECTED;
1091         case USB_CHG_STATE_DETECTED:
1092                 msm_chg_block_off(motg);
1093                 dev_dbg(otg->dev, "charger = %d\n", motg->chg_type);
1094                 schedule_work(&motg->sm_work);
1095                 return;
1096         default:
1097                 return;
1098         }
1099
1100         schedule_delayed_work(&motg->chg_work, delay);
1101 }
1102
1103 /*
1104  * We support OTG, Peripheral only and Host only configurations. In case
1105  * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1106  * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1107  * enabled when switch is controlled by user and default mode is supplied
1108  * by board file, which can be changed by userspace later.
1109  */
1110 static void msm_otg_init_sm(struct msm_otg *motg)
1111 {
1112         struct msm_otg_platform_data *pdata = motg->pdata;
1113         u32 otgsc = readl(USB_OTGSC);
1114
1115         switch (pdata->mode) {
1116         case USB_OTG:
1117                 if (pdata->otg_control == OTG_PHY_CONTROL) {
1118                         if (otgsc & OTGSC_ID)
1119                                 set_bit(ID, &motg->inputs);
1120                         else
1121                                 clear_bit(ID, &motg->inputs);
1122
1123                         if (otgsc & OTGSC_BSV)
1124                                 set_bit(B_SESS_VLD, &motg->inputs);
1125                         else
1126                                 clear_bit(B_SESS_VLD, &motg->inputs);
1127                 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1128                         if (pdata->default_mode == USB_HOST) {
1129                                 clear_bit(ID, &motg->inputs);
1130                         } else if (pdata->default_mode == USB_PERIPHERAL) {
1131                                 set_bit(ID, &motg->inputs);
1132                                 set_bit(B_SESS_VLD, &motg->inputs);
1133                         } else {
1134                                 set_bit(ID, &motg->inputs);
1135                                 clear_bit(B_SESS_VLD, &motg->inputs);
1136                         }
1137                 }
1138                 break;
1139         case USB_HOST:
1140                 clear_bit(ID, &motg->inputs);
1141                 break;
1142         case USB_PERIPHERAL:
1143                 set_bit(ID, &motg->inputs);
1144                 if (otgsc & OTGSC_BSV)
1145                         set_bit(B_SESS_VLD, &motg->inputs);
1146                 else
1147                         clear_bit(B_SESS_VLD, &motg->inputs);
1148                 break;
1149         default:
1150                 break;
1151         }
1152 }
1153
1154 static void msm_otg_sm_work(struct work_struct *w)
1155 {
1156         struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1157         struct otg_transceiver *otg = &motg->otg;
1158
1159         switch (otg->state) {
1160         case OTG_STATE_UNDEFINED:
1161                 dev_dbg(otg->dev, "OTG_STATE_UNDEFINED state\n");
1162                 msm_otg_reset(otg);
1163                 msm_otg_init_sm(motg);
1164                 otg->state = OTG_STATE_B_IDLE;
1165                 /* FALL THROUGH */
1166         case OTG_STATE_B_IDLE:
1167                 dev_dbg(otg->dev, "OTG_STATE_B_IDLE state\n");
1168                 if (!test_bit(ID, &motg->inputs) && otg->host) {
1169                         /* disable BSV bit */
1170                         writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1171                         msm_otg_start_host(otg, 1);
1172                         otg->state = OTG_STATE_A_HOST;
1173                 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1174                         switch (motg->chg_state) {
1175                         case USB_CHG_STATE_UNDEFINED:
1176                                 msm_chg_detect_work(&motg->chg_work.work);
1177                                 break;
1178                         case USB_CHG_STATE_DETECTED:
1179                                 switch (motg->chg_type) {
1180                                 case USB_DCP_CHARGER:
1181                                         msm_otg_notify_charger(motg,
1182                                                         IDEV_CHG_MAX);
1183                                         break;
1184                                 case USB_CDP_CHARGER:
1185                                         msm_otg_notify_charger(motg,
1186                                                         IDEV_CHG_MAX);
1187                                         msm_otg_start_peripheral(otg, 1);
1188                                         otg->state = OTG_STATE_B_PERIPHERAL;
1189                                         break;
1190                                 case USB_SDP_CHARGER:
1191                                         msm_otg_notify_charger(motg, IUNIT);
1192                                         msm_otg_start_peripheral(otg, 1);
1193                                         otg->state = OTG_STATE_B_PERIPHERAL;
1194                                         break;
1195                                 default:
1196                                         break;
1197                                 }
1198                                 break;
1199                         default:
1200                                 break;
1201                         }
1202                 } else {
1203                         /*
1204                          * If charger detection work is pending, decrement
1205                          * the pm usage counter to balance with the one that
1206                          * is incremented in charger detection work.
1207                          */
1208                         if (cancel_delayed_work_sync(&motg->chg_work)) {
1209                                 pm_runtime_put_sync(otg->dev);
1210                                 msm_otg_reset(otg);
1211                         }
1212                         msm_otg_notify_charger(motg, 0);
1213                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1214                         motg->chg_type = USB_INVALID_CHARGER;
1215                 }
1216                 pm_runtime_put_sync(otg->dev);
1217                 break;
1218         case OTG_STATE_B_PERIPHERAL:
1219                 dev_dbg(otg->dev, "OTG_STATE_B_PERIPHERAL state\n");
1220                 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1221                                 !test_bit(ID, &motg->inputs)) {
1222                         msm_otg_notify_charger(motg, 0);
1223                         msm_otg_start_peripheral(otg, 0);
1224                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1225                         motg->chg_type = USB_INVALID_CHARGER;
1226                         otg->state = OTG_STATE_B_IDLE;
1227                         msm_otg_reset(otg);
1228                         schedule_work(w);
1229                 }
1230                 break;
1231         case OTG_STATE_A_HOST:
1232                 dev_dbg(otg->dev, "OTG_STATE_A_HOST state\n");
1233                 if (test_bit(ID, &motg->inputs)) {
1234                         msm_otg_start_host(otg, 0);
1235                         otg->state = OTG_STATE_B_IDLE;
1236                         msm_otg_reset(otg);
1237                         schedule_work(w);
1238                 }
1239                 break;
1240         default:
1241                 break;
1242         }
1243 }
1244
1245 static irqreturn_t msm_otg_irq(int irq, void *data)
1246 {
1247         struct msm_otg *motg = data;
1248         struct otg_transceiver *otg = &motg->otg;
1249         u32 otgsc = 0;
1250
1251         if (atomic_read(&motg->in_lpm)) {
1252                 disable_irq_nosync(irq);
1253                 motg->async_int = 1;
1254                 pm_runtime_get(otg->dev);
1255                 return IRQ_HANDLED;
1256         }
1257
1258         otgsc = readl(USB_OTGSC);
1259         if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1260                 return IRQ_NONE;
1261
1262         if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1263                 if (otgsc & OTGSC_ID)
1264                         set_bit(ID, &motg->inputs);
1265                 else
1266                         clear_bit(ID, &motg->inputs);
1267                 dev_dbg(otg->dev, "ID set/clear\n");
1268                 pm_runtime_get_noresume(otg->dev);
1269         } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1270                 if (otgsc & OTGSC_BSV)
1271                         set_bit(B_SESS_VLD, &motg->inputs);
1272                 else
1273                         clear_bit(B_SESS_VLD, &motg->inputs);
1274                 dev_dbg(otg->dev, "BSV set/clear\n");
1275                 pm_runtime_get_noresume(otg->dev);
1276         }
1277
1278         writel(otgsc, USB_OTGSC);
1279         schedule_work(&motg->sm_work);
1280         return IRQ_HANDLED;
1281 }
1282
1283 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1284 {
1285         struct msm_otg *motg = s->private;
1286         struct otg_transceiver *otg = &motg->otg;
1287
1288         switch (otg->state) {
1289         case OTG_STATE_A_HOST:
1290                 seq_printf(s, "host\n");
1291                 break;
1292         case OTG_STATE_B_PERIPHERAL:
1293                 seq_printf(s, "peripheral\n");
1294                 break;
1295         default:
1296                 seq_printf(s, "none\n");
1297                 break;
1298         }
1299
1300         return 0;
1301 }
1302
1303 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1304 {
1305         return single_open(file, msm_otg_mode_show, inode->i_private);
1306 }
1307
1308 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1309                                 size_t count, loff_t *ppos)
1310 {
1311         struct seq_file *s = file->private_data;
1312         struct msm_otg *motg = s->private;
1313         char buf[16];
1314         struct otg_transceiver *otg = &motg->otg;
1315         int status = count;
1316         enum usb_mode_type req_mode;
1317
1318         memset(buf, 0x00, sizeof(buf));
1319
1320         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1321                 status = -EFAULT;
1322                 goto out;
1323         }
1324
1325         if (!strncmp(buf, "host", 4)) {
1326                 req_mode = USB_HOST;
1327         } else if (!strncmp(buf, "peripheral", 10)) {
1328                 req_mode = USB_PERIPHERAL;
1329         } else if (!strncmp(buf, "none", 4)) {
1330                 req_mode = USB_NONE;
1331         } else {
1332                 status = -EINVAL;
1333                 goto out;
1334         }
1335
1336         switch (req_mode) {
1337         case USB_NONE:
1338                 switch (otg->state) {
1339                 case OTG_STATE_A_HOST:
1340                 case OTG_STATE_B_PERIPHERAL:
1341                         set_bit(ID, &motg->inputs);
1342                         clear_bit(B_SESS_VLD, &motg->inputs);
1343                         break;
1344                 default:
1345                         goto out;
1346                 }
1347                 break;
1348         case USB_PERIPHERAL:
1349                 switch (otg->state) {
1350                 case OTG_STATE_B_IDLE:
1351                 case OTG_STATE_A_HOST:
1352                         set_bit(ID, &motg->inputs);
1353                         set_bit(B_SESS_VLD, &motg->inputs);
1354                         break;
1355                 default:
1356                         goto out;
1357                 }
1358                 break;
1359         case USB_HOST:
1360                 switch (otg->state) {
1361                 case OTG_STATE_B_IDLE:
1362                 case OTG_STATE_B_PERIPHERAL:
1363                         clear_bit(ID, &motg->inputs);
1364                         break;
1365                 default:
1366                         goto out;
1367                 }
1368                 break;
1369         default:
1370                 goto out;
1371         }
1372
1373         pm_runtime_get_sync(otg->dev);
1374         schedule_work(&motg->sm_work);
1375 out:
1376         return status;
1377 }
1378
1379 const struct file_operations msm_otg_mode_fops = {
1380         .open = msm_otg_mode_open,
1381         .read = seq_read,
1382         .write = msm_otg_mode_write,
1383         .llseek = seq_lseek,
1384         .release = single_release,
1385 };
1386
1387 static struct dentry *msm_otg_dbg_root;
1388 static struct dentry *msm_otg_dbg_mode;
1389
1390 static int msm_otg_debugfs_init(struct msm_otg *motg)
1391 {
1392         msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1393
1394         if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1395                 return -ENODEV;
1396
1397         msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1398                                 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1399         if (!msm_otg_dbg_mode) {
1400                 debugfs_remove(msm_otg_dbg_root);
1401                 msm_otg_dbg_root = NULL;
1402                 return -ENODEV;
1403         }
1404
1405         return 0;
1406 }
1407
1408 static void msm_otg_debugfs_cleanup(void)
1409 {
1410         debugfs_remove(msm_otg_dbg_mode);
1411         debugfs_remove(msm_otg_dbg_root);
1412 }
1413
1414 static int __init msm_otg_probe(struct platform_device *pdev)
1415 {
1416         int ret = 0;
1417         struct resource *res;
1418         struct msm_otg *motg;
1419         struct otg_transceiver *otg;
1420
1421         dev_info(&pdev->dev, "msm_otg probe\n");
1422         if (!pdev->dev.platform_data) {
1423                 dev_err(&pdev->dev, "No platform data given. Bailing out\n");
1424                 return -ENODEV;
1425         }
1426
1427         motg = kzalloc(sizeof(struct msm_otg), GFP_KERNEL);
1428         if (!motg) {
1429                 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1430                 return -ENOMEM;
1431         }
1432
1433         motg->pdata = pdev->dev.platform_data;
1434         otg = &motg->otg;
1435         otg->dev = &pdev->dev;
1436
1437         motg->phy_reset_clk = clk_get(&pdev->dev, "usb_phy_clk");
1438         if (IS_ERR(motg->phy_reset_clk)) {
1439                 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
1440                 ret = PTR_ERR(motg->phy_reset_clk);
1441                 goto free_motg;
1442         }
1443
1444         motg->clk = clk_get(&pdev->dev, "usb_hs_clk");
1445         if (IS_ERR(motg->clk)) {
1446                 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1447                 ret = PTR_ERR(motg->clk);
1448                 goto put_phy_reset_clk;
1449         }
1450         clk_set_rate(motg->clk, 60000000);
1451
1452         /*
1453          * If USB Core is running its protocol engine based on CORE CLK,
1454          * CORE CLK  must be running at >55Mhz for correct HSUSB
1455          * operation and USB core cannot tolerate frequency changes on
1456          * CORE CLK. For such USB cores, vote for maximum clk frequency
1457          * on pclk source
1458          */
1459          if (motg->pdata->pclk_src_name) {
1460                 motg->pclk_src = clk_get(&pdev->dev,
1461                         motg->pdata->pclk_src_name);
1462                 if (IS_ERR(motg->pclk_src))
1463                         goto put_clk;
1464                 clk_set_rate(motg->pclk_src, INT_MAX);
1465                 clk_enable(motg->pclk_src);
1466         } else
1467                 motg->pclk_src = ERR_PTR(-ENOENT);
1468
1469
1470         motg->pclk = clk_get(&pdev->dev, "usb_hs_pclk");
1471         if (IS_ERR(motg->pclk)) {
1472                 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1473                 ret = PTR_ERR(motg->pclk);
1474                 goto put_pclk_src;
1475         }
1476
1477         /*
1478          * USB core clock is not present on all MSM chips. This
1479          * clock is introduced to remove the dependency on AXI
1480          * bus frequency.
1481          */
1482         motg->core_clk = clk_get(&pdev->dev, "usb_hs_core_clk");
1483         if (IS_ERR(motg->core_clk))
1484                 motg->core_clk = NULL;
1485
1486         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1487         if (!res) {
1488                 dev_err(&pdev->dev, "failed to get platform resource mem\n");
1489                 ret = -ENODEV;
1490                 goto put_core_clk;
1491         }
1492
1493         motg->regs = ioremap(res->start, resource_size(res));
1494         if (!motg->regs) {
1495                 dev_err(&pdev->dev, "ioremap failed\n");
1496                 ret = -ENOMEM;
1497                 goto put_core_clk;
1498         }
1499         dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1500
1501         motg->irq = platform_get_irq(pdev, 0);
1502         if (!motg->irq) {
1503                 dev_err(&pdev->dev, "platform_get_irq failed\n");
1504                 ret = -ENODEV;
1505                 goto free_regs;
1506         }
1507
1508         clk_enable(motg->clk);
1509         clk_enable(motg->pclk);
1510
1511         ret = msm_hsusb_init_vddcx(motg, 1);
1512         if (ret) {
1513                 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1514                 goto free_regs;
1515         }
1516
1517         ret = msm_hsusb_ldo_init(motg, 1);
1518         if (ret) {
1519                 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1520                 goto vddcx_exit;
1521         }
1522         ret = msm_hsusb_ldo_set_mode(1);
1523         if (ret) {
1524                 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1525                 goto ldo_exit;
1526         }
1527
1528         if (motg->core_clk)
1529                 clk_enable(motg->core_clk);
1530
1531         writel(0, USB_USBINTR);
1532         writel(0, USB_OTGSC);
1533
1534         INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1535         INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1536         ret = request_irq(motg->irq, msm_otg_irq, IRQF_SHARED,
1537                                         "msm_otg", motg);
1538         if (ret) {
1539                 dev_err(&pdev->dev, "request irq failed\n");
1540                 goto disable_clks;
1541         }
1542
1543         otg->init = msm_otg_reset;
1544         otg->set_host = msm_otg_set_host;
1545         otg->set_peripheral = msm_otg_set_peripheral;
1546         otg->set_power = msm_otg_set_power;
1547
1548         otg->io_ops = &msm_otg_io_ops;
1549
1550         ret = otg_set_transceiver(&motg->otg);
1551         if (ret) {
1552                 dev_err(&pdev->dev, "otg_set_transceiver failed\n");
1553                 goto free_irq;
1554         }
1555
1556         platform_set_drvdata(pdev, motg);
1557         device_init_wakeup(&pdev->dev, 1);
1558
1559         if (motg->pdata->mode == USB_OTG &&
1560                         motg->pdata->otg_control == OTG_USER_CONTROL) {
1561                 ret = msm_otg_debugfs_init(motg);
1562                 if (ret)
1563                         dev_dbg(&pdev->dev, "mode debugfs file is"
1564                                         "not available\n");
1565         }
1566
1567         pm_runtime_set_active(&pdev->dev);
1568         pm_runtime_enable(&pdev->dev);
1569
1570         return 0;
1571 free_irq:
1572         free_irq(motg->irq, motg);
1573 disable_clks:
1574         clk_disable(motg->pclk);
1575         clk_disable(motg->clk);
1576 ldo_exit:
1577         msm_hsusb_ldo_init(motg, 0);
1578 vddcx_exit:
1579         msm_hsusb_init_vddcx(motg, 0);
1580 free_regs:
1581         iounmap(motg->regs);
1582 put_core_clk:
1583         if (motg->core_clk)
1584                 clk_put(motg->core_clk);
1585         clk_put(motg->pclk);
1586 put_pclk_src:
1587         if (!IS_ERR(motg->pclk_src)) {
1588                 clk_disable(motg->pclk_src);
1589                 clk_put(motg->pclk_src);
1590         }
1591 put_clk:
1592         clk_put(motg->clk);
1593 put_phy_reset_clk:
1594         clk_put(motg->phy_reset_clk);
1595 free_motg:
1596         kfree(motg);
1597         return ret;
1598 }
1599
1600 static int __devexit msm_otg_remove(struct platform_device *pdev)
1601 {
1602         struct msm_otg *motg = platform_get_drvdata(pdev);
1603         struct otg_transceiver *otg = &motg->otg;
1604         int cnt = 0;
1605
1606         if (otg->host || otg->gadget)
1607                 return -EBUSY;
1608
1609         msm_otg_debugfs_cleanup();
1610         cancel_delayed_work_sync(&motg->chg_work);
1611         cancel_work_sync(&motg->sm_work);
1612
1613         pm_runtime_resume(&pdev->dev);
1614
1615         device_init_wakeup(&pdev->dev, 0);
1616         pm_runtime_disable(&pdev->dev);
1617
1618         otg_set_transceiver(NULL);
1619         free_irq(motg->irq, motg);
1620
1621         /*
1622          * Put PHY in low power mode.
1623          */
1624         ulpi_read(otg, 0x14);
1625         ulpi_write(otg, 0x08, 0x09);
1626
1627         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1628         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1629                 if (readl(USB_PORTSC) & PORTSC_PHCD)
1630                         break;
1631                 udelay(1);
1632                 cnt++;
1633         }
1634         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1635                 dev_err(otg->dev, "Unable to suspend PHY\n");
1636
1637         clk_disable(motg->pclk);
1638         clk_disable(motg->clk);
1639         if (motg->core_clk)
1640                 clk_disable(motg->core_clk);
1641         if (!IS_ERR(motg->pclk_src)) {
1642                 clk_disable(motg->pclk_src);
1643                 clk_put(motg->pclk_src);
1644         }
1645         msm_hsusb_ldo_init(motg, 0);
1646
1647         iounmap(motg->regs);
1648         pm_runtime_set_suspended(&pdev->dev);
1649
1650         clk_put(motg->phy_reset_clk);
1651         clk_put(motg->pclk);
1652         clk_put(motg->clk);
1653         if (motg->core_clk)
1654                 clk_put(motg->core_clk);
1655
1656         kfree(motg);
1657
1658         return 0;
1659 }
1660
1661 #ifdef CONFIG_PM_RUNTIME
1662 static int msm_otg_runtime_idle(struct device *dev)
1663 {
1664         struct msm_otg *motg = dev_get_drvdata(dev);
1665         struct otg_transceiver *otg = &motg->otg;
1666
1667         dev_dbg(dev, "OTG runtime idle\n");
1668
1669         /*
1670          * It is observed some times that a spurious interrupt
1671          * comes when PHY is put into LPM immediately after PHY reset.
1672          * This 1 sec delay also prevents entering into LPM immediately
1673          * after asynchronous interrupt.
1674          */
1675         if (otg->state != OTG_STATE_UNDEFINED)
1676                 pm_schedule_suspend(dev, 1000);
1677
1678         return -EAGAIN;
1679 }
1680
1681 static int msm_otg_runtime_suspend(struct device *dev)
1682 {
1683         struct msm_otg *motg = dev_get_drvdata(dev);
1684
1685         dev_dbg(dev, "OTG runtime suspend\n");
1686         return msm_otg_suspend(motg);
1687 }
1688
1689 static int msm_otg_runtime_resume(struct device *dev)
1690 {
1691         struct msm_otg *motg = dev_get_drvdata(dev);
1692
1693         dev_dbg(dev, "OTG runtime resume\n");
1694         return msm_otg_resume(motg);
1695 }
1696 #endif
1697
1698 #ifdef CONFIG_PM_SLEEP
1699 static int msm_otg_pm_suspend(struct device *dev)
1700 {
1701         struct msm_otg *motg = dev_get_drvdata(dev);
1702
1703         dev_dbg(dev, "OTG PM suspend\n");
1704         return msm_otg_suspend(motg);
1705 }
1706
1707 static int msm_otg_pm_resume(struct device *dev)
1708 {
1709         struct msm_otg *motg = dev_get_drvdata(dev);
1710         int ret;
1711
1712         dev_dbg(dev, "OTG PM resume\n");
1713
1714         ret = msm_otg_resume(motg);
1715         if (ret)
1716                 return ret;
1717
1718         /*
1719          * Runtime PM Documentation recommends bringing the
1720          * device to full powered state upon resume.
1721          */
1722         pm_runtime_disable(dev);
1723         pm_runtime_set_active(dev);
1724         pm_runtime_enable(dev);
1725
1726         return 0;
1727 }
1728 #endif
1729
1730 #ifdef CONFIG_PM
1731 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1732         SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1733         SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1734                                 msm_otg_runtime_idle)
1735 };
1736 #endif
1737
1738 static struct platform_driver msm_otg_driver = {
1739         .remove = __devexit_p(msm_otg_remove),
1740         .driver = {
1741                 .name = DRIVER_NAME,
1742                 .owner = THIS_MODULE,
1743 #ifdef CONFIG_PM
1744                 .pm = &msm_otg_dev_pm_ops,
1745 #endif
1746         },
1747 };
1748
1749 static int __init msm_otg_init(void)
1750 {
1751         return platform_driver_probe(&msm_otg_driver, msm_otg_probe);
1752 }
1753
1754 static void __exit msm_otg_exit(void)
1755 {
1756         platform_driver_unregister(&msm_otg_driver);
1757 }
1758
1759 module_init(msm_otg_init);
1760 module_exit(msm_otg_exit);
1761
1762 MODULE_LICENSE("GPL v2");
1763 MODULE_DESCRIPTION("MSM USB transceiver driver");