1 // SPDX-License-Identifier: GPL-2.0+
3 * Microchip PIC32 MUSB "glue layer"
5 * Copyright (C) 2015, Microchip Technology Inc.
6 * Cristian Birsan <cristian.birsan@microchip.com>
7 * Purna Chandra Mandal <purna.mandal@microchip.com>
9 * Based on the dsps "glue layer" code.
13 #include <dm/device_compat.h>
14 #include <linux/delay.h>
15 #include <linux/usb/musb.h>
16 #include "linux-compat.h"
17 #include "musb_core.h"
18 #include "musb_uboot.h"
20 DECLARE_GLOBAL_DATA_PTR;
22 #define PIC32_TX_EP_MASK 0x0f /* EP0 + 7 Tx EPs */
23 #define PIC32_RX_EP_MASK 0x0e /* 7 Rx EPs */
25 #define MUSB_SOFTRST 0x7f
26 #define MUSB_SOFTRST_NRST BIT(0)
27 #define MUSB_SOFTRST_NRSTX BIT(1)
30 #define USBCRCON_USBWKUPEN BIT(0) /* Enable Wakeup Interrupt */
31 #define USBCRCON_USBRIE BIT(1) /* Enable Remote resume Interrupt */
32 #define USBCRCON_USBIE BIT(2) /* Enable USB General interrupt */
33 #define USBCRCON_SENDMONEN BIT(3) /* Enable Session End VBUS monitoring */
34 #define USBCRCON_BSVALMONEN BIT(4) /* Enable B-Device VBUS monitoring */
35 #define USBCRCON_ASVALMONEN BIT(5) /* Enable A-Device VBUS monitoring */
36 #define USBCRCON_VBUSMONEN BIT(6) /* Enable VBUS monitoring */
37 #define USBCRCON_PHYIDEN BIT(7) /* PHY ID monitoring enable */
38 #define USBCRCON_USBIDVAL BIT(8) /* USB ID value */
39 #define USBCRCON_USBIDOVEN BIT(9) /* USB ID override enable */
40 #define USBCRCON_USBWK BIT(24) /* USB Wakeup Status */
41 #define USBCRCON_USBRF BIT(25) /* USB Resume Status */
42 #define USBCRCON_USBIF BIT(26) /* USB General Interrupt Status */
44 /* PIC32 controller data */
45 struct pic32_musb_data {
46 struct musb_host_data mdata;
48 void __iomem *musb_glue;
51 #define to_pic32_musb_data(d) \
52 container_of(d, struct pic32_musb_data, dev)
54 static void pic32_musb_disable(struct musb *musb)
56 /* no way to shut the controller */
59 static int pic32_musb_enable(struct musb *musb)
61 /* soft reset by NRSTx */
62 musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
64 musb_platform_set_mode(musb, musb->board_mode);
69 static irqreturn_t pic32_interrupt(int irq, void *hci)
71 struct musb *musb = hci;
72 irqreturn_t ret = IRQ_NONE;
75 /* ack usb core interrupts */
76 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
78 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
80 /* ack endpoint interrupts */
81 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX) & PIC32_RX_EP_MASK;
83 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
85 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX) & PIC32_TX_EP_MASK;
87 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
89 /* drop spurious RX and TX if device is disconnected */
90 if (musb->int_usb & MUSB_INTR_DISCONNECT) {
95 if (musb->int_tx || musb->int_rx || musb->int_usb)
96 ret = musb_interrupt(musb);
101 static int pic32_musb_set_mode(struct musb *musb, u8 mode)
103 struct device *dev = musb->controller;
104 struct pic32_musb_data *pdata = to_pic32_musb_data(dev);
108 clrsetbits_le32(pdata->musb_glue + USBCRCON,
109 USBCRCON_USBIDVAL, USBCRCON_USBIDOVEN);
111 case MUSB_PERIPHERAL:
112 setbits_le32(pdata->musb_glue + USBCRCON,
113 USBCRCON_USBIDVAL | USBCRCON_USBIDOVEN);
116 dev_err(dev, "support for OTG is unimplemented\n");
119 dev_err(dev, "unsupported mode %d\n", mode);
126 static int pic32_musb_init(struct musb *musb)
128 struct pic32_musb_data *pdata = to_pic32_musb_data(musb->controller);
132 /* Returns zero if not clocked */
133 hwvers = musb_read_hwvers(musb->mregs);
138 power = musb_readb(musb->mregs, MUSB_POWER);
139 power = power | MUSB_POWER_RESET;
140 musb_writeb(musb->mregs, MUSB_POWER, power);
143 /* Start the on-chip PHY and its PLL. */
144 power = power & ~MUSB_POWER_RESET;
145 musb_writeb(musb->mregs, MUSB_POWER, power);
147 musb->isr = pic32_interrupt;
149 ctrl = USBCRCON_USBIF | USBCRCON_USBRF |
150 USBCRCON_USBWK | USBCRCON_USBIDOVEN |
151 USBCRCON_PHYIDEN | USBCRCON_USBIE |
152 USBCRCON_USBRIE | USBCRCON_USBWKUPEN |
154 writel(ctrl, pdata->musb_glue + USBCRCON);
159 /* PIC32 supports only 32bit read operation */
160 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
162 void __iomem *fifo = hw_ep->fifo;
163 u32 val, rem = len % 4;
165 /* USB stack ensures dst is always 32bit aligned. */
166 readsl(fifo, dst, len / 4);
169 val = musb_readl(fifo, 0);
170 memcpy(dst, &val, rem);
174 const struct musb_platform_ops pic32_musb_ops = {
175 .init = pic32_musb_init,
176 .set_mode = pic32_musb_set_mode,
177 .disable = pic32_musb_disable,
178 .enable = pic32_musb_enable,
181 /* PIC32 default FIFO config - fits in 8KB */
182 static struct musb_fifo_cfg pic32_musb_fifo_config[] = {
183 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
184 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
185 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
186 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
187 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
188 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
189 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
190 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
191 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
192 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
193 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
194 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
195 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
196 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
199 static struct musb_hdrc_config pic32_musb_config = {
200 .fifo_cfg = pic32_musb_fifo_config,
201 .fifo_cfg_size = ARRAY_SIZE(pic32_musb_fifo_config),
208 /* PIC32 has one MUSB controller which can be host or gadget */
209 static struct musb_hdrc_platform_data pic32_musb_plat = {
211 .config = &pic32_musb_config,
212 .power = 250, /* 500mA */
213 .platform_ops = &pic32_musb_ops,
216 static int musb_usb_probe(struct udevice *dev)
218 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
219 struct pic32_musb_data *pdata = dev_get_priv(dev);
220 struct musb_host_data *mdata = &pdata->mdata;
221 struct fdt_resource mc, glue;
222 void *fdt = (void *)gd->fdt_blob;
223 int node = dev_of_offset(dev);
227 priv->desc_before_addr = true;
229 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
232 printf("pic32-musb: resource \"mc\" not found\n");
236 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
239 printf("pic32-musb: resource \"control\" not found\n");
243 mregs = ioremap(mc.start, fdt_resource_size(&mc));
244 pdata->musb_glue = ioremap(glue.start, fdt_resource_size(&glue));
246 /* init controller */
247 #ifdef CONFIG_USB_MUSB_HOST
248 mdata->host = musb_init_controller(&pic32_musb_plat,
253 ret = musb_lowlevel_init(mdata);
255 pic32_musb_plat.mode = MUSB_PERIPHERAL;
256 mdata->host = musb_register(&pic32_musb_plat, &pdata->dev, mregs);
260 if ((ret == 0) && mdata->host)
261 printf("PIC32 MUSB OTG\n");
266 static int musb_usb_remove(struct udevice *dev)
268 struct pic32_musb_data *pdata = dev_get_priv(dev);
270 musb_stop(pdata->mdata.host);
275 static const struct udevice_id pic32_musb_ids[] = {
276 { .compatible = "microchip,pic32mzda-usb" },
280 U_BOOT_DRIVER(usb_musb) = {
281 .name = "pic32-musb",
283 .of_match = pic32_musb_ids,
284 .probe = musb_usb_probe,
285 .remove = musb_usb_remove,
286 #ifdef CONFIG_USB_MUSB_HOST
287 .ops = &musb_usb_ops,
289 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
290 .priv_auto_alloc_size = sizeof(struct pic32_musb_data),