2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
119 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
120 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
125 #define MUSB_VERSION "6.0"
127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
129 #define MUSB_DRIVER_NAME "musb_hdrc"
130 const char musb_driver_name[] = MUSB_DRIVER_NAME;
132 MODULE_DESCRIPTION(DRIVER_INFO);
133 MODULE_AUTHOR(DRIVER_AUTHOR);
134 MODULE_LICENSE("GPL");
135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
138 /*-------------------------------------------------------------------------*/
140 static inline struct musb *dev_to_musb(struct device *dev)
142 #ifdef CONFIG_USB_MUSB_HDRC_HCD
143 /* usbcore insists dev->driver_data is a "struct hcd *" */
144 return hcd_to_musb(dev_get_drvdata(dev));
146 return dev_get_drvdata(dev);
150 /*-------------------------------------------------------------------------*/
152 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
155 * Load an endpoint's FIFO
157 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
159 void __iomem *fifo = hw_ep->fifo;
163 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
164 'T', hw_ep->epnum, fifo, len, src);
166 /* we can't assume unaligned reads work */
167 if (likely((0x01 & (unsigned long) src) == 0)) {
170 /* best case is 32bit-aligned source address */
171 if ((0x02 & (unsigned long) src) == 0) {
173 writesl(fifo, src + index, len >> 2);
174 index += len & ~0x03;
177 musb_writew(fifo, 0, *(u16 *)&src[index]);
182 writesw(fifo, src + index, len >> 1);
183 index += len & ~0x01;
187 musb_writeb(fifo, 0, src[index]);
190 writesb(fifo, src, len);
195 * Unload an endpoint's FIFO
197 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
199 void __iomem *fifo = hw_ep->fifo;
201 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
202 'R', hw_ep->epnum, fifo, len, dst);
204 /* we can't assume unaligned writes work */
205 if (likely((0x01 & (unsigned long) dst) == 0)) {
208 /* best case is 32bit-aligned destination address */
209 if ((0x02 & (unsigned long) dst) == 0) {
211 readsl(fifo, dst, len >> 2);
215 *(u16 *)&dst[index] = musb_readw(fifo, 0);
220 readsw(fifo, dst, len >> 1);
225 dst[index] = musb_readb(fifo, 0);
228 readsb(fifo, dst, len);
232 #endif /* normal PIO */
235 /*-------------------------------------------------------------------------*/
237 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
238 static const u8 musb_test_packet[53] = {
239 /* implicit SYNC then DATA0 to start */
242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
244 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
246 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
247 /* JJJJJJJKKKKKKK x8 */
248 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
250 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
251 /* JKKKKKKK x10, JK */
252 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
254 /* implicit CRC16 then EOP to end */
257 void musb_load_testpacket(struct musb *musb)
259 void __iomem *regs = musb->endpoints[0].regs;
261 musb_ep_select(musb->mregs, 0);
262 musb_write_fifo(musb->control_ep,
263 sizeof(musb_test_packet), musb_test_packet);
264 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
267 /*-------------------------------------------------------------------------*/
269 const char *otg_state_string(struct musb *musb)
271 switch (musb->xceiv->state) {
272 case OTG_STATE_A_IDLE: return "a_idle";
273 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
274 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
275 case OTG_STATE_A_HOST: return "a_host";
276 case OTG_STATE_A_SUSPEND: return "a_suspend";
277 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
278 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
279 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
280 case OTG_STATE_B_IDLE: return "b_idle";
281 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
282 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
283 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
284 case OTG_STATE_B_HOST: return "b_host";
285 default: return "UNDEFINED";
289 #ifdef CONFIG_USB_MUSB_OTG
292 * Handles OTG hnp timeouts, such as b_ase0_brst
294 void musb_otg_timer_func(unsigned long data)
296 struct musb *musb = (struct musb *)data;
299 spin_lock_irqsave(&musb->lock, flags);
300 switch (musb->xceiv->state) {
301 case OTG_STATE_B_WAIT_ACON:
302 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
303 musb_g_disconnect(musb);
304 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
307 case OTG_STATE_A_SUSPEND:
308 case OTG_STATE_A_WAIT_BCON:
309 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
310 musb_set_vbus(musb, 0);
311 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
314 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
316 musb->ignore_disconnect = 0;
317 spin_unlock_irqrestore(&musb->lock, flags);
321 * Stops the HNP transition. Caller must take care of locking.
323 void musb_hnp_stop(struct musb *musb)
325 struct usb_hcd *hcd = musb_to_hcd(musb);
326 void __iomem *mbase = musb->mregs;
329 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
331 switch (musb->xceiv->state) {
332 case OTG_STATE_A_PERIPHERAL:
333 musb_g_disconnect(musb);
334 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
336 case OTG_STATE_B_HOST:
337 DBG(1, "HNP: Disabling HR\n");
338 hcd->self.is_b_host = 0;
339 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
341 reg = musb_readb(mbase, MUSB_POWER);
342 reg |= MUSB_POWER_SUSPENDM;
343 musb_writeb(mbase, MUSB_POWER, reg);
344 /* REVISIT: Start SESSION_REQUEST here? */
347 DBG(1, "HNP: Stopping in unknown state %s\n",
348 otg_state_string(musb));
352 * When returning to A state after HNP, avoid hub_port_rebounce(),
353 * which cause occasional OPT A "Did not receive reset after connect"
356 musb->port1_status &=
357 ~(1 << USB_PORT_FEAT_C_CONNECTION);
363 * Interrupt Service Routine to record USB "global" interrupts.
364 * Since these do not happen often and signify things of
365 * paramount importance, it seems OK to check them individually;
366 * the order of the tests is specified in the manual
368 * @param musb instance pointer
369 * @param int_usb register contents
374 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
375 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
378 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
381 irqreturn_t handled = IRQ_NONE;
382 void __iomem *mbase = musb->mregs;
384 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
387 /* in host mode, the peripheral may issue remote wakeup.
388 * in peripheral mode, the host may resume the link.
389 * spurious RESUME irqs happen too, paired with SUSPEND.
391 if (int_usb & MUSB_INTR_RESUME) {
392 handled = IRQ_HANDLED;
393 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
395 if (devctl & MUSB_DEVCTL_HM) {
396 #ifdef CONFIG_USB_MUSB_HDRC_HCD
397 switch (musb->xceiv->state) {
398 case OTG_STATE_A_SUSPEND:
399 /* remote wakeup? later, GetPortStatus
400 * will stop RESUME signaling
403 if (power & MUSB_POWER_SUSPENDM) {
405 musb->int_usb &= ~MUSB_INTR_SUSPEND;
406 DBG(2, "Spurious SUSPENDM\n");
410 power &= ~MUSB_POWER_SUSPENDM;
411 musb_writeb(mbase, MUSB_POWER,
412 power | MUSB_POWER_RESUME);
414 musb->port1_status |=
415 (USB_PORT_STAT_C_SUSPEND << 16)
416 | MUSB_PORT_STAT_RESUME;
417 musb->rh_timer = jiffies
418 + msecs_to_jiffies(20);
420 musb->xceiv->state = OTG_STATE_A_HOST;
422 usb_hcd_resume_root_hub(musb_to_hcd(musb));
424 case OTG_STATE_B_WAIT_ACON:
425 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
430 WARNING("bogus %s RESUME (%s)\n",
432 otg_state_string(musb));
436 switch (musb->xceiv->state) {
437 #ifdef CONFIG_USB_MUSB_HDRC_HCD
438 case OTG_STATE_A_SUSPEND:
439 /* possibly DISCONNECT is upcoming */
440 musb->xceiv->state = OTG_STATE_A_HOST;
441 usb_hcd_resume_root_hub(musb_to_hcd(musb));
444 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
445 case OTG_STATE_B_WAIT_ACON:
446 case OTG_STATE_B_PERIPHERAL:
447 /* disconnect while suspended? we may
448 * not get a disconnect irq...
450 if ((devctl & MUSB_DEVCTL_VBUS)
451 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
453 musb->int_usb |= MUSB_INTR_DISCONNECT;
454 musb->int_usb &= ~MUSB_INTR_SUSPEND;
459 case OTG_STATE_B_IDLE:
460 musb->int_usb &= ~MUSB_INTR_SUSPEND;
464 WARNING("bogus %s RESUME (%s)\n",
466 otg_state_string(musb));
471 #ifdef CONFIG_USB_MUSB_HDRC_HCD
472 /* see manual for the order of the tests */
473 if (int_usb & MUSB_INTR_SESSREQ) {
474 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
476 /* IRQ arrives from ID pin sense or (later, if VBUS power
477 * is removed) SRP. responses are time critical:
478 * - turn on VBUS (with silicon-specific mechanism)
479 * - go through A_WAIT_VRISE
480 * - ... to A_WAIT_BCON.
481 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
483 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
484 musb->ep0_stage = MUSB_EP0_START;
485 musb->xceiv->state = OTG_STATE_A_IDLE;
487 musb_set_vbus(musb, 1);
489 handled = IRQ_HANDLED;
492 if (int_usb & MUSB_INTR_VBUSERROR) {
495 /* During connection as an A-Device, we may see a short
496 * current spikes causing voltage drop, because of cable
497 * and peripheral capacitance combined with vbus draw.
498 * (So: less common with truly self-powered devices, where
499 * vbus doesn't act like a power supply.)
501 * Such spikes are short; usually less than ~500 usec, max
502 * of ~2 msec. That is, they're not sustained overcurrent
503 * errors, though they're reported using VBUSERROR irqs.
505 * Workarounds: (a) hardware: use self powered devices.
506 * (b) software: ignore non-repeated VBUS errors.
508 * REVISIT: do delays from lots of DEBUG_KERNEL checks
509 * make trouble here, keeping VBUS < 4.4V ?
511 switch (musb->xceiv->state) {
512 case OTG_STATE_A_HOST:
513 /* recovery is dicey once we've gotten past the
514 * initial stages of enumeration, but if VBUS
515 * stayed ok at the other end of the link, and
516 * another reset is due (at least for high speed,
517 * to redo the chirp etc), it might work OK...
519 case OTG_STATE_A_WAIT_BCON:
520 case OTG_STATE_A_WAIT_VRISE:
521 if (musb->vbuserr_retry) {
522 musb->vbuserr_retry--;
524 devctl |= MUSB_DEVCTL_SESSION;
525 musb_writeb(mbase, MUSB_DEVCTL, devctl);
527 musb->port1_status |=
528 (1 << USB_PORT_FEAT_OVER_CURRENT)
529 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
536 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
537 otg_state_string(musb),
540 switch (devctl & MUSB_DEVCTL_VBUS) {
541 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
542 s = "<SessEnd"; break;
543 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
544 s = "<AValid"; break;
545 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
546 s = "<VBusValid"; break;
547 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
551 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
554 /* go through A_WAIT_VFALL then start a new session */
556 musb_set_vbus(musb, 0);
557 handled = IRQ_HANDLED;
561 if (int_usb & MUSB_INTR_SUSPEND) {
562 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
563 otg_state_string(musb), devctl, power);
564 handled = IRQ_HANDLED;
566 switch (musb->xceiv->state) {
567 #ifdef CONFIG_USB_MUSB_OTG
568 case OTG_STATE_A_PERIPHERAL:
569 /* We also come here if the cable is removed, since
570 * this silicon doesn't report ID-no-longer-grounded.
572 * We depend on T(a_wait_bcon) to shut us down, and
573 * hope users don't do anything dicey during this
574 * undesired detour through A_WAIT_BCON.
577 usb_hcd_resume_root_hub(musb_to_hcd(musb));
578 musb_root_disconnect(musb);
579 musb_platform_try_idle(musb, jiffies
580 + msecs_to_jiffies(musb->a_wait_bcon
581 ? : OTG_TIME_A_WAIT_BCON));
585 case OTG_STATE_B_IDLE:
586 if (!musb->is_active)
588 case OTG_STATE_B_PERIPHERAL:
589 musb_g_suspend(musb);
590 musb->is_active = is_otg_enabled(musb)
591 && musb->xceiv->gadget->b_hnp_enable;
592 if (musb->is_active) {
593 #ifdef CONFIG_USB_MUSB_OTG
594 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
595 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
596 mod_timer(&musb->otg_timer, jiffies
598 OTG_TIME_B_ASE0_BRST));
602 case OTG_STATE_A_WAIT_BCON:
603 if (musb->a_wait_bcon != 0)
604 musb_platform_try_idle(musb, jiffies
605 + msecs_to_jiffies(musb->a_wait_bcon));
607 case OTG_STATE_A_HOST:
608 musb->xceiv->state = OTG_STATE_A_SUSPEND;
609 musb->is_active = is_otg_enabled(musb)
610 && musb->xceiv->host->b_hnp_enable;
612 case OTG_STATE_B_HOST:
613 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
614 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
617 /* "should not happen" */
623 if (int_usb & MUSB_INTR_CONNECT) {
624 struct usb_hcd *hcd = musb_to_hcd(musb);
626 handled = IRQ_HANDLED;
628 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
630 musb->ep0_stage = MUSB_EP0_START;
632 #ifdef CONFIG_USB_MUSB_OTG
633 /* flush endpoints when transitioning from Device Mode */
634 if (is_peripheral_active(musb)) {
635 /* REVISIT HNP; just force disconnect */
637 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
638 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
639 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
641 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
642 |USB_PORT_STAT_HIGH_SPEED
643 |USB_PORT_STAT_ENABLE
645 musb->port1_status |= USB_PORT_STAT_CONNECTION
646 |(USB_PORT_STAT_C_CONNECTION << 16);
648 /* high vs full speed is just a guess until after reset */
649 if (devctl & MUSB_DEVCTL_LSDEV)
650 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
652 /* indicate new connection to OTG machine */
653 switch (musb->xceiv->state) {
654 case OTG_STATE_B_PERIPHERAL:
655 if (int_usb & MUSB_INTR_SUSPEND) {
656 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
657 int_usb &= ~MUSB_INTR_SUSPEND;
660 DBG(1, "CONNECT as b_peripheral???\n");
662 case OTG_STATE_B_WAIT_ACON:
663 DBG(1, "HNP: CONNECT, now b_host\n");
665 musb->xceiv->state = OTG_STATE_B_HOST;
666 hcd->self.is_b_host = 1;
667 musb->ignore_disconnect = 0;
668 del_timer(&musb->otg_timer);
671 if ((devctl & MUSB_DEVCTL_VBUS)
672 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
673 musb->xceiv->state = OTG_STATE_A_HOST;
674 hcd->self.is_b_host = 0;
679 /* poke the root hub */
682 usb_hcd_poll_rh_status(hcd);
684 usb_hcd_resume_root_hub(hcd);
686 DBG(1, "CONNECT (%s) devctl %02x\n",
687 otg_state_string(musb), devctl);
689 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
691 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
692 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
693 otg_state_string(musb),
694 MUSB_MODE(musb), devctl);
695 handled = IRQ_HANDLED;
697 switch (musb->xceiv->state) {
698 #ifdef CONFIG_USB_MUSB_HDRC_HCD
699 case OTG_STATE_A_HOST:
700 case OTG_STATE_A_SUSPEND:
701 usb_hcd_resume_root_hub(musb_to_hcd(musb));
702 musb_root_disconnect(musb);
703 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
704 musb_platform_try_idle(musb, jiffies
705 + msecs_to_jiffies(musb->a_wait_bcon));
708 #ifdef CONFIG_USB_MUSB_OTG
709 case OTG_STATE_B_HOST:
710 /* REVISIT this behaves for "real disconnect"
711 * cases; make sure the other transitions from
712 * from B_HOST act right too. The B_HOST code
713 * in hnp_stop() is currently not used...
715 musb_root_disconnect(musb);
716 musb_to_hcd(musb)->self.is_b_host = 0;
717 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
719 musb_g_disconnect(musb);
721 case OTG_STATE_A_PERIPHERAL:
723 musb_root_disconnect(musb);
725 case OTG_STATE_B_WAIT_ACON:
728 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
729 case OTG_STATE_B_PERIPHERAL:
730 case OTG_STATE_B_IDLE:
731 musb_g_disconnect(musb);
735 WARNING("unhandled DISCONNECT transition (%s)\n",
736 otg_state_string(musb));
741 /* mentor saves a bit: bus reset and babble share the same irq.
742 * only host sees babble; only peripheral sees bus reset.
744 if (int_usb & MUSB_INTR_RESET) {
745 handled = IRQ_HANDLED;
746 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
748 * Looks like non-HS BABBLE can be ignored, but
749 * HS BABBLE is an error condition. For HS the solution
750 * is to avoid babble in the first place and fix what
751 * caused BABBLE. When HS BABBLE happens we can only
754 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
755 DBG(1, "BABBLE devctl: %02x\n", devctl);
757 ERR("Stopping host session -- babble\n");
758 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
760 } else if (is_peripheral_capable()) {
761 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
762 switch (musb->xceiv->state) {
763 #ifdef CONFIG_USB_OTG
764 case OTG_STATE_A_SUSPEND:
765 /* We need to ignore disconnect on suspend
766 * otherwise tusb 2.0 won't reconnect after a
767 * power cycle, which breaks otg compliance.
769 musb->ignore_disconnect = 1;
772 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
773 /* never use invalid T(a_wait_bcon) */
774 DBG(1, "HNP: in %s, %d msec timeout\n",
775 otg_state_string(musb),
777 mod_timer(&musb->otg_timer, jiffies
778 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
780 case OTG_STATE_A_PERIPHERAL:
781 musb->ignore_disconnect = 0;
782 del_timer(&musb->otg_timer);
785 case OTG_STATE_B_WAIT_ACON:
786 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
787 otg_state_string(musb));
788 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
792 case OTG_STATE_B_IDLE:
793 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
795 case OTG_STATE_B_PERIPHERAL:
799 DBG(1, "Unhandled BUS RESET as %s\n",
800 otg_state_string(musb));
806 /* REVISIT ... this would be for multiplexing periodic endpoints, or
807 * supporting transfer phasing to prevent exceeding ISO bandwidth
808 * limits of a given frame or microframe.
810 * It's not needed for peripheral side, which dedicates endpoints;
811 * though it _might_ use SOF irqs for other purposes.
813 * And it's not currently needed for host side, which also dedicates
814 * endpoints, relies on TX/RX interval registers, and isn't claimed
815 * to support ISO transfers yet.
817 if (int_usb & MUSB_INTR_SOF) {
818 void __iomem *mbase = musb->mregs;
819 struct musb_hw_ep *ep;
823 DBG(6, "START_OF_FRAME\n");
824 handled = IRQ_HANDLED;
826 /* start any periodic Tx transfers waiting for current frame */
827 frame = musb_readw(mbase, MUSB_FRAME);
828 ep = musb->endpoints;
829 for (epnum = 1; (epnum < musb->nr_endpoints)
830 && (musb->epmask >= (1 << epnum));
833 * FIXME handle framecounter wraps (12 bits)
834 * eliminate duplicated StartUrb logic
836 if (ep->dwWaitFrame >= frame) {
838 pr_debug("SOF --> periodic TX%s on %d\n",
839 ep->tx_channel ? " DMA" : "",
842 musb_h_tx_start(musb, epnum);
844 cppi_hostdma_start(musb, epnum);
846 } /* end of for loop */
850 schedule_work(&musb->irq_work);
855 /*-------------------------------------------------------------------------*/
858 * Program the HDRC to start (enable interrupts, dma, etc.).
860 void musb_start(struct musb *musb)
862 void __iomem *regs = musb->mregs;
863 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
865 DBG(2, "<== devctl %02x\n", devctl);
867 /* Set INT enable registers, enable interrupts */
868 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
869 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
870 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
872 musb_writeb(regs, MUSB_TESTMODE, 0);
874 /* put into basic highspeed mode and start session */
875 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
876 | MUSB_POWER_SOFTCONN
878 /* ENSUSPEND wedges tusb */
879 /* | MUSB_POWER_ENSUSPEND */
883 devctl = musb_readb(regs, MUSB_DEVCTL);
884 devctl &= ~MUSB_DEVCTL_SESSION;
886 if (is_otg_enabled(musb)) {
887 /* session started after:
888 * (a) ID-grounded irq, host mode;
889 * (b) vbus present/connect IRQ, peripheral mode;
890 * (c) peripheral initiates, using SRP
892 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
895 devctl |= MUSB_DEVCTL_SESSION;
897 } else if (is_host_enabled(musb)) {
898 /* assume ID pin is hard-wired to ground */
899 devctl |= MUSB_DEVCTL_SESSION;
901 } else /* peripheral is enabled */ {
902 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
905 musb_platform_enable(musb);
906 musb_writeb(regs, MUSB_DEVCTL, devctl);
910 static void musb_generic_disable(struct musb *musb)
912 void __iomem *mbase = musb->mregs;
915 /* disable interrupts */
916 musb_writeb(mbase, MUSB_INTRUSBE, 0);
917 musb_writew(mbase, MUSB_INTRTXE, 0);
918 musb_writew(mbase, MUSB_INTRRXE, 0);
921 musb_writeb(mbase, MUSB_DEVCTL, 0);
923 /* flush pending interrupts */
924 temp = musb_readb(mbase, MUSB_INTRUSB);
925 temp = musb_readw(mbase, MUSB_INTRTX);
926 temp = musb_readw(mbase, MUSB_INTRRX);
931 * Make the HDRC stop (disable interrupts, etc.);
932 * reversible by musb_start
933 * called on gadget driver unregister
934 * with controller locked, irqs blocked
935 * acts as a NOP unless some role activated the hardware
937 void musb_stop(struct musb *musb)
939 /* stop IRQs, timers, ... */
940 musb_platform_disable(musb);
941 musb_generic_disable(musb);
942 DBG(3, "HDRC disabled\n");
945 * - mark host and/or peripheral drivers unusable/inactive
946 * - disable DMA (and enable it in HdrcStart)
947 * - make sure we can musb_start() after musb_stop(); with
948 * OTG mode, gadget driver module rmmod/modprobe cycles that
951 musb_platform_try_idle(musb, 0);
954 static void musb_shutdown(struct platform_device *pdev)
956 struct musb *musb = dev_to_musb(&pdev->dev);
959 spin_lock_irqsave(&musb->lock, flags);
960 musb_platform_disable(musb);
961 musb_generic_disable(musb);
963 clk_put(musb->clock);
966 spin_unlock_irqrestore(&musb->lock, flags);
968 /* FIXME power down */
972 /*-------------------------------------------------------------------------*/
975 * The silicon either has hard-wired endpoint configurations, or else
976 * "dynamic fifo" sizing. The driver has support for both, though at this
977 * writing only the dynamic sizing is very well tested. Since we switched
978 * away from compile-time hardware parameters, we can no longer rely on
979 * dead code elimination to leave only the relevant one in the object file.
981 * We don't currently use dynamic fifo setup capability to do anything
982 * more than selecting one of a bunch of predefined configurations.
984 #if defined(CONFIG_USB_TUSB6010) || \
985 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
986 static ushort __initdata fifo_mode = 4;
988 static ushort __initdata fifo_mode = 2;
991 /* "modprobe ... fifo_mode=1" etc */
992 module_param(fifo_mode, ushort, 0);
993 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
996 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
997 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1001 enum fifo_style style;
1007 * tables defining fifo_mode values. define more if you like.
1008 * for host side, make sure both halves of ep1 are set up.
1011 /* mode 0 - fits in 2KB */
1012 static struct fifo_cfg __initdata mode_0_cfg[] = {
1013 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1014 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1015 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1016 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1017 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1020 /* mode 1 - fits in 4KB */
1021 static struct fifo_cfg __initdata mode_1_cfg[] = {
1022 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1023 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1024 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1025 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1026 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1029 /* mode 2 - fits in 4KB */
1030 static struct fifo_cfg __initdata mode_2_cfg[] = {
1031 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1032 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1033 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1034 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1035 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1036 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1039 /* mode 3 - fits in 4KB */
1040 static struct fifo_cfg __initdata mode_3_cfg[] = {
1041 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1042 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1043 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1044 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1045 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1046 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1049 /* mode 4 - fits in 16KB */
1050 static struct fifo_cfg __initdata mode_4_cfg[] = {
1051 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1052 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1053 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1054 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1055 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1056 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1057 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1058 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1059 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1060 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1061 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1062 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1063 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1064 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1065 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1066 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1067 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1068 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1069 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1070 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1071 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1072 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1073 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1074 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1075 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1076 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1077 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1080 /* mode 5 - fits in 8KB */
1081 static struct fifo_cfg __initdata mode_5_cfg[] = {
1082 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1083 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1084 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1085 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1086 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1087 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1088 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1089 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1090 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1091 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1092 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1093 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1094 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1095 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1096 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1097 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1098 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1099 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1100 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1101 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1102 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1103 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1104 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1105 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1106 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1107 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1108 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1112 * configure a fifo; for non-shared endpoints, this may be called
1113 * once for a tx fifo and once for an rx fifo.
1115 * returns negative errno or offset for next fifo.
1118 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1119 const struct fifo_cfg *cfg, u16 offset)
1121 void __iomem *mbase = musb->mregs;
1123 u16 maxpacket = cfg->maxpacket;
1124 u16 c_off = offset >> 3;
1127 /* expect hw_ep has already been zero-initialized */
1129 size = ffs(max(maxpacket, (u16) 8)) - 1;
1130 maxpacket = 1 << size;
1133 if (cfg->mode == BUF_DOUBLE) {
1134 if ((offset + (maxpacket << 1)) >
1135 (1 << (musb->config->ram_bits + 2)))
1137 c_size |= MUSB_FIFOSZ_DPB;
1139 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1143 /* configure the FIFO */
1144 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1146 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1147 /* EP0 reserved endpoint for control, bidirectional;
1148 * EP1 reserved for bulk, two unidirection halves.
1150 if (hw_ep->epnum == 1)
1151 musb->bulk_ep = hw_ep;
1152 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1154 switch (cfg->style) {
1156 musb_write_txfifosz(mbase, c_size);
1157 musb_write_txfifoadd(mbase, c_off);
1158 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1159 hw_ep->max_packet_sz_tx = maxpacket;
1162 musb_write_rxfifosz(mbase, c_size);
1163 musb_write_rxfifoadd(mbase, c_off);
1164 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1165 hw_ep->max_packet_sz_rx = maxpacket;
1168 musb_write_txfifosz(mbase, c_size);
1169 musb_write_txfifoadd(mbase, c_off);
1170 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1171 hw_ep->max_packet_sz_rx = maxpacket;
1173 musb_write_rxfifosz(mbase, c_size);
1174 musb_write_rxfifoadd(mbase, c_off);
1175 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1176 hw_ep->max_packet_sz_tx = maxpacket;
1178 hw_ep->is_shared_fifo = true;
1182 /* NOTE rx and tx endpoint irqs aren't managed separately,
1183 * which happens to be ok
1185 musb->epmask |= (1 << hw_ep->epnum);
1187 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1190 static struct fifo_cfg __initdata ep0_cfg = {
1191 .style = FIFO_RXTX, .maxpacket = 64,
1194 static int __init ep_config_from_table(struct musb *musb)
1196 const struct fifo_cfg *cfg;
1199 struct musb_hw_ep *hw_ep = musb->endpoints;
1201 switch (fifo_mode) {
1207 n = ARRAY_SIZE(mode_0_cfg);
1211 n = ARRAY_SIZE(mode_1_cfg);
1215 n = ARRAY_SIZE(mode_2_cfg);
1219 n = ARRAY_SIZE(mode_3_cfg);
1223 n = ARRAY_SIZE(mode_4_cfg);
1227 n = ARRAY_SIZE(mode_5_cfg);
1231 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1232 musb_driver_name, fifo_mode);
1235 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1236 /* assert(offset > 0) */
1238 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1239 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1242 for (i = 0; i < n; i++) {
1243 u8 epn = cfg->hw_ep_num;
1245 if (epn >= musb->config->num_eps) {
1246 pr_debug("%s: invalid ep %d\n",
1247 musb_driver_name, epn);
1250 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1252 pr_debug("%s: mem overrun, ep %d\n",
1253 musb_driver_name, epn);
1257 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1260 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1262 n + 1, musb->config->num_eps * 2 - 1,
1263 offset, (1 << (musb->config->ram_bits + 2)));
1265 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1266 if (!musb->bulk_ep) {
1267 pr_debug("%s: missing bulk\n", musb_driver_name);
1277 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1278 * @param musb the controller
1280 static int __init ep_config_from_hw(struct musb *musb)
1283 struct musb_hw_ep *hw_ep;
1284 void *mbase = musb->mregs;
1287 DBG(2, "<== static silicon ep config\n");
1289 /* FIXME pick up ep0 maxpacket size */
1291 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1292 musb_ep_select(mbase, epnum);
1293 hw_ep = musb->endpoints + epnum;
1295 ret = musb_read_fifosize(musb, hw_ep, epnum);
1299 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1301 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1302 /* pick an RX/TX endpoint for bulk */
1303 if (hw_ep->max_packet_sz_tx < 512
1304 || hw_ep->max_packet_sz_rx < 512)
1307 /* REVISIT: this algorithm is lazy, we should at least
1308 * try to pick a double buffered endpoint.
1312 musb->bulk_ep = hw_ep;
1316 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1317 if (!musb->bulk_ep) {
1318 pr_debug("%s: missing bulk\n", musb_driver_name);
1326 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1328 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1329 * configure endpoints, or take their config from silicon
1331 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1335 char aInfo[90], aRevision[32], aDate[12];
1336 void __iomem *mbase = musb->mregs;
1340 /* log core options (read using indexed model) */
1341 reg = musb_read_configdata(mbase);
1343 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1344 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1345 strcat(aInfo, ", dyn FIFOs");
1346 musb->dyn_fifo = true;
1348 if (reg & MUSB_CONFIGDATA_MPRXE) {
1349 strcat(aInfo, ", bulk combine");
1350 musb->bulk_combine = true;
1352 if (reg & MUSB_CONFIGDATA_MPTXE) {
1353 strcat(aInfo, ", bulk split");
1354 musb->bulk_split = true;
1356 if (reg & MUSB_CONFIGDATA_HBRXE) {
1357 strcat(aInfo, ", HB-ISO Rx");
1358 musb->hb_iso_rx = true;
1360 if (reg & MUSB_CONFIGDATA_HBTXE) {
1361 strcat(aInfo, ", HB-ISO Tx");
1362 musb->hb_iso_tx = true;
1364 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1365 strcat(aInfo, ", SoftConn");
1367 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1368 musb_driver_name, reg, aInfo);
1371 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1372 musb->is_multipoint = 1;
1375 musb->is_multipoint = 0;
1377 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1378 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1380 "%s: kernel must blacklist external hubs\n",
1386 /* log release info */
1387 musb->hwvers = musb_read_hwvers(mbase);
1388 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1389 MUSB_HWVERS_MINOR(musb->hwvers),
1390 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1391 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1392 musb_driver_name, type, aRevision, aDate);
1395 musb_configure_ep0(musb);
1397 /* discover endpoint configuration */
1398 musb->nr_endpoints = 1;
1402 status = ep_config_from_table(musb);
1404 status = ep_config_from_hw(musb);
1409 /* finish init, and print endpoint config */
1410 for (i = 0; i < musb->nr_endpoints; i++) {
1411 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1413 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1414 #ifdef CONFIG_USB_TUSB6010
1415 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1416 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1417 hw_ep->fifo_sync_va =
1418 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1421 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1423 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1426 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1427 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1428 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1429 hw_ep->rx_reinit = 1;
1430 hw_ep->tx_reinit = 1;
1433 if (hw_ep->max_packet_sz_tx) {
1435 "%s: hw_ep %d%s, %smax %d\n",
1436 musb_driver_name, i,
1437 hw_ep->is_shared_fifo ? "shared" : "tx",
1438 hw_ep->tx_double_buffered
1439 ? "doublebuffer, " : "",
1440 hw_ep->max_packet_sz_tx);
1442 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1444 "%s: hw_ep %d%s, %smax %d\n",
1445 musb_driver_name, i,
1447 hw_ep->rx_double_buffered
1448 ? "doublebuffer, " : "",
1449 hw_ep->max_packet_sz_rx);
1451 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1452 DBG(1, "hw_ep %d not configured\n", i);
1458 /*-------------------------------------------------------------------------*/
1460 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1462 static irqreturn_t generic_interrupt(int irq, void *__hci)
1464 unsigned long flags;
1465 irqreturn_t retval = IRQ_NONE;
1466 struct musb *musb = __hci;
1468 spin_lock_irqsave(&musb->lock, flags);
1470 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1471 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1472 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1474 if (musb->int_usb || musb->int_tx || musb->int_rx)
1475 retval = musb_interrupt(musb);
1477 spin_unlock_irqrestore(&musb->lock, flags);
1483 #define generic_interrupt NULL
1487 * handle all the irqs defined by the HDRC core. for now we expect: other
1488 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1489 * will be assigned, and the irq will already have been acked.
1491 * called in irq context with spinlock held, irqs blocked
1493 irqreturn_t musb_interrupt(struct musb *musb)
1495 irqreturn_t retval = IRQ_NONE;
1500 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1501 power = musb_readb(musb->mregs, MUSB_POWER);
1503 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1504 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1505 musb->int_usb, musb->int_tx, musb->int_rx);
1507 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1508 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1509 if (!musb->gadget_driver) {
1510 DBG(5, "No gadget driver loaded\n");
1515 /* the core can interrupt us for multiple reasons; docs have
1516 * a generic interrupt flowchart to follow
1518 if (musb->int_usb & STAGE0_MASK)
1519 retval |= musb_stage0_irq(musb, musb->int_usb,
1522 /* "stage 1" is handling endpoint irqs */
1524 /* handle endpoint 0 first */
1525 if (musb->int_tx & 1) {
1526 if (devctl & MUSB_DEVCTL_HM)
1527 retval |= musb_h_ep0_irq(musb);
1529 retval |= musb_g_ep0_irq(musb);
1532 /* RX on endpoints 1-15 */
1533 reg = musb->int_rx >> 1;
1537 /* musb_ep_select(musb->mregs, ep_num); */
1538 /* REVISIT just retval = ep->rx_irq(...) */
1539 retval = IRQ_HANDLED;
1540 if (devctl & MUSB_DEVCTL_HM) {
1541 if (is_host_capable())
1542 musb_host_rx(musb, ep_num);
1544 if (is_peripheral_capable())
1545 musb_g_rx(musb, ep_num);
1553 /* TX on endpoints 1-15 */
1554 reg = musb->int_tx >> 1;
1558 /* musb_ep_select(musb->mregs, ep_num); */
1559 /* REVISIT just retval |= ep->tx_irq(...) */
1560 retval = IRQ_HANDLED;
1561 if (devctl & MUSB_DEVCTL_HM) {
1562 if (is_host_capable())
1563 musb_host_tx(musb, ep_num);
1565 if (is_peripheral_capable())
1566 musb_g_tx(musb, ep_num);
1577 #ifndef CONFIG_MUSB_PIO_ONLY
1578 static int __initdata use_dma = 1;
1580 /* "modprobe ... use_dma=0" etc */
1581 module_param(use_dma, bool, 0);
1582 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1584 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1586 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1588 /* called with controller lock already held */
1591 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1592 if (!is_cppi_enabled()) {
1594 if (devctl & MUSB_DEVCTL_HM)
1595 musb_h_ep0_irq(musb);
1597 musb_g_ep0_irq(musb);
1601 /* endpoints 1..15 */
1603 if (devctl & MUSB_DEVCTL_HM) {
1604 if (is_host_capable())
1605 musb_host_tx(musb, epnum);
1607 if (is_peripheral_capable())
1608 musb_g_tx(musb, epnum);
1612 if (devctl & MUSB_DEVCTL_HM) {
1613 if (is_host_capable())
1614 musb_host_rx(musb, epnum);
1616 if (is_peripheral_capable())
1617 musb_g_rx(musb, epnum);
1627 /*-------------------------------------------------------------------------*/
1632 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1634 struct musb *musb = dev_to_musb(dev);
1635 unsigned long flags;
1638 spin_lock_irqsave(&musb->lock, flags);
1639 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1640 spin_unlock_irqrestore(&musb->lock, flags);
1646 musb_mode_store(struct device *dev, struct device_attribute *attr,
1647 const char *buf, size_t n)
1649 struct musb *musb = dev_to_musb(dev);
1650 unsigned long flags;
1653 spin_lock_irqsave(&musb->lock, flags);
1654 if (sysfs_streq(buf, "host"))
1655 status = musb_platform_set_mode(musb, MUSB_HOST);
1656 else if (sysfs_streq(buf, "peripheral"))
1657 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1658 else if (sysfs_streq(buf, "otg"))
1659 status = musb_platform_set_mode(musb, MUSB_OTG);
1662 spin_unlock_irqrestore(&musb->lock, flags);
1664 return (status == 0) ? n : status;
1666 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1669 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1670 const char *buf, size_t n)
1672 struct musb *musb = dev_to_musb(dev);
1673 unsigned long flags;
1676 if (sscanf(buf, "%lu", &val) < 1) {
1677 dev_err(dev, "Invalid VBUS timeout ms value\n");
1681 spin_lock_irqsave(&musb->lock, flags);
1682 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1683 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1684 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1685 musb->is_active = 0;
1686 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1687 spin_unlock_irqrestore(&musb->lock, flags);
1693 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1695 struct musb *musb = dev_to_musb(dev);
1696 unsigned long flags;
1700 spin_lock_irqsave(&musb->lock, flags);
1701 val = musb->a_wait_bcon;
1702 /* FIXME get_vbus_status() is normally #defined as false...
1703 * and is effectively TUSB-specific.
1705 vbus = musb_platform_get_vbus_status(musb);
1706 spin_unlock_irqrestore(&musb->lock, flags);
1708 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1709 vbus ? "on" : "off", val);
1711 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1713 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1715 /* Gadget drivers can't know that a host is connected so they might want
1716 * to start SRP, but users can. This allows userspace to trigger SRP.
1719 musb_srp_store(struct device *dev, struct device_attribute *attr,
1720 const char *buf, size_t n)
1722 struct musb *musb = dev_to_musb(dev);
1725 if (sscanf(buf, "%hu", &srp) != 1
1727 dev_err(dev, "SRP: Value must be 1\n");
1732 musb_g_wakeup(musb);
1736 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1738 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1740 static struct attribute *musb_attributes[] = {
1741 &dev_attr_mode.attr,
1742 &dev_attr_vbus.attr,
1743 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1749 static const struct attribute_group musb_attr_group = {
1750 .attrs = musb_attributes,
1755 /* Only used to provide driver mode change events */
1756 static void musb_irq_work(struct work_struct *data)
1758 struct musb *musb = container_of(data, struct musb, irq_work);
1759 static int old_state;
1761 if (musb->xceiv->state != old_state) {
1762 old_state = musb->xceiv->state;
1763 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1767 /* --------------------------------------------------------------------------
1771 static struct musb *__init
1772 allocate_instance(struct device *dev,
1773 struct musb_hdrc_config *config, void __iomem *mbase)
1776 struct musb_hw_ep *ep;
1778 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1779 struct usb_hcd *hcd;
1781 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1784 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1786 musb = hcd_to_musb(hcd);
1787 INIT_LIST_HEAD(&musb->control);
1788 INIT_LIST_HEAD(&musb->in_bulk);
1789 INIT_LIST_HEAD(&musb->out_bulk);
1791 hcd->uses_new_polling = 1;
1793 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1794 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1796 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1799 dev_set_drvdata(dev, musb);
1803 musb->mregs = mbase;
1804 musb->ctrl_base = mbase;
1805 musb->nIrq = -ENODEV;
1806 musb->config = config;
1807 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1808 for (epnum = 0, ep = musb->endpoints;
1809 epnum < musb->config->num_eps;
1815 musb->controller = dev;
1819 static void musb_free(struct musb *musb)
1821 /* this has multiple entry modes. it handles fault cleanup after
1822 * probe(), where things may be partially set up, as well as rmmod
1823 * cleanup after everything's been de-activated.
1827 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1830 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1831 musb_gadget_cleanup(musb);
1834 if (musb->nIrq >= 0) {
1836 disable_irq_wake(musb->nIrq);
1837 free_irq(musb->nIrq, musb);
1839 if (is_dma_capable() && musb->dma_controller) {
1840 struct dma_controller *c = musb->dma_controller;
1843 dma_controller_destroy(c);
1846 #ifdef CONFIG_USB_MUSB_OTG
1847 put_device(musb->xceiv->dev);
1850 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1851 musb_platform_exit(musb);
1852 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1855 clk_disable(musb->clock);
1856 clk_put(musb->clock);
1859 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1860 usb_put_hcd(musb_to_hcd(musb));
1867 * Perform generic per-controller initialization.
1869 * @pDevice: the controller (already clocked, etc)
1871 * @mregs: virtual address of controller registers,
1872 * not yet corrected for platform-specific offsets
1875 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1879 struct musb_hdrc_platform_data *plat = dev->platform_data;
1881 /* The driver might handle more features than the board; OK.
1882 * Fail when the board needs a feature that's not enabled.
1885 dev_dbg(dev, "no platform_data?\n");
1888 switch (plat->mode) {
1890 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1895 case MUSB_PERIPHERAL:
1896 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1902 #ifdef CONFIG_USB_MUSB_OTG
1908 dev_err(dev, "incompatible Kconfig role setting\n");
1913 musb = allocate_instance(dev, plat->config, ctrl);
1917 spin_lock_init(&musb->lock);
1918 musb->board_mode = plat->mode;
1919 musb->board_set_power = plat->set_power;
1920 musb->set_clock = plat->set_clock;
1921 musb->min_power = plat->min_power;
1923 /* Clock usage is chip-specific ... functional clock (DaVinci,
1924 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1925 * code does is make sure a clock handle is available; platform
1926 * code manages it during start/stop and suspend/resume.
1929 musb->clock = clk_get(dev, plat->clock);
1930 if (IS_ERR(musb->clock)) {
1931 status = PTR_ERR(musb->clock);
1937 /* The musb_platform_init() call:
1938 * - adjusts musb->mregs and musb->isr if needed,
1939 * - may initialize an integrated tranceiver
1940 * - initializes musb->xceiv, usually by otg_get_transceiver()
1941 * - activates clocks.
1942 * - stops powering VBUS
1943 * - assigns musb->board_set_vbus if host mode is enabled
1945 * There are various transciever configurations. Blackfin,
1946 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1947 * external/discrete ones in various flavors (twl4030 family,
1948 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1950 musb->isr = generic_interrupt;
1951 status = musb_platform_init(musb);
1960 #ifndef CONFIG_MUSB_PIO_ONLY
1961 if (use_dma && dev->dma_mask) {
1962 struct dma_controller *c;
1964 c = dma_controller_create(musb, musb->mregs);
1965 musb->dma_controller = c;
1970 /* ideally this would be abstracted in platform setup */
1971 if (!is_dma_capable() || !musb->dma_controller)
1972 dev->dma_mask = NULL;
1974 /* be sure interrupts are disabled before connecting ISR */
1975 musb_platform_disable(musb);
1976 musb_generic_disable(musb);
1978 /* setup musb parts of the core (especially endpoints) */
1979 status = musb_core_init(plat->config->multipoint
1980 ? MUSB_CONTROLLER_MHDRC
1981 : MUSB_CONTROLLER_HDRC, musb);
1985 #ifdef CONFIG_USB_MUSB_OTG
1986 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1989 /* Init IRQ workqueue before request_irq */
1990 INIT_WORK(&musb->irq_work, musb_irq_work);
1992 /* attach to the IRQ */
1993 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1994 dev_err(dev, "request_irq %d failed!\n", nIrq);
1999 /* FIXME this handles wakeup irqs wrong */
2000 if (enable_irq_wake(nIrq) == 0) {
2002 device_init_wakeup(dev, 1);
2007 /* host side needs more setup */
2008 if (is_host_enabled(musb)) {
2009 struct usb_hcd *hcd = musb_to_hcd(musb);
2012 otg_set_host(musb->xceiv, &hcd->self);
2014 if (is_otg_enabled(musb))
2015 hcd->self.otg_port = 1;
2016 musb->xceiv->host = &hcd->self;
2017 hcd->power_budget = 2 * (plat->power ? : 250);
2019 /* program PHY to use external vBus if required */
2020 if (plat->extvbus) {
2021 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL);
2022 busctl |= MUSB_ULPI_USE_EXTVBUS;
2023 musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl);
2027 /* For the host-only role, we can activate right away.
2028 * (We expect the ID pin to be forcibly grounded!!)
2029 * Otherwise, wait till the gadget driver hooks up.
2031 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2032 MUSB_HST_MODE(musb);
2033 musb->xceiv->default_a = 1;
2034 musb->xceiv->state = OTG_STATE_A_IDLE;
2036 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2040 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2042 musb_readb(musb->mregs, MUSB_DEVCTL),
2043 (musb_readb(musb->mregs, MUSB_DEVCTL)
2044 & MUSB_DEVCTL_BDEVICE
2047 } else /* peripheral is enabled */ {
2048 MUSB_DEV_MODE(musb);
2049 musb->xceiv->default_a = 0;
2050 musb->xceiv->state = OTG_STATE_B_IDLE;
2052 status = musb_gadget_setup(musb);
2056 DBG(1, "%s mode, status %d, dev%02x\n",
2057 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2059 musb_readb(musb->mregs, MUSB_DEVCTL));
2064 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2069 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2071 switch (musb->board_mode) {
2072 case MUSB_HOST: s = "Host"; break;
2073 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2074 default: s = "OTG"; break;
2077 (is_dma_capable() && musb->dma_controller)
2084 musb_platform_exit(musb);
2086 dev_err(musb->controller,
2087 "musb_init_controller failed with status %d\n", status);
2090 clk_put(musb->clock);
2091 device_init_wakeup(dev, 0);
2098 /*-------------------------------------------------------------------------*/
2100 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2101 * bridge to a platform device; this driver then suffices.
2104 #ifndef CONFIG_MUSB_PIO_ONLY
2105 static u64 *orig_dma_mask;
2108 static int __init musb_probe(struct platform_device *pdev)
2110 struct device *dev = &pdev->dev;
2111 int irq = platform_get_irq(pdev, 0);
2113 struct resource *iomem;
2116 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2117 if (!iomem || irq == 0)
2120 base = ioremap(iomem->start, resource_size(iomem));
2122 dev_err(dev, "ioremap failed\n");
2126 #ifndef CONFIG_MUSB_PIO_ONLY
2127 /* clobbered by use_dma=n */
2128 orig_dma_mask = dev->dma_mask;
2131 status = musb_init_controller(dev, irq, base);
2138 static int __exit musb_remove(struct platform_device *pdev)
2140 struct musb *musb = dev_to_musb(&pdev->dev);
2141 void __iomem *ctrl_base = musb->ctrl_base;
2143 /* this gets called on rmmod.
2144 * - Host mode: host may still be active
2145 * - Peripheral mode: peripheral is deactivated (or never-activated)
2146 * - OTG mode: both roles are deactivated (or never-activated)
2148 musb_shutdown(pdev);
2149 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2150 if (musb->board_mode == MUSB_HOST)
2151 usb_remove_hcd(musb_to_hcd(musb));
2155 device_init_wakeup(&pdev->dev, 0);
2156 #ifndef CONFIG_MUSB_PIO_ONLY
2157 pdev->dev.dma_mask = orig_dma_mask;
2164 static struct musb_context_registers musb_context;
2166 void musb_save_context(struct musb *musb)
2169 void __iomem *musb_base = musb->mregs;
2171 if (is_host_enabled(musb)) {
2172 musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
2173 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2175 musb_context.power = musb_readb(musb_base, MUSB_POWER);
2176 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2177 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2178 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2179 musb_context.index = musb_readb(musb_base, MUSB_INDEX);
2180 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2182 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2183 musb_writeb(musb_base, MUSB_INDEX, i);
2184 musb_context.index_regs[i].txmaxp =
2185 musb_readw(musb_base, 0x10 + MUSB_TXMAXP);
2186 musb_context.index_regs[i].txcsr =
2187 musb_readw(musb_base, 0x10 + MUSB_TXCSR);
2188 musb_context.index_regs[i].rxmaxp =
2189 musb_readw(musb_base, 0x10 + MUSB_RXMAXP);
2190 musb_context.index_regs[i].rxcsr =
2191 musb_readw(musb_base, 0x10 + MUSB_RXCSR);
2193 if (musb->dyn_fifo) {
2194 musb_context.index_regs[i].txfifoadd =
2195 musb_read_txfifoadd(musb_base);
2196 musb_context.index_regs[i].rxfifoadd =
2197 musb_read_rxfifoadd(musb_base);
2198 musb_context.index_regs[i].txfifosz =
2199 musb_read_txfifosz(musb_base);
2200 musb_context.index_regs[i].rxfifosz =
2201 musb_read_rxfifosz(musb_base);
2203 if (is_host_enabled(musb)) {
2204 musb_context.index_regs[i].txtype =
2205 musb_readb(musb_base, 0x10 + MUSB_TXTYPE);
2206 musb_context.index_regs[i].txinterval =
2207 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL);
2208 musb_context.index_regs[i].rxtype =
2209 musb_readb(musb_base, 0x10 + MUSB_RXTYPE);
2210 musb_context.index_regs[i].rxinterval =
2211 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL);
2213 musb_context.index_regs[i].txfunaddr =
2214 musb_read_txfunaddr(musb_base, i);
2215 musb_context.index_regs[i].txhubaddr =
2216 musb_read_txhubaddr(musb_base, i);
2217 musb_context.index_regs[i].txhubport =
2218 musb_read_txhubport(musb_base, i);
2220 musb_context.index_regs[i].rxfunaddr =
2221 musb_read_rxfunaddr(musb_base, i);
2222 musb_context.index_regs[i].rxhubaddr =
2223 musb_read_rxhubaddr(musb_base, i);
2224 musb_context.index_regs[i].rxhubport =
2225 musb_read_rxhubport(musb_base, i);
2229 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2231 musb_platform_save_context(musb, &musb_context);
2234 void musb_restore_context(struct musb *musb)
2237 void __iomem *musb_base = musb->mregs;
2238 void __iomem *ep_target_regs;
2240 musb_platform_restore_context(musb, &musb_context);
2242 if (is_host_enabled(musb)) {
2243 musb_writew(musb_base, MUSB_FRAME, musb_context.frame);
2244 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode);
2246 musb_writeb(musb_base, MUSB_POWER, musb_context.power);
2247 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe);
2248 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe);
2249 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
2250 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
2252 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2253 musb_writeb(musb_base, MUSB_INDEX, i);
2254 musb_writew(musb_base, 0x10 + MUSB_TXMAXP,
2255 musb_context.index_regs[i].txmaxp);
2256 musb_writew(musb_base, 0x10 + MUSB_TXCSR,
2257 musb_context.index_regs[i].txcsr);
2258 musb_writew(musb_base, 0x10 + MUSB_RXMAXP,
2259 musb_context.index_regs[i].rxmaxp);
2260 musb_writew(musb_base, 0x10 + MUSB_RXCSR,
2261 musb_context.index_regs[i].rxcsr);
2263 if (musb->dyn_fifo) {
2264 musb_write_txfifosz(musb_base,
2265 musb_context.index_regs[i].txfifosz);
2266 musb_write_rxfifosz(musb_base,
2267 musb_context.index_regs[i].rxfifosz);
2268 musb_write_txfifoadd(musb_base,
2269 musb_context.index_regs[i].txfifoadd);
2270 musb_write_rxfifoadd(musb_base,
2271 musb_context.index_regs[i].rxfifoadd);
2274 if (is_host_enabled(musb)) {
2275 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE,
2276 musb_context.index_regs[i].txtype);
2277 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL,
2278 musb_context.index_regs[i].txinterval);
2279 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE,
2280 musb_context.index_regs[i].rxtype);
2281 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL,
2283 musb_context.index_regs[i].rxinterval);
2284 musb_write_txfunaddr(musb_base, i,
2285 musb_context.index_regs[i].txfunaddr);
2286 musb_write_txhubaddr(musb_base, i,
2287 musb_context.index_regs[i].txhubaddr);
2288 musb_write_txhubport(musb_base, i,
2289 musb_context.index_regs[i].txhubport);
2292 musb_read_target_reg_base(i, musb_base);
2294 musb_write_rxfunaddr(ep_target_regs,
2295 musb_context.index_regs[i].rxfunaddr);
2296 musb_write_rxhubaddr(ep_target_regs,
2297 musb_context.index_regs[i].rxhubaddr);
2298 musb_write_rxhubport(ep_target_regs,
2299 musb_context.index_regs[i].rxhubport);
2303 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2306 static int musb_suspend(struct device *dev)
2308 struct platform_device *pdev = to_platform_device(dev);
2309 unsigned long flags;
2310 struct musb *musb = dev_to_musb(&pdev->dev);
2315 spin_lock_irqsave(&musb->lock, flags);
2317 if (is_peripheral_active(musb)) {
2318 /* FIXME force disconnect unless we know USB will wake
2319 * the system up quickly enough to respond ...
2321 } else if (is_host_active(musb)) {
2322 /* we know all the children are suspended; sometimes
2323 * they will even be wakeup-enabled.
2327 musb_save_context(musb);
2329 if (musb->set_clock)
2330 musb->set_clock(musb->clock, 0);
2332 clk_disable(musb->clock);
2333 spin_unlock_irqrestore(&musb->lock, flags);
2337 static int musb_resume_noirq(struct device *dev)
2339 struct platform_device *pdev = to_platform_device(dev);
2340 struct musb *musb = dev_to_musb(&pdev->dev);
2345 if (musb->set_clock)
2346 musb->set_clock(musb->clock, 1);
2348 clk_enable(musb->clock);
2350 musb_restore_context(musb);
2352 /* for static cmos like DaVinci, register values were preserved
2353 * unless for some reason the whole soc powered down or the USB
2354 * module got reset through the PSC (vs just being disabled).
2359 static const struct dev_pm_ops musb_dev_pm_ops = {
2360 .suspend = musb_suspend,
2361 .resume_noirq = musb_resume_noirq,
2364 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2366 #define MUSB_DEV_PM_OPS NULL
2369 static struct platform_driver musb_driver = {
2371 .name = (char *)musb_driver_name,
2372 .bus = &platform_bus_type,
2373 .owner = THIS_MODULE,
2374 .pm = MUSB_DEV_PM_OPS,
2376 .remove = __exit_p(musb_remove),
2377 .shutdown = musb_shutdown,
2380 /*-------------------------------------------------------------------------*/
2382 static int __init musb_init(void)
2384 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2389 pr_info("%s: version " MUSB_VERSION ", "
2390 #ifdef CONFIG_MUSB_PIO_ONLY
2392 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2394 #elif defined(CONFIG_USB_INVENTRA_DMA)
2396 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2402 #ifdef CONFIG_USB_MUSB_OTG
2403 "otg (peripheral+host)"
2404 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2406 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2410 musb_driver_name, musb_debug);
2411 return platform_driver_probe(&musb_driver, musb_probe);
2414 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2415 * and before usb gadget and host-side drivers start to register
2417 fs_initcall(musb_init);
2419 static void __exit musb_cleanup(void)
2421 platform_driver_unregister(&musb_driver);
2423 module_exit(musb_cleanup);