2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
103 #include "musb_core.h"
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111 #define MUSB_VERSION "6.0"
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124 /*-------------------------------------------------------------------------*/
126 static inline struct musb *dev_to_musb(struct device *dev)
128 return dev_get_drvdata(dev);
131 /*-------------------------------------------------------------------------*/
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
136 void __iomem *addr = otg->io_priv;
142 pm_runtime_get_sync(otg->io_dev);
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
173 pm_runtime_put(otg->io_dev);
178 static int musb_ulpi_write(struct otg_transceiver *otg,
179 u32 offset, u32 data)
181 void __iomem *addr = otg->io_priv;
187 pm_runtime_get_sync(otg->io_dev);
189 /* Make sure the transceiver is not in low power mode */
190 power = musb_readb(addr, MUSB_POWER);
191 power &= ~MUSB_POWER_SUSPENDM;
192 musb_writeb(addr, MUSB_POWER, power);
194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
199 & MUSB_ULPI_REG_CMPLT)) {
207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
208 r &= ~MUSB_ULPI_REG_CMPLT;
209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
212 pm_runtime_put(otg->io_dev);
217 #define musb_ulpi_read NULL
218 #define musb_ulpi_write NULL
221 static struct otg_io_access_ops musb_ulpi_access = {
222 .read = musb_ulpi_read,
223 .write = musb_ulpi_write,
226 /*-------------------------------------------------------------------------*/
228 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
231 * Load an endpoint's FIFO
233 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
235 struct musb *musb = hw_ep->musb;
236 void __iomem *fifo = hw_ep->fifo;
240 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
241 'T', hw_ep->epnum, fifo, len, src);
243 /* we can't assume unaligned reads work */
244 if (likely((0x01 & (unsigned long) src) == 0)) {
247 /* best case is 32bit-aligned source address */
248 if ((0x02 & (unsigned long) src) == 0) {
250 writesl(fifo, src + index, len >> 2);
251 index += len & ~0x03;
254 musb_writew(fifo, 0, *(u16 *)&src[index]);
259 writesw(fifo, src + index, len >> 1);
260 index += len & ~0x01;
264 musb_writeb(fifo, 0, src[index]);
267 writesb(fifo, src, len);
271 #if !defined(CONFIG_USB_MUSB_AM35X)
273 * Unload an endpoint's FIFO
275 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
277 struct musb *musb = hw_ep->musb;
278 void __iomem *fifo = hw_ep->fifo;
280 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
281 'R', hw_ep->epnum, fifo, len, dst);
283 /* we can't assume unaligned writes work */
284 if (likely((0x01 & (unsigned long) dst) == 0)) {
287 /* best case is 32bit-aligned destination address */
288 if ((0x02 & (unsigned long) dst) == 0) {
290 readsl(fifo, dst, len >> 2);
294 *(u16 *)&dst[index] = musb_readw(fifo, 0);
299 readsw(fifo, dst, len >> 1);
304 dst[index] = musb_readb(fifo, 0);
307 readsb(fifo, dst, len);
312 #endif /* normal PIO */
315 /*-------------------------------------------------------------------------*/
317 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
318 static const u8 musb_test_packet[53] = {
319 /* implicit SYNC then DATA0 to start */
322 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
324 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
326 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
327 /* JJJJJJJKKKKKKK x8 */
328 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
330 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
331 /* JKKKKKKK x10, JK */
332 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
334 /* implicit CRC16 then EOP to end */
337 void musb_load_testpacket(struct musb *musb)
339 void __iomem *regs = musb->endpoints[0].regs;
341 musb_ep_select(musb->mregs, 0);
342 musb_write_fifo(musb->control_ep,
343 sizeof(musb_test_packet), musb_test_packet);
344 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
347 /*-------------------------------------------------------------------------*/
350 * Handles OTG hnp timeouts, such as b_ase0_brst
352 void musb_otg_timer_func(unsigned long data)
354 struct musb *musb = (struct musb *)data;
357 spin_lock_irqsave(&musb->lock, flags);
358 switch (musb->xceiv->state) {
359 case OTG_STATE_B_WAIT_ACON:
360 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
361 musb_g_disconnect(musb);
362 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
365 case OTG_STATE_A_SUSPEND:
366 case OTG_STATE_A_WAIT_BCON:
367 dev_dbg(musb->controller, "HNP: %s timeout\n",
368 otg_state_string(musb->xceiv->state));
369 musb_platform_set_vbus(musb, 0);
370 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
373 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
374 otg_state_string(musb->xceiv->state));
376 musb->ignore_disconnect = 0;
377 spin_unlock_irqrestore(&musb->lock, flags);
381 * Stops the HNP transition. Caller must take care of locking.
383 void musb_hnp_stop(struct musb *musb)
385 struct usb_hcd *hcd = musb_to_hcd(musb);
386 void __iomem *mbase = musb->mregs;
389 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
391 switch (musb->xceiv->state) {
392 case OTG_STATE_A_PERIPHERAL:
393 musb_g_disconnect(musb);
394 dev_dbg(musb->controller, "HNP: back to %s\n",
395 otg_state_string(musb->xceiv->state));
397 case OTG_STATE_B_HOST:
398 dev_dbg(musb->controller, "HNP: Disabling HR\n");
399 hcd->self.is_b_host = 0;
400 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
402 reg = musb_readb(mbase, MUSB_POWER);
403 reg |= MUSB_POWER_SUSPENDM;
404 musb_writeb(mbase, MUSB_POWER, reg);
405 /* REVISIT: Start SESSION_REQUEST here? */
408 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
409 otg_state_string(musb->xceiv->state));
413 * When returning to A state after HNP, avoid hub_port_rebounce(),
414 * which cause occasional OPT A "Did not receive reset after connect"
417 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
421 * Interrupt Service Routine to record USB "global" interrupts.
422 * Since these do not happen often and signify things of
423 * paramount importance, it seems OK to check them individually;
424 * the order of the tests is specified in the manual
426 * @param musb instance pointer
427 * @param int_usb register contents
432 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
435 irqreturn_t handled = IRQ_NONE;
437 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
440 /* in host mode, the peripheral may issue remote wakeup.
441 * in peripheral mode, the host may resume the link.
442 * spurious RESUME irqs happen too, paired with SUSPEND.
444 if (int_usb & MUSB_INTR_RESUME) {
445 handled = IRQ_HANDLED;
446 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
448 if (devctl & MUSB_DEVCTL_HM) {
449 void __iomem *mbase = musb->mregs;
451 switch (musb->xceiv->state) {
452 case OTG_STATE_A_SUSPEND:
453 /* remote wakeup? later, GetPortStatus
454 * will stop RESUME signaling
457 if (power & MUSB_POWER_SUSPENDM) {
459 musb->int_usb &= ~MUSB_INTR_SUSPEND;
460 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
464 power &= ~MUSB_POWER_SUSPENDM;
465 musb_writeb(mbase, MUSB_POWER,
466 power | MUSB_POWER_RESUME);
468 musb->port1_status |=
469 (USB_PORT_STAT_C_SUSPEND << 16)
470 | MUSB_PORT_STAT_RESUME;
471 musb->rh_timer = jiffies
472 + msecs_to_jiffies(20);
474 musb->xceiv->state = OTG_STATE_A_HOST;
476 usb_hcd_resume_root_hub(musb_to_hcd(musb));
478 case OTG_STATE_B_WAIT_ACON:
479 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
484 WARNING("bogus %s RESUME (%s)\n",
486 otg_state_string(musb->xceiv->state));
489 switch (musb->xceiv->state) {
490 case OTG_STATE_A_SUSPEND:
491 /* possibly DISCONNECT is upcoming */
492 musb->xceiv->state = OTG_STATE_A_HOST;
493 usb_hcd_resume_root_hub(musb_to_hcd(musb));
495 case OTG_STATE_B_WAIT_ACON:
496 case OTG_STATE_B_PERIPHERAL:
497 /* disconnect while suspended? we may
498 * not get a disconnect irq...
500 if ((devctl & MUSB_DEVCTL_VBUS)
501 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
503 musb->int_usb |= MUSB_INTR_DISCONNECT;
504 musb->int_usb &= ~MUSB_INTR_SUSPEND;
509 case OTG_STATE_B_IDLE:
510 musb->int_usb &= ~MUSB_INTR_SUSPEND;
513 WARNING("bogus %s RESUME (%s)\n",
515 otg_state_string(musb->xceiv->state));
520 /* see manual for the order of the tests */
521 if (int_usb & MUSB_INTR_SESSREQ) {
522 void __iomem *mbase = musb->mregs;
524 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
525 && (devctl & MUSB_DEVCTL_BDEVICE)) {
526 dev_dbg(musb->controller, "SessReq while on B state\n");
530 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
531 otg_state_string(musb->xceiv->state));
533 /* IRQ arrives from ID pin sense or (later, if VBUS power
534 * is removed) SRP. responses are time critical:
535 * - turn on VBUS (with silicon-specific mechanism)
536 * - go through A_WAIT_VRISE
537 * - ... to A_WAIT_BCON.
538 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
540 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
541 musb->ep0_stage = MUSB_EP0_START;
542 musb->xceiv->state = OTG_STATE_A_IDLE;
544 musb_platform_set_vbus(musb, 1);
546 handled = IRQ_HANDLED;
549 if (int_usb & MUSB_INTR_VBUSERROR) {
552 /* During connection as an A-Device, we may see a short
553 * current spikes causing voltage drop, because of cable
554 * and peripheral capacitance combined with vbus draw.
555 * (So: less common with truly self-powered devices, where
556 * vbus doesn't act like a power supply.)
558 * Such spikes are short; usually less than ~500 usec, max
559 * of ~2 msec. That is, they're not sustained overcurrent
560 * errors, though they're reported using VBUSERROR irqs.
562 * Workarounds: (a) hardware: use self powered devices.
563 * (b) software: ignore non-repeated VBUS errors.
565 * REVISIT: do delays from lots of DEBUG_KERNEL checks
566 * make trouble here, keeping VBUS < 4.4V ?
568 switch (musb->xceiv->state) {
569 case OTG_STATE_A_HOST:
570 /* recovery is dicey once we've gotten past the
571 * initial stages of enumeration, but if VBUS
572 * stayed ok at the other end of the link, and
573 * another reset is due (at least for high speed,
574 * to redo the chirp etc), it might work OK...
576 case OTG_STATE_A_WAIT_BCON:
577 case OTG_STATE_A_WAIT_VRISE:
578 if (musb->vbuserr_retry) {
579 void __iomem *mbase = musb->mregs;
581 musb->vbuserr_retry--;
583 devctl |= MUSB_DEVCTL_SESSION;
584 musb_writeb(mbase, MUSB_DEVCTL, devctl);
586 musb->port1_status |=
587 USB_PORT_STAT_OVERCURRENT
588 | (USB_PORT_STAT_C_OVERCURRENT << 16);
595 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
596 "VBUS_ERROR in %s (%02x, %02x, %s), retry #%d, port1 %08x\n",
597 otg_state_string(musb->xceiv->state),
600 switch (devctl & MUSB_DEVCTL_VBUS) {
601 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
602 s = "<SessEnd"; break;
603 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
604 s = "<AValid"; break;
605 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
606 s = "<VBusValid"; break;
607 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
611 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
614 /* go through A_WAIT_VFALL then start a new session */
616 musb_platform_set_vbus(musb, 0);
617 handled = IRQ_HANDLED;
620 if (int_usb & MUSB_INTR_SUSPEND) {
621 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
622 otg_state_string(musb->xceiv->state), devctl, power);
623 handled = IRQ_HANDLED;
625 switch (musb->xceiv->state) {
626 case OTG_STATE_A_PERIPHERAL:
627 /* We also come here if the cable is removed, since
628 * this silicon doesn't report ID-no-longer-grounded.
630 * We depend on T(a_wait_bcon) to shut us down, and
631 * hope users don't do anything dicey during this
632 * undesired detour through A_WAIT_BCON.
635 usb_hcd_resume_root_hub(musb_to_hcd(musb));
636 musb_root_disconnect(musb);
637 musb_platform_try_idle(musb, jiffies
638 + msecs_to_jiffies(musb->a_wait_bcon
639 ? : OTG_TIME_A_WAIT_BCON));
642 case OTG_STATE_B_IDLE:
643 if (!musb->is_active)
645 case OTG_STATE_B_PERIPHERAL:
646 musb_g_suspend(musb);
647 musb->is_active = is_otg_enabled(musb)
648 && musb->xceiv->gadget->b_hnp_enable;
649 if (musb->is_active) {
650 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
651 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
652 mod_timer(&musb->otg_timer, jiffies
654 OTG_TIME_B_ASE0_BRST));
657 case OTG_STATE_A_WAIT_BCON:
658 if (musb->a_wait_bcon != 0)
659 musb_platform_try_idle(musb, jiffies
660 + msecs_to_jiffies(musb->a_wait_bcon));
662 case OTG_STATE_A_HOST:
663 musb->xceiv->state = OTG_STATE_A_SUSPEND;
664 musb->is_active = is_otg_enabled(musb)
665 && musb->xceiv->host->b_hnp_enable;
667 case OTG_STATE_B_HOST:
668 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
669 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
672 /* "should not happen" */
677 switch (musb->xceiv->state) {
678 case OTG_STATE_B_IDLE:
679 case OTG_STATE_B_PERIPHERAL:
680 cancel_delayed_work(&musb->vbus_workaround_work);
681 schedule_delayed_work(&musb->vbus_workaround_work, HZ / 2);
687 if (int_usb & MUSB_INTR_CONNECT) {
688 struct usb_hcd *hcd = musb_to_hcd(musb);
690 handled = IRQ_HANDLED;
692 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
694 musb->ep0_stage = MUSB_EP0_START;
696 /* flush endpoints when transitioning from Device Mode */
697 if (is_peripheral_active(musb)) {
698 /* REVISIT HNP; just force disconnect */
700 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
701 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
702 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
703 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
704 |USB_PORT_STAT_HIGH_SPEED
705 |USB_PORT_STAT_ENABLE
707 musb->port1_status |= USB_PORT_STAT_CONNECTION
708 |(USB_PORT_STAT_C_CONNECTION << 16);
710 /* high vs full speed is just a guess until after reset */
711 if (devctl & MUSB_DEVCTL_LSDEV)
712 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
714 /* indicate new connection to OTG machine */
715 switch (musb->xceiv->state) {
716 case OTG_STATE_B_PERIPHERAL:
717 if (int_usb & MUSB_INTR_SUSPEND) {
718 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
719 int_usb &= ~MUSB_INTR_SUSPEND;
722 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
724 case OTG_STATE_B_WAIT_ACON:
725 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
727 musb->xceiv->state = OTG_STATE_B_HOST;
728 hcd->self.is_b_host = 1;
729 musb->ignore_disconnect = 0;
730 del_timer(&musb->otg_timer);
733 if ((devctl & MUSB_DEVCTL_VBUS)
734 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
735 musb->xceiv->state = OTG_STATE_A_HOST;
736 hcd->self.is_b_host = 0;
741 /* poke the root hub */
744 usb_hcd_poll_rh_status(hcd);
746 usb_hcd_resume_root_hub(hcd);
748 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
749 otg_state_string(musb->xceiv->state), devctl);
752 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
753 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
754 otg_state_string(musb->xceiv->state),
755 MUSB_MODE(musb), devctl);
756 handled = IRQ_HANDLED;
758 switch (musb->xceiv->state) {
759 case OTG_STATE_A_HOST:
760 case OTG_STATE_A_SUSPEND:
761 usb_hcd_resume_root_hub(musb_to_hcd(musb));
762 musb_root_disconnect(musb);
763 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
764 musb_platform_try_idle(musb, jiffies
765 + msecs_to_jiffies(musb->a_wait_bcon));
767 case OTG_STATE_B_HOST:
768 /* REVISIT this behaves for "real disconnect"
769 * cases; make sure the other transitions from
770 * from B_HOST act right too. The B_HOST code
771 * in hnp_stop() is currently not used...
773 musb_root_disconnect(musb);
774 musb_to_hcd(musb)->self.is_b_host = 0;
775 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
777 musb_g_disconnect(musb);
779 case OTG_STATE_A_PERIPHERAL:
781 musb_root_disconnect(musb);
783 case OTG_STATE_B_WAIT_ACON:
785 case OTG_STATE_B_PERIPHERAL:
786 case OTG_STATE_B_IDLE:
787 musb_g_disconnect(musb);
790 WARNING("unhandled DISCONNECT transition (%s)\n",
791 otg_state_string(musb->xceiv->state));
796 /* mentor saves a bit: bus reset and babble share the same irq.
797 * only host sees babble; only peripheral sees bus reset.
799 if (int_usb & MUSB_INTR_RESET) {
800 handled = IRQ_HANDLED;
801 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
803 * Looks like non-HS BABBLE can be ignored, but
804 * HS BABBLE is an error condition. For HS the solution
805 * is to avoid babble in the first place and fix what
806 * caused BABBLE. When HS BABBLE happens we can only
809 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
810 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
812 ERR("Stopping host session -- babble\n");
813 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
815 } else if (is_peripheral_capable()) {
816 dev_dbg(musb->controller, "BUS RESET as %s\n",
817 otg_state_string(musb->xceiv->state));
818 switch (musb->xceiv->state) {
819 case OTG_STATE_A_SUSPEND:
820 /* We need to ignore disconnect on suspend
821 * otherwise tusb 2.0 won't reconnect after a
822 * power cycle, which breaks otg compliance.
824 musb->ignore_disconnect = 1;
827 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
828 /* never use invalid T(a_wait_bcon) */
829 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
830 otg_state_string(musb->xceiv->state),
832 mod_timer(&musb->otg_timer, jiffies
833 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
835 case OTG_STATE_A_PERIPHERAL:
836 musb->ignore_disconnect = 0;
837 del_timer(&musb->otg_timer);
840 case OTG_STATE_B_WAIT_ACON:
841 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
842 otg_state_string(musb->xceiv->state));
843 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
846 case OTG_STATE_B_IDLE:
847 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
849 case OTG_STATE_B_PERIPHERAL:
853 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
854 otg_state_string(musb->xceiv->state));
860 /* REVISIT ... this would be for multiplexing periodic endpoints, or
861 * supporting transfer phasing to prevent exceeding ISO bandwidth
862 * limits of a given frame or microframe.
864 * It's not needed for peripheral side, which dedicates endpoints;
865 * though it _might_ use SOF irqs for other purposes.
867 * And it's not currently needed for host side, which also dedicates
868 * endpoints, relies on TX/RX interval registers, and isn't claimed
869 * to support ISO transfers yet.
871 if (int_usb & MUSB_INTR_SOF) {
872 void __iomem *mbase = musb->mregs;
873 struct musb_hw_ep *ep;
877 dev_dbg(musb->controller, "START_OF_FRAME\n");
878 handled = IRQ_HANDLED;
880 /* start any periodic Tx transfers waiting for current frame */
881 frame = musb_readw(mbase, MUSB_FRAME);
882 ep = musb->endpoints;
883 for (epnum = 1; (epnum < musb->nr_endpoints)
884 && (musb->epmask >= (1 << epnum));
887 * FIXME handle framecounter wraps (12 bits)
888 * eliminate duplicated StartUrb logic
890 if (ep->dwWaitFrame >= frame) {
892 pr_debug("SOF --> periodic TX%s on %d\n",
893 ep->tx_channel ? " DMA" : "",
896 musb_h_tx_start(musb, epnum);
898 cppi_hostdma_start(musb, epnum);
900 } /* end of for loop */
904 schedule_work(&musb->irq_work);
909 /*-------------------------------------------------------------------------*/
912 * Program the HDRC to start (enable interrupts, dma, etc.).
914 void musb_start(struct musb *musb)
916 void __iomem *regs = musb->mregs;
917 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
919 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
921 /* Set INT enable registers, enable interrupts */
922 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
923 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
924 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
926 musb_writeb(regs, MUSB_TESTMODE, 0);
928 /* put into basic highspeed mode and start session */
929 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
931 /* ENSUSPEND wedges tusb */
932 /* | MUSB_POWER_ENSUSPEND */
936 devctl = musb_readb(regs, MUSB_DEVCTL);
937 devctl &= ~MUSB_DEVCTL_SESSION;
939 if (is_otg_enabled(musb)) {
940 /* session started after:
941 * (a) ID-grounded irq, host mode;
942 * (b) vbus present/connect IRQ, peripheral mode;
943 * (c) peripheral initiates, using SRP
945 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
948 // devctl |= MUSB_DEVCTL_SESSION;
950 } else if (is_host_enabled(musb)) {
951 /* assume ID pin is hard-wired to ground */
952 devctl |= MUSB_DEVCTL_SESSION;
954 } else /* peripheral is enabled */ {
955 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
958 musb_platform_enable(musb);
959 musb_writeb(regs, MUSB_DEVCTL, devctl);
963 static void musb_generic_disable(struct musb *musb)
965 void __iomem *mbase = musb->mregs;
968 /* disable interrupts */
969 musb_writeb(mbase, MUSB_INTRUSBE, 0);
970 musb_writew(mbase, MUSB_INTRTXE, 0);
971 musb_writew(mbase, MUSB_INTRRXE, 0);
974 musb_writeb(mbase, MUSB_DEVCTL, 0);
976 /* flush pending interrupts */
977 temp = musb_readb(mbase, MUSB_INTRUSB);
978 temp = musb_readw(mbase, MUSB_INTRTX);
979 temp = musb_readw(mbase, MUSB_INTRRX);
984 * Make the HDRC stop (disable interrupts, etc.);
985 * reversible by musb_start
986 * called on gadget driver unregister
987 * with controller locked, irqs blocked
988 * acts as a NOP unless some role activated the hardware
990 void musb_stop(struct musb *musb)
992 /* stop IRQs, timers, ... */
993 musb_platform_disable(musb);
994 musb_generic_disable(musb);
995 dev_dbg(musb->controller, "HDRC disabled\n");
998 * - mark host and/or peripheral drivers unusable/inactive
999 * - disable DMA (and enable it in HdrcStart)
1000 * - make sure we can musb_start() after musb_stop(); with
1001 * OTG mode, gadget driver module rmmod/modprobe cycles that
1004 musb_platform_try_idle(musb, 0);
1007 static void musb_shutdown(struct platform_device *pdev)
1009 struct musb *musb = dev_to_musb(&pdev->dev);
1010 unsigned long flags;
1012 pm_runtime_get_sync(musb->controller);
1014 musb_gadget_cleanup(musb);
1016 spin_lock_irqsave(&musb->lock, flags);
1017 musb_platform_disable(musb);
1018 musb_generic_disable(musb);
1019 spin_unlock_irqrestore(&musb->lock, flags);
1021 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1022 usb_remove_hcd(musb_to_hcd(musb));
1023 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1024 musb_platform_exit(musb);
1026 pm_runtime_put(musb->controller);
1028 cancel_delayed_work(&musb->vbus_workaround_work);
1030 /* FIXME power down */
1034 /*-------------------------------------------------------------------------*/
1037 * The silicon either has hard-wired endpoint configurations, or else
1038 * "dynamic fifo" sizing. The driver has support for both, though at this
1039 * writing only the dynamic sizing is very well tested. Since we switched
1040 * away from compile-time hardware parameters, we can no longer rely on
1041 * dead code elimination to leave only the relevant one in the object file.
1043 * We don't currently use dynamic fifo setup capability to do anything
1044 * more than selecting one of a bunch of predefined configurations.
1046 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1047 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1048 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1049 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1050 || defined(CONFIG_USB_MUSB_AM35X) \
1051 || defined(CONFIG_USB_MUSB_AM35X_MODULE)
1052 static ushort __initdata fifo_mode = 4;
1053 #elif defined(CONFIG_USB_MUSB_UX500) \
1054 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1055 static ushort __initdata fifo_mode = 5;
1057 static ushort __initdata fifo_mode = 2;
1060 /* "modprobe ... fifo_mode=1" etc */
1061 module_param(fifo_mode, ushort, 0);
1062 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1065 * tables defining fifo_mode values. define more if you like.
1066 * for host side, make sure both halves of ep1 are set up.
1069 /* mode 0 - fits in 2KB */
1070 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1071 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1072 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1073 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1074 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1075 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1078 /* mode 1 - fits in 4KB */
1079 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1080 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1081 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1082 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1083 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1084 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1087 /* mode 2 - fits in 4KB */
1088 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1089 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1090 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1091 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1092 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1093 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1094 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1097 /* mode 3 - fits in 4KB */
1098 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1099 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1100 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1101 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1102 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1103 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1104 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1107 /* mode 4 - fits in 16KB */
1108 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1109 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1110 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1111 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1112 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1113 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1114 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1115 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1116 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1117 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1118 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1119 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1120 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1121 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1122 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1123 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1124 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1125 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1126 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1127 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1128 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1129 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1130 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1131 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1132 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1133 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1134 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1135 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1138 /* mode 5 - fits in 8KB */
1139 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1140 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1141 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1142 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1143 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1144 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1145 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1146 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1147 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1148 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1149 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1150 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1151 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1152 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1153 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1154 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1155 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1156 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1157 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1158 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1159 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1160 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1161 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1162 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1163 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1164 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1165 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1166 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1170 * configure a fifo; for non-shared endpoints, this may be called
1171 * once for a tx fifo and once for an rx fifo.
1173 * returns negative errno or offset for next fifo.
1176 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1177 const struct musb_fifo_cfg *cfg, u16 offset)
1179 void __iomem *mbase = musb->mregs;
1181 u16 maxpacket = cfg->maxpacket;
1182 u16 c_off = offset >> 3;
1185 /* expect hw_ep has already been zero-initialized */
1187 size = ffs(max(maxpacket, (u16) 8)) - 1;
1188 maxpacket = 1 << size;
1191 if (cfg->mode == BUF_DOUBLE) {
1192 if ((offset + (maxpacket << 1)) >
1193 (1 << (musb->config->ram_bits + 2)))
1195 c_size |= MUSB_FIFOSZ_DPB;
1197 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1201 /* configure the FIFO */
1202 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1204 /* EP0 reserved endpoint for control, bidirectional;
1205 * EP1 reserved for bulk, two unidirection halves.
1207 if (hw_ep->epnum == 1)
1208 musb->bulk_ep = hw_ep;
1209 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1210 switch (cfg->style) {
1212 musb_write_txfifosz(mbase, c_size);
1213 musb_write_txfifoadd(mbase, c_off);
1214 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1215 hw_ep->max_packet_sz_tx = maxpacket;
1218 musb_write_rxfifosz(mbase, c_size);
1219 musb_write_rxfifoadd(mbase, c_off);
1220 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1221 hw_ep->max_packet_sz_rx = maxpacket;
1224 musb_write_txfifosz(mbase, c_size);
1225 musb_write_txfifoadd(mbase, c_off);
1226 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1227 hw_ep->max_packet_sz_rx = maxpacket;
1229 musb_write_rxfifosz(mbase, c_size);
1230 musb_write_rxfifoadd(mbase, c_off);
1231 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1232 hw_ep->max_packet_sz_tx = maxpacket;
1234 hw_ep->is_shared_fifo = true;
1238 /* NOTE rx and tx endpoint irqs aren't managed separately,
1239 * which happens to be ok
1241 musb->epmask |= (1 << hw_ep->epnum);
1243 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1246 static struct musb_fifo_cfg __initdata ep0_cfg = {
1247 .style = FIFO_RXTX, .maxpacket = 64,
1250 static int __init ep_config_from_table(struct musb *musb)
1252 const struct musb_fifo_cfg *cfg;
1255 struct musb_hw_ep *hw_ep = musb->endpoints;
1257 if (musb->config->fifo_cfg) {
1258 cfg = musb->config->fifo_cfg;
1259 n = musb->config->fifo_cfg_size;
1263 switch (fifo_mode) {
1269 n = ARRAY_SIZE(mode_0_cfg);
1273 n = ARRAY_SIZE(mode_1_cfg);
1277 n = ARRAY_SIZE(mode_2_cfg);
1281 n = ARRAY_SIZE(mode_3_cfg);
1285 n = ARRAY_SIZE(mode_4_cfg);
1289 n = ARRAY_SIZE(mode_5_cfg);
1293 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1294 musb_driver_name, fifo_mode);
1298 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1299 /* assert(offset > 0) */
1301 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1302 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1305 for (i = 0; i < n; i++) {
1306 u8 epn = cfg->hw_ep_num;
1308 if (epn >= musb->config->num_eps) {
1309 pr_debug("%s: invalid ep %d\n",
1310 musb_driver_name, epn);
1313 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1315 pr_debug("%s: mem overrun, ep %d\n",
1316 musb_driver_name, epn);
1320 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1323 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1325 n + 1, musb->config->num_eps * 2 - 1,
1326 offset, (1 << (musb->config->ram_bits + 2)));
1328 if (!musb->bulk_ep) {
1329 pr_debug("%s: missing bulk\n", musb_driver_name);
1338 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1339 * @param musb the controller
1341 static int __init ep_config_from_hw(struct musb *musb)
1344 struct musb_hw_ep *hw_ep;
1345 void *mbase = musb->mregs;
1348 dev_dbg(musb->controller, "<== static silicon ep config\n");
1350 /* FIXME pick up ep0 maxpacket size */
1352 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1353 musb_ep_select(mbase, epnum);
1354 hw_ep = musb->endpoints + epnum;
1356 ret = musb_read_fifosize(musb, hw_ep, epnum);
1360 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1362 /* pick an RX/TX endpoint for bulk */
1363 if (hw_ep->max_packet_sz_tx < 512
1364 || hw_ep->max_packet_sz_rx < 512)
1367 /* REVISIT: this algorithm is lazy, we should at least
1368 * try to pick a double buffered endpoint.
1372 musb->bulk_ep = hw_ep;
1375 if (!musb->bulk_ep) {
1376 pr_debug("%s: missing bulk\n", musb_driver_name);
1383 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1385 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1386 * configure endpoints, or take their config from silicon
1388 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1392 char aInfo[90], aRevision[32], aDate[12];
1393 void __iomem *mbase = musb->mregs;
1397 /* log core options (read using indexed model) */
1398 reg = musb_read_configdata(mbase);
1400 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1401 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1402 strcat(aInfo, ", dyn FIFOs");
1403 musb->dyn_fifo = true;
1405 if (reg & MUSB_CONFIGDATA_MPRXE) {
1406 strcat(aInfo, ", bulk combine");
1407 musb->bulk_combine = true;
1409 if (reg & MUSB_CONFIGDATA_MPTXE) {
1410 strcat(aInfo, ", bulk split");
1411 musb->bulk_split = true;
1413 if (reg & MUSB_CONFIGDATA_HBRXE) {
1414 strcat(aInfo, ", HB-ISO Rx");
1415 musb->hb_iso_rx = true;
1417 if (reg & MUSB_CONFIGDATA_HBTXE) {
1418 strcat(aInfo, ", HB-ISO Tx");
1419 musb->hb_iso_tx = true;
1421 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1422 strcat(aInfo, ", SoftConn");
1424 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1425 musb_driver_name, reg, aInfo);
1428 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1429 musb->is_multipoint = 1;
1432 musb->is_multipoint = 0;
1434 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1436 "%s: kernel must blacklist external hubs\n",
1441 /* log release info */
1442 musb->hwvers = musb_read_hwvers(mbase);
1443 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1444 MUSB_HWVERS_MINOR(musb->hwvers),
1445 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1446 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1447 musb_driver_name, type, aRevision, aDate);
1450 musb_configure_ep0(musb);
1452 /* discover endpoint configuration */
1453 musb->nr_endpoints = 1;
1457 status = ep_config_from_table(musb);
1459 status = ep_config_from_hw(musb);
1464 /* finish init, and print endpoint config */
1465 for (i = 0; i < musb->nr_endpoints; i++) {
1466 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1468 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1469 #ifdef CONFIG_USB_MUSB_TUSB6010
1470 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1471 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1472 hw_ep->fifo_sync_va =
1473 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1476 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1478 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1481 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1482 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1483 hw_ep->rx_reinit = 1;
1484 hw_ep->tx_reinit = 1;
1486 if (hw_ep->max_packet_sz_tx) {
1487 dev_dbg(musb->controller,
1488 "%s: hw_ep %d%s, %smax %d\n",
1489 musb_driver_name, i,
1490 hw_ep->is_shared_fifo ? "shared" : "tx",
1491 hw_ep->tx_double_buffered
1492 ? "doublebuffer, " : "",
1493 hw_ep->max_packet_sz_tx);
1495 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1496 dev_dbg(musb->controller,
1497 "%s: hw_ep %d%s, %smax %d\n",
1498 musb_driver_name, i,
1500 hw_ep->rx_double_buffered
1501 ? "doublebuffer, " : "",
1502 hw_ep->max_packet_sz_rx);
1504 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1505 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1511 /*-------------------------------------------------------------------------*/
1513 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1514 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
1516 static irqreturn_t generic_interrupt(int irq, void *__hci)
1518 unsigned long flags;
1519 irqreturn_t retval = IRQ_NONE;
1520 struct musb *musb = __hci;
1522 spin_lock_irqsave(&musb->lock, flags);
1524 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1525 /* SOF is not enabled, but status is still often set */
1526 musb->int_usb &= ~MUSB_INTR_SOF;
1527 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1528 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1530 if (musb->int_usb || musb->int_tx || musb->int_rx)
1531 retval = musb_interrupt(musb);
1533 spin_unlock_irqrestore(&musb->lock, flags);
1539 #define generic_interrupt NULL
1543 * handle all the irqs defined by the HDRC core. for now we expect: other
1544 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1545 * will be assigned, and the irq will already have been acked.
1547 * called in irq context with spinlock held, irqs blocked
1549 irqreturn_t musb_interrupt(struct musb *musb)
1551 irqreturn_t retval = IRQ_NONE;
1556 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1557 power = musb_readb(musb->mregs, MUSB_POWER);
1559 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1560 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1561 musb->int_usb, musb->int_tx, musb->int_rx);
1563 /* the core can interrupt us for multiple reasons; docs have
1564 * a generic interrupt flowchart to follow
1567 retval |= musb_stage0_irq(musb, musb->int_usb,
1570 /* "stage 1" is handling endpoint irqs */
1572 /* handle endpoint 0 first */
1573 if (musb->int_tx & 1) {
1574 if (devctl & MUSB_DEVCTL_HM)
1575 retval |= musb_h_ep0_irq(musb);
1577 retval |= musb_g_ep0_irq(musb);
1580 /* RX on endpoints 1-15 */
1581 reg = musb->int_rx >> 1;
1585 /* musb_ep_select(musb->mregs, ep_num); */
1586 /* REVISIT just retval = ep->rx_irq(...) */
1587 retval = IRQ_HANDLED;
1588 if (devctl & MUSB_DEVCTL_HM) {
1589 if (is_host_capable())
1590 musb_host_rx(musb, ep_num);
1592 if (is_peripheral_capable())
1593 musb_g_rx(musb, ep_num);
1601 /* TX on endpoints 1-15 */
1602 reg = musb->int_tx >> 1;
1606 /* musb_ep_select(musb->mregs, ep_num); */
1607 /* REVISIT just retval |= ep->tx_irq(...) */
1608 retval = IRQ_HANDLED;
1609 if (devctl & MUSB_DEVCTL_HM) {
1610 if (is_host_capable())
1611 musb_host_tx(musb, ep_num);
1613 if (is_peripheral_capable())
1614 musb_g_tx(musb, ep_num);
1623 EXPORT_SYMBOL_GPL(musb_interrupt);
1625 #ifndef CONFIG_MUSB_PIO_ONLY
1626 static int __initdata use_dma = 1;
1628 /* "modprobe ... use_dma=0" etc */
1629 module_param(use_dma, bool, 0);
1630 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1632 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1634 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1636 /* called with controller lock already held */
1639 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1640 if (!is_cppi_enabled()) {
1642 if (devctl & MUSB_DEVCTL_HM)
1643 musb_h_ep0_irq(musb);
1645 musb_g_ep0_irq(musb);
1649 /* endpoints 1..15 */
1651 if (devctl & MUSB_DEVCTL_HM) {
1652 if (is_host_capable())
1653 musb_host_tx(musb, epnum);
1655 if (is_peripheral_capable())
1656 musb_g_tx(musb, epnum);
1660 if (devctl & MUSB_DEVCTL_HM) {
1661 if (is_host_capable())
1662 musb_host_rx(musb, epnum);
1664 if (is_peripheral_capable())
1665 musb_g_rx(musb, epnum);
1675 /*-------------------------------------------------------------------------*/
1680 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1682 struct musb *musb = dev_to_musb(dev);
1683 unsigned long flags;
1686 spin_lock_irqsave(&musb->lock, flags);
1687 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1688 spin_unlock_irqrestore(&musb->lock, flags);
1694 musb_mode_store(struct device *dev, struct device_attribute *attr,
1695 const char *buf, size_t n)
1697 struct musb *musb = dev_to_musb(dev);
1698 unsigned long flags;
1701 spin_lock_irqsave(&musb->lock, flags);
1702 if (sysfs_streq(buf, "host"))
1703 status = musb_platform_set_mode(musb, MUSB_HOST);
1704 else if (sysfs_streq(buf, "peripheral"))
1705 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1706 else if (sysfs_streq(buf, "otg"))
1707 status = musb_platform_set_mode(musb, MUSB_OTG);
1710 spin_unlock_irqrestore(&musb->lock, flags);
1712 return (status == 0) ? n : status;
1714 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1717 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1718 const char *buf, size_t n)
1720 struct musb *musb = dev_to_musb(dev);
1721 unsigned long flags;
1724 if (sscanf(buf, "%lu", &val) < 1) {
1725 dev_err(dev, "Invalid VBUS timeout ms value\n");
1729 spin_lock_irqsave(&musb->lock, flags);
1730 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1731 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1732 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1733 musb->is_active = 0;
1734 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1735 spin_unlock_irqrestore(&musb->lock, flags);
1741 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1743 struct musb *musb = dev_to_musb(dev);
1744 unsigned long flags;
1748 spin_lock_irqsave(&musb->lock, flags);
1749 val = musb->a_wait_bcon;
1750 /* FIXME get_vbus_status() is normally #defined as false...
1751 * and is effectively TUSB-specific.
1753 vbus = musb_platform_get_vbus_status(musb);
1754 spin_unlock_irqrestore(&musb->lock, flags);
1756 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1757 vbus ? "on" : "off", val);
1759 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1761 /* Gadget drivers can't know that a host is connected so they might want
1762 * to start SRP, but users can. This allows userspace to trigger SRP.
1765 musb_srp_store(struct device *dev, struct device_attribute *attr,
1766 const char *buf, size_t n)
1768 struct musb *musb = dev_to_musb(dev);
1771 if (sscanf(buf, "%hu", &srp) != 1
1773 dev_err(dev, "SRP: Value must be 1\n");
1778 musb_g_wakeup(musb);
1782 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1784 static struct attribute *musb_attributes[] = {
1785 &dev_attr_mode.attr,
1786 &dev_attr_vbus.attr,
1791 static const struct attribute_group musb_attr_group = {
1792 .attrs = musb_attributes,
1797 /* Only used to provide driver mode change events */
1798 static void musb_irq_work(struct work_struct *data)
1800 struct musb *musb = container_of(data, struct musb, irq_work);
1801 static int old_state;
1803 if (musb->xceiv->state != old_state) {
1804 old_state = musb->xceiv->state;
1805 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1809 #include <linux/usb/ulpi.h>
1811 static void musb_vbus_workaround_work(struct work_struct *work)
1813 struct musb *musb = container_of(work, struct musb, vbus_workaround_work.work);
1817 if (musb_ulpi_access.write == NULL)
1820 pm_runtime_get_sync(musb->controller);
1822 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1825 * I don't really know why but VBUS sometimes gets stuck and
1826 * causes session to never end. It would look like some pullup
1827 * is enabled when it shouldn't be on certain PHY states.
1828 * Turning on pulldowns magically drains VBUS to zero and allows
1829 * session to end, so let's do that here.
1831 * XXX: probably better check VBUS on TWL?
1832 * beagle sometimes has session bit set but no VBUS on twl?
1834 if ((musb->xceiv->state == OTG_STATE_B_PERIPHERAL ||
1835 musb->xceiv->state == OTG_STATE_B_IDLE) &&
1836 (devctl & MUSB_DEVCTL_VBUS) != (3 << MUSB_DEVCTL_VBUS_SHIFT) &&
1837 (devctl & MUSB_DEVCTL_VBUS) != (0 << MUSB_DEVCTL_VBUS_SHIFT)) {
1838 dev_dbg(musb->controller, "VBUS workaround..\n");
1839 ret = musb_ulpi_access.write(musb->xceiv, ULPI_SET(ULPI_OTG_CTRL),
1840 ULPI_OTG_CTRL_DM_PULLDOWN | ULPI_OTG_CTRL_DP_PULLDOWN);
1842 // dev_err(musb->controller, "VBUS workaround error\n");
1845 pm_runtime_put(musb->controller);
1848 /* --------------------------------------------------------------------------
1852 static struct musb *__init
1853 allocate_instance(struct device *dev,
1854 struct musb_hdrc_config *config, void __iomem *mbase)
1857 struct musb_hw_ep *ep;
1859 struct usb_hcd *hcd;
1861 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1864 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1866 musb = hcd_to_musb(hcd);
1867 INIT_LIST_HEAD(&musb->control);
1868 INIT_LIST_HEAD(&musb->in_bulk);
1869 INIT_LIST_HEAD(&musb->out_bulk);
1871 hcd->uses_new_polling = 1;
1874 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1875 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1876 dev_set_drvdata(dev, musb);
1877 musb->mregs = mbase;
1878 musb->ctrl_base = mbase;
1879 musb->nIrq = -ENODEV;
1880 musb->config = config;
1881 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1882 for (epnum = 0, ep = musb->endpoints;
1883 epnum < musb->config->num_eps;
1889 musb->controller = dev;
1894 static void musb_free(struct musb *musb)
1896 /* this has multiple entry modes. it handles fault cleanup after
1897 * probe(), where things may be partially set up, as well as rmmod
1898 * cleanup after everything's been de-activated.
1902 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1905 if (musb->nIrq >= 0) {
1907 disable_irq_wake(musb->nIrq);
1908 free_irq(musb->nIrq, musb);
1910 if (is_dma_capable() && musb->dma_controller) {
1911 struct dma_controller *c = musb->dma_controller;
1914 dma_controller_destroy(c);
1917 usb_put_hcd(musb_to_hcd(musb));
1921 * Perform generic per-controller initialization.
1923 * @pDevice: the controller (already clocked, etc)
1925 * @mregs: virtual address of controller registers,
1926 * not yet corrected for platform-specific offsets
1929 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1933 struct musb_hdrc_platform_data *plat = dev->platform_data;
1935 /* The driver might handle more features than the board; OK.
1936 * Fail when the board needs a feature that's not enabled.
1939 dev_dbg(dev, "no platform_data?\n");
1945 musb = allocate_instance(dev, plat->config, ctrl);
1951 pm_runtime_use_autosuspend(musb->controller);
1952 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1953 pm_runtime_enable(musb->controller);
1955 spin_lock_init(&musb->lock);
1956 musb->board_mode = plat->mode;
1957 musb->board_set_power = plat->set_power;
1958 musb->min_power = plat->min_power;
1959 musb->ops = plat->platform_ops;
1961 /* The musb_platform_init() call:
1962 * - adjusts musb->mregs and musb->isr if needed,
1963 * - may initialize an integrated tranceiver
1964 * - initializes musb->xceiv, usually by otg_get_transceiver()
1965 * - stops powering VBUS
1967 * There are various transceiver configurations. Blackfin,
1968 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1969 * external/discrete ones in various flavors (twl4030 family,
1970 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1972 musb->isr = generic_interrupt;
1973 status = musb_platform_init(musb);
1982 if (!musb->xceiv->io_ops) {
1983 musb->xceiv->io_dev = musb->controller;
1984 musb->xceiv->io_priv = musb->mregs;
1985 musb->xceiv->io_ops = &musb_ulpi_access;
1988 #ifndef CONFIG_MUSB_PIO_ONLY
1989 if (use_dma && dev->dma_mask) {
1990 struct dma_controller *c;
1992 c = dma_controller_create(musb, musb->mregs);
1993 musb->dma_controller = c;
1998 /* ideally this would be abstracted in platform setup */
1999 if (!is_dma_capable() || !musb->dma_controller)
2000 dev->dma_mask = NULL;
2002 /* be sure interrupts are disabled before connecting ISR */
2003 musb_platform_disable(musb);
2004 musb_generic_disable(musb);
2006 /* setup musb parts of the core (especially endpoints) */
2007 status = musb_core_init(plat->config->multipoint
2008 ? MUSB_CONTROLLER_MHDRC
2009 : MUSB_CONTROLLER_HDRC, musb);
2013 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2015 /* Init IRQ workqueue before request_irq */
2016 INIT_WORK(&musb->irq_work, musb_irq_work);
2018 INIT_DELAYED_WORK(&musb->vbus_workaround_work, musb_vbus_workaround_work);
2020 /* attach to the IRQ */
2021 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2022 dev_err(dev, "request_irq %d failed!\n", nIrq);
2027 /* FIXME this handles wakeup irqs wrong */
2028 if (enable_irq_wake(nIrq) == 0) {
2030 device_init_wakeup(dev, 1);
2035 /* host side needs more setup */
2036 if (is_host_enabled(musb)) {
2037 struct usb_hcd *hcd = musb_to_hcd(musb);
2039 otg_set_host(musb->xceiv, &hcd->self);
2041 if (is_otg_enabled(musb))
2042 hcd->self.otg_port = 1;
2043 musb->xceiv->host = &hcd->self;
2044 hcd->power_budget = 2 * (plat->power ? : 250);
2046 /* program PHY to use external vBus if required */
2047 if (plat->extvbus) {
2048 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2049 busctl |= MUSB_ULPI_USE_EXTVBUS;
2050 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2054 /* For the host-only role, we can activate right away.
2055 * (We expect the ID pin to be forcibly grounded!!)
2056 * Otherwise, wait till the gadget driver hooks up.
2058 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2059 struct usb_hcd *hcd = musb_to_hcd(musb);
2061 MUSB_HST_MODE(musb);
2062 musb->xceiv->default_a = 1;
2063 musb->xceiv->state = OTG_STATE_A_IDLE;
2065 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2067 hcd->self.uses_pio_for_control = 1;
2068 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2070 musb_readb(musb->mregs, MUSB_DEVCTL),
2071 (musb_readb(musb->mregs, MUSB_DEVCTL)
2072 & MUSB_DEVCTL_BDEVICE
2075 } else /* peripheral is enabled */ {
2076 if (musb->xceiv->default_a) {
2077 MUSB_HST_MODE(musb);
2078 musb->xceiv->state = OTG_STATE_A_IDLE;
2080 MUSB_DEV_MODE(musb);
2081 musb->xceiv->state = OTG_STATE_B_IDLE;
2084 status = musb_gadget_setup(musb);
2086 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2087 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2089 musb_readb(musb->mregs, MUSB_DEVCTL));
2095 pm_runtime_put(musb->controller);
2097 status = musb_init_debugfs(musb);
2102 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2107 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2109 switch (musb->board_mode) {
2110 case MUSB_HOST: s = "Host"; break;
2111 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2112 default: s = "OTG"; break;
2115 (is_dma_capable() && musb->dma_controller)
2122 musb_exit_debugfs(musb);
2125 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2126 usb_remove_hcd(musb_to_hcd(musb));
2128 musb_gadget_cleanup(musb);
2132 device_init_wakeup(dev, 0);
2133 musb_platform_exit(musb);
2136 dev_err(musb->controller,
2137 "musb_init_controller failed with status %d\n", status);
2147 /*-------------------------------------------------------------------------*/
2149 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2150 * bridge to a platform device; this driver then suffices.
2153 #ifndef CONFIG_MUSB_PIO_ONLY
2154 static u64 *orig_dma_mask;
2157 static int __init musb_probe(struct platform_device *pdev)
2159 struct device *dev = &pdev->dev;
2160 int irq = platform_get_irq_byname(pdev, "mc");
2162 struct resource *iomem;
2165 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2166 if (!iomem || irq <= 0)
2169 base = ioremap(iomem->start, resource_size(iomem));
2171 dev_err(dev, "ioremap failed\n");
2175 #ifndef CONFIG_MUSB_PIO_ONLY
2176 /* clobbered by use_dma=n */
2177 orig_dma_mask = dev->dma_mask;
2179 status = musb_init_controller(dev, irq, base);
2186 static int __exit musb_remove(struct platform_device *pdev)
2188 struct musb *musb = dev_to_musb(&pdev->dev);
2189 void __iomem *ctrl_base = musb->ctrl_base;
2191 /* this gets called on rmmod.
2192 * - Host mode: host may still be active
2193 * - Peripheral mode: peripheral is deactivated (or never-activated)
2194 * - OTG mode: both roles are deactivated (or never-activated)
2196 musb_exit_debugfs(musb);
2197 musb_shutdown(pdev);
2201 device_init_wakeup(&pdev->dev, 0);
2202 #ifndef CONFIG_MUSB_PIO_ONLY
2203 pdev->dev.dma_mask = orig_dma_mask;
2210 static void musb_save_context(struct musb *musb)
2213 void __iomem *musb_base = musb->mregs;
2216 if (is_host_enabled(musb)) {
2217 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2218 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2219 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2221 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2222 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2223 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2224 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2225 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2226 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2228 for (i = 0; i < musb->config->num_eps; ++i) {
2229 struct musb_hw_ep *hw_ep;
2231 hw_ep = &musb->endpoints[i];
2239 musb_writeb(musb_base, MUSB_INDEX, i);
2240 musb->context.index_regs[i].txmaxp =
2241 musb_readw(epio, MUSB_TXMAXP);
2242 musb->context.index_regs[i].txcsr =
2243 musb_readw(epio, MUSB_TXCSR);
2244 musb->context.index_regs[i].rxmaxp =
2245 musb_readw(epio, MUSB_RXMAXP);
2246 musb->context.index_regs[i].rxcsr =
2247 musb_readw(epio, MUSB_RXCSR);
2249 if (musb->dyn_fifo) {
2250 musb->context.index_regs[i].txfifoadd =
2251 musb_read_txfifoadd(musb_base);
2252 musb->context.index_regs[i].rxfifoadd =
2253 musb_read_rxfifoadd(musb_base);
2254 musb->context.index_regs[i].txfifosz =
2255 musb_read_txfifosz(musb_base);
2256 musb->context.index_regs[i].rxfifosz =
2257 musb_read_rxfifosz(musb_base);
2259 if (is_host_enabled(musb)) {
2260 musb->context.index_regs[i].txtype =
2261 musb_readb(epio, MUSB_TXTYPE);
2262 musb->context.index_regs[i].txinterval =
2263 musb_readb(epio, MUSB_TXINTERVAL);
2264 musb->context.index_regs[i].rxtype =
2265 musb_readb(epio, MUSB_RXTYPE);
2266 musb->context.index_regs[i].rxinterval =
2267 musb_readb(epio, MUSB_RXINTERVAL);
2269 musb->context.index_regs[i].txfunaddr =
2270 musb_read_txfunaddr(musb_base, i);
2271 musb->context.index_regs[i].txhubaddr =
2272 musb_read_txhubaddr(musb_base, i);
2273 musb->context.index_regs[i].txhubport =
2274 musb_read_txhubport(musb_base, i);
2276 musb->context.index_regs[i].rxfunaddr =
2277 musb_read_rxfunaddr(musb_base, i);
2278 musb->context.index_regs[i].rxhubaddr =
2279 musb_read_rxhubaddr(musb_base, i);
2280 musb->context.index_regs[i].rxhubport =
2281 musb_read_rxhubport(musb_base, i);
2286 static void musb_restore_context(struct musb *musb)
2289 void __iomem *musb_base = musb->mregs;
2290 void __iomem *ep_target_regs;
2293 if (is_host_enabled(musb)) {
2294 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2295 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2296 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2298 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2299 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2300 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2301 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2302 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2304 for (i = 0; i < musb->config->num_eps; ++i) {
2305 struct musb_hw_ep *hw_ep;
2307 hw_ep = &musb->endpoints[i];
2315 musb_writeb(musb_base, MUSB_INDEX, i);
2316 musb_writew(epio, MUSB_TXMAXP,
2317 musb->context.index_regs[i].txmaxp);
2318 musb_writew(epio, MUSB_TXCSR,
2319 musb->context.index_regs[i].txcsr);
2320 musb_writew(epio, MUSB_RXMAXP,
2321 musb->context.index_regs[i].rxmaxp);
2322 musb_writew(epio, MUSB_RXCSR,
2323 musb->context.index_regs[i].rxcsr);
2325 if (musb->dyn_fifo) {
2326 musb_write_txfifosz(musb_base,
2327 musb->context.index_regs[i].txfifosz);
2328 musb_write_rxfifosz(musb_base,
2329 musb->context.index_regs[i].rxfifosz);
2330 musb_write_txfifoadd(musb_base,
2331 musb->context.index_regs[i].txfifoadd);
2332 musb_write_rxfifoadd(musb_base,
2333 musb->context.index_regs[i].rxfifoadd);
2336 if (is_host_enabled(musb)) {
2337 musb_writeb(epio, MUSB_TXTYPE,
2338 musb->context.index_regs[i].txtype);
2339 musb_writeb(epio, MUSB_TXINTERVAL,
2340 musb->context.index_regs[i].txinterval);
2341 musb_writeb(epio, MUSB_RXTYPE,
2342 musb->context.index_regs[i].rxtype);
2343 musb_writeb(epio, MUSB_RXINTERVAL,
2345 musb->context.index_regs[i].rxinterval);
2346 musb_write_txfunaddr(musb_base, i,
2347 musb->context.index_regs[i].txfunaddr);
2348 musb_write_txhubaddr(musb_base, i,
2349 musb->context.index_regs[i].txhubaddr);
2350 musb_write_txhubport(musb_base, i,
2351 musb->context.index_regs[i].txhubport);
2354 musb_read_target_reg_base(i, musb_base);
2356 musb_write_rxfunaddr(ep_target_regs,
2357 musb->context.index_regs[i].rxfunaddr);
2358 musb_write_rxhubaddr(ep_target_regs,
2359 musb->context.index_regs[i].rxhubaddr);
2360 musb_write_rxhubport(ep_target_regs,
2361 musb->context.index_regs[i].rxhubport);
2364 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2367 static int musb_suspend(struct device *dev)
2369 struct musb *musb = dev_to_musb(dev);
2370 unsigned long flags;
2373 spin_lock_irqsave(&musb->lock, flags);
2376 /* FIXME force disconnect unless we know USB will wake
2377 * the system up quickly enough to respond ...
2380 * FIXME: musb must be already runtime suspended at this point.
2381 * If it's not, framework will try to suspend it late when
2382 * i2c will be off, and twl4030 will want to access it for it's
2383 * stuff, causing data abort.
2385 int pm_usage_count =
2386 atomic_read(&musb->controller->power.usage_count);
2387 if (pm_usage_count > 1) {
2388 dev_err(dev, "can't suspend while still active, "
2389 "try removing gadget drivers (usage_count %d)\n",
2395 spin_unlock_irqrestore(&musb->lock, flags);
2399 static int musb_resume_noirq(struct device *dev)
2401 /* for static cmos like DaVinci, register values were preserved
2402 * unless for some reason the whole soc powered down or the USB
2403 * module got reset through the PSC (vs just being disabled).
2408 static int musb_runtime_suspend(struct device *dev)
2410 struct musb *musb = dev_to_musb(dev);
2412 musb_save_context(musb);
2417 static int musb_runtime_resume(struct device *dev)
2419 struct musb *musb = dev_to_musb(dev);
2420 static int first = 1;
2423 * When pm_runtime_get_sync called for the first time in driver
2424 * init, some of the structure is still not initialized which is
2425 * used in restore function. But clock needs to be
2426 * enabled before any register access, so
2427 * pm_runtime_get_sync has to be called.
2428 * Also context restore without save does not make
2432 musb_restore_context(musb);
2438 static const struct dev_pm_ops musb_dev_pm_ops = {
2439 .suspend = musb_suspend,
2440 .resume_noirq = musb_resume_noirq,
2441 .runtime_suspend = musb_runtime_suspend,
2442 .runtime_resume = musb_runtime_resume,
2445 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2447 #define MUSB_DEV_PM_OPS NULL
2450 static struct platform_driver musb_driver = {
2452 .name = (char *)musb_driver_name,
2453 .bus = &platform_bus_type,
2454 .owner = THIS_MODULE,
2455 .pm = MUSB_DEV_PM_OPS,
2457 .remove = __exit_p(musb_remove),
2458 .shutdown = musb_shutdown,
2461 /*-------------------------------------------------------------------------*/
2463 static int __init musb_init(void)
2468 pr_info("%s: version " MUSB_VERSION ", ?dma?, otg (peripheral+host)\n",
2470 return platform_driver_probe(&musb_driver, musb_probe);
2473 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2474 * and before usb gadget and host-side drivers start to register
2476 fs_initcall(musb_init);
2478 static void __exit musb_cleanup(void)
2480 platform_driver_unregister(&musb_driver);
2482 module_exit(musb_cleanup);