2 * MUSB OTG controller driver for Blackfin Processors
4 * Copyright 2006-2008 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
14 #include <linux/init.h>
15 #include <linux/list.h>
16 #include <linux/gpio.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
21 #include <asm/cacheflush.h>
23 #include "musb_core.h"
28 struct platform_device *musb;
32 * Load an endpoint's FIFO
34 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
36 void __iomem *fifo = hw_ep->fifo;
37 void __iomem *epio = hw_ep->regs;
38 u8 epnum = hw_ep->epnum;
42 musb_writew(epio, MUSB_TXCOUNT, len);
44 DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
45 hw_ep->epnum, fifo, len, src, epio);
47 dump_fifo_data(src, len);
49 if (!ANOMALY_05000380 && epnum != 0) {
52 flush_dcache_range((unsigned long)src,
53 (unsigned long)(src + len));
55 /* Setup DMA address register */
57 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
60 dma_reg = (u32)src >> 16;
61 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
64 /* Setup DMA count register */
65 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
66 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
70 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
71 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
74 /* Wait for compelete */
75 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
78 /* acknowledge dma interrupt */
79 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
83 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
88 if (unlikely((unsigned long)src & 0x01))
89 outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
91 outsw((unsigned long)fifo, src, (len + 1) >> 1);
95 * Unload an endpoint's FIFO
97 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
99 void __iomem *fifo = hw_ep->fifo;
100 u8 epnum = hw_ep->epnum;
102 if (ANOMALY_05000467 && epnum != 0) {
105 invalidate_dcache_range((unsigned long)dst,
106 (unsigned long)(dst + len));
108 /* Setup DMA address register */
110 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
113 dma_reg = (u32)dst >> 16;
114 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
117 /* Setup DMA count register */
118 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
119 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
123 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
124 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
127 /* Wait for compelete */
128 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
131 /* acknowledge dma interrupt */
132 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
136 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
140 /* Read the last byte of packet with odd size from address fifo + 4
141 * to trigger 1 byte access to EP0 FIFO.
144 *dst = (u8)inw((unsigned long)fifo + 4);
146 if (unlikely((unsigned long)dst & 0x01))
147 insw_8((unsigned long)fifo, dst, len >> 1);
149 insw((unsigned long)fifo, dst, len >> 1);
152 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
155 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
156 'R', hw_ep->epnum, fifo, len, dst);
158 dump_fifo_data(dst, len);
161 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
164 irqreturn_t retval = IRQ_NONE;
165 struct musb *musb = __hci;
167 spin_lock_irqsave(&musb->lock, flags);
169 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
170 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
171 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
173 if (musb->int_usb || musb->int_tx || musb->int_rx) {
174 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
175 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
176 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
177 retval = musb_interrupt(musb);
180 /* Start sampling ID pin, when plug is removed from MUSB */
181 if (is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE
182 || musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
183 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
184 musb->a_wait_bcon = TIMER_DELAY;
187 spin_unlock_irqrestore(&musb->lock, flags);
192 static void musb_conn_timer_handler(unsigned long _musb)
194 struct musb *musb = (void *)_musb;
199 spin_lock_irqsave(&musb->lock, flags);
200 switch (musb->xceiv->state) {
201 case OTG_STATE_A_IDLE:
202 case OTG_STATE_A_WAIT_BCON:
203 /* Start a new session */
204 val = musb_readw(musb->mregs, MUSB_DEVCTL);
205 val &= ~MUSB_DEVCTL_SESSION;
206 musb_writew(musb->mregs, MUSB_DEVCTL, val);
207 val |= MUSB_DEVCTL_SESSION;
208 musb_writew(musb->mregs, MUSB_DEVCTL, val);
209 /* Check if musb is host or peripheral. */
210 val = musb_readw(musb->mregs, MUSB_DEVCTL);
212 if (!(val & MUSB_DEVCTL_BDEVICE)) {
213 gpio_set_value(musb->config->gpio_vrsel, 1);
214 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
216 gpio_set_value(musb->config->gpio_vrsel, 0);
217 /* Ignore VBUSERROR and SUSPEND IRQ */
218 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
219 val &= ~MUSB_INTR_VBUSERROR;
220 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
222 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
223 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
224 if (is_otg_enabled(musb))
225 musb->xceiv->state = OTG_STATE_B_IDLE;
227 musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
229 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
231 case OTG_STATE_B_IDLE:
233 if (!is_peripheral_enabled(musb))
235 /* Start a new session. It seems that MUSB needs taking
236 * some time to recognize the type of the plug inserted?
238 val = musb_readw(musb->mregs, MUSB_DEVCTL);
239 val |= MUSB_DEVCTL_SESSION;
240 musb_writew(musb->mregs, MUSB_DEVCTL, val);
241 val = musb_readw(musb->mregs, MUSB_DEVCTL);
243 if (!(val & MUSB_DEVCTL_BDEVICE)) {
244 gpio_set_value(musb->config->gpio_vrsel, 1);
245 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
247 gpio_set_value(musb->config->gpio_vrsel, 0);
249 /* Ignore VBUSERROR and SUSPEND IRQ */
250 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
251 val &= ~MUSB_INTR_VBUSERROR;
252 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
254 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
255 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
257 /* Toggle the Soft Conn bit, so that we can response to
258 * the inserting of either A-plug or B-plug.
261 val = musb_readb(musb->mregs, MUSB_POWER);
262 val &= ~MUSB_POWER_SOFTCONN;
263 musb_writeb(musb->mregs, MUSB_POWER, val);
266 val = musb_readb(musb->mregs, MUSB_POWER);
267 val |= MUSB_POWER_SOFTCONN;
268 musb_writeb(musb->mregs, MUSB_POWER, val);
271 /* The delay time is set to 1/4 second by default,
272 * shortening it, if accelerating A-plug detection
273 * is needed in OTG mode.
275 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
279 DBG(1, "%s state not handled\n", otg_state_string(musb));
282 spin_unlock_irqrestore(&musb->lock, flags);
284 DBG(4, "state is %s\n", otg_state_string(musb));
287 static void bfin_musb_enable(struct musb *musb)
289 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
290 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
291 musb->a_wait_bcon = TIMER_DELAY;
295 static void bfin_musb_disable(struct musb *musb)
299 static void bfin_musb_set_vbus(struct musb *musb, int is_on)
301 int value = musb->config->gpio_vrsel_active;
304 gpio_set_value(musb->config->gpio_vrsel, value);
306 DBG(1, "VBUS %s, devctl %02x "
307 /* otg %3x conf %08x prcm %08x */ "\n",
308 otg_state_string(musb),
309 musb_readb(musb->mregs, MUSB_DEVCTL));
312 static int bfin_musb_set_power(struct otg_transceiver *x, unsigned mA)
317 static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
319 if (!is_otg_enabled(musb) && is_host_enabled(musb))
320 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
323 static int bfin_musb_get_vbus_status(struct musb *musb)
328 static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
333 static void bfin_musb_reg_init(struct musb *musb)
335 if (ANOMALY_05000346) {
336 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
340 if (ANOMALY_05000347) {
341 bfin_write_USB_APHY_CNTRL(0x0);
345 /* Configure PLL oscillator register */
346 bfin_write_USB_PLLOSC_CTRL(0x30a8);
349 bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
352 bfin_write_USB_EP_NI0_RXMAXP(64);
355 bfin_write_USB_EP_NI0_TXMAXP(64);
358 /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
359 bfin_write_USB_GLOBINTR(0x7);
362 bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
363 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
364 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
365 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
366 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
370 static int bfin_musb_init(struct musb *musb)
374 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
375 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
376 * be low for DEVICE mode and high for HOST mode. We set it high
377 * here because we are in host mode
380 if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
381 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
382 musb->config->gpio_vrsel);
385 gpio_direction_output(musb->config->gpio_vrsel, 0);
387 usb_nop_xceiv_register();
388 musb->xceiv = otg_get_transceiver();
390 gpio_free(musb->config->gpio_vrsel);
394 bfin_musb_reg_init(musb);
396 if (is_host_enabled(musb)) {
397 musb->board_set_vbus = bfin_musb_set_vbus;
398 setup_timer(&musb_conn_timer,
399 musb_conn_timer_handler, (unsigned long) musb);
401 if (is_peripheral_enabled(musb))
402 musb->xceiv->set_power = bfin_musb_set_power;
404 musb->isr = blackfin_interrupt;
410 void musb_platform_save_context(struct musb *musb,
411 struct musb_context_registers *musb_context)
413 if (is_host_active(musb))
415 * During hibernate gpio_vrsel will change from high to low
416 * low which will generate wakeup event resume the system
417 * immediately. Set it to 0 before hibernate to avoid this
420 gpio_set_value(musb->config->gpio_vrsel, 0);
423 void musb_platform_restore_context(struct musb *musb,
424 struct musb_context_registers *musb_context)
426 bfin_musb_reg_init(musb);
430 static int bfin_musb_exit(struct musb *musb)
432 gpio_free(musb->config->gpio_vrsel);
434 otg_put_transceiver(musb->xceiv);
435 usb_nop_xceiv_unregister();
439 const struct musb_platform_ops musb_ops = {
440 .init = bfin_musb_init,
441 .exit = bfin_musb_exit,
443 .enable = bfin_musb_enable,
444 .disable = bfin_musb_disable,
446 .set_mode = bfin_musb_set_mode,
447 .try_idle = bfin_musb_try_idle,
449 .vbus_status = bfin_musb_vbus_status,
450 .set_vbus = bfin_musb_set_vbus,
453 static u64 bfin_dmamask = DMA_BIT_MASK(32);
455 static int __init bfin_probe(struct platform_device *pdev)
457 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
458 struct platform_device *musb;
459 struct bfin_glue *glue;
463 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
465 dev_err(&pdev->dev, "failed to allocate glue context\n");
469 musb = platform_device_alloc("musb-hdrc", -1);
471 dev_err(&pdev->dev, "failed to allocate musb device\n");
475 musb->dev.parent = &pdev->dev;
476 musb->dev.dma_mask = &bfin_dmamask;
477 musb->dev.coherent_dma_mask = bfin_dmamask;
479 glue->dev = &pdev->dev;
482 platform_set_drvdata(pdev, glue);
484 ret = platform_device_add_resources(musb, pdev->resource,
485 pdev->num_resources);
487 dev_err(&pdev->dev, "failed to add resources\n");
491 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
493 dev_err(&pdev->dev, "failed to add platform_data\n");
497 ret = platform_device_add(musb);
499 dev_err(&pdev->dev, "failed to register musb device\n");
506 platform_device_put(musb);
515 static int __exit bfin_remove(struct platform_device *pdev)
517 struct bfin_glue *glue = platform_get_drvdata(pdev);
519 platform_device_del(glue->musb);
520 platform_device_put(glue->musb);
526 static struct platform_driver bfin_driver = {
527 .remove = __exit_p(bfin_remove),
533 MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
534 MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
535 MODULE_LICENSE("GPL v2");
537 static int __init bfin_init(void)
539 return platform_driver_probe(&bfin_driver, bfin_probe);
541 subsys_initcall(bfin_init);
543 static void __exit bfin_exit(void)
545 platform_driver_unregister(&bfin_driver);
547 module_exit(bfin_exit);