3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software Foundation,
21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #ifndef __LINUX_XHCI_HCD_H
25 #define __LINUX_XHCI_HCD_H
27 #include <linux/usb.h>
28 #include <linux/timer.h>
29 #include <linux/kernel.h>
30 #include <linux/usb/hcd.h>
32 /* Code sharing between pci-quirks and xhci hcd */
33 #include "xhci-ext-caps.h"
34 #include "pci-quirks.h"
36 /* xHCI PCI Configuration Registers */
37 #define XHCI_SBRN_OFFSET (0x60)
39 /* Max number of USB devices for any host controller - limit in section 6.1 */
40 #define MAX_HC_SLOTS 256
41 /* Section 5.3.3 - MaxPorts */
42 #define MAX_HC_PORTS 127
45 * xHCI register interface.
46 * This corresponds to the eXtensible Host Controller Interface (xHCI)
47 * Revision 0.95 specification
51 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
52 * @hc_capbase: length of the capabilities register and HC version number
53 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
54 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
55 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
56 * @hcc_params: HCCPARAMS - Capability Parameters
57 * @db_off: DBOFF - Doorbell array offset
58 * @run_regs_off: RTSOFF - Runtime register space offset
60 struct xhci_cap_regs {
68 /* Reserved up to (CAPLENGTH - 0x1C) */
71 /* hc_capbase bitmasks */
72 /* bits 7:0 - how long is the Capabilities register */
73 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
75 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
77 /* HCSPARAMS1 - hcs_params1 - bitmasks */
78 /* bits 0:7, Max Device Slots */
79 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
80 #define HCS_SLOTS_MASK 0xff
81 /* bits 8:18, Max Interrupters */
82 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
83 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
84 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
86 /* HCSPARAMS2 - hcs_params2 - bitmasks */
87 /* bits 0:3, frames or uframes that SW needs to queue transactions
88 * ahead of the HW to meet periodic deadlines */
89 #define HCS_IST(p) (((p) >> 0) & 0xf)
90 /* bits 4:7, max number of Event Ring segments */
91 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
92 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
93 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
94 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
95 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
97 /* HCSPARAMS3 - hcs_params3 - bitmasks */
98 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
99 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
100 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
101 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
103 /* HCCPARAMS - hcc_params - bitmasks */
104 /* true: HC can use 64-bit address pointers */
105 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
106 /* true: HC can do bandwidth negotiation */
107 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
108 /* true: HC uses 64-byte Device Context structures
109 * FIXME 64-byte context structures aren't supported yet.
111 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
112 /* true: HC has port power switches */
113 #define HCC_PPC(p) ((p) & (1 << 3))
114 /* true: HC has port indicators */
115 #define HCS_INDICATOR(p) ((p) & (1 << 4))
116 /* true: HC has Light HC Reset Capability */
117 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
118 /* true: HC supports latency tolerance messaging */
119 #define HCC_LTC(p) ((p) & (1 << 6))
120 /* true: no secondary Stream ID Support */
121 #define HCC_NSS(p) ((p) & (1 << 7))
122 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
123 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
124 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
125 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
127 /* db_off bitmask - bits 0:1 reserved */
128 #define DBOFF_MASK (~0x3)
130 /* run_regs_off bitmask - bits 0:4 reserved */
131 #define RTSOFF_MASK (~0x1f)
134 /* Number of registers per port */
135 #define NUM_PORT_REGS 4
138 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
139 * @command: USBCMD - xHC command register
140 * @status: USBSTS - xHC status register
141 * @page_size: This indicates the page size that the host controller
142 * supports. If bit n is set, the HC supports a page size
143 * of 2^(n+12), up to a 128MB page size.
144 * 4K is the minimum page size.
145 * @cmd_ring: CRP - 64-bit Command Ring Pointer
146 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
147 * @config_reg: CONFIG - Configure Register
148 * @port_status_base: PORTSCn - base address for Port Status and Control
149 * Each port has a Port Status and Control register,
150 * followed by a Port Power Management Status and Control
151 * register, a Port Link Info register, and a reserved
153 * @port_power_base: PORTPMSCn - base address for
154 * Port Power Management Status and Control
155 * @port_link_base: PORTLIn - base address for Port Link Info (current
156 * Link PM state and control) for USB 2.1 and USB 3.0
159 struct xhci_op_regs {
165 __le32 dev_notification;
167 /* rsvd: offset 0x20-2F */
171 /* rsvd: offset 0x3C-3FF */
172 __le32 reserved4[241];
173 /* port 1 registers, which serve as a base address for other ports */
174 __le32 port_status_base;
175 __le32 port_power_base;
176 __le32 port_link_base;
178 /* registers for ports 2-255 */
179 __le32 reserved6[NUM_PORT_REGS*254];
182 /* USBCMD - USB command - command bitmasks */
183 /* start/stop HC execution - do not write unless HC is halted*/
184 #define CMD_RUN XHCI_CMD_RUN
185 /* Reset HC - resets internal HC state machine and all registers (except
186 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
187 * The xHCI driver must reinitialize the xHC after setting this bit.
189 #define CMD_RESET (1 << 1)
190 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
191 #define CMD_EIE XHCI_CMD_EIE
192 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
193 #define CMD_HSEIE XHCI_CMD_HSEIE
194 /* bits 4:6 are reserved (and should be preserved on writes). */
195 /* light reset (port status stays unchanged) - reset completed when this is 0 */
196 #define CMD_LRESET (1 << 7)
197 /* host controller save/restore state. */
198 #define CMD_CSS (1 << 8)
199 #define CMD_CRS (1 << 9)
200 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
201 #define CMD_EWE XHCI_CMD_EWE
202 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
203 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
204 * '0' means the xHC can power it off if all ports are in the disconnect,
205 * disabled, or powered-off state.
207 #define CMD_PM_INDEX (1 << 11)
208 /* bits 12:31 are reserved (and should be preserved on writes). */
210 /* IMAN - Interrupt Management Register */
211 #define IMAN_IE (1 << 1)
212 #define IMAN_IP (1 << 0)
214 /* USBSTS - USB status - status bitmasks */
215 /* HC not running - set to 1 when run/stop bit is cleared. */
216 #define STS_HALT XHCI_STS_HALT
217 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
218 #define STS_FATAL (1 << 2)
219 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
220 #define STS_EINT (1 << 3)
221 /* port change detect */
222 #define STS_PORT (1 << 4)
223 /* bits 5:7 reserved and zeroed */
224 /* save state status - '1' means xHC is saving state */
225 #define STS_SAVE (1 << 8)
226 /* restore state status - '1' means xHC is restoring state */
227 #define STS_RESTORE (1 << 9)
228 /* true: save or restore error */
229 #define STS_SRE (1 << 10)
230 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
231 #define STS_CNR XHCI_STS_CNR
232 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
233 #define STS_HCE (1 << 12)
234 /* bits 13:31 reserved and should be preserved */
237 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
238 * Generate a device notification event when the HC sees a transaction with a
239 * notification type that matches a bit set in this bit field.
241 #define DEV_NOTE_MASK (0xffff)
242 #define ENABLE_DEV_NOTE(x) (1 << (x))
243 /* Most of the device notification types should only be used for debug.
244 * SW does need to pay attention to function wake notifications.
246 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
248 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
249 /* bit 0 is the command ring cycle state */
250 /* stop ring operation after completion of the currently executing command */
251 #define CMD_RING_PAUSE (1 << 1)
252 /* stop ring immediately - abort the currently executing command */
253 #define CMD_RING_ABORT (1 << 2)
254 /* true: command ring is running */
255 #define CMD_RING_RUNNING (1 << 3)
256 /* bits 4:5 reserved and should be preserved */
257 /* Command Ring pointer - bit mask for the lower 32 bits. */
258 #define CMD_RING_RSVD_BITS (0x3f)
260 /* CONFIG - Configure Register - config_reg bitmasks */
261 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
262 #define MAX_DEVS(p) ((p) & 0xff)
263 /* bits 8:31 - reserved and should be preserved */
265 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
266 /* true: device connected */
267 #define PORT_CONNECT (1 << 0)
268 /* true: port enabled */
269 #define PORT_PE (1 << 1)
270 /* bit 2 reserved and zeroed */
271 /* true: port has an over-current condition */
272 #define PORT_OC (1 << 3)
273 /* true: port reset signaling asserted */
274 #define PORT_RESET (1 << 4)
275 /* Port Link State - bits 5:8
276 * A read gives the current link PM state of the port,
277 * a write with Link State Write Strobe set sets the link state.
279 #define PORT_PLS_MASK (0xf << 5)
280 #define XDEV_U0 (0x0 << 5)
281 #define XDEV_U2 (0x2 << 5)
282 #define XDEV_U3 (0x3 << 5)
283 #define XDEV_POLLING (0x7 << 5)
284 #define XDEV_COMP_MODE (0xa << 5)
285 #define XDEV_RESUME (0xf << 5)
286 /* true: port has power (see HCC_PPC) */
287 #define PORT_POWER (1 << 9)
288 /* bits 10:13 indicate device speed:
289 * 0 - undefined speed - port hasn't be initialized by a reset yet
296 #define DEV_SPEED_MASK (0xf << 10)
297 #define XDEV_FS (0x1 << 10)
298 #define XDEV_LS (0x2 << 10)
299 #define XDEV_HS (0x3 << 10)
300 #define XDEV_SS (0x4 << 10)
301 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
302 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
303 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
304 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
305 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
306 /* Bits 20:23 in the Slot Context are the speed for the device */
307 #define SLOT_SPEED_FS (XDEV_FS << 10)
308 #define SLOT_SPEED_LS (XDEV_LS << 10)
309 #define SLOT_SPEED_HS (XDEV_HS << 10)
310 #define SLOT_SPEED_SS (XDEV_SS << 10)
311 /* Port Indicator Control */
312 #define PORT_LED_OFF (0 << 14)
313 #define PORT_LED_AMBER (1 << 14)
314 #define PORT_LED_GREEN (2 << 14)
315 #define PORT_LED_MASK (3 << 14)
316 /* Port Link State Write Strobe - set this when changing link state */
317 #define PORT_LINK_STROBE (1 << 16)
318 /* true: connect status change */
319 #define PORT_CSC (1 << 17)
320 /* true: port enable change */
321 #define PORT_PEC (1 << 18)
322 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
323 * into an enabled state, and the device into the default state. A "warm" reset
324 * also resets the link, forcing the device through the link training sequence.
325 * SW can also look at the Port Reset register to see when warm reset is done.
327 #define PORT_WRC (1 << 19)
328 /* true: over-current change */
329 #define PORT_OCC (1 << 20)
330 /* true: reset change - 1 to 0 transition of PORT_RESET */
331 #define PORT_RC (1 << 21)
332 /* port link status change - set on some port link state transitions:
334 * ------------------------------------------------------------------------------
335 * - U3 to Resume Wakeup signaling from a device
336 * - Resume to Recovery to U0 USB 3.0 device resume
337 * - Resume to U0 USB 2.0 device resume
338 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
339 * - U3 to U0 Software resume of USB 2.0 device complete
340 * - U2 to U0 L1 resume of USB 2.1 device complete
341 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
342 * - U0 to disabled L1 entry error with USB 2.1 device
343 * - Any state to inactive Error on USB 3.0 port
345 #define PORT_PLC (1 << 22)
346 /* port configure error change - port failed to configure its link partner */
347 #define PORT_CEC (1 << 23)
348 /* Cold Attach Status - xHC can set this bit to report device attached during
349 * Sx state. Warm port reset should be perfomed to clear this bit and move port
350 * to connected state.
352 #define PORT_CAS (1 << 24)
353 /* wake on connect (enable) */
354 #define PORT_WKCONN_E (1 << 25)
355 /* wake on disconnect (enable) */
356 #define PORT_WKDISC_E (1 << 26)
357 /* wake on over-current (enable) */
358 #define PORT_WKOC_E (1 << 27)
359 /* bits 28:29 reserved */
360 /* true: device is removable - for USB 3.0 roothub emulation */
361 #define PORT_DEV_REMOVE (1 << 30)
362 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
363 #define PORT_WR (1 << 31)
365 /* We mark duplicate entries with -1 */
366 #define DUPLICATE_ENTRY ((u8)(-1))
368 /* Port Power Management Status and Control - port_power_base bitmasks */
369 /* Inactivity timer value for transitions into U1, in microseconds.
370 * Timeout can be up to 127us. 0xFF means an infinite timeout.
372 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
373 /* Inactivity timer value for transitions into U2 */
374 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
375 /* Bits 24:31 for port testing */
377 /* USB2 Protocol PORTSPMSC */
378 #define PORT_L1S_MASK 7
379 #define PORT_L1S_SUCCESS 1
380 #define PORT_RWE (1 << 3)
381 #define PORT_HIRD(p) (((p) & 0xf) << 4)
382 #define PORT_HIRD_MASK (0xf << 4)
383 #define PORT_L1DS(p) (((p) & 0xff) << 8)
384 #define PORT_HLE (1 << 16)
387 * struct xhci_intr_reg - Interrupt Register Set
388 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
389 * interrupts and check for pending interrupts.
390 * @irq_control: IMOD - Interrupt Moderation Register.
391 * Used to throttle interrupts.
392 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
393 * @erst_base: ERST base address.
394 * @erst_dequeue: Event ring dequeue pointer.
396 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
397 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
398 * multiple segments of the same size. The HC places events on the ring and
399 * "updates the Cycle bit in the TRBs to indicate to software the current
400 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
401 * updates the dequeue pointer.
403 struct xhci_intr_reg {
412 /* irq_pending bitmasks */
413 #define ER_IRQ_PENDING(p) ((p) & 0x1)
414 /* bits 2:31 need to be preserved */
415 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
416 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
417 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
418 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
420 /* irq_control bitmasks */
421 /* Minimum interval between interrupts (in 250ns intervals). The interval
422 * between interrupts will be longer if there are no events on the event ring.
423 * Default is 4000 (1 ms).
425 #define ER_IRQ_INTERVAL_MASK (0xffff)
426 /* Counter used to count down the time to the next interrupt - HW use only */
427 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
429 /* erst_size bitmasks */
430 /* Preserve bits 16:31 of erst_size */
431 #define ERST_SIZE_MASK (0xffff << 16)
433 /* erst_dequeue bitmasks */
434 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
435 * where the current dequeue pointer lies. This is an optional HW hint.
437 #define ERST_DESI_MASK (0x7)
438 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
439 * a work queue (or delayed service routine)?
441 #define ERST_EHB (1 << 3)
442 #define ERST_PTR_MASK (0xf)
445 * struct xhci_run_regs
447 * MFINDEX - current microframe number
449 * Section 5.5 Host Controller Runtime Registers:
450 * "Software should read and write these registers using only Dword (32 bit)
451 * or larger accesses"
453 struct xhci_run_regs {
454 __le32 microframe_index;
456 struct xhci_intr_reg ir_set[128];
460 * struct doorbell_array
462 * Bits 0 - 7: Endpoint target
464 * Bits 16 - 31: Stream ID
468 struct xhci_doorbell_array {
469 __le32 doorbell[256];
472 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
473 #define DB_VALUE_HOST 0x00000000
476 * struct xhci_protocol_caps
477 * @revision: major revision, minor revision, capability ID,
478 * and next capability pointer.
479 * @name_string: Four ASCII characters to say which spec this xHC
480 * follows, typically "USB ".
481 * @port_info: Port offset, count, and protocol-defined information.
483 struct xhci_protocol_caps {
489 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
490 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
491 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
494 * struct xhci_container_ctx
495 * @type: Type of context. Used to calculated offsets to contained contexts.
496 * @size: Size of the context data
497 * @bytes: The raw context data given to HW
498 * @dma: dma address of the bytes
500 * Represents either a Device or Input context. Holds a pointer to the raw
501 * memory used for the context (bytes) and dma address of it (dma).
503 struct xhci_container_ctx {
505 #define XHCI_CTX_TYPE_DEVICE 0x1
506 #define XHCI_CTX_TYPE_INPUT 0x2
515 * struct xhci_slot_ctx
516 * @dev_info: Route string, device speed, hub info, and last valid endpoint
517 * @dev_info2: Max exit latency for device number, root hub port number
518 * @tt_info: tt_info is used to construct split transaction tokens
519 * @dev_state: slot state and device address
521 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
522 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
523 * reserved at the end of the slot context for HC internal use.
525 struct xhci_slot_ctx {
530 /* offset 0x10 to 0x1f reserved for HC internal use */
534 /* dev_info bitmasks */
535 /* Route String - 0:19 */
536 #define ROUTE_STRING_MASK (0xfffff)
537 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
538 #define DEV_SPEED (0xf << 20)
539 /* bit 24 reserved */
540 /* Is this LS/FS device connected through a HS hub? - bit 25 */
541 #define DEV_MTT (0x1 << 25)
542 /* Set if the device is a hub - bit 26 */
543 #define DEV_HUB (0x1 << 26)
544 /* Index of the last valid endpoint context in this device context - 27:31 */
545 #define LAST_CTX_MASK (0x1f << 27)
546 #define LAST_CTX(p) ((p) << 27)
547 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
548 #define SLOT_FLAG (1 << 0)
549 #define EP0_FLAG (1 << 1)
551 /* dev_info2 bitmasks */
552 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
553 #define MAX_EXIT (0xffff)
554 /* Root hub port number that is needed to access the USB device */
555 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
556 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
557 /* Maximum number of ports under a hub device */
558 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
560 /* tt_info bitmasks */
562 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
563 * The Slot ID of the hub that isolates the high speed signaling from
564 * this low or full-speed device. '0' if attached to root hub port.
566 #define TT_SLOT (0xff)
568 * The number of the downstream facing port of the high-speed hub
569 * '0' if the device is not low or full speed.
571 #define TT_PORT (0xff << 8)
572 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
574 /* dev_state bitmasks */
575 /* USB device address - assigned by the HC */
576 #define DEV_ADDR_MASK (0xff)
577 /* bits 8:26 reserved */
579 #define SLOT_STATE (0x1f << 27)
580 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
582 #define SLOT_STATE_DISABLED 0
583 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
584 #define SLOT_STATE_DEFAULT 1
585 #define SLOT_STATE_ADDRESSED 2
586 #define SLOT_STATE_CONFIGURED 3
590 * @ep_info: endpoint state, streams, mult, and interval information.
591 * @ep_info2: information on endpoint type, max packet size, max burst size,
592 * error count, and whether the HC will force an event for all
594 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
595 * defines one stream, this points to the endpoint transfer ring.
596 * Otherwise, it points to a stream context array, which has a
597 * ring pointer for each flow.
599 * Average TRB lengths for the endpoint ring and
600 * max payload within an Endpoint Service Interval Time (ESIT).
602 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
603 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
604 * reserved at the end of the endpoint context for HC internal use.
611 /* offset 0x14 - 0x1f reserved for HC internal use */
615 /* ep_info bitmasks */
617 * Endpoint State - bits 0:2
620 * 2 - halted due to halt condition - ok to manipulate endpoint ring
625 #define EP_STATE_MASK (0xf)
626 #define EP_STATE_DISABLED 0
627 #define EP_STATE_RUNNING 1
628 #define EP_STATE_HALTED 2
629 #define EP_STATE_STOPPED 3
630 #define EP_STATE_ERROR 4
631 /* Mult - Max number of burtst within an interval, in EP companion desc. */
632 #define EP_MULT(p) (((p) & 0x3) << 8)
633 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
634 /* bits 10:14 are Max Primary Streams */
635 /* bit 15 is Linear Stream Array */
636 /* Interval - period between requests to an endpoint - 125u increments. */
637 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
638 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
639 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
640 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
641 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
642 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
643 #define EP_HAS_LSA (1 << 15)
645 /* ep_info2 bitmasks */
647 * Force Event - generate transfer events for all TRBs for this endpoint
648 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
650 #define FORCE_EVENT (0x1)
651 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
652 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
653 #define EP_TYPE(p) ((p) << 3)
654 #define ISOC_OUT_EP 1
655 #define BULK_OUT_EP 2
662 /* bit 7 is Host Initiate Disable - for disabling stream selection */
663 #define MAX_BURST(p) (((p)&0xff) << 8)
664 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
665 #define MAX_PACKET(p) (((p)&0xffff) << 16)
666 #define MAX_PACKET_MASK (0xffff << 16)
667 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
669 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
672 #define GET_MAX_PACKET(p) ((p) & 0x7ff)
674 /* tx_info bitmasks */
675 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
676 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
677 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
680 #define EP_CTX_CYCLE_MASK (1 << 0)
684 * struct xhci_input_control_context
685 * Input control context; see section 6.2.5.
687 * @drop_context: set the bit of the endpoint context you want to disable
688 * @add_context: set the bit of the endpoint context you want to enable
690 struct xhci_input_control_ctx {
696 #define EP_IS_ADDED(ctrl_ctx, i) \
697 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
698 #define EP_IS_DROPPED(ctrl_ctx, i) \
699 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
701 /* Represents everything that is needed to issue a command on the command ring.
702 * It's useful to pre-allocate these for commands that cannot fail due to
703 * out-of-memory errors, like freeing streams.
705 struct xhci_command {
706 /* Input context for changing device state */
707 struct xhci_container_ctx *in_ctx;
709 /* If completion is null, no one is waiting on this command
710 * and the structure can be freed after the command completes.
712 struct completion *completion;
713 union xhci_trb *command_trb;
714 struct list_head cmd_list;
717 /* drop context bitmasks */
718 #define DROP_EP(x) (0x1 << x)
719 /* add context bitmasks */
720 #define ADD_EP(x) (0x1 << x)
722 struct xhci_stream_ctx {
723 /* 64-bit stream ring address, cycle state, and stream type */
725 /* offset 0x14 - 0x1f reserved for HC internal use */
729 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
730 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
731 /* Secondary stream array type, dequeue pointer is to a transfer ring */
733 /* Primary stream array type, dequeue pointer is to a transfer ring */
735 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
740 #define SCT_SSA_128 6
741 #define SCT_SSA_256 7
743 /* Assume no secondary streams for now */
744 struct xhci_stream_info {
745 struct xhci_ring **stream_rings;
746 /* Number of streams, including stream 0 (which drivers can't use) */
747 unsigned int num_streams;
748 /* The stream context array may be bigger than
749 * the number of streams the driver asked for
751 struct xhci_stream_ctx *stream_ctx_array;
752 unsigned int num_stream_ctxs;
753 dma_addr_t ctx_array_dma;
754 /* For mapping physical TRB addresses to segments in stream rings */
755 struct radix_tree_root trb_address_map;
756 struct xhci_command *free_streams_command;
759 #define SMALL_STREAM_ARRAY_SIZE 256
760 #define MEDIUM_STREAM_ARRAY_SIZE 1024
762 /* Some Intel xHCI host controllers need software to keep track of the bus
763 * bandwidth. Keep track of endpoint info here. Each root port is allocated
764 * the full bus bandwidth. We must also treat TTs (including each port under a
765 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
766 * (DMI) also limits the total bandwidth (across all domains) that can be used.
768 struct xhci_bw_info {
769 /* ep_interval is zero-based */
770 unsigned int ep_interval;
771 /* mult and num_packets are one-based */
773 unsigned int num_packets;
774 unsigned int max_packet_size;
775 unsigned int max_esit_payload;
779 /* "Block" sizes in bytes the hardware uses for different device speeds.
780 * The logic in this part of the hardware limits the number of bits the hardware
781 * can use, so must represent bandwidth in a less precise manner to mimic what
782 * the scheduler hardware computes.
789 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
790 * with each byte transferred. SuperSpeed devices have an initial overhead to
791 * set up bursts. These are in blocks, see above. LS overhead has already been
792 * translated into FS blocks.
794 #define DMI_OVERHEAD 8
795 #define DMI_OVERHEAD_BURST 4
796 #define SS_OVERHEAD 8
797 #define SS_OVERHEAD_BURST 32
798 #define HS_OVERHEAD 26
799 #define FS_OVERHEAD 20
800 #define LS_OVERHEAD 128
801 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
802 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
803 * of overhead associated with split transfers crossing microframe boundaries.
804 * 31 blocks is pure protocol overhead.
806 #define TT_HS_OVERHEAD (31 + 94)
807 #define TT_DMI_OVERHEAD (25 + 12)
809 /* Bandwidth limits in blocks */
810 #define FS_BW_LIMIT 1285
811 #define TT_BW_LIMIT 1320
812 #define HS_BW_LIMIT 1607
813 #define SS_BW_LIMIT_IN 3906
814 #define DMI_BW_LIMIT_IN 3906
815 #define SS_BW_LIMIT_OUT 3906
816 #define DMI_BW_LIMIT_OUT 3906
818 /* Percentage of bus bandwidth reserved for non-periodic transfers */
819 #define FS_BW_RESERVED 10
820 #define HS_BW_RESERVED 20
821 #define SS_BW_RESERVED 10
823 struct xhci_virt_ep {
824 struct xhci_ring *ring;
825 /* Related to endpoints that are configured to use stream IDs only */
826 struct xhci_stream_info *stream_info;
827 /* Temporary storage in case the configure endpoint command fails and we
828 * have to restore the device state to the previous state
830 struct xhci_ring *new_ring;
831 unsigned int ep_state;
832 #define SET_DEQ_PENDING (1 << 0)
833 #define EP_HALTED (1 << 1) /* For stall handling */
834 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
835 /* Transitioning the endpoint to using streams, don't enqueue URBs */
836 #define EP_GETTING_STREAMS (1 << 3)
837 #define EP_HAS_STREAMS (1 << 4)
838 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
839 #define EP_GETTING_NO_STREAMS (1 << 5)
840 /* ---- Related to URB cancellation ---- */
841 struct list_head cancelled_td_list;
842 struct xhci_td *stopped_td;
843 unsigned int stopped_stream;
844 /* Watchdog timer for stop endpoint command to cancel URBs */
845 struct timer_list stop_cmd_timer;
846 int stop_cmds_pending;
847 struct xhci_hcd *xhci;
848 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
849 * command. We'll need to update the ring's dequeue segment and dequeue
850 * pointer after the command completes.
852 struct xhci_segment *queued_deq_seg;
853 union xhci_trb *queued_deq_ptr;
855 * Sometimes the xHC can not process isochronous endpoint ring quickly
856 * enough, and it will miss some isoc tds on the ring and generate
857 * a Missed Service Error Event.
858 * Set skip flag when receive a Missed Service Error Event and
859 * process the missed tds on the endpoint ring.
862 /* Bandwidth checking storage */
863 struct xhci_bw_info bw_info;
864 struct list_head bw_endpoint_list;
867 enum xhci_overhead_type {
868 LS_OVERHEAD_TYPE = 0,
873 struct xhci_interval_bw {
874 unsigned int num_packets;
875 /* Sorted by max packet size.
876 * Head of the list is the greatest max packet size.
878 struct list_head endpoints;
879 /* How many endpoints of each speed are present. */
880 unsigned int overhead[3];
883 #define XHCI_MAX_INTERVAL 16
885 struct xhci_interval_bw_table {
886 unsigned int interval0_esit_payload;
887 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
888 /* Includes reserved bandwidth for async endpoints */
889 unsigned int bw_used;
890 unsigned int ss_bw_in;
891 unsigned int ss_bw_out;
895 struct xhci_virt_device {
896 struct usb_device *udev;
898 * Commands to the hardware are passed an "input context" that
899 * tells the hardware what to change in its data structures.
900 * The hardware will return changes in an "output context" that
901 * software must allocate for the hardware. We need to keep
902 * track of input and output contexts separately because
903 * these commands might fail and we don't trust the hardware.
905 struct xhci_container_ctx *out_ctx;
906 /* Used for addressing devices and configuration changes */
907 struct xhci_container_ctx *in_ctx;
908 /* Rings saved to ensure old alt settings can be re-instated */
909 struct xhci_ring **ring_cache;
910 int num_rings_cached;
911 /* Store xHC assigned device address */
913 #define XHCI_MAX_RINGS_CACHED 31
914 struct xhci_virt_ep eps[31];
915 struct completion cmd_completion;
916 /* Status of the last command issued for this device */
918 struct list_head cmd_list;
921 struct xhci_interval_bw_table *bw_table;
922 struct xhci_tt_bw_info *tt_info;
926 * For each roothub, keep track of the bandwidth information for each periodic
929 * If a high speed hub is attached to the roothub, each TT associated with that
930 * hub is a separate bandwidth domain. The interval information for the
931 * endpoints on the devices under that TT will appear in the TT structure.
933 struct xhci_root_port_bw_info {
934 struct list_head tts;
935 unsigned int num_active_tts;
936 struct xhci_interval_bw_table bw_table;
939 struct xhci_tt_bw_info {
940 struct list_head tt_list;
943 struct xhci_interval_bw_table bw_table;
949 * struct xhci_device_context_array
950 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
952 struct xhci_device_context_array {
953 /* 64-bit device addresses; we only write 32-bit addresses */
954 __le64 dev_context_ptrs[MAX_HC_SLOTS];
955 /* private xHCD pointers */
958 /* TODO: write function to set the 64-bit device DMA address */
960 * TODO: change this to be dynamically sized at HC mem init time since the HC
961 * might not be able to handle the maximum number of devices possible.
965 struct xhci_transfer_event {
966 /* 64-bit buffer address, or immediate data */
969 /* This field is interpreted differently based on the type of TRB */
973 /* Transfer event TRB length bit mask */
975 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
977 /** Transfer Event bit fields **/
978 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
980 /* Completion Code - only applicable for some types of TRBs */
981 #define COMP_CODE_MASK (0xff << 24)
982 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
983 #define COMP_SUCCESS 1
984 /* Data Buffer Error */
985 #define COMP_DB_ERR 2
986 /* Babble Detected Error */
987 #define COMP_BABBLE 3
988 /* USB Transaction Error */
989 #define COMP_TX_ERR 4
990 /* TRB Error - some TRB field is invalid */
991 #define COMP_TRB_ERR 5
992 /* Stall Error - USB device is stalled */
994 /* Resource Error - HC doesn't have memory for that device configuration */
995 #define COMP_ENOMEM 7
996 /* Bandwidth Error - not enough room in schedule for this dev config */
997 #define COMP_BW_ERR 8
998 /* No Slots Available Error - HC ran out of device slots */
999 #define COMP_ENOSLOTS 9
1000 /* Invalid Stream Type Error */
1001 #define COMP_STREAM_ERR 10
1002 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
1003 #define COMP_EBADSLT 11
1004 /* Endpoint Not Enabled Error */
1005 #define COMP_EBADEP 12
1007 #define COMP_SHORT_TX 13
1008 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
1009 #define COMP_UNDERRUN 14
1010 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
1011 #define COMP_OVERRUN 15
1012 /* Virtual Function Event Ring Full Error */
1013 #define COMP_VF_FULL 16
1014 /* Parameter Error - Context parameter is invalid */
1015 #define COMP_EINVAL 17
1016 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1017 #define COMP_BW_OVER 18
1018 /* Context State Error - illegal context state transition requested */
1019 #define COMP_CTX_STATE 19
1020 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1021 #define COMP_PING_ERR 20
1022 /* Event Ring is full */
1023 #define COMP_ER_FULL 21
1024 /* Incompatible Device Error */
1025 #define COMP_DEV_ERR 22
1026 /* Missed Service Error - HC couldn't service an isoc ep within interval */
1027 #define COMP_MISSED_INT 23
1028 /* Successfully stopped command ring */
1029 #define COMP_CMD_STOP 24
1030 /* Successfully aborted current command and stopped command ring */
1031 #define COMP_CMD_ABORT 25
1032 /* Stopped - transfer was terminated by a stop endpoint command */
1033 #define COMP_STOP 26
1034 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1035 #define COMP_STOP_INVAL 27
1036 /* Control Abort Error - Debug Capability - control pipe aborted */
1037 #define COMP_DBG_ABORT 28
1038 /* Max Exit Latency Too Large Error */
1039 #define COMP_MEL_ERR 29
1040 /* TRB type 30 reserved */
1041 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1042 #define COMP_BUFF_OVER 31
1043 /* Event Lost Error - xHC has an "internal event overrun condition" */
1044 #define COMP_ISSUES 32
1045 /* Undefined Error - reported when other error codes don't apply */
1046 #define COMP_UNKNOWN 33
1047 /* Invalid Stream ID Error */
1048 #define COMP_STRID_ERR 34
1049 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1050 #define COMP_2ND_BW_ERR 35
1051 /* Split Transaction Error */
1052 #define COMP_SPLIT_ERR 36
1054 struct xhci_link_trb {
1055 /* 64-bit segment pointer*/
1061 /* control bitfields */
1062 #define LINK_TOGGLE (0x1<<1)
1064 /* Command completion event TRB */
1065 struct xhci_event_cmd {
1066 /* Pointer to command TRB, or the value passed by the event data trb */
1072 /* flags bitmasks */
1073 /* bits 16:23 are the virtual function ID */
1074 /* bits 24:31 are the slot ID */
1075 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1076 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1078 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1079 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1080 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1082 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1083 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1084 #define LAST_EP_INDEX 30
1086 /* Set TR Dequeue Pointer command TRB fields */
1087 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1088 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1091 /* Port Status Change Event TRB fields */
1092 /* Port ID - bits 31:24 */
1093 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1095 /* Normal TRB fields */
1096 /* transfer_len bitmasks - bits 0:16 */
1097 #define TRB_LEN(p) ((p) & 0x1ffff)
1098 /* Interrupter Target - which MSI-X vector to target the completion event at */
1099 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1100 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1101 #define TRB_TBC(p) (((p) & 0x3) << 7)
1102 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1104 /* Cycle bit - indicates TRB ownership by HC or HCD */
1105 #define TRB_CYCLE (1<<0)
1107 * Force next event data TRB to be evaluated before task switch.
1108 * Used to pass OS data back after a TD completes.
1110 #define TRB_ENT (1<<1)
1111 /* Interrupt on short packet */
1112 #define TRB_ISP (1<<2)
1113 /* Set PCIe no snoop attribute */
1114 #define TRB_NO_SNOOP (1<<3)
1115 /* Chain multiple TRBs into a TD */
1116 #define TRB_CHAIN (1<<4)
1117 /* Interrupt on completion */
1118 #define TRB_IOC (1<<5)
1119 /* The buffer pointer contains immediate data */
1120 #define TRB_IDT (1<<6)
1122 /* Block Event Interrupt */
1123 #define TRB_BEI (1<<9)
1125 /* Control transfer TRB specific fields */
1126 #define TRB_DIR_IN (1<<16)
1127 #define TRB_TX_TYPE(p) ((p) << 16)
1128 #define TRB_DATA_OUT 2
1129 #define TRB_DATA_IN 3
1131 /* Isochronous TRB specific fields */
1132 #define TRB_SIA (1<<31)
1134 struct xhci_generic_trb {
1139 struct xhci_link_trb link;
1140 struct xhci_transfer_event trans_event;
1141 struct xhci_event_cmd event_cmd;
1142 struct xhci_generic_trb generic;
1146 #define TRB_TYPE_BITMASK (0xfc00)
1147 #define TRB_TYPE(p) ((p) << 10)
1148 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1150 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1151 #define TRB_NORMAL 1
1152 /* setup stage for control transfers */
1154 /* data stage for control transfers */
1156 /* status stage for control transfers */
1157 #define TRB_STATUS 4
1158 /* isoc transfers */
1160 /* TRB for linking ring segments */
1162 #define TRB_EVENT_DATA 7
1163 /* Transfer Ring No-op (not for the command ring) */
1164 #define TRB_TR_NOOP 8
1166 /* Enable Slot Command */
1167 #define TRB_ENABLE_SLOT 9
1168 /* Disable Slot Command */
1169 #define TRB_DISABLE_SLOT 10
1170 /* Address Device Command */
1171 #define TRB_ADDR_DEV 11
1172 /* Configure Endpoint Command */
1173 #define TRB_CONFIG_EP 12
1174 /* Evaluate Context Command */
1175 #define TRB_EVAL_CONTEXT 13
1176 /* Reset Endpoint Command */
1177 #define TRB_RESET_EP 14
1178 /* Stop Transfer Ring Command */
1179 #define TRB_STOP_RING 15
1180 /* Set Transfer Ring Dequeue Pointer Command */
1181 #define TRB_SET_DEQ 16
1182 /* Reset Device Command */
1183 #define TRB_RESET_DEV 17
1184 /* Force Event Command (opt) */
1185 #define TRB_FORCE_EVENT 18
1186 /* Negotiate Bandwidth Command (opt) */
1187 #define TRB_NEG_BANDWIDTH 19
1188 /* Set Latency Tolerance Value Command (opt) */
1189 #define TRB_SET_LT 20
1190 /* Get port bandwidth Command */
1191 #define TRB_GET_BW 21
1192 /* Force Header Command - generate a transaction or link management packet */
1193 #define TRB_FORCE_HEADER 22
1194 /* No-op Command - not for transfer rings */
1195 #define TRB_CMD_NOOP 23
1196 /* TRB IDs 24-31 reserved */
1198 /* Transfer Event */
1199 #define TRB_TRANSFER 32
1200 /* Command Completion Event */
1201 #define TRB_COMPLETION 33
1202 /* Port Status Change Event */
1203 #define TRB_PORT_STATUS 34
1204 /* Bandwidth Request Event (opt) */
1205 #define TRB_BANDWIDTH_EVENT 35
1206 /* Doorbell Event (opt) */
1207 #define TRB_DOORBELL 36
1208 /* Host Controller Event */
1209 #define TRB_HC_EVENT 37
1210 /* Device Notification Event - device sent function wake notification */
1211 #define TRB_DEV_NOTE 38
1212 /* MFINDEX Wrap Event - microframe counter wrapped */
1213 #define TRB_MFINDEX_WRAP 39
1214 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1216 /* Nec vendor-specific command completion event. */
1217 #define TRB_NEC_CMD_COMP 48
1218 /* Get NEC firmware revision. */
1219 #define TRB_NEC_GET_FW 49
1221 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1222 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1223 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1224 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1225 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1226 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1228 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1229 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1232 * TRBS_PER_SEGMENT must be a multiple of 4,
1233 * since the command ring is 64-byte aligned.
1234 * It must also be greater than 16.
1236 #define TRBS_PER_SEGMENT 256
1237 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1238 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1239 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1240 /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE).
1241 * Change this if you change TRBS_PER_SEGMENT!
1243 #define SEGMENT_SHIFT 10
1244 /* TRB buffer pointers can't cross 64KB boundaries */
1245 #define TRB_MAX_BUFF_SHIFT 16
1246 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1248 struct xhci_segment {
1249 union xhci_trb *trbs;
1250 /* private to HCD */
1251 struct xhci_segment *next;
1256 struct list_head td_list;
1257 struct list_head cancelled_td_list;
1259 struct xhci_segment *start_seg;
1260 union xhci_trb *first_trb;
1261 union xhci_trb *last_trb;
1262 /* actual_length of the URB has already been set */
1263 bool urb_length_set;
1266 /* xHCI command default timeout value */
1267 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1269 /* command descriptor */
1271 struct list_head cancel_cmd_list;
1272 struct xhci_command *command;
1273 union xhci_trb *cmd_trb;
1276 struct xhci_dequeue_state {
1277 struct xhci_segment *new_deq_seg;
1278 union xhci_trb *new_deq_ptr;
1279 int new_cycle_state;
1283 struct xhci_segment *first_seg;
1284 union xhci_trb *enqueue;
1285 struct xhci_segment *enq_seg;
1286 unsigned int enq_updates;
1287 union xhci_trb *dequeue;
1288 struct xhci_segment *deq_seg;
1289 unsigned int deq_updates;
1290 struct list_head td_list;
1292 * Write the cycle state into the TRB cycle field to give ownership of
1293 * the TRB to the host controller (if we are the producer), or to check
1294 * if we own the TRB (if we are the consumer). See section 4.9.1.
1297 unsigned int stream_id;
1298 bool last_td_was_short;
1301 struct xhci_erst_entry {
1302 /* 64-bit event ring segment address */
1310 struct xhci_erst_entry *entries;
1311 unsigned int num_entries;
1312 /* xhci->event_ring keeps track of segment dma addresses */
1313 dma_addr_t erst_dma_addr;
1314 /* Num entries the ERST can contain */
1315 unsigned int erst_size;
1318 struct xhci_scratchpad {
1322 dma_addr_t *sp_dma_buffers;
1328 struct xhci_td *td[0];
1332 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1333 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1334 * meaning 64 ring segments.
1335 * Initial allocated size of the ERST, in number of entries */
1336 #define ERST_NUM_SEGS 1
1337 /* Initial allocated size of the ERST, in number of entries */
1338 #define ERST_SIZE 64
1339 /* Initial number of event segment rings allocated */
1340 #define ERST_ENTRIES 1
1341 /* Poll every 60 seconds */
1342 #define POLL_TIMEOUT 60
1343 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1344 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1345 /* XXX: Make these module parameters */
1362 struct list_head list;
1365 struct xhci_bus_state {
1366 unsigned long bus_suspended;
1367 unsigned long next_statechange;
1369 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1370 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1372 u32 suspended_ports;
1373 unsigned long resume_done[USB_MAXCHILDREN];
1376 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1378 if (hcd->speed == HCD_USB3)
1384 /* There is one ehci_hci structure per controller */
1386 struct usb_hcd *main_hcd;
1387 struct usb_hcd *shared_hcd;
1388 /* glue to PCI and HCD framework */
1389 struct xhci_cap_regs __iomem *cap_regs;
1390 struct xhci_op_regs __iomem *op_regs;
1391 struct xhci_run_regs __iomem *run_regs;
1392 struct xhci_doorbell_array __iomem *dba;
1393 /* Our HCD's current interrupter register set */
1394 struct xhci_intr_reg __iomem *ir_set;
1396 /* Cached register copies of read-only HC data */
1404 /* packed release number */
1408 u8 max_interrupters;
1413 /* 4KB min, 128MB max */
1415 /* Valid values are 12 to 20, inclusive */
1419 struct msix_entry *msix_entries;
1420 /* data structures */
1421 struct xhci_device_context_array *dcbaa;
1422 struct xhci_ring *cmd_ring;
1423 unsigned int cmd_ring_state;
1424 #define CMD_RING_STATE_RUNNING (1 << 0)
1425 #define CMD_RING_STATE_ABORTED (1 << 1)
1426 #define CMD_RING_STATE_STOPPED (1 << 2)
1427 struct list_head cancel_cmd_list;
1428 unsigned int cmd_ring_reserved_trbs;
1429 struct xhci_ring *event_ring;
1430 struct xhci_erst erst;
1432 struct xhci_scratchpad *scratchpad;
1433 /* Store LPM test failed devices' information */
1434 struct list_head lpm_failed_devs;
1436 /* slot enabling and address device helpers */
1437 struct completion addr_dev;
1439 /* Internal mirror of the HW's dcbaa */
1440 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1441 /* For keeping track of bandwidth domains per roothub. */
1442 struct xhci_root_port_bw_info *rh_bw;
1445 struct dma_pool *device_pool;
1446 struct dma_pool *segment_pool;
1447 struct dma_pool *small_streams_pool;
1448 struct dma_pool *medium_streams_pool;
1450 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1451 /* Poll the rings - for debugging */
1452 struct timer_list event_ring_timer;
1455 /* Host controller watchdog timer structures */
1456 unsigned int xhc_state;
1460 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1462 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1463 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1464 * that sees this status (other than the timer that set it) should stop touching
1465 * hardware immediately. Interrupt handlers should return immediately when
1466 * they see this status (any time they drop and re-acquire xhci->lock).
1467 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1468 * putting the TD on the canceled list, etc.
1470 * There are no reports of xHCI host controllers that display this issue.
1472 #define XHCI_STATE_DYING (1 << 0)
1473 #define XHCI_STATE_HALTED (1 << 1)
1476 unsigned int quirks;
1477 #define XHCI_LINK_TRB_QUIRK (1 << 0)
1478 #define XHCI_RESET_EP_QUIRK (1 << 1)
1479 #define XHCI_NEC_HOST (1 << 2)
1480 #define XHCI_AMD_PLL_FIX (1 << 3)
1481 #define XHCI_SPURIOUS_SUCCESS (1 << 4)
1483 * Certain Intel host controllers have a limit to the number of endpoint
1484 * contexts they can handle. Ideally, they would signal that they can't handle
1485 * anymore endpoint contexts by returning a Resource Error for the Configure
1486 * Endpoint command, but they don't. Instead they expect software to keep track
1487 * of the number of active endpoints for them, across configure endpoint
1488 * commands, reset device commands, disable slot commands, and address device
1491 #define XHCI_EP_LIMIT_QUIRK (1 << 5)
1492 #define XHCI_BROKEN_MSI (1 << 6)
1493 #define XHCI_RESET_ON_RESUME (1 << 7)
1494 #define XHCI_SW_BW_CHECKING (1 << 8)
1495 #define XHCI_AMD_0x96_HOST (1 << 9)
1496 #define XHCI_TRUST_TX_LENGTH (1 << 10)
1497 #define XHCI_INTEL_HOST (1 << 12)
1498 #define XHCI_SPURIOUS_REBOOT (1 << 13)
1499 #define XHCI_COMP_MODE_QUIRK (1 << 14)
1500 #define XHCI_AVOID_BEI (1 << 15)
1501 #define XHCI_SLOW_SUSPEND (1 << 17)
1502 #define XHCI_SPURIOUS_WAKEUP (1 << 18)
1503 #define XHCI_PME_STUCK_QUIRK (1 << 20)
1504 #define XHCI_MISSING_CAS (1 << 24)
1505 #define XHCI_U2_DISABLE_WAKE (1 << 27)
1506 unsigned int num_active_eps;
1507 unsigned int limit_active_eps;
1508 /* There are two roothubs to keep track of bus suspend info for */
1509 struct xhci_bus_state bus_state[2];
1510 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1512 /* Array of pointers to USB 3.0 PORTSC registers */
1513 __le32 __iomem **usb3_ports;
1514 unsigned int num_usb3_ports;
1515 /* Array of pointers to USB 2.0 PORTSC registers */
1516 __le32 __iomem **usb2_ports;
1517 unsigned int num_usb2_ports;
1518 /* support xHCI 0.96 spec USB2 software LPM */
1519 unsigned sw_lpm_support:1;
1520 /* support xHCI 1.0 spec USB2 hardware LPM */
1521 unsigned hw_lpm_support:1;
1522 /* Compliance Mode Recovery Data */
1523 struct timer_list comp_mode_recovery_timer;
1525 /* Compliance Mode Timer Triggered every 2 seconds */
1526 #define COMP_MODE_RCVRY_MSECS 2000
1529 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1530 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1532 return *((struct xhci_hcd **) (hcd->hcd_priv));
1535 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1537 return xhci->main_hcd;
1540 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1541 #define XHCI_DEBUG 1
1543 #define XHCI_DEBUG 0
1546 #define xhci_dbg(xhci, fmt, args...) \
1547 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1548 #define xhci_info(xhci, fmt, args...) \
1549 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1550 #define xhci_err(xhci, fmt, args...) \
1551 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1552 #define xhci_warn(xhci, fmt, args...) \
1553 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1555 /* TODO: copied from ehci.h - can be refactored? */
1556 /* xHCI spec says all registers are little endian */
1557 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1558 __le32 __iomem *regs)
1562 static inline void xhci_writel(struct xhci_hcd *xhci,
1563 const unsigned int val, __le32 __iomem *regs)
1569 * Registers should always be accessed with double word or quad word accesses.
1571 * Some xHCI implementations may support 64-bit address pointers. Registers
1572 * with 64-bit address pointers should be written to with dword accesses by
1573 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1574 * xHCI implementations that do not support 64-bit address pointers will ignore
1575 * the high dword, and write order is irrelevant.
1577 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1578 __le64 __iomem *regs)
1580 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1581 u64 val_lo = readl(ptr);
1582 u64 val_hi = readl(ptr + 1);
1583 return val_lo + (val_hi << 32);
1585 static inline void xhci_write_64(struct xhci_hcd *xhci,
1586 const u64 val, __le64 __iomem *regs)
1588 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1589 u32 val_lo = lower_32_bits(val);
1590 u32 val_hi = upper_32_bits(val);
1592 writel(val_lo, ptr);
1593 writel(val_hi, ptr + 1);
1596 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1598 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1601 /* xHCI debugging */
1602 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1603 void xhci_print_registers(struct xhci_hcd *xhci);
1604 void xhci_dbg_regs(struct xhci_hcd *xhci);
1605 void xhci_print_run_regs(struct xhci_hcd *xhci);
1606 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1607 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1608 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1609 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1610 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1611 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1612 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1613 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1614 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1615 struct xhci_container_ctx *ctx);
1616 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1617 unsigned int slot_id, unsigned int ep_index,
1618 struct xhci_virt_ep *ep);
1620 /* xHCI memory management */
1621 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1622 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1623 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1624 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1625 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1626 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1627 struct usb_device *udev);
1628 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1629 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1630 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1631 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1632 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1633 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1634 struct xhci_bw_info *ep_bw,
1635 struct xhci_interval_bw_table *bw_table,
1636 struct usb_device *udev,
1637 struct xhci_virt_ep *virt_ep,
1638 struct xhci_tt_bw_info *tt_info);
1639 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1640 struct xhci_virt_device *virt_dev,
1641 int old_active_eps);
1642 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1643 void xhci_update_bw_info(struct xhci_hcd *xhci,
1644 struct xhci_container_ctx *in_ctx,
1645 struct xhci_input_control_ctx *ctrl_ctx,
1646 struct xhci_virt_device *virt_dev);
1647 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1648 struct xhci_container_ctx *in_ctx,
1649 struct xhci_container_ctx *out_ctx,
1650 unsigned int ep_index);
1651 void xhci_slot_copy(struct xhci_hcd *xhci,
1652 struct xhci_container_ctx *in_ctx,
1653 struct xhci_container_ctx *out_ctx);
1654 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1655 struct usb_device *udev, struct usb_host_endpoint *ep,
1657 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1658 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1659 struct xhci_virt_device *virt_dev,
1660 unsigned int ep_index);
1661 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1662 unsigned int num_stream_ctxs,
1663 unsigned int num_streams, gfp_t flags);
1664 void xhci_free_stream_info(struct xhci_hcd *xhci,
1665 struct xhci_stream_info *stream_info);
1666 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1667 struct xhci_ep_ctx *ep_ctx,
1668 struct xhci_stream_info *stream_info);
1669 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1670 struct xhci_ep_ctx *ep_ctx,
1671 struct xhci_virt_ep *ep);
1672 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1673 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1674 struct xhci_ring *xhci_dma_to_transfer_ring(
1675 struct xhci_virt_ep *ep,
1677 struct xhci_ring *xhci_stream_id_to_ring(
1678 struct xhci_virt_device *dev,
1679 unsigned int ep_index,
1680 unsigned int stream_id);
1681 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1682 bool allocate_in_ctx, bool allocate_completion,
1684 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1685 void xhci_free_command(struct xhci_hcd *xhci,
1686 struct xhci_command *command);
1690 int xhci_register_pci(void);
1691 void xhci_unregister_pci(void);
1693 static inline int xhci_register_pci(void) { return 0; }
1694 static inline void xhci_unregister_pci(void) {}
1697 /* xHCI host controller glue */
1698 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1699 int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
1700 u32 mask, u32 done, int usec);
1701 void xhci_quiesce(struct xhci_hcd *xhci);
1702 int xhci_halt(struct xhci_hcd *xhci);
1703 int xhci_reset(struct xhci_hcd *xhci);
1704 int xhci_init(struct usb_hcd *hcd);
1705 int xhci_run(struct usb_hcd *hcd);
1706 void xhci_stop(struct usb_hcd *hcd);
1707 void xhci_shutdown(struct usb_hcd *hcd);
1708 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1711 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1712 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1714 #define xhci_suspend NULL
1715 #define xhci_resume NULL
1718 int xhci_get_frame(struct usb_hcd *hcd);
1719 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1720 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd);
1721 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1722 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1723 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1724 struct xhci_virt_device *virt_dev,
1725 struct usb_device *hdev,
1726 struct usb_tt *tt, gfp_t mem_flags);
1727 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1728 struct usb_host_endpoint **eps, unsigned int num_eps,
1729 unsigned int num_streams, gfp_t mem_flags);
1730 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1731 struct usb_host_endpoint **eps, unsigned int num_eps,
1733 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1734 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1735 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1736 struct usb_device *udev, int enable);
1737 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1738 struct usb_tt *tt, gfp_t mem_flags);
1739 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1740 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1741 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1742 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1743 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1744 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1745 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1746 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1748 /* xHCI ring, segment, TRB, and TD functions */
1749 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1750 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1751 union xhci_trb *start_trb, union xhci_trb *end_trb,
1752 dma_addr_t suspect_dma);
1753 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1754 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1755 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1756 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1758 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1759 u32 field1, u32 field2, u32 field3, u32 field4);
1760 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1761 unsigned int ep_index, int suspend);
1762 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1763 int slot_id, unsigned int ep_index);
1764 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1765 int slot_id, unsigned int ep_index);
1766 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1767 int slot_id, unsigned int ep_index);
1768 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1769 struct urb *urb, int slot_id, unsigned int ep_index);
1770 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1771 u32 slot_id, bool command_must_succeed);
1772 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1774 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1775 unsigned int ep_index);
1776 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1777 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1778 unsigned int slot_id, unsigned int ep_index,
1779 unsigned int stream_id, struct xhci_td *cur_td,
1780 struct xhci_dequeue_state *state);
1781 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1782 unsigned int slot_id, unsigned int ep_index,
1783 unsigned int stream_id,
1784 struct xhci_dequeue_state *deq_state);
1785 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1786 struct usb_device *udev, unsigned int ep_index);
1787 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1788 unsigned int slot_id, unsigned int ep_index,
1789 struct xhci_dequeue_state *deq_state);
1790 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1791 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
1792 union xhci_trb *cmd_trb);
1793 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1794 unsigned int ep_index, unsigned int stream_id);
1796 /* xHCI roothub code */
1797 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1798 int port_id, u32 link_state);
1799 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1800 int port_id, u32 port_bit);
1801 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1802 char *buf, u16 wLength);
1803 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1806 int xhci_bus_suspend(struct usb_hcd *hcd);
1807 int xhci_bus_resume(struct usb_hcd *hcd);
1809 #define xhci_bus_suspend NULL
1810 #define xhci_bus_resume NULL
1811 #endif /* CONFIG_PM */
1813 u32 xhci_port_state_to_neutral(u32 state);
1814 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1816 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1819 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1820 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1821 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1823 #endif /* __LINUX_XHCI_HCD_H */