drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return (le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK)
 117                         == TRB_TYPE(TRB_LINK);
 118 }
 119
 120 static int enqueue_is_link_trb(struct xhci_ring *ring)
 121 {
 122         struct xhci_link_trb *link = &ring->enqueue->link;
 123         return ((le32_to_cpu(link->control) & TRB_TYPE_BITMASK) ==
 124                 TRB_TYPE(TRB_LINK));
 125 }
 126
 127 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 128  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 129  * effect the ring dequeue or enqueue pointers.
 130  */
 131 static void next_trb(struct xhci_hcd *xhci,
 132                 struct xhci_ring *ring,
 133                 struct xhci_segment **seg,
 134                 union xhci_trb **trb)
 135 {
 136         if (last_trb(xhci, ring, *seg, *trb)) {
 137                 *seg = (*seg)->next;
 138                 *trb = ((*seg)->trbs);
 139         } else {
 140                 (*trb)++;
 141         }
 142 }
 143
 144 /*
 145  * See Cycle bit rules. SW is the consumer for the event ring only.
 146  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 147  */
 148 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 149 {
 150         union xhci_trb *next = ++(ring->dequeue);
 151         unsigned long long addr;
 152
 153         ring->deq_updates++;
 154         /* Update the dequeue pointer further if that was a link TRB or we're at
 155          * the end of an event ring segment (which doesn't have link TRBS)
 156          */
 157         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 158                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 159                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 160                         if (!in_interrupt())
 161                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 162                                                 ring,
 163                                                 (unsigned int) ring->cycle_state);
 164                 }
 165                 ring->deq_seg = ring->deq_seg->next;
 166                 ring->dequeue = ring->deq_seg->trbs;
 167                 next = ring->dequeue;
 168         }
 169         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 170         if (ring == xhci->cmd_ring)
 171                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 172         else
 173                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 174 }
 175
 176 /*
 177  * See Cycle bit rules. SW is the consumer for the event ring only.
 178  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 179  *
 180  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 181  * chain bit is set), then set the chain bit in all the following link TRBs.
 182  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 183  * have their chain bit cleared (so that each Link TRB is a separate TD).
 184  *
 185  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 186  * set, but other sections talk about dealing with the chain bit set.  This was
 187  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 188  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 189  *
 190  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 191  *                      prepare_transfer()?
 192  */
 193 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 194                 bool consumer, bool more_trbs_coming)
 195 {
 196         u32 chain;
 197         union xhci_trb *next;
 198         unsigned long long addr;
 199
 200         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 201         next = ++(ring->enqueue);
 202
 203         ring->enq_updates++;
 204         /* Update the dequeue pointer further if that was a link TRB or we're at
 205          * the end of an event ring segment (which doesn't have link TRBS)
 206          */
 207         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 208                 if (!consumer) {
 209                         if (ring != xhci->event_ring) {
 210                                 /*
 211                                  * If the caller doesn't plan on enqueueing more
 212                                  * TDs before ringing the doorbell, then we
 213                                  * don't want to give the link TRB to the
 214                                  * hardware just yet.  We'll give the link TRB
 215                                  * back in prepare_ring() just before we enqueue
 216                                  * the TD at the top of the ring.
 217                                  */
 218                                 if (!chain && !more_trbs_coming)
 219                                         break;
 220
 221                                 /* If we're not dealing with 0.95 hardware,
 222                                  * carry over the chain bit of the previous TRB
 223                                  * (which may mean the chain bit is cleared).
 224                                  */
 225                                 if (!xhci_link_trb_quirk(xhci)) {
 226                                         next->link.control &=
 227                                                 cpu_to_le32(~TRB_CHAIN);
 228                                         next->link.control |=
 229                                                 cpu_to_le32(chain);
 230                                 }
 231                                 /* Give this link TRB to the hardware */
 232                                 wmb();
 233                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 234                         }
 235                         /* Toggle the cycle bit after the last ring segment. */
 236                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 237                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 238                                 if (!in_interrupt())
 239                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 240                                                         ring,
 241                                                         (unsigned int) ring->cycle_state);
 242                         }
 243                 }
 244                 ring->enq_seg = ring->enq_seg->next;
 245                 ring->enqueue = ring->enq_seg->trbs;
 246                 next = ring->enqueue;
 247         }
 248         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 249         if (ring == xhci->event_ring)
 250                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 251         else if (ring == xhci->cmd_ring)
 252                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 253         else
 254                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 255 }
 256
 257 /*
 258  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 259  * above.
 260  * FIXME: this would be simpler and faster if we just kept track of the number
 261  * of free TRBs in a ring.
 262  */
 263 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 264                 unsigned int num_trbs)
 265 {
 266         int i;
 267         union xhci_trb *enq = ring->enqueue;
 268         struct xhci_segment *enq_seg = ring->enq_seg;
 269         struct xhci_segment *cur_seg;
 270         unsigned int left_on_ring;
 271
 272         /* If we are currently pointing to a link TRB, advance the
 273          * enqueue pointer before checking for space */
 274         while (last_trb(xhci, ring, enq_seg, enq)) {
 275                 enq_seg = enq_seg->next;
 276                 enq = enq_seg->trbs;
 277         }
 278
 279         /* Check if ring is empty */
 280         if (enq == ring->dequeue) {
 281                 /* Can't use link trbs */
 282                 left_on_ring = TRBS_PER_SEGMENT - 1;
 283                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 284                                 cur_seg = cur_seg->next)
 285                         left_on_ring += TRBS_PER_SEGMENT - 1;
 286
 287                 /* Always need one TRB free in the ring. */
 288                 left_on_ring -= 1;
 289                 if (num_trbs > left_on_ring) {
 290                         xhci_warn(xhci, "Not enough room on ring; "
 291                                         "need %u TRBs, %u TRBs left\n",
 292                                         num_trbs, left_on_ring);
 293                         return 0;
 294                 }
 295                 return 1;
 296         }
 297         /* Make sure there's an extra empty TRB available */
 298         for (i = 0; i <= num_trbs; ++i) {
 299                 if (enq == ring->dequeue)
 300                         return 0;
 301                 enq++;
 302                 while (last_trb(xhci, ring, enq_seg, enq)) {
 303                         enq_seg = enq_seg->next;
 304                         enq = enq_seg->trbs;
 305                 }
 306         }
 307         return 1;
 308 }
 309
 310 /* Ring the host controller doorbell after placing a command on the ring */
 311 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 312 {
 313         xhci_dbg(xhci, "// Ding dong!\n");
 314         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 315         /* Flush PCI posted writes */
 316         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 317 }
 318
 319 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 320                 unsigned int slot_id,
 321                 unsigned int ep_index,
 322                 unsigned int stream_id)
 323 {
 324         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 325         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 326         unsigned int ep_state = ep->ep_state;
 327
 328         /* Don't ring the doorbell for this endpoint if there are pending
 329          * cancellations because we don't want to interrupt processing.
 330          * We don't want to restart any stream rings if there's a set dequeue
 331          * pointer command pending because the device can choose to start any
 332          * stream once the endpoint is on the HW schedule.
 333          * FIXME - check all the stream rings for pending cancellations.
 334          */
 335         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 336             (ep_state & EP_HALTED))
 337                 return;
 338         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 339         /* The CPU has better things to do at this point than wait for a
 340          * write-posting flush.  It'll get there soon enough.
 341          */
 342 }
 343
 344 /* Ring the doorbell for any rings with pending URBs */
 345 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 346                 unsigned int slot_id,
 347                 unsigned int ep_index)
 348 {
 349         unsigned int stream_id;
 350         struct xhci_virt_ep *ep;
 351
 352         ep = &xhci->devs[slot_id]->eps[ep_index];
 353
 354         /* A ring has pending URBs if its TD list is not empty */
 355         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 356                 if (!(list_empty(&ep->ring->td_list)))
 357                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 358                 return;
 359         }
 360
 361         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 362                         stream_id++) {
 363                 struct xhci_stream_info *stream_info = ep->stream_info;
 364                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 365                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 366                                                 stream_id);
 367         }
 368 }
 369
 370 /*
 371  * Find the segment that trb is in.  Start searching in start_seg.
 372  * If we must move past a segment that has a link TRB with a toggle cycle state
 373  * bit set, then we will toggle the value pointed at by cycle_state.
 374  */
 375 static struct xhci_segment *find_trb_seg(
 376                 struct xhci_segment *start_seg,
 377                 union xhci_trb  *trb, int *cycle_state)
 378 {
 379         struct xhci_segment *cur_seg = start_seg;
 380         struct xhci_generic_trb *generic_trb;
 381
 382         while (cur_seg->trbs > trb ||
 383                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 384                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 385                 if (le32_to_cpu(generic_trb->field[3]) & LINK_TOGGLE)
 386                         *cycle_state ^= 0x1;
 387                 cur_seg = cur_seg->next;
 388                 if (cur_seg == start_seg)
 389                         /* Looped over the entire list.  Oops! */
 390                         return NULL;
 391         }
 392         return cur_seg;
 393 }
 394
 395
 396 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 397                 unsigned int slot_id, unsigned int ep_index,
 398                 unsigned int stream_id)
 399 {
 400         struct xhci_virt_ep *ep;
 401
 402         ep = &xhci->devs[slot_id]->eps[ep_index];
 403         /* Common case: no streams */
 404         if (!(ep->ep_state & EP_HAS_STREAMS))
 405                 return ep->ring;
 406
 407         if (stream_id == 0) {
 408                 xhci_warn(xhci,
 409                                 "WARN: Slot ID %u, ep index %u has streams, "
 410                                 "but URB has no stream ID.\n",
 411                                 slot_id, ep_index);
 412                 return NULL;
 413         }
 414
 415         if (stream_id < ep->stream_info->num_streams)
 416                 return ep->stream_info->stream_rings[stream_id];
 417
 418         xhci_warn(xhci,
 419                         "WARN: Slot ID %u, ep index %u has "
 420                         "stream IDs 1 to %u allocated, "
 421                         "but stream ID %u is requested.\n",
 422                         slot_id, ep_index,
 423                         ep->stream_info->num_streams - 1,
 424                         stream_id);
 425         return NULL;
 426 }
 427
 428 /* Get the right ring for the given URB.
 429  * If the endpoint supports streams, boundary check the URB's stream ID.
 430  * If the endpoint doesn't support streams, return the singular endpoint ring.
 431  */
 432 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 433                 struct urb *urb)
 434 {
 435         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 436                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 437 }
 438
 439 /*
 440  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 441  * Record the new state of the xHC's endpoint ring dequeue segment,
 442  * dequeue pointer, and new consumer cycle state in state.
 443  * Update our internal representation of the ring's dequeue pointer.
 444  *
 445  * We do this in three jumps:
 446  *  - First we update our new ring state to be the same as when the xHC stopped.
 447  *  - Then we traverse the ring to find the segment that contains
 448  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 449  *    any link TRBs with the toggle cycle bit set.
 450  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 451  *    if we've moved it past a link TRB with the toggle cycle bit set.
 452  *
 453  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 454  * with correct __le32 accesses they should work fine.  Only users of this are
 455  * in here.
 456  */
 457 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 458                 unsigned int slot_id, unsigned int ep_index,
 459                 unsigned int stream_id, struct xhci_td *cur_td,
 460                 struct xhci_dequeue_state *state)
 461 {
 462         struct xhci_virt_device *dev = xhci->devs[slot_id];
 463         struct xhci_ring *ep_ring;
 464         struct xhci_generic_trb *trb;
 465         struct xhci_ep_ctx *ep_ctx;
 466         dma_addr_t addr;
 467
 468         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 469                         ep_index, stream_id);
 470         if (!ep_ring) {
 471                 xhci_warn(xhci, "WARN can't find new dequeue state "
 472                                 "for invalid stream ID %u.\n",
 473                                 stream_id);
 474                 return;
 475         }
 476         state->new_cycle_state = 0;
 477         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 478         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 479                         dev->eps[ep_index].stopped_trb,
 480                         &state->new_cycle_state);
 481         if (!state->new_deq_seg) {
 482                 WARN_ON(1);
 483                 return;
 484         }
 485
 486         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 487         xhci_dbg(xhci, "Finding endpoint context\n");
 488         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 489         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 490
 491         state->new_deq_ptr = cur_td->last_trb;
 492         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 493         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 494                         state->new_deq_ptr,
 495                         &state->new_cycle_state);
 496         if (!state->new_deq_seg) {
 497                 WARN_ON(1);
 498                 return;
 499         }
 500
 501         trb = &state->new_deq_ptr->generic;
 502         if ((le32_to_cpu(trb->field[3]) & TRB_TYPE_BITMASK) ==
 503             TRB_TYPE(TRB_LINK) && (le32_to_cpu(trb->field[3]) & LINK_TOGGLE))
 504                 state->new_cycle_state ^= 0x1;
 505         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 506
 507         /*
 508          * If there is only one segment in a ring, find_trb_seg()'s while loop
 509          * will not run, and it will return before it has a chance to see if it
 510          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 511          * ended just before the link TRB on a one-segment ring, or if the TD
 512          * wrapped around the top of the ring, because it doesn't have the TD in
 513          * question.  Look for the one-segment case where stalled TRB's address
 514          * is greater than the new dequeue pointer address.
 515          */
 516         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 517                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 518                 state->new_cycle_state ^= 0x1;
 519         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 520
 521         /* Don't update the ring cycle state for the producer (us). */
 522         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 523                         state->new_deq_seg);
 524         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 525         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 526                         (unsigned long long) addr);
 527 }
 528
 529 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 530                 struct xhci_td *cur_td)
 531 {
 532         struct xhci_segment *cur_seg;
 533         union xhci_trb *cur_trb;
 534
 535         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 536                         true;
 537                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 538                 if ((le32_to_cpu(cur_trb->generic.field[3]) & TRB_TYPE_BITMASK)
 539                     == TRB_TYPE(TRB_LINK)) {
 540                         /* Unchain any chained Link TRBs, but
 541                          * leave the pointers intact.
 542                          */
 543                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 544                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 545                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 546                                         "in seg %p (0x%llx dma)\n",
 547                                         cur_trb,
 548                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 549                                         cur_seg,
 550                                         (unsigned long long)cur_seg->dma);
 551                 } else {
 552                         cur_trb->generic.field[0] = 0;
 553                         cur_trb->generic.field[1] = 0;
 554                         cur_trb->generic.field[2] = 0;
 555                         /* Preserve only the cycle bit of this TRB */
 556                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 557                         cur_trb->generic.field[3] |= cpu_to_le32(
 558                                 TRB_TYPE(TRB_TR_NOOP));
 559                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 560                                         "in seg %p (0x%llx dma)\n",
 561                                         cur_trb,
 562                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 563                                         cur_seg,
 564                                         (unsigned long long)cur_seg->dma);
 565                 }
 566                 if (cur_trb == cur_td->last_trb)
 567                         break;
 568         }
 569 }
 570
 571 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 572                 unsigned int ep_index, unsigned int stream_id,
 573                 struct xhci_segment *deq_seg,
 574                 union xhci_trb *deq_ptr, u32 cycle_state);
 575
 576 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 577                 unsigned int slot_id, unsigned int ep_index,
 578                 unsigned int stream_id,
 579                 struct xhci_dequeue_state *deq_state)
 580 {
 581         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 582
 583         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 584                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 585                         deq_state->new_deq_seg,
 586                         (unsigned long long)deq_state->new_deq_seg->dma,
 587                         deq_state->new_deq_ptr,
 588                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 589                         deq_state->new_cycle_state);
 590         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 591                         deq_state->new_deq_seg,
 592                         deq_state->new_deq_ptr,
 593                         (u32) deq_state->new_cycle_state);
 594         /* Stop the TD queueing code from ringing the doorbell until
 595          * this command completes.  The HC won't set the dequeue pointer
 596          * if the ring is running, and ringing the doorbell starts the
 597          * ring running.
 598          */
 599         ep->ep_state |= SET_DEQ_PENDING;
 600 }
 601
 602 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 603                 struct xhci_virt_ep *ep)
 604 {
 605         ep->ep_state &= ~EP_HALT_PENDING;
 606         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 607          * timer is running on another CPU, we don't decrement stop_cmds_pending
 608          * (since we didn't successfully stop the watchdog timer).
 609          */
 610         if (del_timer(&ep->stop_cmd_timer))
 611                 ep->stop_cmds_pending--;
 612 }
 613
 614 /* Must be called with xhci->lock held in interrupt context */
 615 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 616                 struct xhci_td *cur_td, int status, char *adjective)
 617 {
 618         struct usb_hcd *hcd;
 619         struct urb      *urb;
 620         struct urb_priv *urb_priv;
 621
 622         urb = cur_td->urb;
 623         urb_priv = urb->hcpriv;
 624         urb_priv->td_cnt++;
 625         hcd = bus_to_hcd(urb->dev->bus);
 626
 627         /* Only giveback urb when this is the last td in urb */
 628         if (urb_priv->td_cnt == urb_priv->length) {
 629                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 630                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 631                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 632                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 633                                         usb_amd_quirk_pll_enable();
 634                         }
 635                 }
 636                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 637                 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb);
 638
 639                 spin_unlock(&xhci->lock);
 640                 usb_hcd_giveback_urb(hcd, urb, status);
 641                 xhci_urb_free_priv(xhci, urb_priv);
 642                 spin_lock(&xhci->lock);
 643                 xhci_dbg(xhci, "%s URB given back\n", adjective);
 644         }
 645 }
 646
 647 /*
 648  * When we get a command completion for a Stop Endpoint Command, we need to
 649  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 650  *
 651  *  1. If the HW was in the middle of processing the TD that needs to be
 652  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 653  *     in the TD with a Set Dequeue Pointer Command.
 654  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 655  *     bit cleared) so that the HW will skip over them.
 656  */
 657 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 658                 union xhci_trb *trb, struct xhci_event_cmd *event)
 659 {
 660         unsigned int slot_id;
 661         unsigned int ep_index;
 662         struct xhci_virt_device *virt_dev;
 663         struct xhci_ring *ep_ring;
 664         struct xhci_virt_ep *ep;
 665         struct list_head *entry;
 666         struct xhci_td *cur_td = NULL;
 667         struct xhci_td *last_unlinked_td;
 668
 669         struct xhci_dequeue_state deq_state;
 670
 671         if (unlikely(TRB_TO_SUSPEND_PORT(
 672                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 673                 slot_id = TRB_TO_SLOT_ID(
 674                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 675                 virt_dev = xhci->devs[slot_id];
 676                 if (virt_dev)
 677                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 678                                 event);
 679                 else
 680                         xhci_warn(xhci, "Stop endpoint command "
 681                                 "completion for disabled slot %u\n",
 682                                 slot_id);
 683                 return;
 684         }
 685
 686         memset(&deq_state, 0, sizeof(deq_state));
 687         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 688         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 689         ep = &xhci->devs[slot_id]->eps[ep_index];
 690
 691         if (list_empty(&ep->cancelled_td_list)) {
 692                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 693                 ep->stopped_td = NULL;
 694                 ep->stopped_trb = NULL;
 695                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 696                 return;
 697         }
 698
 699         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 700          * We have the xHCI lock, so nothing can modify this list until we drop
 701          * it.  We're also in the event handler, so we can't get re-interrupted
 702          * if another Stop Endpoint command completes
 703          */
 704         list_for_each(entry, &ep->cancelled_td_list) {
 705                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 706                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 707                                 cur_td->first_trb,
 708                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 709                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 710                 if (!ep_ring) {
 711                         /* This shouldn't happen unless a driver is mucking
 712                          * with the stream ID after submission.  This will
 713                          * leave the TD on the hardware ring, and the hardware
 714                          * will try to execute it, and may access a buffer
 715                          * that has already been freed.  In the best case, the
 716                          * hardware will execute it, and the event handler will
 717                          * ignore the completion event for that TD, since it was
 718                          * removed from the td_list for that endpoint.  In
 719                          * short, don't muck with the stream ID after
 720                          * submission.
 721                          */
 722                         xhci_warn(xhci, "WARN Cancelled URB %p "
 723                                         "has invalid stream ID %u.\n",
 724                                         cur_td->urb,
 725                                         cur_td->urb->stream_id);
 726                         goto remove_finished_td;
 727                 }
 728                 /*
 729                  * If we stopped on the TD we need to cancel, then we have to
 730                  * move the xHC endpoint ring dequeue pointer past this TD.
 731                  */
 732                 if (cur_td == ep->stopped_td)
 733                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 734                                         cur_td->urb->stream_id,
 735                                         cur_td, &deq_state);
 736                 else
 737                         td_to_noop(xhci, ep_ring, cur_td);
 738 remove_finished_td:
 739                 /*
 740                  * The event handler won't see a completion for this TD anymore,
 741                  * so remove it from the endpoint ring's TD list.  Keep it in
 742                  * the cancelled TD list for URB completion later.
 743                  */
 744                 list_del(&cur_td->td_list);
 745         }
 746         last_unlinked_td = cur_td;
 747         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 748
 749         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 750         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 751                 xhci_queue_new_dequeue_state(xhci,
 752                                 slot_id, ep_index,
 753                                 ep->stopped_td->urb->stream_id,
 754                                 &deq_state);
 755                 xhci_ring_cmd_db(xhci);
 756         } else {
 757                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 758                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 759         }
 760         ep->stopped_td = NULL;
 761         ep->stopped_trb = NULL;
 762
 763         /*
 764          * Drop the lock and complete the URBs in the cancelled TD list.
 765          * New TDs to be cancelled might be added to the end of the list before
 766          * we can complete all the URBs for the TDs we already unlinked.
 767          * So stop when we've completed the URB for the last TD we unlinked.
 768          */
 769         do {
 770                 cur_td = list_entry(ep->cancelled_td_list.next,
 771                                 struct xhci_td, cancelled_td_list);
 772                 list_del(&cur_td->cancelled_td_list);
 773
 774                 /* Clean up the cancelled URB */
 775                 /* Doesn't matter what we pass for status, since the core will
 776                  * just overwrite it (because the URB has been unlinked).
 777                  */
 778                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 779
 780                 /* Stop processing the cancelled list if the watchdog timer is
 781                  * running.
 782                  */
 783                 if (xhci->xhc_state & XHCI_STATE_DYING)
 784                         return;
 785         } while (cur_td != last_unlinked_td);
 786
 787         /* Return to the event handler with xhci->lock re-acquired */
 788 }
 789
 790 /* Watchdog timer function for when a stop endpoint command fails to complete.
 791  * In this case, we assume the host controller is broken or dying or dead.  The
 792  * host may still be completing some other events, so we have to be careful to
 793  * let the event ring handler and the URB dequeueing/enqueueing functions know
 794  * through xhci->state.
 795  *
 796  * The timer may also fire if the host takes a very long time to respond to the
 797  * command, and the stop endpoint command completion handler cannot delete the
 798  * timer before the timer function is called.  Another endpoint cancellation may
 799  * sneak in before the timer function can grab the lock, and that may queue
 800  * another stop endpoint command and add the timer back.  So we cannot use a
 801  * simple flag to say whether there is a pending stop endpoint command for a
 802  * particular endpoint.
 803  *
 804  * Instead we use a combination of that flag and a counter for the number of
 805  * pending stop endpoint commands.  If the timer is the tail end of the last
 806  * stop endpoint command, and the endpoint's command is still pending, we assume
 807  * the host is dying.
 808  */
 809 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 810 {
 811         struct xhci_hcd *xhci;
 812         struct xhci_virt_ep *ep;
 813         struct xhci_virt_ep *temp_ep;
 814         struct xhci_ring *ring;
 815         struct xhci_td *cur_td;
 816         int ret, i, j;
 817
 818         ep = (struct xhci_virt_ep *) arg;
 819         xhci = ep->xhci;
 820
 821         spin_lock(&xhci->lock);
 822
 823         ep->stop_cmds_pending--;
 824         if (xhci->xhc_state & XHCI_STATE_DYING) {
 825                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 826                                 "xHCI as DYING, exiting.\n");
 827                 spin_unlock(&xhci->lock);
 828                 return;
 829         }
 830         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 831                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 832                                 "exiting.\n");
 833                 spin_unlock(&xhci->lock);
 834                 return;
 835         }
 836
 837         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 838         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 839         /* Oops, HC is dead or dying or at least not responding to the stop
 840          * endpoint command.
 841          */
 842         xhci->xhc_state |= XHCI_STATE_DYING;
 843         /* Disable interrupts from the host controller and start halting it */
 844         xhci_quiesce(xhci);
 845         spin_unlock(&xhci->lock);
 846
 847         ret = xhci_halt(xhci);
 848
 849         spin_lock(&xhci->lock);
 850         if (ret < 0) {
 851                 /* This is bad; the host is not responding to commands and it's
 852                  * not allowing itself to be halted.  At least interrupts are
 853                  * disabled. If we call usb_hc_died(), it will attempt to
 854                  * disconnect all device drivers under this host.  Those
 855                  * disconnect() methods will wait for all URBs to be unlinked,
 856                  * so we must complete them.
 857                  */
 858                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 859                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 860                 /* We could turn all TDs on the rings to no-ops.  This won't
 861                  * help if the host has cached part of the ring, and is slow if
 862                  * we want to preserve the cycle bit.  Skip it and hope the host
 863                  * doesn't touch the memory.
 864                  */
 865         }
 866         for (i = 0; i < MAX_HC_SLOTS; i++) {
 867                 if (!xhci->devs[i])
 868                         continue;
 869                 for (j = 0; j < 31; j++) {
 870                         temp_ep = &xhci->devs[i]->eps[j];
 871                         ring = temp_ep->ring;
 872                         if (!ring)
 873                                 continue;
 874                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 875                                         "ep index %u\n", i, j);
 876                         while (!list_empty(&ring->td_list)) {
 877                                 cur_td = list_first_entry(&ring->td_list,
 878                                                 struct xhci_td,
 879                                                 td_list);
 880                                 list_del(&cur_td->td_list);
 881                                 if (!list_empty(&cur_td->cancelled_td_list))
 882                                         list_del(&cur_td->cancelled_td_list);
 883                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 884                                                 -ESHUTDOWN, "killed");
 885                         }
 886                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 887                                 cur_td = list_first_entry(
 888                                                 &temp_ep->cancelled_td_list,
 889                                                 struct xhci_td,
 890                                                 cancelled_td_list);
 891                                 list_del(&cur_td->cancelled_td_list);
 892                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 893                                                 -ESHUTDOWN, "killed");
 894                         }
 895                 }
 896         }
 897         spin_unlock(&xhci->lock);
 898         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 899         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 900         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 901 }
 902
 903 /*
 904  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 905  * we need to clear the set deq pending flag in the endpoint ring state, so that
 906  * the TD queueing code can ring the doorbell again.  We also need to ring the
 907  * endpoint doorbell to restart the ring, but only if there aren't more
 908  * cancellations pending.
 909  */
 910 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 911                 struct xhci_event_cmd *event,
 912                 union xhci_trb *trb)
 913 {
 914         unsigned int slot_id;
 915         unsigned int ep_index;
 916         unsigned int stream_id;
 917         struct xhci_ring *ep_ring;
 918         struct xhci_virt_device *dev;
 919         struct xhci_ep_ctx *ep_ctx;
 920         struct xhci_slot_ctx *slot_ctx;
 921
 922         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 923         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 924         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
 925         dev = xhci->devs[slot_id];
 926
 927         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 928         if (!ep_ring) {
 929                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 930                                 "freed stream ID %u\n",
 931                                 stream_id);
 932                 /* XXX: Harmless??? */
 933                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 934                 return;
 935         }
 936
 937         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 938         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 939
 940         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
 941                 unsigned int ep_state;
 942                 unsigned int slot_state;
 943
 944                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
 945                 case COMP_TRB_ERR:
 946                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 947                                         "of stream ID configuration\n");
 948                         break;
 949                 case COMP_CTX_STATE:
 950                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 951                                         "to incorrect slot or ep state.\n");
 952                         ep_state = le32_to_cpu(ep_ctx->ep_info);
 953                         ep_state &= EP_STATE_MASK;
 954                         slot_state = le32_to_cpu(slot_ctx->dev_state);
 955                         slot_state = GET_SLOT_STATE(slot_state);
 956                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 957                                         slot_state, ep_state);
 958                         break;
 959                 case COMP_EBADSLT:
 960                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 961                                         "slot %u was not enabled.\n", slot_id);
 962                         break;
 963                 default:
 964                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 965                                         "completion code of %u.\n",
 966                                   GET_COMP_CODE(le32_to_cpu(event->status)));
 967                         break;
 968                 }
 969                 /* OK what do we do now?  The endpoint state is hosed, and we
 970                  * should never get to this point if the synchronization between
 971                  * queueing, and endpoint state are correct.  This might happen
 972                  * if the device gets disconnected after we've finished
 973                  * cancelling URBs, which might not be an error...
 974                  */
 975         } else {
 976                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 977                          le64_to_cpu(ep_ctx->deq));
 978                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
 979                                          dev->eps[ep_index].queued_deq_ptr) ==
 980                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
 981                         /* Update the ring's dequeue segment and dequeue pointer
 982                          * to reflect the new position.
 983                          */
 984                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
 985                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
 986                 } else {
 987                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
 988                                         "Ptr command & xHCI internal state.\n");
 989                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
 990                                         dev->eps[ep_index].queued_deq_seg,
 991                                         dev->eps[ep_index].queued_deq_ptr);
 992                 }
 993         }
 994
 995         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 996         dev->eps[ep_index].queued_deq_seg = NULL;
 997         dev->eps[ep_index].queued_deq_ptr = NULL;
 998         /* Restart any rings with pending URBs */
 999         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1000 }
1001
1002 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1003                 struct xhci_event_cmd *event,
1004                 union xhci_trb *trb)
1005 {
1006         int slot_id;
1007         unsigned int ep_index;
1008
1009         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1010         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1011         /* This command will only fail if the endpoint wasn't halted,
1012          * but we don't care.
1013          */
1014         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1015                  (unsigned int) GET_COMP_CODE(le32_to_cpu(event->status)));
1016
1017         /* HW with the reset endpoint quirk needs to have a configure endpoint
1018          * command complete before the endpoint can be used.  Queue that here
1019          * because the HW can't handle two commands being queued in a row.
1020          */
1021         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1022                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1023                 xhci_queue_configure_endpoint(xhci,
1024                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1025                                 false);
1026                 xhci_ring_cmd_db(xhci);
1027         } else {
1028                 /* Clear our internal halted state and restart the ring(s) */
1029                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1030                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1031         }
1032 }
1033
1034 /* Check to see if a command in the device's command queue matches this one.
1035  * Signal the completion or free the command, and return 1.  Return 0 if the
1036  * completed command isn't at the head of the command list.
1037  */
1038 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1039                 struct xhci_virt_device *virt_dev,
1040                 struct xhci_event_cmd *event)
1041 {
1042         struct xhci_command *command;
1043
1044         if (list_empty(&virt_dev->cmd_list))
1045                 return 0;
1046
1047         command = list_entry(virt_dev->cmd_list.next,
1048                         struct xhci_command, cmd_list);
1049         if (xhci->cmd_ring->dequeue != command->command_trb)
1050                 return 0;
1051
1052         command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1053         list_del(&command->cmd_list);
1054         if (command->completion)
1055                 complete(command->completion);
1056         else
1057                 xhci_free_command(xhci, command);
1058         return 1;
1059 }
1060
1061 static void handle_cmd_completion(struct xhci_hcd *xhci,
1062                 struct xhci_event_cmd *event)
1063 {
1064         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1065         u64 cmd_dma;
1066         dma_addr_t cmd_dequeue_dma;
1067         struct xhci_input_control_ctx *ctrl_ctx;
1068         struct xhci_virt_device *virt_dev;
1069         unsigned int ep_index;
1070         struct xhci_ring *ep_ring;
1071         unsigned int ep_state;
1072
1073         cmd_dma = le64_to_cpu(event->cmd_trb);
1074         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1075                         xhci->cmd_ring->dequeue);
1076         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1077         if (cmd_dequeue_dma == 0) {
1078                 xhci->error_bitmask |= 1 << 4;
1079                 return;
1080         }
1081         /* Does the DMA address match our internal dequeue pointer address? */
1082         if (cmd_dma != (u64) cmd_dequeue_dma) {
1083                 xhci->error_bitmask |= 1 << 5;
1084                 return;
1085         }
1086         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1087                 & TRB_TYPE_BITMASK) {
1088         case TRB_TYPE(TRB_ENABLE_SLOT):
1089                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1090                         xhci->slot_id = slot_id;
1091                 else
1092                         xhci->slot_id = 0;
1093                 complete(&xhci->addr_dev);
1094                 break;
1095         case TRB_TYPE(TRB_DISABLE_SLOT):
1096                 if (xhci->devs[slot_id])
1097                         xhci_free_virt_device(xhci, slot_id);
1098                 break;
1099         case TRB_TYPE(TRB_CONFIG_EP):
1100                 virt_dev = xhci->devs[slot_id];
1101                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1102                         break;
1103                 /*
1104                  * Configure endpoint commands can come from the USB core
1105                  * configuration or alt setting changes, or because the HW
1106                  * needed an extra configure endpoint command after a reset
1107                  * endpoint command or streams were being configured.
1108                  * If the command was for a halted endpoint, the xHCI driver
1109                  * is not waiting on the configure endpoint command.
1110                  */
1111                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1112                                 virt_dev->in_ctx);
1113                 /* Input ctx add_flags are the endpoint index plus one */
1114                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1115                 /* A usb_set_interface() call directly after clearing a halted
1116                  * condition may race on this quirky hardware.  Not worth
1117                  * worrying about, since this is prototype hardware.  Not sure
1118                  * if this will work for streams, but streams support was
1119                  * untested on this prototype.
1120                  */
1121                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1122                                 ep_index != (unsigned int) -1 &&
1123                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1124                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1125                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1126                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1127                         if (!(ep_state & EP_HALTED))
1128                                 goto bandwidth_change;
1129                         xhci_dbg(xhci, "Completed config ep cmd - "
1130                                         "last ep index = %d, state = %d\n",
1131                                         ep_index, ep_state);
1132                         /* Clear internal halted state and restart ring(s) */
1133                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1134                                 ~EP_HALTED;
1135                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1136                         break;
1137                 }
1138 bandwidth_change:
1139                 xhci_dbg(xhci, "Completed config ep cmd\n");
1140                 xhci->devs[slot_id]->cmd_status =
1141                         GET_COMP_CODE(le32_to_cpu(event->status));
1142                 complete(&xhci->devs[slot_id]->cmd_completion);
1143                 break;
1144         case TRB_TYPE(TRB_EVAL_CONTEXT):
1145                 virt_dev = xhci->devs[slot_id];
1146                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1147                         break;
1148                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1149                 complete(&xhci->devs[slot_id]->cmd_completion);
1150                 break;
1151         case TRB_TYPE(TRB_ADDR_DEV):
1152                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1153                 complete(&xhci->addr_dev);
1154                 break;
1155         case TRB_TYPE(TRB_STOP_RING):
1156                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1157                 break;
1158         case TRB_TYPE(TRB_SET_DEQ):
1159                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1160                 break;
1161         case TRB_TYPE(TRB_CMD_NOOP):
1162                 break;
1163         case TRB_TYPE(TRB_RESET_EP):
1164                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1165                 break;
1166         case TRB_TYPE(TRB_RESET_DEV):
1167                 xhci_dbg(xhci, "Completed reset device command.\n");
1168                 slot_id = TRB_TO_SLOT_ID(
1169                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1170                 virt_dev = xhci->devs[slot_id];
1171                 if (virt_dev)
1172                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1173                 else
1174                         xhci_warn(xhci, "Reset device command completion "
1175                                         "for disabled slot %u\n", slot_id);
1176                 break;
1177         case TRB_TYPE(TRB_NEC_GET_FW):
1178                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1179                         xhci->error_bitmask |= 1 << 6;
1180                         break;
1181                 }
1182                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1183                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1184                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1185                 break;
1186         default:
1187                 /* Skip over unknown commands on the event ring */
1188                 xhci->error_bitmask |= 1 << 6;
1189                 break;
1190         }
1191         inc_deq(xhci, xhci->cmd_ring, false);
1192 }
1193
1194 static void handle_vendor_event(struct xhci_hcd *xhci,
1195                 union xhci_trb *event)
1196 {
1197         u32 trb_type;
1198
1199         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1200         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1201         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1202                 handle_cmd_completion(xhci, &event->event_cmd);
1203 }
1204
1205 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1206  * port registers -- USB 3.0 and USB 2.0).
1207  *
1208  * Returns a zero-based port number, which is suitable for indexing into each of
1209  * the split roothubs' port arrays and bus state arrays.
1210  */
1211 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1212                 struct xhci_hcd *xhci, u32 port_id)
1213 {
1214         unsigned int i;
1215         unsigned int num_similar_speed_ports = 0;
1216
1217         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1218          * and usb2_ports are 0-based indexes.  Count the number of similar
1219          * speed ports, up to 1 port before this port.
1220          */
1221         for (i = 0; i < (port_id - 1); i++) {
1222                 u8 port_speed = xhci->port_array[i];
1223
1224                 /*
1225                  * Skip ports that don't have known speeds, or have duplicate
1226                  * Extended Capabilities port speed entries.
1227                  */
1228                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1229                         continue;
1230
1231                 /*
1232                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1233                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1234                  * matches the device speed, it's a similar speed port.
1235                  */
1236                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1237                         num_similar_speed_ports++;
1238         }
1239         return num_similar_speed_ports;
1240 }
1241
1242 static void handle_port_status(struct xhci_hcd *xhci,
1243                 union xhci_trb *event)
1244 {
1245         struct usb_hcd *hcd;
1246         u32 port_id;
1247         u32 temp, temp1;
1248         int max_ports;
1249         int slot_id;
1250         unsigned int faked_port_index;
1251         u8 major_revision;
1252         struct xhci_bus_state *bus_state;
1253         __le32 __iomem **port_array;
1254         bool bogus_port_status = false;
1255
1256         /* Port status change events always have a successful completion code */
1257         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1258                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1259                 xhci->error_bitmask |= 1 << 8;
1260         }
1261         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1262         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1263
1264         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1265         if ((port_id <= 0) || (port_id > max_ports)) {
1266                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1267                 bogus_port_status = true;
1268                 goto cleanup;
1269         }
1270
1271         /* Figure out which usb_hcd this port is attached to:
1272          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1273          */
1274         major_revision = xhci->port_array[port_id - 1];
1275         if (major_revision == 0) {
1276                 xhci_warn(xhci, "Event for port %u not in "
1277                                 "Extended Capabilities, ignoring.\n",
1278                                 port_id);
1279                 bogus_port_status = true;
1280                 goto cleanup;
1281         }
1282         if (major_revision == DUPLICATE_ENTRY) {
1283                 xhci_warn(xhci, "Event for port %u duplicated in"
1284                                 "Extended Capabilities, ignoring.\n",
1285                                 port_id);
1286                 bogus_port_status = true;
1287                 goto cleanup;
1288         }
1289
1290         /*
1291          * Hardware port IDs reported by a Port Status Change Event include USB
1292          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1293          * resume event, but we first need to translate the hardware port ID
1294          * into the index into the ports on the correct split roothub, and the
1295          * correct bus_state structure.
1296          */
1297         /* Find the right roothub. */
1298         hcd = xhci_to_hcd(xhci);
1299         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1300                 hcd = xhci->shared_hcd;
1301         bus_state = &xhci->bus_state[hcd_index(hcd)];
1302         if (hcd->speed == HCD_USB3)
1303                 port_array = xhci->usb3_ports;
1304         else
1305                 port_array = xhci->usb2_ports;
1306         /* Find the faked port hub number */
1307         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1308                         port_id);
1309
1310         temp = xhci_readl(xhci, port_array[faked_port_index]);
1311         if (hcd->state == HC_STATE_SUSPENDED) {
1312                 xhci_dbg(xhci, "resume root hub\n");
1313                 usb_hcd_resume_root_hub(hcd);
1314         }
1315
1316         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1317                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1318
1319                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1320                 if (!(temp1 & CMD_RUN)) {
1321                         xhci_warn(xhci, "xHC is not running.\n");
1322                         goto cleanup;
1323                 }
1324
1325                 if (DEV_SUPERSPEED(temp)) {
1326                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1327                         temp = xhci_port_state_to_neutral(temp);
1328                         temp &= ~PORT_PLS_MASK;
1329                         temp |= PORT_LINK_STROBE | XDEV_U0;
1330                         xhci_writel(xhci, temp, port_array[faked_port_index]);
1331                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1332                                         faked_port_index);
1333                         if (!slot_id) {
1334                                 xhci_dbg(xhci, "slot_id is zero\n");
1335                                 goto cleanup;
1336                         }
1337                         xhci_ring_device(xhci, slot_id);
1338                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1339                         /* Clear PORT_PLC */
1340                         temp = xhci_readl(xhci, port_array[faked_port_index]);
1341                         temp = xhci_port_state_to_neutral(temp);
1342                         temp |= PORT_PLC;
1343                         xhci_writel(xhci, temp, port_array[faked_port_index]);
1344                 } else {
1345                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1346                         bus_state->resume_done[faked_port_index] = jiffies +
1347                                 msecs_to_jiffies(20);
1348                         mod_timer(&hcd->rh_timer,
1349                                   bus_state->resume_done[faked_port_index]);
1350                         /* Do the rest in GetPortStatus */
1351                 }
1352         }
1353
1354 cleanup:
1355         /* Update event ring dequeue pointer before dropping the lock */
1356         inc_deq(xhci, xhci->event_ring, true);
1357
1358         /* Don't make the USB core poll the roothub if we got a bad port status
1359          * change event.  Besides, at that point we can't tell which roothub
1360          * (USB 2.0 or USB 3.0) to kick.
1361          */
1362         if (bogus_port_status)
1363                 return;
1364
1365         spin_unlock(&xhci->lock);
1366         /* Pass this up to the core */
1367         usb_hcd_poll_rh_status(hcd);
1368         spin_lock(&xhci->lock);
1369 }
1370
1371 /*
1372  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1373  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1374  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1375  * returns 0.
1376  */
1377 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1378                 union xhci_trb  *start_trb,
1379                 union xhci_trb  *end_trb,
1380                 dma_addr_t      suspect_dma)
1381 {
1382         dma_addr_t start_dma;
1383         dma_addr_t end_seg_dma;
1384         dma_addr_t end_trb_dma;
1385         struct xhci_segment *cur_seg;
1386
1387         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1388         cur_seg = start_seg;
1389
1390         do {
1391                 if (start_dma == 0)
1392                         return NULL;
1393                 /* We may get an event for a Link TRB in the middle of a TD */
1394                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1395                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1396                 /* If the end TRB isn't in this segment, this is set to 0 */
1397                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1398
1399                 if (end_trb_dma > 0) {
1400                         /* The end TRB is in this segment, so suspect should be here */
1401                         if (start_dma <= end_trb_dma) {
1402                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1403                                         return cur_seg;
1404                         } else {
1405                                 /* Case for one segment with
1406                                  * a TD wrapped around to the top
1407                                  */
1408                                 if ((suspect_dma >= start_dma &&
1409                                                         suspect_dma <= end_seg_dma) ||
1410                                                 (suspect_dma >= cur_seg->dma &&
1411                                                  suspect_dma <= end_trb_dma))
1412                                         return cur_seg;
1413                         }
1414                         return NULL;
1415                 } else {
1416                         /* Might still be somewhere in this segment */
1417                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1418                                 return cur_seg;
1419                 }
1420                 cur_seg = cur_seg->next;
1421                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1422         } while (cur_seg != start_seg);
1423
1424         return NULL;
1425 }
1426
1427 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1428                 unsigned int slot_id, unsigned int ep_index,
1429                 unsigned int stream_id,
1430                 struct xhci_td *td, union xhci_trb *event_trb)
1431 {
1432         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1433         ep->ep_state |= EP_HALTED;
1434         ep->stopped_td = td;
1435         ep->stopped_trb = event_trb;
1436         ep->stopped_stream = stream_id;
1437
1438         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1439         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1440
1441         ep->stopped_td = NULL;
1442         ep->stopped_trb = NULL;
1443         ep->stopped_stream = 0;
1444
1445         xhci_ring_cmd_db(xhci);
1446 }
1447
1448 /* Check if an error has halted the endpoint ring.  The class driver will
1449  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1450  * However, a babble and other errors also halt the endpoint ring, and the class
1451  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1452  * Ring Dequeue Pointer command manually.
1453  */
1454 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1455                 struct xhci_ep_ctx *ep_ctx,
1456                 unsigned int trb_comp_code)
1457 {
1458         /* TRB completion codes that may require a manual halt cleanup */
1459         if (trb_comp_code == COMP_TX_ERR ||
1460                         trb_comp_code == COMP_BABBLE ||
1461                         trb_comp_code == COMP_SPLIT_ERR)
1462                 /* The 0.96 spec says a babbling control endpoint
1463                  * is not halted. The 0.96 spec says it is.  Some HW
1464                  * claims to be 0.95 compliant, but it halts the control
1465                  * endpoint anyway.  Check if a babble halted the
1466                  * endpoint.
1467                  */
1468                 if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == EP_STATE_HALTED)
1469                         return 1;
1470
1471         return 0;
1472 }
1473
1474 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1475 {
1476         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1477                 /* Vendor defined "informational" completion code,
1478                  * treat as not-an-error.
1479                  */
1480                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1481                                 trb_comp_code);
1482                 xhci_dbg(xhci, "Treating code as success.\n");
1483                 return 1;
1484         }
1485         return 0;
1486 }
1487
1488 /*
1489  * Finish the td processing, remove the td from td list;
1490  * Return 1 if the urb can be given back.
1491  */
1492 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1493         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1494         struct xhci_virt_ep *ep, int *status, bool skip)
1495 {
1496         struct xhci_virt_device *xdev;
1497         struct xhci_ring *ep_ring;
1498         unsigned int slot_id;
1499         int ep_index;
1500         struct urb *urb = NULL;
1501         struct xhci_ep_ctx *ep_ctx;
1502         int ret = 0;
1503         struct urb_priv *urb_priv;
1504         u32 trb_comp_code;
1505
1506         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1507         xdev = xhci->devs[slot_id];
1508         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1509         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1510         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1511         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1512
1513         if (skip)
1514                 goto td_cleanup;
1515
1516         if (trb_comp_code == COMP_STOP_INVAL ||
1517                         trb_comp_code == COMP_STOP) {
1518                 /* The Endpoint Stop Command completion will take care of any
1519                  * stopped TDs.  A stopped TD may be restarted, so don't update
1520                  * the ring dequeue pointer or take this TD off any lists yet.
1521                  */
1522                 ep->stopped_td = td;
1523                 ep->stopped_trb = event_trb;
1524                 return 0;
1525         } else {
1526                 if (trb_comp_code == COMP_STALL) {
1527                         /* The transfer is completed from the driver's
1528                          * perspective, but we need to issue a set dequeue
1529                          * command for this stalled endpoint to move the dequeue
1530                          * pointer past the TD.  We can't do that here because
1531                          * the halt condition must be cleared first.  Let the
1532                          * USB class driver clear the stall later.
1533                          */
1534                         ep->stopped_td = td;
1535                         ep->stopped_trb = event_trb;
1536                         ep->stopped_stream = ep_ring->stream_id;
1537                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1538                                         ep_ctx, trb_comp_code)) {
1539                         /* Other types of errors halt the endpoint, but the
1540                          * class driver doesn't call usb_reset_endpoint() unless
1541                          * the error is -EPIPE.  Clear the halted status in the
1542                          * xHCI hardware manually.
1543                          */
1544                         xhci_cleanup_halted_endpoint(xhci,
1545                                         slot_id, ep_index, ep_ring->stream_id,
1546                                         td, event_trb);
1547                 } else {
1548                         /* Update ring dequeue pointer */
1549                         while (ep_ring->dequeue != td->last_trb)
1550                                 inc_deq(xhci, ep_ring, false);
1551                         inc_deq(xhci, ep_ring, false);
1552                 }
1553
1554 td_cleanup:
1555                 /* Clean up the endpoint's TD list */
1556                 urb = td->urb;
1557                 urb_priv = urb->hcpriv;
1558
1559                 /* Do one last check of the actual transfer length.
1560                  * If the host controller said we transferred more data than
1561                  * the buffer length, urb->actual_length will be a very big
1562                  * number (since it's unsigned).  Play it safe and say we didn't
1563                  * transfer anything.
1564                  */
1565                 if (urb->actual_length > urb->transfer_buffer_length) {
1566                         xhci_warn(xhci, "URB transfer length is wrong, "
1567                                         "xHC issue? req. len = %u, "
1568                                         "act. len = %u\n",
1569                                         urb->transfer_buffer_length,
1570                                         urb->actual_length);
1571                         urb->actual_length = 0;
1572                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1573                                 *status = -EREMOTEIO;
1574                         else
1575                                 *status = 0;
1576                 }
1577                 list_del(&td->td_list);
1578                 /* Was this TD slated to be cancelled but completed anyway? */
1579                 if (!list_empty(&td->cancelled_td_list))
1580                         list_del(&td->cancelled_td_list);
1581
1582                 urb_priv->td_cnt++;
1583                 /* Giveback the urb when all the tds are completed */
1584                 if (urb_priv->td_cnt == urb_priv->length) {
1585                         ret = 1;
1586                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1587                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1588                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1589                                         == 0) {
1590                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1591                                                 usb_amd_quirk_pll_enable();
1592                                 }
1593                         }
1594                 }
1595         }
1596
1597         return ret;
1598 }
1599
1600 /*
1601  * Process control tds, update urb status and actual_length.
1602  */
1603 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1604         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1605         struct xhci_virt_ep *ep, int *status)
1606 {
1607         struct xhci_virt_device *xdev;
1608         struct xhci_ring *ep_ring;
1609         unsigned int slot_id;
1610         int ep_index;
1611         struct xhci_ep_ctx *ep_ctx;
1612         u32 trb_comp_code;
1613
1614         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1615         xdev = xhci->devs[slot_id];
1616         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1617         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1618         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1619         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1620
1621         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1622         switch (trb_comp_code) {
1623         case COMP_SUCCESS:
1624                 if (event_trb == ep_ring->dequeue) {
1625                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1626                                         "without IOC set??\n");
1627                         *status = -ESHUTDOWN;
1628                 } else if (event_trb != td->last_trb) {
1629                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1630                                         "without IOC set??\n");
1631                         *status = -ESHUTDOWN;
1632                 } else {
1633                         xhci_dbg(xhci, "Successful control transfer!\n");
1634                         *status = 0;
1635                 }
1636                 break;
1637         case COMP_SHORT_TX:
1638                 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1639                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1640                         *status = -EREMOTEIO;
1641                 else
1642                         *status = 0;
1643                 break;
1644         case COMP_STOP_INVAL:
1645         case COMP_STOP:
1646                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1647         default:
1648                 if (!xhci_requires_manual_halt_cleanup(xhci,
1649                                         ep_ctx, trb_comp_code))
1650                         break;
1651                 xhci_dbg(xhci, "TRB error code %u, "
1652                                 "halted endpoint index = %u\n",
1653                                 trb_comp_code, ep_index);
1654                 /* else fall through */
1655         case COMP_STALL:
1656                 /* Did we transfer part of the data (middle) phase? */
1657                 if (event_trb != ep_ring->dequeue &&
1658                                 event_trb != td->last_trb)
1659                         td->urb->actual_length =
1660                                 td->urb->transfer_buffer_length
1661                                 - TRB_LEN(le32_to_cpu(event->transfer_len));
1662                 else
1663                         td->urb->actual_length = 0;
1664
1665                 xhci_cleanup_halted_endpoint(xhci,
1666                         slot_id, ep_index, 0, td, event_trb);
1667                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1668         }
1669         /*
1670          * Did we transfer any data, despite the errors that might have
1671          * happened?  I.e. did we get past the setup stage?
1672          */
1673         if (event_trb != ep_ring->dequeue) {
1674                 /* The event was for the status stage */
1675                 if (event_trb == td->last_trb) {
1676                         if (td->urb->actual_length != 0) {
1677                                 /* Don't overwrite a previously set error code
1678                                  */
1679                                 if ((*status == -EINPROGRESS || *status == 0) &&
1680                                                 (td->urb->transfer_flags
1681                                                  & URB_SHORT_NOT_OK))
1682                                         /* Did we already see a short data
1683                                          * stage? */
1684                                         *status = -EREMOTEIO;
1685                         } else {
1686                                 td->urb->actual_length =
1687                                         td->urb->transfer_buffer_length;
1688                         }
1689                 } else {
1690                 /* Maybe the event was for the data stage? */
1691                         td->urb->actual_length =
1692                                 td->urb->transfer_buffer_length -
1693                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1694                         xhci_dbg(xhci, "Waiting for status "
1695                                         "stage event\n");
1696                         return 0;
1697                 }
1698         }
1699
1700         return finish_td(xhci, td, event_trb, event, ep, status, false);
1701 }
1702
1703 /*
1704  * Process isochronous tds, update urb packet status and actual_length.
1705  */
1706 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1707         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1708         struct xhci_virt_ep *ep, int *status)
1709 {
1710         struct xhci_ring *ep_ring;
1711         struct urb_priv *urb_priv;
1712         int idx;
1713         int len = 0;
1714         union xhci_trb *cur_trb;
1715         struct xhci_segment *cur_seg;
1716         struct usb_iso_packet_descriptor *frame;
1717         u32 trb_comp_code;
1718         bool skip_td = false;
1719
1720         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1721         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1722         urb_priv = td->urb->hcpriv;
1723         idx = urb_priv->td_cnt;
1724         frame = &td->urb->iso_frame_desc[idx];
1725
1726         /* handle completion code */
1727         switch (trb_comp_code) {
1728         case COMP_SUCCESS:
1729                 frame->status = 0;
1730                 xhci_dbg(xhci, "Successful isoc transfer!\n");
1731                 break;
1732         case COMP_SHORT_TX:
1733                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1734                                 -EREMOTEIO : 0;
1735                 break;
1736         case COMP_BW_OVER:
1737                 frame->status = -ECOMM;
1738                 skip_td = true;
1739                 break;
1740         case COMP_BUFF_OVER:
1741         case COMP_BABBLE:
1742                 frame->status = -EOVERFLOW;
1743                 skip_td = true;
1744                 break;
1745         case COMP_STALL:
1746                 frame->status = -EPROTO;
1747                 skip_td = true;
1748                 break;
1749         case COMP_STOP:
1750         case COMP_STOP_INVAL:
1751                 break;
1752         default:
1753                 frame->status = -1;
1754                 break;
1755         }
1756
1757         if (trb_comp_code == COMP_SUCCESS || skip_td) {
1758                 frame->actual_length = frame->length;
1759                 td->urb->actual_length += frame->length;
1760         } else {
1761                 for (cur_trb = ep_ring->dequeue,
1762                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1763                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1764                         if ((le32_to_cpu(cur_trb->generic.field[3]) &
1765                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1766                             (le32_to_cpu(cur_trb->generic.field[3]) &
1767                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1768                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1769                 }
1770                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1771                         TRB_LEN(le32_to_cpu(event->transfer_len));
1772
1773                 if (trb_comp_code != COMP_STOP_INVAL) {
1774                         frame->actual_length = len;
1775                         td->urb->actual_length += len;
1776                 }
1777         }
1778
1779         if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS)
1780                 *status = 0;
1781
1782         return finish_td(xhci, td, event_trb, event, ep, status, false);
1783 }
1784
1785 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1786                         struct xhci_transfer_event *event,
1787                         struct xhci_virt_ep *ep, int *status)
1788 {
1789         struct xhci_ring *ep_ring;
1790         struct urb_priv *urb_priv;
1791         struct usb_iso_packet_descriptor *frame;
1792         int idx;
1793
1794         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1795         urb_priv = td->urb->hcpriv;
1796         idx = urb_priv->td_cnt;
1797         frame = &td->urb->iso_frame_desc[idx];
1798
1799         /* The transfer is partly done */
1800         *status = -EXDEV;
1801         frame->status = -EXDEV;
1802
1803         /* calc actual length */
1804         frame->actual_length = 0;
1805
1806         /* Update ring dequeue pointer */
1807         while (ep_ring->dequeue != td->last_trb)
1808                 inc_deq(xhci, ep_ring, false);
1809         inc_deq(xhci, ep_ring, false);
1810
1811         return finish_td(xhci, td, NULL, event, ep, status, true);
1812 }
1813
1814 /*
1815  * Process bulk and interrupt tds, update urb status and actual_length.
1816  */
1817 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1818         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1819         struct xhci_virt_ep *ep, int *status)
1820 {
1821         struct xhci_ring *ep_ring;
1822         union xhci_trb *cur_trb;
1823         struct xhci_segment *cur_seg;
1824         u32 trb_comp_code;
1825
1826         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1827         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1828
1829         switch (trb_comp_code) {
1830         case COMP_SUCCESS:
1831                 /* Double check that the HW transferred everything. */
1832                 if (event_trb != td->last_trb) {
1833                         xhci_warn(xhci, "WARN Successful completion "
1834                                         "on short TX\n");
1835                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1836                                 *status = -EREMOTEIO;
1837                         else
1838                                 *status = 0;
1839                 } else {
1840                         if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1841                                 xhci_dbg(xhci, "Successful bulk "
1842                                                 "transfer!\n");
1843                         else
1844                                 xhci_dbg(xhci, "Successful interrupt "
1845                                                 "transfer!\n");
1846                         *status = 0;
1847                 }
1848                 break;
1849         case COMP_SHORT_TX:
1850                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1851                         *status = -EREMOTEIO;
1852                 else
1853                         *status = 0;
1854                 break;
1855         default:
1856                 /* Others already handled above */
1857                 break;
1858         }
1859         xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1860                         "%d bytes untransferred\n",
1861                         td->urb->ep->desc.bEndpointAddress,
1862                         td->urb->transfer_buffer_length,
1863                  TRB_LEN(le32_to_cpu(event->transfer_len)));
1864         /* Fast path - was this the last TRB in the TD for this URB? */
1865         if (event_trb == td->last_trb) {
1866                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1867                         td->urb->actual_length =
1868                                 td->urb->transfer_buffer_length -
1869                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1870                         if (td->urb->transfer_buffer_length <
1871                                         td->urb->actual_length) {
1872                                 xhci_warn(xhci, "HC gave bad length "
1873                                                 "of %d bytes left\n",
1874                                           TRB_LEN(le32_to_cpu(event->transfer_len)));
1875                                 td->urb->actual_length = 0;
1876                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1877                                         *status = -EREMOTEIO;
1878                                 else
1879                                         *status = 0;
1880                         }
1881                         /* Don't overwrite a previously set error code */
1882                         if (*status == -EINPROGRESS) {
1883                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1884                                         *status = -EREMOTEIO;
1885                                 else
1886                                         *status = 0;
1887                         }
1888                 } else {
1889                         td->urb->actual_length =
1890                                 td->urb->transfer_buffer_length;
1891                         /* Ignore a short packet completion if the
1892                          * untransferred length was zero.
1893                          */
1894                         if (*status == -EREMOTEIO)
1895                                 *status = 0;
1896                 }
1897         } else {
1898                 /* Slow path - walk the list, starting from the dequeue
1899                  * pointer, to get the actual length transferred.
1900                  */
1901                 td->urb->actual_length = 0;
1902                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1903                                 cur_trb != event_trb;
1904                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1905                         if ((le32_to_cpu(cur_trb->generic.field[3]) &
1906                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1907                             (le32_to_cpu(cur_trb->generic.field[3]) &
1908                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1909                                 td->urb->actual_length +=
1910                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1911                 }
1912                 /* If the ring didn't stop on a Link or No-op TRB, add
1913                  * in the actual bytes transferred from the Normal TRB
1914                  */
1915                 if (trb_comp_code != COMP_STOP_INVAL)
1916                         td->urb->actual_length +=
1917                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1918                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1919         }
1920
1921         return finish_td(xhci, td, event_trb, event, ep, status, false);
1922 }
1923
1924 /*
1925  * If this function returns an error condition, it means it got a Transfer
1926  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1927  * At this point, the host controller is probably hosed and should be reset.
1928  */
1929 static int handle_tx_event(struct xhci_hcd *xhci,
1930                 struct xhci_transfer_event *event)
1931 {
1932         struct xhci_virt_device *xdev;
1933         struct xhci_virt_ep *ep;
1934         struct xhci_ring *ep_ring;
1935         unsigned int slot_id;
1936         int ep_index;
1937         struct xhci_td *td = NULL;
1938         dma_addr_t event_dma;
1939         struct xhci_segment *event_seg;
1940         union xhci_trb *event_trb;
1941         struct urb *urb = NULL;
1942         int status = -EINPROGRESS;
1943         struct urb_priv *urb_priv;
1944         struct xhci_ep_ctx *ep_ctx;
1945         u32 trb_comp_code;
1946         int ret = 0;
1947
1948         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1949         xdev = xhci->devs[slot_id];
1950         if (!xdev) {
1951                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1952                 return -ENODEV;
1953         }
1954
1955         /* Endpoint ID is 1 based, our index is zero based */
1956         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1957         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1958         ep = &xdev->eps[ep_index];
1959         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1960         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1961         if (!ep_ring ||
1962             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
1963             EP_STATE_DISABLED) {
1964                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1965                                 "or incorrect stream ring\n");
1966                 return -ENODEV;
1967         }
1968
1969         event_dma = le64_to_cpu(event->buffer);
1970         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1971         /* Look for common error cases */
1972         switch (trb_comp_code) {
1973         /* Skip codes that require special handling depending on
1974          * transfer type
1975          */
1976         case COMP_SUCCESS:
1977         case COMP_SHORT_TX:
1978                 break;
1979         case COMP_STOP:
1980                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1981                 break;
1982         case COMP_STOP_INVAL:
1983                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1984                 break;
1985         case COMP_STALL:
1986                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1987                 ep->ep_state |= EP_HALTED;
1988                 status = -EPIPE;
1989                 break;
1990         case COMP_TRB_ERR:
1991                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1992                 status = -EILSEQ;
1993                 break;
1994         case COMP_SPLIT_ERR:
1995         case COMP_TX_ERR:
1996                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1997                 status = -EPROTO;
1998                 break;
1999         case COMP_BABBLE:
2000                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
2001                 status = -EOVERFLOW;
2002                 break;
2003         case COMP_DB_ERR:
2004                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2005                 status = -ENOSR;
2006                 break;
2007         case COMP_BW_OVER:
2008                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2009                 break;
2010         case COMP_BUFF_OVER:
2011                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2012                 break;
2013         case COMP_UNDERRUN:
2014                 /*
2015                  * When the Isoch ring is empty, the xHC will generate
2016                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2017                  * Underrun Event for OUT Isoch endpoint.
2018                  */
2019                 xhci_dbg(xhci, "underrun event on endpoint\n");
2020                 if (!list_empty(&ep_ring->td_list))
2021                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2022                                         "still with TDs queued?\n",
2023                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2024                                  ep_index);
2025                 goto cleanup;
2026         case COMP_OVERRUN:
2027                 xhci_dbg(xhci, "overrun event on endpoint\n");
2028                 if (!list_empty(&ep_ring->td_list))
2029                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2030                                         "still with TDs queued?\n",
2031                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2032                                  ep_index);
2033                 goto cleanup;
2034         case COMP_MISSED_INT:
2035                 /*
2036                  * When encounter missed service error, one or more isoc tds
2037                  * may be missed by xHC.
2038                  * Set skip flag of the ep_ring; Complete the missed tds as
2039                  * short transfer when process the ep_ring next time.
2040                  */
2041                 ep->skip = true;
2042                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2043                 goto cleanup;
2044         default:
2045                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2046                         status = 0;
2047                         break;
2048                 }
2049                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2050                                 "busted\n");
2051                 goto cleanup;
2052         }
2053
2054         do {
2055                 /* This TRB should be in the TD at the head of this ring's
2056                  * TD list.
2057                  */
2058                 if (list_empty(&ep_ring->td_list)) {
2059                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2060                                         "with no TDs queued?\n",
2061                                   TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2062                                   ep_index);
2063                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2064                                  (unsigned int) (le32_to_cpu(event->flags)
2065                                                  & TRB_TYPE_BITMASK)>>10);
2066                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2067                         if (ep->skip) {
2068                                 ep->skip = false;
2069                                 xhci_dbg(xhci, "td_list is empty while skip "
2070                                                 "flag set. Clear skip flag.\n");
2071                         }
2072                         ret = 0;
2073                         goto cleanup;
2074                 }
2075
2076                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2077
2078                 /* Is this a TRB in the currently executing TD? */
2079                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2080                                 td->last_trb, event_dma);
2081                 if (!event_seg) {
2082                         if (!ep->skip ||
2083                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2084                                 /* HC is busted, give up! */
2085                                 xhci_err(xhci,
2086                                         "ERROR Transfer event TRB DMA ptr not "
2087                                         "part of current TD\n");
2088                                 return -ESHUTDOWN;
2089                         }
2090
2091                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2092                         goto cleanup;
2093                 }
2094
2095                 if (ep->skip) {
2096                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2097                         ep->skip = false;
2098                 }
2099
2100                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2101                                                 sizeof(*event_trb)];
2102                 /*
2103                  * No-op TRB should not trigger interrupts.
2104                  * If event_trb is a no-op TRB, it means the
2105                  * corresponding TD has been cancelled. Just ignore
2106                  * the TD.
2107                  */
2108                 if ((le32_to_cpu(event_trb->generic.field[3])
2109                              & TRB_TYPE_BITMASK)
2110                                  == TRB_TYPE(TRB_TR_NOOP)) {
2111                         xhci_dbg(xhci,
2112                                  "event_trb is a no-op TRB. Skip it\n");
2113                         goto cleanup;
2114                 }
2115
2116                 /* Now update the urb's actual_length and give back to
2117                  * the core
2118                  */
2119                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2120                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2121                                                  &status);
2122                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2123                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2124                                                  &status);
2125                 else
2126                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2127                                                  ep, &status);
2128
2129 cleanup:
2130                 /*
2131                  * Do not update event ring dequeue pointer if ep->skip is set.
2132                  * Will roll back to continue process missed tds.
2133                  */
2134                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2135                         inc_deq(xhci, xhci->event_ring, true);
2136                 }
2137
2138                 if (ret) {
2139                         urb = td->urb;
2140                         urb_priv = urb->hcpriv;
2141                         /* Leave the TD around for the reset endpoint function
2142                          * to use(but only if it's not a control endpoint,
2143                          * since we already queued the Set TR dequeue pointer
2144                          * command for stalled control endpoints).
2145                          */
2146                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2147                                 (trb_comp_code != COMP_STALL &&
2148                                         trb_comp_code != COMP_BABBLE))
2149                                 xhci_urb_free_priv(xhci, urb_priv);
2150
2151                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2152                         xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2153                                         "status = %d\n",
2154                                         urb, urb->actual_length, status);
2155                         spin_unlock(&xhci->lock);
2156                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2157                         spin_lock(&xhci->lock);
2158                 }
2159
2160         /*
2161          * If ep->skip is set, it means there are missed tds on the
2162          * endpoint ring need to take care of.
2163          * Process them as short transfer until reach the td pointed by
2164          * the event.
2165          */
2166         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2167
2168         return 0;
2169 }
2170
2171 /*
2172  * This function handles all OS-owned events on the event ring.  It may drop
2173  * xhci->lock between event processing (e.g. to pass up port status changes).
2174  * Returns >0 for "possibly more events to process" (caller should call again),
2175  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2176  */
2177 static int xhci_handle_event(struct xhci_hcd *xhci)
2178 {
2179         union xhci_trb *event;
2180         int update_ptrs = 1;
2181         int ret;
2182
2183         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2184                 xhci->error_bitmask |= 1 << 1;
2185                 return 0;
2186         }
2187
2188         event = xhci->event_ring->dequeue;
2189         /* Does the HC or OS own the TRB? */
2190         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2191             xhci->event_ring->cycle_state) {
2192                 xhci->error_bitmask |= 1 << 2;
2193                 return 0;
2194         }
2195
2196         /*
2197          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2198          * speculative reads of the event's flags/data below.
2199          */
2200         rmb();
2201         /* FIXME: Handle more event types. */
2202         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2203         case TRB_TYPE(TRB_COMPLETION):
2204                 handle_cmd_completion(xhci, &event->event_cmd);
2205                 break;
2206         case TRB_TYPE(TRB_PORT_STATUS):
2207                 handle_port_status(xhci, event);
2208                 update_ptrs = 0;
2209                 break;
2210         case TRB_TYPE(TRB_TRANSFER):
2211                 ret = handle_tx_event(xhci, &event->trans_event);
2212                 if (ret < 0)
2213                         xhci->error_bitmask |= 1 << 9;
2214                 else
2215                         update_ptrs = 0;
2216                 break;
2217         default:
2218                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2219                     TRB_TYPE(48))
2220                         handle_vendor_event(xhci, event);
2221                 else
2222                         xhci->error_bitmask |= 1 << 3;
2223         }
2224         /* Any of the above functions may drop and re-acquire the lock, so check
2225          * to make sure a watchdog timer didn't mark the host as non-responsive.
2226          */
2227         if (xhci->xhc_state & XHCI_STATE_DYING) {
2228                 xhci_dbg(xhci, "xHCI host dying, returning from "
2229                                 "event handler.\n");
2230                 return 0;
2231         }
2232
2233         if (update_ptrs)
2234                 /* Update SW event ring dequeue pointer */
2235                 inc_deq(xhci, xhci->event_ring, true);
2236
2237         /* Are there more items on the event ring?  Caller will call us again to
2238          * check.
2239          */
2240         return 1;
2241 }
2242
2243 /*
2244  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2245  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2246  * indicators of an event TRB error, but we check the status *first* to be safe.
2247  */
2248 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2249 {
2250         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2251         u32 status;
2252         union xhci_trb *trb;
2253         u64 temp_64;
2254         union xhci_trb *event_ring_deq;
2255         dma_addr_t deq;
2256
2257         spin_lock(&xhci->lock);
2258         trb = xhci->event_ring->dequeue;
2259         /* Check if the xHC generated the interrupt, or the irq is shared */
2260         status = xhci_readl(xhci, &xhci->op_regs->status);
2261         if (status == 0xffffffff)
2262                 goto hw_died;
2263
2264         if (!(status & STS_EINT)) {
2265                 spin_unlock(&xhci->lock);
2266                 return IRQ_NONE;
2267         }
2268         if (status & STS_FATAL) {
2269                 xhci_warn(xhci, "WARNING: Host System Error\n");
2270                 xhci_halt(xhci);
2271 hw_died:
2272                 spin_unlock(&xhci->lock);
2273                 return -ESHUTDOWN;
2274         }
2275
2276         /*
2277          * Clear the op reg interrupt status first,
2278          * so we can receive interrupts from other MSI-X interrupters.
2279          * Write 1 to clear the interrupt status.
2280          */
2281         status |= STS_EINT;
2282         xhci_writel(xhci, status, &xhci->op_regs->status);
2283         /* FIXME when MSI-X is supported and there are multiple vectors */
2284         /* Clear the MSI-X event interrupt status */
2285
2286         if (hcd->irq != -1) {
2287                 u32 irq_pending;
2288                 /* Acknowledge the PCI interrupt */
2289                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2290                 irq_pending |= 0x3;
2291                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2292         }
2293
2294         if (xhci->xhc_state & XHCI_STATE_DYING) {
2295                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2296                                 "Shouldn't IRQs be disabled?\n");
2297                 /* Clear the event handler busy flag (RW1C);
2298                  * the event ring should be empty.
2299                  */
2300                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2301                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2302                                 &xhci->ir_set->erst_dequeue);
2303                 spin_unlock(&xhci->lock);
2304
2305                 return IRQ_HANDLED;
2306         }
2307
2308         event_ring_deq = xhci->event_ring->dequeue;
2309         /* FIXME this should be a delayed service routine
2310          * that clears the EHB.
2311          */
2312         while (xhci_handle_event(xhci) > 0) {}
2313
2314         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2315         /* If necessary, update the HW's version of the event ring deq ptr. */
2316         if (event_ring_deq != xhci->event_ring->dequeue) {
2317                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2318                                 xhci->event_ring->dequeue);
2319                 if (deq == 0)
2320                         xhci_warn(xhci, "WARN something wrong with SW event "
2321                                         "ring dequeue ptr.\n");
2322                 /* Update HC event ring dequeue pointer */
2323                 temp_64 &= ERST_PTR_MASK;
2324                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2325         }
2326
2327         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2328         temp_64 |= ERST_EHB;
2329         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2330
2331         spin_unlock(&xhci->lock);
2332
2333         return IRQ_HANDLED;
2334 }
2335
2336 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2337 {
2338         irqreturn_t ret;
2339         struct xhci_hcd *xhci;
2340
2341         xhci = hcd_to_xhci(hcd);
2342         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2343         if (xhci->shared_hcd)
2344                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2345
2346         ret = xhci_irq(hcd);
2347
2348         return ret;
2349 }
2350
2351 /****           Endpoint Ring Operations        ****/
2352
2353 /*
2354  * Generic function for queueing a TRB on a ring.
2355  * The caller must have checked to make sure there's room on the ring.
2356  *
2357  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2358  *                      prepare_transfer()?
2359  */
2360 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2361                 bool consumer, bool more_trbs_coming,
2362                 u32 field1, u32 field2, u32 field3, u32 field4)
2363 {
2364         struct xhci_generic_trb *trb;
2365
2366         trb = &ring->enqueue->generic;
2367         trb->field[0] = cpu_to_le32(field1);
2368         trb->field[1] = cpu_to_le32(field2);
2369         trb->field[2] = cpu_to_le32(field3);
2370         trb->field[3] = cpu_to_le32(field4);
2371         inc_enq(xhci, ring, consumer, more_trbs_coming);
2372 }
2373
2374 /*
2375  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2376  * FIXME allocate segments if the ring is full.
2377  */
2378 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2379                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2380 {
2381         /* Make sure the endpoint has been added to xHC schedule */
2382         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
2383         switch (ep_state) {
2384         case EP_STATE_DISABLED:
2385                 /*
2386                  * USB core changed config/interfaces without notifying us,
2387                  * or hardware is reporting the wrong state.
2388                  */
2389                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2390                 return -ENOENT;
2391         case EP_STATE_ERROR:
2392                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2393                 /* FIXME event handling code for error needs to clear it */
2394                 /* XXX not sure if this should be -ENOENT or not */
2395                 return -EINVAL;
2396         case EP_STATE_HALTED:
2397                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2398         case EP_STATE_STOPPED:
2399         case EP_STATE_RUNNING:
2400                 break;
2401         default:
2402                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2403                 /*
2404                  * FIXME issue Configure Endpoint command to try to get the HC
2405                  * back into a known state.
2406                  */
2407                 return -EINVAL;
2408         }
2409         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2410                 /* FIXME allocate more room */
2411                 xhci_err(xhci, "ERROR no room on ep ring\n");
2412                 return -ENOMEM;
2413         }
2414
2415         if (enqueue_is_link_trb(ep_ring)) {
2416                 struct xhci_ring *ring = ep_ring;
2417                 union xhci_trb *next;
2418
2419                 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
2420                 next = ring->enqueue;
2421
2422                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2423                         /* If we're not dealing with 0.95 hardware,
2424                          * clear the chain bit.
2425                          */
2426                         if (!xhci_link_trb_quirk(xhci))
2427                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2428                         else
2429                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2430
2431                         wmb();
2432                         next->link.control ^= cpu_to_le32((u32) TRB_CYCLE);
2433
2434                         /* Toggle the cycle bit after the last ring segment. */
2435                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2436                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2437                                 if (!in_interrupt()) {
2438                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2439                                                 "state for ring %p = %i\n",
2440                                                 ring, (unsigned int)ring->cycle_state);
2441                                 }
2442                         }
2443                         ring->enq_seg = ring->enq_seg->next;
2444                         ring->enqueue = ring->enq_seg->trbs;
2445                         next = ring->enqueue;
2446                 }
2447         }
2448
2449         return 0;
2450 }
2451
2452 static int prepare_transfer(struct xhci_hcd *xhci,
2453                 struct xhci_virt_device *xdev,
2454                 unsigned int ep_index,
2455                 unsigned int stream_id,
2456                 unsigned int num_trbs,
2457                 struct urb *urb,
2458                 unsigned int td_index,
2459                 gfp_t mem_flags)
2460 {
2461         int ret;
2462         struct urb_priv *urb_priv;
2463         struct xhci_td  *td;
2464         struct xhci_ring *ep_ring;
2465         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2466
2467         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2468         if (!ep_ring) {
2469                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2470                                 stream_id);
2471                 return -EINVAL;
2472         }
2473
2474         ret = prepare_ring(xhci, ep_ring,
2475                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2476                            num_trbs, mem_flags);
2477         if (ret)
2478                 return ret;
2479
2480         urb_priv = urb->hcpriv;
2481         td = urb_priv->td[td_index];
2482
2483         INIT_LIST_HEAD(&td->td_list);
2484         INIT_LIST_HEAD(&td->cancelled_td_list);
2485
2486         if (td_index == 0) {
2487                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2488                 if (unlikely(ret)) {
2489                         xhci_urb_free_priv(xhci, urb_priv);
2490                         urb->hcpriv = NULL;
2491                         return ret;
2492                 }
2493         }
2494
2495         td->urb = urb;
2496         /* Add this TD to the tail of the endpoint ring's TD list */
2497         list_add_tail(&td->td_list, &ep_ring->td_list);
2498         td->start_seg = ep_ring->enq_seg;
2499         td->first_trb = ep_ring->enqueue;
2500
2501         urb_priv->td[td_index] = td;
2502
2503         return 0;
2504 }
2505
2506 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2507 {
2508         int num_sgs, num_trbs, running_total, temp, i;
2509         struct scatterlist *sg;
2510
2511         sg = NULL;
2512         num_sgs = urb->num_sgs;
2513         temp = urb->transfer_buffer_length;
2514
2515         xhci_dbg(xhci, "count sg list trbs: \n");
2516         num_trbs = 0;
2517         for_each_sg(urb->sg, sg, num_sgs, i) {
2518                 unsigned int previous_total_trbs = num_trbs;
2519                 unsigned int len = sg_dma_len(sg);
2520
2521                 /* Scatter gather list entries may cross 64KB boundaries */
2522                 running_total = TRB_MAX_BUFF_SIZE -
2523                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2524                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2525                 if (running_total != 0)
2526                         num_trbs++;
2527
2528                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2529                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2530                         num_trbs++;
2531                         running_total += TRB_MAX_BUFF_SIZE;
2532                 }
2533                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2534                                 i, (unsigned long long)sg_dma_address(sg),
2535                                 len, len, num_trbs - previous_total_trbs);
2536
2537                 len = min_t(int, len, temp);
2538                 temp -= len;
2539                 if (temp == 0)
2540                         break;
2541         }
2542         xhci_dbg(xhci, "\n");
2543         if (!in_interrupt())
2544                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2545                                 "num_trbs = %d\n",
2546                                 urb->ep->desc.bEndpointAddress,
2547                                 urb->transfer_buffer_length,
2548                                 num_trbs);
2549         return num_trbs;
2550 }
2551
2552 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2553 {
2554         if (num_trbs != 0)
2555                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2556                                 "TRBs, %d left\n", __func__,
2557                                 urb->ep->desc.bEndpointAddress, num_trbs);
2558         if (running_total != urb->transfer_buffer_length)
2559                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2560                                 "queued %#x (%d), asked for %#x (%d)\n",
2561                                 __func__,
2562                                 urb->ep->desc.bEndpointAddress,
2563                                 running_total, running_total,
2564                                 urb->transfer_buffer_length,
2565                                 urb->transfer_buffer_length);
2566 }
2567
2568 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2569                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2570                 struct xhci_generic_trb *start_trb)
2571 {
2572         /*
2573          * Pass all the TRBs to the hardware at once and make sure this write
2574          * isn't reordered.
2575          */
2576         wmb();
2577         if (start_cycle)
2578                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2579         else
2580                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2581         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2582 }
2583
2584 /*
2585  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2586  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2587  * (comprised of sg list entries) can take several service intervals to
2588  * transmit.
2589  */
2590 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2591                 struct urb *urb, int slot_id, unsigned int ep_index)
2592 {
2593         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2594                         xhci->devs[slot_id]->out_ctx, ep_index);
2595         int xhci_interval;
2596         int ep_interval;
2597
2598         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2599         ep_interval = urb->interval;
2600         /* Convert to microframes */
2601         if (urb->dev->speed == USB_SPEED_LOW ||
2602                         urb->dev->speed == USB_SPEED_FULL)
2603                 ep_interval *= 8;
2604         /* FIXME change this to a warning and a suggestion to use the new API
2605          * to set the polling interval (once the API is added).
2606          */
2607         if (xhci_interval != ep_interval) {
2608                 if (printk_ratelimit())
2609                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2610                                         " (%d microframe%s) than xHCI "
2611                                         "(%d microframe%s)\n",
2612                                         ep_interval,
2613                                         ep_interval == 1 ? "" : "s",
2614                                         xhci_interval,
2615                                         xhci_interval == 1 ? "" : "s");
2616                 urb->interval = xhci_interval;
2617                 /* Convert back to frames for LS/FS devices */
2618                 if (urb->dev->speed == USB_SPEED_LOW ||
2619                                 urb->dev->speed == USB_SPEED_FULL)
2620                         urb->interval /= 8;
2621         }
2622         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2623 }
2624
2625 /*
2626  * The TD size is the number of bytes remaining in the TD (including this TRB),
2627  * right shifted by 10.
2628  * It must fit in bits 21:17, so it can't be bigger than 31.
2629  */
2630 static u32 xhci_td_remainder(unsigned int remainder)
2631 {
2632         u32 max = (1 << (21 - 17 + 1)) - 1;
2633
2634         if ((remainder >> 10) >= max)
2635                 return max << 17;
2636         else
2637                 return (remainder >> 10) << 17;
2638 }
2639
2640 /*
2641  * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2642  * the TD (*not* including this TRB).
2643  *
2644  * Total TD packet count = total_packet_count =
2645  *     roundup(TD size in bytes / wMaxPacketSize)
2646  *
2647  * Packets transferred up to and including this TRB = packets_transferred =
2648  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2649  *
2650  * TD size = total_packet_count - packets_transferred
2651  *
2652  * It must fit in bits 21:17, so it can't be bigger than 31.
2653  */
2654
2655 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2656                 unsigned int total_packet_count, struct urb *urb)
2657 {
2658         int packets_transferred;
2659
2660         /* All the TRB queueing functions don't count the current TRB in
2661          * running_total.
2662          */
2663         packets_transferred = (running_total + trb_buff_len) /
2664                 le16_to_cpu(urb->ep->desc.wMaxPacketSize);
2665
2666         return xhci_td_remainder(total_packet_count - packets_transferred);
2667 }
2668
2669 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2670                 struct urb *urb, int slot_id, unsigned int ep_index)
2671 {
2672         struct xhci_ring *ep_ring;
2673         unsigned int num_trbs;
2674         struct urb_priv *urb_priv;
2675         struct xhci_td *td;
2676         struct scatterlist *sg;
2677         int num_sgs;
2678         int trb_buff_len, this_sg_len, running_total;
2679         unsigned int total_packet_count;
2680         bool first_trb;
2681         u64 addr;
2682         bool more_trbs_coming;
2683
2684         struct xhci_generic_trb *start_trb;
2685         int start_cycle;
2686
2687         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2688         if (!ep_ring)
2689                 return -EINVAL;
2690
2691         num_trbs = count_sg_trbs_needed(xhci, urb);
2692         num_sgs = urb->num_sgs;
2693         total_packet_count = roundup(urb->transfer_buffer_length,
2694                         le16_to_cpu(urb->ep->desc.wMaxPacketSize));
2695
2696         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2697                         ep_index, urb->stream_id,
2698                         num_trbs, urb, 0, mem_flags);
2699         if (trb_buff_len < 0)
2700                 return trb_buff_len;
2701
2702         urb_priv = urb->hcpriv;
2703         td = urb_priv->td[0];
2704
2705         /*
2706          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2707          * until we've finished creating all the other TRBs.  The ring's cycle
2708          * state may change as we enqueue the other TRBs, so save it too.
2709          */
2710         start_trb = &ep_ring->enqueue->generic;
2711         start_cycle = ep_ring->cycle_state;
2712
2713         running_total = 0;
2714         /*
2715          * How much data is in the first TRB?
2716          *
2717          * There are three forces at work for TRB buffer pointers and lengths:
2718          * 1. We don't want to walk off the end of this sg-list entry buffer.
2719          * 2. The transfer length that the driver requested may be smaller than
2720          *    the amount of memory allocated for this scatter-gather list.
2721          * 3. TRBs buffers can't cross 64KB boundaries.
2722          */
2723         sg = urb->sg;
2724         addr = (u64) sg_dma_address(sg);
2725         this_sg_len = sg_dma_len(sg);
2726         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2727         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2728         if (trb_buff_len > urb->transfer_buffer_length)
2729                 trb_buff_len = urb->transfer_buffer_length;
2730         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2731                         trb_buff_len);
2732
2733         first_trb = true;
2734         /* Queue the first TRB, even if it's zero-length */
2735         do {
2736                 u32 field = 0;
2737                 u32 length_field = 0;
2738                 u32 remainder = 0;
2739
2740                 /* Don't change the cycle bit of the first TRB until later */
2741                 if (first_trb) {
2742                         first_trb = false;
2743                         if (start_cycle == 0)
2744                                 field |= 0x1;
2745                 } else
2746                         field |= ep_ring->cycle_state;
2747
2748                 /* Chain all the TRBs together; clear the chain bit in the last
2749                  * TRB to indicate it's the last TRB in the chain.
2750                  */
2751                 if (num_trbs > 1) {
2752                         field |= TRB_CHAIN;
2753                 } else {
2754                         /* FIXME - add check for ZERO_PACKET flag before this */
2755                         td->last_trb = ep_ring->enqueue;
2756                         field |= TRB_IOC;
2757                 }
2758
2759                 /* Only set interrupt on short packet for IN endpoints */
2760                 if (usb_urb_dir_in(urb))
2761                         field |= TRB_ISP;
2762
2763                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2764                                 "64KB boundary at %#x, end dma = %#x\n",
2765                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
2766                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2767                                 (unsigned int) addr + trb_buff_len);
2768                 if (TRB_MAX_BUFF_SIZE -
2769                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2770                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2771                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2772                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2773                                         (unsigned int) addr + trb_buff_len);
2774                 }
2775
2776                 /* Set the TRB length, TD size, and interrupter fields. */
2777                 if (xhci->hci_version < 0x100) {
2778                         remainder = xhci_td_remainder(
2779                                         urb->transfer_buffer_length -
2780                                         running_total);
2781                 } else {
2782                         remainder = xhci_v1_0_td_remainder(running_total,
2783                                         trb_buff_len, total_packet_count, urb);
2784                 }
2785                 length_field = TRB_LEN(trb_buff_len) |
2786                         remainder |
2787                         TRB_INTR_TARGET(0);
2788
2789                 if (num_trbs > 1)
2790                         more_trbs_coming = true;
2791                 else
2792                         more_trbs_coming = false;
2793                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2794                                 lower_32_bits(addr),
2795                                 upper_32_bits(addr),
2796                                 length_field,
2797                                 field | TRB_TYPE(TRB_NORMAL));
2798                 --num_trbs;
2799                 running_total += trb_buff_len;
2800
2801                 /* Calculate length for next transfer --
2802                  * Are we done queueing all the TRBs for this sg entry?
2803                  */
2804                 this_sg_len -= trb_buff_len;
2805                 if (this_sg_len == 0) {
2806                         --num_sgs;
2807                         if (num_sgs == 0)
2808                                 break;
2809                         sg = sg_next(sg);
2810                         addr = (u64) sg_dma_address(sg);
2811                         this_sg_len = sg_dma_len(sg);
2812                 } else {
2813                         addr += trb_buff_len;
2814                 }
2815
2816                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2817                         (addr & (TRB_MAX_BUFF_SIZE - 1));
2818                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2819                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2820                         trb_buff_len =
2821                                 urb->transfer_buffer_length - running_total;
2822         } while (running_total < urb->transfer_buffer_length);
2823
2824         check_trb_math(urb, num_trbs, running_total);
2825         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2826                         start_cycle, start_trb);
2827         return 0;
2828 }
2829
2830 /* This is very similar to what ehci-q.c qtd_fill() does */
2831 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2832                 struct urb *urb, int slot_id, unsigned int ep_index)
2833 {
2834         struct xhci_ring *ep_ring;
2835         struct urb_priv *urb_priv;
2836         struct xhci_td *td;
2837         int num_trbs;
2838         struct xhci_generic_trb *start_trb;
2839         bool first_trb;
2840         bool more_trbs_coming;
2841         int start_cycle;
2842         u32 field, length_field;
2843
2844         int running_total, trb_buff_len, ret;
2845         unsigned int total_packet_count;
2846         u64 addr;
2847
2848         if (urb->num_sgs)
2849                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2850
2851         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2852         if (!ep_ring)
2853                 return -EINVAL;
2854
2855         num_trbs = 0;
2856         /* How much data is (potentially) left before the 64KB boundary? */
2857         running_total = TRB_MAX_BUFF_SIZE -
2858                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2859         running_total &= TRB_MAX_BUFF_SIZE - 1;
2860
2861         /* If there's some data on this 64KB chunk, or we have to send a
2862          * zero-length transfer, we need at least one TRB
2863          */
2864         if (running_total != 0 || urb->transfer_buffer_length == 0)
2865                 num_trbs++;
2866         /* How many more 64KB chunks to transfer, how many more TRBs? */
2867         while (running_total < urb->transfer_buffer_length) {
2868                 num_trbs++;
2869                 running_total += TRB_MAX_BUFF_SIZE;
2870         }
2871         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2872
2873         if (!in_interrupt())
2874                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2875                                 "addr = %#llx, num_trbs = %d\n",
2876                                 urb->ep->desc.bEndpointAddress,
2877                                 urb->transfer_buffer_length,
2878                                 urb->transfer_buffer_length,
2879                                 (unsigned long long)urb->transfer_dma,
2880                                 num_trbs);
2881
2882         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2883                         ep_index, urb->stream_id,
2884                         num_trbs, urb, 0, mem_flags);
2885         if (ret < 0)
2886                 return ret;
2887
2888         urb_priv = urb->hcpriv;
2889         td = urb_priv->td[0];
2890
2891         /*
2892          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2893          * until we've finished creating all the other TRBs.  The ring's cycle
2894          * state may change as we enqueue the other TRBs, so save it too.
2895          */
2896         start_trb = &ep_ring->enqueue->generic;
2897         start_cycle = ep_ring->cycle_state;
2898
2899         running_total = 0;
2900         total_packet_count = roundup(urb->transfer_buffer_length,
2901                         le16_to_cpu(urb->ep->desc.wMaxPacketSize));
2902         /* How much data is in the first TRB? */
2903         addr = (u64) urb->transfer_dma;
2904         trb_buff_len = TRB_MAX_BUFF_SIZE -
2905                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2906         if (trb_buff_len > urb->transfer_buffer_length)
2907                 trb_buff_len = urb->transfer_buffer_length;
2908
2909         first_trb = true;
2910
2911         /* Queue the first TRB, even if it's zero-length */
2912         do {
2913                 u32 remainder = 0;
2914                 field = 0;
2915
2916                 /* Don't change the cycle bit of the first TRB until later */
2917                 if (first_trb) {
2918                         first_trb = false;
2919                         if (start_cycle == 0)
2920                                 field |= 0x1;
2921                 } else
2922                         field |= ep_ring->cycle_state;
2923
2924                 /* Chain all the TRBs together; clear the chain bit in the last
2925                  * TRB to indicate it's the last TRB in the chain.
2926                  */
2927                 if (num_trbs > 1) {
2928                         field |= TRB_CHAIN;
2929                 } else {
2930                         /* FIXME - add check for ZERO_PACKET flag before this */
2931                         td->last_trb = ep_ring->enqueue;
2932                         field |= TRB_IOC;
2933                 }
2934
2935                 /* Only set interrupt on short packet for IN endpoints */
2936                 if (usb_urb_dir_in(urb))
2937                         field |= TRB_ISP;
2938
2939                 /* Set the TRB length, TD size, and interrupter fields. */
2940                 if (xhci->hci_version < 0x100) {
2941                         remainder = xhci_td_remainder(
2942                                         urb->transfer_buffer_length -
2943                                         running_total);
2944                 } else {
2945                         remainder = xhci_v1_0_td_remainder(running_total,
2946                                         trb_buff_len, total_packet_count, urb);
2947                 }
2948                 length_field = TRB_LEN(trb_buff_len) |
2949                         remainder |
2950                         TRB_INTR_TARGET(0);
2951
2952                 if (num_trbs > 1)
2953                         more_trbs_coming = true;
2954                 else
2955                         more_trbs_coming = false;
2956                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2957                                 lower_32_bits(addr),
2958                                 upper_32_bits(addr),
2959                                 length_field,
2960                                 field | TRB_TYPE(TRB_NORMAL));
2961                 --num_trbs;
2962                 running_total += trb_buff_len;
2963
2964                 /* Calculate length for next transfer */
2965                 addr += trb_buff_len;
2966                 trb_buff_len = urb->transfer_buffer_length - running_total;
2967                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2968                         trb_buff_len = TRB_MAX_BUFF_SIZE;
2969         } while (running_total < urb->transfer_buffer_length);
2970
2971         check_trb_math(urb, num_trbs, running_total);
2972         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2973                         start_cycle, start_trb);
2974         return 0;
2975 }
2976
2977 /* Caller must have locked xhci->lock */
2978 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2979                 struct urb *urb, int slot_id, unsigned int ep_index)
2980 {
2981         struct xhci_ring *ep_ring;
2982         int num_trbs;
2983         int ret;
2984         struct usb_ctrlrequest *setup;
2985         struct xhci_generic_trb *start_trb;
2986         int start_cycle;
2987         u32 field, length_field;
2988         struct urb_priv *urb_priv;
2989         struct xhci_td *td;
2990
2991         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2992         if (!ep_ring)
2993                 return -EINVAL;
2994
2995         /*
2996          * Need to copy setup packet into setup TRB, so we can't use the setup
2997          * DMA address.
2998          */
2999         if (!urb->setup_packet)
3000                 return -EINVAL;
3001
3002         if (!in_interrupt())
3003                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3004                                 slot_id, ep_index);
3005         /* 1 TRB for setup, 1 for status */
3006         num_trbs = 2;
3007         /*
3008          * Don't need to check if we need additional event data and normal TRBs,
3009          * since data in control transfers will never get bigger than 16MB
3010          * XXX: can we get a buffer that crosses 64KB boundaries?
3011          */
3012         if (urb->transfer_buffer_length > 0)
3013                 num_trbs++;
3014         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3015                         ep_index, urb->stream_id,
3016                         num_trbs, urb, 0, mem_flags);
3017         if (ret < 0)
3018                 return ret;
3019
3020         urb_priv = urb->hcpriv;
3021         td = urb_priv->td[0];
3022
3023         /*
3024          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3025          * until we've finished creating all the other TRBs.  The ring's cycle
3026          * state may change as we enqueue the other TRBs, so save it too.
3027          */
3028         start_trb = &ep_ring->enqueue->generic;
3029         start_cycle = ep_ring->cycle_state;
3030
3031         /* Queue setup TRB - see section 6.4.1.2.1 */
3032         /* FIXME better way to translate setup_packet into two u32 fields? */
3033         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3034         field = 0;
3035         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3036         if (start_cycle == 0)
3037                 field |= 0x1;
3038
3039         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3040         if (xhci->hci_version == 0x100) {
3041                 if (urb->transfer_buffer_length > 0) {
3042                         if (setup->bRequestType & USB_DIR_IN)
3043                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3044                         else
3045                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3046                 }
3047         }
3048
3049         queue_trb(xhci, ep_ring, false, true,
3050                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3051                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3052                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3053                   /* Immediate data in pointer */
3054                   field);
3055
3056         /* If there's data, queue data TRBs */
3057         /* Only set interrupt on short packet for IN endpoints */
3058         if (usb_urb_dir_in(urb))
3059                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3060         else
3061                 field = TRB_TYPE(TRB_DATA);
3062
3063         length_field = TRB_LEN(urb->transfer_buffer_length) |
3064                 xhci_td_remainder(urb->transfer_buffer_length) |
3065                 TRB_INTR_TARGET(0);
3066         if (urb->transfer_buffer_length > 0) {
3067                 if (setup->bRequestType & USB_DIR_IN)
3068                         field |= TRB_DIR_IN;
3069                 queue_trb(xhci, ep_ring, false, true,
3070                                 lower_32_bits(urb->transfer_dma),
3071                                 upper_32_bits(urb->transfer_dma),
3072                                 length_field,
3073                                 field | ep_ring->cycle_state);
3074         }
3075
3076         /* Save the DMA address of the last TRB in the TD */
3077         td->last_trb = ep_ring->enqueue;
3078
3079         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3080         /* If the device sent data, the status stage is an OUT transfer */
3081         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3082                 field = 0;
3083         else
3084                 field = TRB_DIR_IN;
3085         queue_trb(xhci, ep_ring, false, false,
3086                         0,
3087                         0,
3088                         TRB_INTR_TARGET(0),
3089                         /* Event on completion */
3090                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3091
3092         giveback_first_trb(xhci, slot_id, ep_index, 0,
3093                         start_cycle, start_trb);
3094         return 0;
3095 }
3096
3097 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3098                 struct urb *urb, int i)
3099 {
3100         int num_trbs = 0;
3101         u64 addr, td_len, running_total;
3102
3103         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3104         td_len = urb->iso_frame_desc[i].length;
3105
3106         running_total = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3107         running_total &= TRB_MAX_BUFF_SIZE - 1;
3108         if (running_total != 0)
3109                 num_trbs++;
3110
3111         while (running_total < td_len) {
3112                 num_trbs++;
3113                 running_total += TRB_MAX_BUFF_SIZE;
3114         }
3115
3116         return num_trbs;
3117 }
3118
3119 /*
3120  * The transfer burst count field of the isochronous TRB defines the number of
3121  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3122  * devices can burst up to bMaxBurst number of packets per service interval.
3123  * This field is zero based, meaning a value of zero in the field means one
3124  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3125  * zero.  Only xHCI 1.0 host controllers support this field.
3126  */
3127 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3128                 struct usb_device *udev,
3129                 struct urb *urb, unsigned int total_packet_count)
3130 {
3131         unsigned int max_burst;
3132
3133         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3134                 return 0;
3135
3136         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3137         return roundup(total_packet_count, max_burst + 1) - 1;
3138 }
3139
3140 /*
3141  * Returns the number of packets in the last "burst" of packets.  This field is
3142  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3143  * the last burst packet count is equal to the total number of packets in the
3144  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3145  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3146  * contain 1 to (bMaxBurst + 1) packets.
3147  */
3148 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3149                 struct usb_device *udev,
3150                 struct urb *urb, unsigned int total_packet_count)
3151 {
3152         unsigned int max_burst;
3153         unsigned int residue;
3154
3155         if (xhci->hci_version < 0x100)
3156                 return 0;
3157
3158         switch (udev->speed) {
3159         case USB_SPEED_SUPER:
3160                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3161                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3162                 residue = total_packet_count % (max_burst + 1);
3163                 /* If residue is zero, the last burst contains (max_burst + 1)
3164                  * number of packets, but the TLBPC field is zero-based.
3165                  */
3166                 if (residue == 0)
3167                         return max_burst;
3168                 return residue - 1;
3169         default:
3170                 if (total_packet_count == 0)
3171                         return 0;
3172                 return total_packet_count - 1;
3173         }
3174 }
3175
3176 /* This is for isoc transfer */
3177 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3178                 struct urb *urb, int slot_id, unsigned int ep_index)
3179 {
3180         struct xhci_ring *ep_ring;
3181         struct urb_priv *urb_priv;
3182         struct xhci_td *td;
3183         int num_tds, trbs_per_td;
3184         struct xhci_generic_trb *start_trb;
3185         bool first_trb;
3186         int start_cycle;
3187         u32 field, length_field;
3188         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3189         u64 start_addr, addr;
3190         int i, j;
3191         bool more_trbs_coming;
3192
3193         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3194
3195         num_tds = urb->number_of_packets;
3196         if (num_tds < 1) {
3197                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3198                 return -EINVAL;
3199         }
3200
3201         if (!in_interrupt())
3202                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3203                                 " addr = %#llx, num_tds = %d\n",
3204                                 urb->ep->desc.bEndpointAddress,
3205                                 urb->transfer_buffer_length,
3206                                 urb->transfer_buffer_length,
3207                                 (unsigned long long)urb->transfer_dma,
3208                                 num_tds);
3209
3210         start_addr = (u64) urb->transfer_dma;
3211         start_trb = &ep_ring->enqueue->generic;
3212         start_cycle = ep_ring->cycle_state;
3213
3214         /* Queue the first TRB, even if it's zero-length */
3215         for (i = 0; i < num_tds; i++) {
3216                 unsigned int total_packet_count;
3217                 unsigned int burst_count;
3218                 unsigned int residue;
3219
3220                 first_trb = true;
3221                 running_total = 0;
3222                 addr = start_addr + urb->iso_frame_desc[i].offset;
3223                 td_len = urb->iso_frame_desc[i].length;
3224                 td_remain_len = td_len;
3225                 /* FIXME: Ignoring zero-length packets, can those happen? */
3226                 total_packet_count = roundup(td_len,
3227                                 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
3228                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3229                                 total_packet_count);
3230                 residue = xhci_get_last_burst_packet_count(xhci,
3231                                 urb->dev, urb, total_packet_count);
3232
3233                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3234
3235                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3236                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3237                 if (ret < 0)
3238                         return ret;
3239
3240                 urb_priv = urb->hcpriv;
3241                 td = urb_priv->td[i];
3242
3243                 for (j = 0; j < trbs_per_td; j++) {
3244                         u32 remainder = 0;
3245                         field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3246
3247                         if (first_trb) {
3248                                 /* Queue the isoc TRB */
3249                                 field |= TRB_TYPE(TRB_ISOC);
3250                                 /* Assume URB_ISO_ASAP is set */
3251                                 field |= TRB_SIA;
3252                                 if (i == 0) {
3253                                         if (start_cycle == 0)
3254                                                 field |= 0x1;
3255                                 } else
3256                                         field |= ep_ring->cycle_state;
3257                                 first_trb = false;
3258                         } else {
3259                                 /* Queue other normal TRBs */
3260                                 field |= TRB_TYPE(TRB_NORMAL);
3261                                 field |= ep_ring->cycle_state;
3262                         }
3263
3264                         /* Only set interrupt on short packet for IN EPs */
3265                         if (usb_urb_dir_in(urb))
3266                                 field |= TRB_ISP;
3267
3268                         /* Chain all the TRBs together; clear the chain bit in
3269                          * the last TRB to indicate it's the last TRB in the
3270                          * chain.
3271                          */
3272                         if (j < trbs_per_td - 1) {
3273                                 field |= TRB_CHAIN;
3274                                 more_trbs_coming = true;
3275                         } else {
3276                                 td->last_trb = ep_ring->enqueue;
3277                                 field |= TRB_IOC;
3278                                 if (xhci->hci_version == 0x100) {
3279                                         /* Set BEI bit except for the last td */
3280                                         if (i < num_tds - 1)
3281                                                 field |= TRB_BEI;
3282                                 }
3283                                 more_trbs_coming = false;
3284                         }
3285
3286                         /* Calculate TRB length */
3287                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3288                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3289                         if (trb_buff_len > td_remain_len)
3290                                 trb_buff_len = td_remain_len;
3291
3292                         /* Set the TRB length, TD size, & interrupter fields. */
3293                         if (xhci->hci_version < 0x100) {
3294                                 remainder = xhci_td_remainder(
3295                                                 td_len - running_total);
3296                         } else {
3297                                 remainder = xhci_v1_0_td_remainder(
3298                                                 running_total, trb_buff_len,
3299                                                 total_packet_count, urb);
3300                         }
3301                         length_field = TRB_LEN(trb_buff_len) |
3302                                 remainder |
3303                                 TRB_INTR_TARGET(0);
3304
3305                         queue_trb(xhci, ep_ring, false, more_trbs_coming,
3306                                 lower_32_bits(addr),
3307                                 upper_32_bits(addr),
3308                                 length_field,
3309                                 field);
3310                         running_total += trb_buff_len;
3311
3312                         addr += trb_buff_len;
3313                         td_remain_len -= trb_buff_len;
3314                 }
3315
3316                 /* Check TD length */
3317                 if (running_total != td_len) {
3318                         xhci_err(xhci, "ISOC TD length unmatch\n");
3319                         return -EINVAL;
3320                 }
3321         }
3322
3323         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3324                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3325                         usb_amd_quirk_pll_disable();
3326         }
3327         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3328
3329         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3330                         start_cycle, start_trb);
3331         return 0;
3332 }
3333
3334 /*
3335  * Check transfer ring to guarantee there is enough room for the urb.
3336  * Update ISO URB start_frame and interval.
3337  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3338  * update the urb->start_frame by now.
3339  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3340  */
3341 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3342                 struct urb *urb, int slot_id, unsigned int ep_index)
3343 {
3344         struct xhci_virt_device *xdev;
3345         struct xhci_ring *ep_ring;
3346         struct xhci_ep_ctx *ep_ctx;
3347         int start_frame;
3348         int xhci_interval;
3349         int ep_interval;
3350         int num_tds, num_trbs, i;
3351         int ret;
3352
3353         xdev = xhci->devs[slot_id];
3354         ep_ring = xdev->eps[ep_index].ring;
3355         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3356
3357         num_trbs = 0;
3358         num_tds = urb->number_of_packets;
3359         for (i = 0; i < num_tds; i++)
3360                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3361
3362         /* Check the ring to guarantee there is enough room for the whole urb.
3363          * Do not insert any td of the urb to the ring if the check failed.
3364          */
3365         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3366                            num_trbs, mem_flags);
3367         if (ret)
3368                 return ret;
3369
3370         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3371         start_frame &= 0x3fff;
3372
3373         urb->start_frame = start_frame;
3374         if (urb->dev->speed == USB_SPEED_LOW ||
3375                         urb->dev->speed == USB_SPEED_FULL)
3376                 urb->start_frame >>= 3;
3377
3378         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3379         ep_interval = urb->interval;
3380         /* Convert to microframes */
3381         if (urb->dev->speed == USB_SPEED_LOW ||
3382                         urb->dev->speed == USB_SPEED_FULL)
3383                 ep_interval *= 8;
3384         /* FIXME change this to a warning and a suggestion to use the new API
3385          * to set the polling interval (once the API is added).
3386          */
3387         if (xhci_interval != ep_interval) {
3388                 if (printk_ratelimit())
3389                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3390                                         " (%d microframe%s) than xHCI "
3391                                         "(%d microframe%s)\n",
3392                                         ep_interval,
3393                                         ep_interval == 1 ? "" : "s",
3394                                         xhci_interval,
3395                                         xhci_interval == 1 ? "" : "s");
3396                 urb->interval = xhci_interval;
3397                 /* Convert back to frames for LS/FS devices */
3398                 if (urb->dev->speed == USB_SPEED_LOW ||
3399                                 urb->dev->speed == USB_SPEED_FULL)
3400                         urb->interval /= 8;
3401         }
3402         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3403 }
3404
3405 /****           Command Ring Operations         ****/
3406
3407 /* Generic function for queueing a command TRB on the command ring.
3408  * Check to make sure there's room on the command ring for one command TRB.
3409  * Also check that there's room reserved for commands that must not fail.
3410  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3411  * then only check for the number of reserved spots.
3412  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3413  * because the command event handler may want to resubmit a failed command.
3414  */
3415 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3416                 u32 field3, u32 field4, bool command_must_succeed)
3417 {
3418         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3419         int ret;
3420
3421         if (!command_must_succeed)
3422                 reserved_trbs++;
3423
3424         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3425                         reserved_trbs, GFP_ATOMIC);
3426         if (ret < 0) {
3427                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3428                 if (command_must_succeed)
3429                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3430                                         "unfailable commands failed.\n");
3431                 return ret;
3432         }
3433         queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3434                         field4 | xhci->cmd_ring->cycle_state);
3435         return 0;
3436 }
3437
3438 /* Queue a slot enable or disable request on the command ring */
3439 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3440 {
3441         return queue_command(xhci, 0, 0, 0,
3442                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3443 }
3444
3445 /* Queue an address device command TRB */
3446 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3447                 u32 slot_id)
3448 {
3449         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3450                         upper_32_bits(in_ctx_ptr), 0,
3451                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3452                         false);
3453 }
3454
3455 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3456                 u32 field1, u32 field2, u32 field3, u32 field4)
3457 {
3458         return queue_command(xhci, field1, field2, field3, field4, false);
3459 }
3460
3461 /* Queue a reset device command TRB */
3462 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3463 {
3464         return queue_command(xhci, 0, 0, 0,
3465                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3466                         false);
3467 }
3468
3469 /* Queue a configure endpoint command TRB */
3470 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3471                 u32 slot_id, bool command_must_succeed)
3472 {
3473         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3474                         upper_32_bits(in_ctx_ptr), 0,
3475                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3476                         command_must_succeed);
3477 }
3478
3479 /* Queue an evaluate context command TRB */
3480 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3481                 u32 slot_id)
3482 {
3483         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3484                         upper_32_bits(in_ctx_ptr), 0,
3485                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3486                         false);
3487 }
3488
3489 /*
3490  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3491  * activity on an endpoint that is about to be suspended.
3492  */
3493 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3494                 unsigned int ep_index, int suspend)
3495 {
3496         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3497         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3498         u32 type = TRB_TYPE(TRB_STOP_RING);
3499         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3500
3501         return queue_command(xhci, 0, 0, 0,
3502                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3503 }
3504
3505 /* Set Transfer Ring Dequeue Pointer command.
3506  * This should not be used for endpoints that have streams enabled.
3507  */
3508 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3509                 unsigned int ep_index, unsigned int stream_id,
3510                 struct xhci_segment *deq_seg,
3511                 union xhci_trb *deq_ptr, u32 cycle_state)
3512 {
3513         dma_addr_t addr;
3514         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3515         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3516         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3517         u32 type = TRB_TYPE(TRB_SET_DEQ);
3518         struct xhci_virt_ep *ep;
3519
3520         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3521         if (addr == 0) {
3522                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3523                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3524                                 deq_seg, deq_ptr);
3525                 return 0;
3526         }
3527         ep = &xhci->devs[slot_id]->eps[ep_index];
3528         if ((ep->ep_state & SET_DEQ_PENDING)) {
3529                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3530                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3531                 return 0;
3532         }
3533         ep->queued_deq_seg = deq_seg;
3534         ep->queued_deq_ptr = deq_ptr;
3535         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3536                         upper_32_bits(addr), trb_stream_id,
3537                         trb_slot_id | trb_ep_index | type, false);
3538 }
3539
3540 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3541                 unsigned int ep_index)
3542 {
3543         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3544         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3545         u32 type = TRB_TYPE(TRB_RESET_EP);
3546
3547         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3548                         false);
3549 }