2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
82 unsigned long segment_offset;
84 if (!seg || !trb || trb < seg->trbs)
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
90 return seg->dma + (segment_offset * sizeof(*trb));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
116 return TRB_TYPE_LINK_LE32(trb->link.control);
119 static int enqueue_is_link_trb(struct xhci_ring *ring)
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return TRB_TYPE_LINK_LE32(link->control);
125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
129 static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
134 if (last_trb(xhci, ring, *seg, *trb)) {
136 *trb = ((*seg)->trbs);
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
148 unsigned long long addr;
154 * Update the dequeue pointer further if that was a link TRB or
155 * we're at the end of an event ring segment (which doesn't have
158 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
159 if (consumer && last_trb_on_last_seg(xhci, ring,
160 ring->deq_seg, ring->dequeue)) {
162 xhci_dbg(xhci, "Toggle cycle state "
163 "for ring %p = %i\n",
167 ring->cycle_state = (ring->cycle_state ? 0 : 1);
169 ring->deq_seg = ring->deq_seg->next;
170 ring->dequeue = ring->deq_seg->trbs;
174 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
176 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
180 * See Cycle bit rules. SW is the consumer for the event ring only.
181 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
183 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
184 * chain bit is set), then set the chain bit in all the following link TRBs.
185 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
186 * have their chain bit cleared (so that each Link TRB is a separate TD).
188 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
189 * set, but other sections talk about dealing with the chain bit set. This was
190 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
191 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
193 * @more_trbs_coming: Will you enqueue more TRBs before calling
194 * prepare_transfer()?
196 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
197 bool consumer, bool more_trbs_coming, bool isoc)
200 union xhci_trb *next;
201 unsigned long long addr;
203 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
204 next = ++(ring->enqueue);
207 /* Update the dequeue pointer further if that was a link TRB or we're at
208 * the end of an event ring segment (which doesn't have link TRBS)
210 while (last_trb(xhci, ring, ring->enq_seg, next)) {
212 if (ring != xhci->event_ring) {
214 * If the caller doesn't plan on enqueueing more
215 * TDs before ringing the doorbell, then we
216 * don't want to give the link TRB to the
217 * hardware just yet. We'll give the link TRB
218 * back in prepare_ring() just before we enqueue
219 * the TD at the top of the ring.
221 if (!chain && !more_trbs_coming)
224 /* If we're not dealing with 0.95 hardware or
225 * isoc rings on AMD 0.96 host,
226 * carry over the chain bit of the previous TRB
227 * (which may mean the chain bit is cleared).
229 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
230 && !xhci_link_trb_quirk(xhci)) {
231 next->link.control &=
232 cpu_to_le32(~TRB_CHAIN);
233 next->link.control |=
236 /* Give this link TRB to the hardware */
238 next->link.control ^= cpu_to_le32(TRB_CYCLE);
240 /* Toggle the cycle bit after the last ring segment. */
241 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
242 ring->cycle_state = (ring->cycle_state ? 0 : 1);
244 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
246 (unsigned int) ring->cycle_state);
249 ring->enq_seg = ring->enq_seg->next;
250 ring->enqueue = ring->enq_seg->trbs;
251 next = ring->enqueue;
253 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
257 * Check to see if there's room to enqueue num_trbs on the ring. See rules
259 * FIXME: this would be simpler and faster if we just kept track of the number
260 * of free TRBs in a ring.
262 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
263 unsigned int num_trbs)
266 union xhci_trb *enq = ring->enqueue;
267 struct xhci_segment *enq_seg = ring->enq_seg;
268 struct xhci_segment *cur_seg;
269 unsigned int left_on_ring;
271 /* If we are currently pointing to a link TRB, advance the
272 * enqueue pointer before checking for space */
273 while (last_trb(xhci, ring, enq_seg, enq)) {
274 enq_seg = enq_seg->next;
278 /* Check if ring is empty */
279 if (enq == ring->dequeue) {
280 /* Can't use link trbs */
281 left_on_ring = TRBS_PER_SEGMENT - 1;
282 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
283 cur_seg = cur_seg->next)
284 left_on_ring += TRBS_PER_SEGMENT - 1;
286 /* Always need one TRB free in the ring. */
288 if (num_trbs > left_on_ring) {
289 xhci_warn(xhci, "Not enough room on ring; "
290 "need %u TRBs, %u TRBs left\n",
291 num_trbs, left_on_ring);
296 /* Make sure there's an extra empty TRB available */
297 for (i = 0; i <= num_trbs; ++i) {
298 if (enq == ring->dequeue)
301 while (last_trb(xhci, ring, enq_seg, enq)) {
302 enq_seg = enq_seg->next;
309 /* Ring the host controller doorbell after placing a command on the ring */
310 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
312 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
315 xhci_dbg(xhci, "// Ding dong!\n");
316 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
317 /* Flush PCI posted writes */
318 xhci_readl(xhci, &xhci->dba->doorbell[0]);
321 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
326 xhci_dbg(xhci, "Abort command ring\n");
328 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
329 xhci_dbg(xhci, "The command ring isn't running, "
330 "Have the command ring been stopped?\n");
334 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
335 if (!(temp_64 & CMD_RING_RUNNING)) {
336 xhci_dbg(xhci, "Command ring had been stopped\n");
339 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
340 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
341 &xhci->op_regs->cmd_ring);
343 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
344 * time the completion od all xHCI commands, including
345 * the Command Abort operation. If software doesn't see
346 * CRR negated in a timely manner (e.g. longer than 5
347 * seconds), then it should assume that the there are
348 * larger problems with the xHC and assert HCRST.
350 ret = handshake(xhci, &xhci->op_regs->cmd_ring,
351 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
353 xhci_err(xhci, "Stopped the command ring failed, "
354 "maybe the host is dead\n");
355 xhci->xhc_state |= XHCI_STATE_DYING;
364 static int xhci_queue_cd(struct xhci_hcd *xhci,
365 struct xhci_command *command,
366 union xhci_trb *cmd_trb)
369 cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
372 INIT_LIST_HEAD(&cd->cancel_cmd_list);
374 cd->command = command;
375 cd->cmd_trb = cmd_trb;
376 list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
382 * Cancel the command which has issue.
384 * Some commands may hang due to waiting for acknowledgement from
385 * usb device. It is outside of the xHC's ability to control and
386 * will cause the command ring is blocked. When it occurs software
387 * should intervene to recover the command ring.
388 * See Section 4.6.1.1 and 4.6.1.2
390 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
391 union xhci_trb *cmd_trb)
396 spin_lock_irqsave(&xhci->lock, flags);
398 if (xhci->xhc_state & XHCI_STATE_DYING) {
399 xhci_warn(xhci, "Abort the command ring,"
400 " but the xHCI is dead.\n");
405 /* queue the cmd desriptor to cancel_cmd_list */
406 retval = xhci_queue_cd(xhci, command, cmd_trb);
408 xhci_warn(xhci, "Queuing command descriptor failed.\n");
412 /* abort command ring */
413 retval = xhci_abort_cmd_ring(xhci);
415 xhci_err(xhci, "Abort command ring failed\n");
416 if (unlikely(retval == -ESHUTDOWN)) {
417 spin_unlock_irqrestore(&xhci->lock, flags);
418 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
419 xhci_dbg(xhci, "xHCI host controller is dead.\n");
425 spin_unlock_irqrestore(&xhci->lock, flags);
429 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
430 unsigned int slot_id,
431 unsigned int ep_index,
432 unsigned int stream_id)
434 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
435 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
436 unsigned int ep_state = ep->ep_state;
438 /* Don't ring the doorbell for this endpoint if there are pending
439 * cancellations because we don't want to interrupt processing.
440 * We don't want to restart any stream rings if there's a set dequeue
441 * pointer command pending because the device can choose to start any
442 * stream once the endpoint is on the HW schedule.
443 * FIXME - check all the stream rings for pending cancellations.
445 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
446 (ep_state & EP_HALTED))
448 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
449 /* The CPU has better things to do at this point than wait for a
450 * write-posting flush. It'll get there soon enough.
454 /* Ring the doorbell for any rings with pending URBs */
455 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
456 unsigned int slot_id,
457 unsigned int ep_index)
459 unsigned int stream_id;
460 struct xhci_virt_ep *ep;
462 ep = &xhci->devs[slot_id]->eps[ep_index];
464 /* A ring has pending URBs if its TD list is not empty */
465 if (!(ep->ep_state & EP_HAS_STREAMS)) {
466 if (ep->ring && !(list_empty(&ep->ring->td_list)))
467 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
471 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
473 struct xhci_stream_info *stream_info = ep->stream_info;
474 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
475 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
481 * Find the segment that trb is in. Start searching in start_seg.
482 * If we must move past a segment that has a link TRB with a toggle cycle state
483 * bit set, then we will toggle the value pointed at by cycle_state.
485 static struct xhci_segment *find_trb_seg(
486 struct xhci_segment *start_seg,
487 union xhci_trb *trb, int *cycle_state)
489 struct xhci_segment *cur_seg = start_seg;
490 struct xhci_generic_trb *generic_trb;
492 while (cur_seg->trbs > trb ||
493 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
494 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
495 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
497 cur_seg = cur_seg->next;
498 if (cur_seg == start_seg)
499 /* Looped over the entire list. Oops! */
506 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
507 unsigned int slot_id, unsigned int ep_index,
508 unsigned int stream_id)
510 struct xhci_virt_ep *ep;
512 ep = &xhci->devs[slot_id]->eps[ep_index];
513 /* Common case: no streams */
514 if (!(ep->ep_state & EP_HAS_STREAMS))
517 if (stream_id == 0) {
519 "WARN: Slot ID %u, ep index %u has streams, "
520 "but URB has no stream ID.\n",
525 if (stream_id < ep->stream_info->num_streams)
526 return ep->stream_info->stream_rings[stream_id];
529 "WARN: Slot ID %u, ep index %u has "
530 "stream IDs 1 to %u allocated, "
531 "but stream ID %u is requested.\n",
533 ep->stream_info->num_streams - 1,
538 /* Get the right ring for the given URB.
539 * If the endpoint supports streams, boundary check the URB's stream ID.
540 * If the endpoint doesn't support streams, return the singular endpoint ring.
542 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
545 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
546 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
550 * Move the xHC's endpoint ring dequeue pointer past cur_td.
551 * Record the new state of the xHC's endpoint ring dequeue segment,
552 * dequeue pointer, and new consumer cycle state in state.
553 * Update our internal representation of the ring's dequeue pointer.
555 * We do this in three jumps:
556 * - First we update our new ring state to be the same as when the xHC stopped.
557 * - Then we traverse the ring to find the segment that contains
558 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
559 * any link TRBs with the toggle cycle bit set.
560 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
561 * if we've moved it past a link TRB with the toggle cycle bit set.
563 * Some of the uses of xhci_generic_trb are grotty, but if they're done
564 * with correct __le32 accesses they should work fine. Only users of this are
567 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
568 unsigned int slot_id, unsigned int ep_index,
569 unsigned int stream_id, struct xhci_td *cur_td,
570 struct xhci_dequeue_state *state)
572 struct xhci_virt_device *dev = xhci->devs[slot_id];
573 struct xhci_virt_ep *ep = &dev->eps[ep_index];
574 struct xhci_ring *ep_ring;
575 struct xhci_segment *new_seg;
576 union xhci_trb *new_deq;
579 bool cycle_found = false;
580 bool td_last_trb_found = false;
582 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
583 ep_index, stream_id);
585 xhci_warn(xhci, "WARN can't find new dequeue state "
586 "for invalid stream ID %u.\n",
591 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
592 xhci_dbg(xhci, "Finding endpoint context\n");
593 /* 4.6.9 the css flag is written to the stream context for streams */
594 if (ep->ep_state & EP_HAS_STREAMS) {
595 struct xhci_stream_ctx *ctx =
596 &ep->stream_info->stream_ctx_array[stream_id];
597 hw_dequeue = le64_to_cpu(ctx->stream_ring);
599 struct xhci_ep_ctx *ep_ctx
600 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
601 hw_dequeue = le64_to_cpu(ep_ctx->deq);
604 new_seg = ep_ring->deq_seg;
605 new_deq = ep_ring->dequeue;
606 state->new_cycle_state = hw_dequeue & 0x1;
609 * We want to find the pointer, segment and cycle state of the new trb
610 * (the one after current TD's last_trb). We know the cycle state at
611 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
615 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
616 == (dma_addr_t)(hw_dequeue & ~0xf)) {
618 if (td_last_trb_found)
621 if (new_deq == cur_td->last_trb)
622 td_last_trb_found = true;
625 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
626 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
627 state->new_cycle_state ^= 0x1;
629 next_trb(xhci, ep_ring, &new_seg, &new_deq);
631 /* Search wrapped around, bail out */
632 if (new_deq == ep->ring->dequeue) {
633 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
634 state->new_deq_seg = NULL;
635 state->new_deq_ptr = NULL;
639 } while (!cycle_found || !td_last_trb_found);
641 state->new_deq_seg = new_seg;
642 state->new_deq_ptr = new_deq;
644 /* Don't update the ring cycle state for the producer (us). */
645 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
647 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
649 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
650 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
651 (unsigned long long) addr);
654 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
655 * (The last TRB actually points to the ring enqueue pointer, which is not part
656 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
658 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
659 struct xhci_td *cur_td, bool flip_cycle)
661 struct xhci_segment *cur_seg;
662 union xhci_trb *cur_trb;
664 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
666 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
667 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
668 /* Unchain any chained Link TRBs, but
669 * leave the pointers intact.
671 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
672 /* Flip the cycle bit (link TRBs can't be the first
676 cur_trb->generic.field[3] ^=
677 cpu_to_le32(TRB_CYCLE);
678 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
679 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
680 "in seg %p (0x%llx dma)\n",
682 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
684 (unsigned long long)cur_seg->dma);
686 cur_trb->generic.field[0] = 0;
687 cur_trb->generic.field[1] = 0;
688 cur_trb->generic.field[2] = 0;
689 /* Preserve only the cycle bit of this TRB */
690 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
691 /* Flip the cycle bit except on the first or last TRB */
692 if (flip_cycle && cur_trb != cur_td->first_trb &&
693 cur_trb != cur_td->last_trb)
694 cur_trb->generic.field[3] ^=
695 cpu_to_le32(TRB_CYCLE);
696 cur_trb->generic.field[3] |= cpu_to_le32(
697 TRB_TYPE(TRB_TR_NOOP));
698 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
699 "in seg %p (0x%llx dma)\n",
701 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
703 (unsigned long long)cur_seg->dma);
705 if (cur_trb == cur_td->last_trb)
710 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
711 unsigned int ep_index, unsigned int stream_id,
712 struct xhci_segment *deq_seg,
713 union xhci_trb *deq_ptr, u32 cycle_state);
715 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
716 unsigned int slot_id, unsigned int ep_index,
717 unsigned int stream_id,
718 struct xhci_dequeue_state *deq_state)
720 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
722 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
723 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
724 deq_state->new_deq_seg,
725 (unsigned long long)deq_state->new_deq_seg->dma,
726 deq_state->new_deq_ptr,
727 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
728 deq_state->new_cycle_state);
729 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
730 deq_state->new_deq_seg,
731 deq_state->new_deq_ptr,
732 (u32) deq_state->new_cycle_state);
733 /* Stop the TD queueing code from ringing the doorbell until
734 * this command completes. The HC won't set the dequeue pointer
735 * if the ring is running, and ringing the doorbell starts the
738 ep->ep_state |= SET_DEQ_PENDING;
741 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
742 struct xhci_virt_ep *ep)
744 ep->ep_state &= ~EP_HALT_PENDING;
745 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
746 * timer is running on another CPU, we don't decrement stop_cmds_pending
747 * (since we didn't successfully stop the watchdog timer).
749 if (del_timer(&ep->stop_cmd_timer))
750 ep->stop_cmds_pending--;
753 /* Must be called with xhci->lock held in interrupt context */
754 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
755 struct xhci_td *cur_td, int status, char *adjective)
759 struct urb_priv *urb_priv;
762 urb_priv = urb->hcpriv;
764 hcd = bus_to_hcd(urb->dev->bus);
766 /* Only giveback urb when this is the last td in urb */
767 if (urb_priv->td_cnt == urb_priv->length) {
768 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
769 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
770 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
771 if (xhci->quirks & XHCI_AMD_PLL_FIX)
772 usb_amd_quirk_pll_enable();
775 usb_hcd_unlink_urb_from_ep(hcd, urb);
777 spin_unlock(&xhci->lock);
778 usb_hcd_giveback_urb(hcd, urb, status);
779 xhci_urb_free_priv(xhci, urb_priv);
780 spin_lock(&xhci->lock);
785 * When we get a command completion for a Stop Endpoint Command, we need to
786 * unlink any cancelled TDs from the ring. There are two ways to do that:
788 * 1. If the HW was in the middle of processing the TD that needs to be
789 * cancelled, then we must move the ring's dequeue pointer past the last TRB
790 * in the TD with a Set Dequeue Pointer Command.
791 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
792 * bit cleared) so that the HW will skip over them.
794 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
795 union xhci_trb *trb, struct xhci_event_cmd *event)
797 unsigned int slot_id;
798 unsigned int ep_index;
799 struct xhci_virt_device *virt_dev;
800 struct xhci_ring *ep_ring;
801 struct xhci_virt_ep *ep;
802 struct list_head *entry;
803 struct xhci_td *cur_td = NULL;
804 struct xhci_td *last_unlinked_td;
806 struct xhci_dequeue_state deq_state;
808 if (unlikely(TRB_TO_SUSPEND_PORT(
809 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
810 slot_id = TRB_TO_SLOT_ID(
811 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
812 virt_dev = xhci->devs[slot_id];
814 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
817 xhci_warn(xhci, "Stop endpoint command "
818 "completion for disabled slot %u\n",
823 memset(&deq_state, 0, sizeof(deq_state));
824 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
825 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
826 ep = &xhci->devs[slot_id]->eps[ep_index];
828 if (list_empty(&ep->cancelled_td_list)) {
829 xhci_stop_watchdog_timer_in_irq(xhci, ep);
830 ep->stopped_td = NULL;
831 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
835 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
836 * We have the xHCI lock, so nothing can modify this list until we drop
837 * it. We're also in the event handler, so we can't get re-interrupted
838 * if another Stop Endpoint command completes
840 list_for_each(entry, &ep->cancelled_td_list) {
841 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
842 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
844 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
845 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
847 /* This shouldn't happen unless a driver is mucking
848 * with the stream ID after submission. This will
849 * leave the TD on the hardware ring, and the hardware
850 * will try to execute it, and may access a buffer
851 * that has already been freed. In the best case, the
852 * hardware will execute it, and the event handler will
853 * ignore the completion event for that TD, since it was
854 * removed from the td_list for that endpoint. In
855 * short, don't muck with the stream ID after
858 xhci_warn(xhci, "WARN Cancelled URB %p "
859 "has invalid stream ID %u.\n",
861 cur_td->urb->stream_id);
862 goto remove_finished_td;
865 * If we stopped on the TD we need to cancel, then we have to
866 * move the xHC endpoint ring dequeue pointer past this TD.
868 if (cur_td == ep->stopped_td)
869 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
870 cur_td->urb->stream_id,
873 td_to_noop(xhci, ep_ring, cur_td, false);
876 * The event handler won't see a completion for this TD anymore,
877 * so remove it from the endpoint ring's TD list. Keep it in
878 * the cancelled TD list for URB completion later.
880 list_del_init(&cur_td->td_list);
882 last_unlinked_td = cur_td;
883 xhci_stop_watchdog_timer_in_irq(xhci, ep);
885 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
886 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
887 xhci_queue_new_dequeue_state(xhci,
889 ep->stopped_td->urb->stream_id,
891 xhci_ring_cmd_db(xhci);
893 /* Otherwise ring the doorbell(s) to restart queued transfers */
894 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
897 /* Clear stopped_td if endpoint is not halted */
898 if (!(ep->ep_state & EP_HALTED))
899 ep->stopped_td = NULL;
902 * Drop the lock and complete the URBs in the cancelled TD list.
903 * New TDs to be cancelled might be added to the end of the list before
904 * we can complete all the URBs for the TDs we already unlinked.
905 * So stop when we've completed the URB for the last TD we unlinked.
908 cur_td = list_entry(ep->cancelled_td_list.next,
909 struct xhci_td, cancelled_td_list);
910 list_del_init(&cur_td->cancelled_td_list);
912 /* Clean up the cancelled URB */
913 /* Doesn't matter what we pass for status, since the core will
914 * just overwrite it (because the URB has been unlinked).
916 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
918 /* Stop processing the cancelled list if the watchdog timer is
921 if (xhci->xhc_state & XHCI_STATE_DYING)
923 } while (cur_td != last_unlinked_td);
925 /* Return to the event handler with xhci->lock re-acquired */
928 /* Watchdog timer function for when a stop endpoint command fails to complete.
929 * In this case, we assume the host controller is broken or dying or dead. The
930 * host may still be completing some other events, so we have to be careful to
931 * let the event ring handler and the URB dequeueing/enqueueing functions know
932 * through xhci->state.
934 * The timer may also fire if the host takes a very long time to respond to the
935 * command, and the stop endpoint command completion handler cannot delete the
936 * timer before the timer function is called. Another endpoint cancellation may
937 * sneak in before the timer function can grab the lock, and that may queue
938 * another stop endpoint command and add the timer back. So we cannot use a
939 * simple flag to say whether there is a pending stop endpoint command for a
940 * particular endpoint.
942 * Instead we use a combination of that flag and a counter for the number of
943 * pending stop endpoint commands. If the timer is the tail end of the last
944 * stop endpoint command, and the endpoint's command is still pending, we assume
947 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
949 struct xhci_hcd *xhci;
950 struct xhci_virt_ep *ep;
951 struct xhci_virt_ep *temp_ep;
952 struct xhci_ring *ring;
953 struct xhci_td *cur_td;
957 ep = (struct xhci_virt_ep *) arg;
960 spin_lock_irqsave(&xhci->lock, flags);
962 ep->stop_cmds_pending--;
963 if (xhci->xhc_state & XHCI_STATE_DYING) {
964 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
965 "xHCI as DYING, exiting.\n");
966 spin_unlock_irqrestore(&xhci->lock, flags);
969 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
970 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
972 spin_unlock_irqrestore(&xhci->lock, flags);
976 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
977 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
978 /* Oops, HC is dead or dying or at least not responding to the stop
981 xhci->xhc_state |= XHCI_STATE_DYING;
982 /* Disable interrupts from the host controller and start halting it */
984 spin_unlock_irqrestore(&xhci->lock, flags);
986 ret = xhci_halt(xhci);
988 spin_lock_irqsave(&xhci->lock, flags);
990 /* This is bad; the host is not responding to commands and it's
991 * not allowing itself to be halted. At least interrupts are
992 * disabled. If we call usb_hc_died(), it will attempt to
993 * disconnect all device drivers under this host. Those
994 * disconnect() methods will wait for all URBs to be unlinked,
995 * so we must complete them.
997 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
998 xhci_warn(xhci, "Completing active URBs anyway.\n");
999 /* We could turn all TDs on the rings to no-ops. This won't
1000 * help if the host has cached part of the ring, and is slow if
1001 * we want to preserve the cycle bit. Skip it and hope the host
1002 * doesn't touch the memory.
1005 for (i = 0; i < MAX_HC_SLOTS; i++) {
1008 for (j = 0; j < 31; j++) {
1009 temp_ep = &xhci->devs[i]->eps[j];
1010 ring = temp_ep->ring;
1013 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
1014 "ep index %u\n", i, j);
1015 while (!list_empty(&ring->td_list)) {
1016 cur_td = list_first_entry(&ring->td_list,
1019 list_del_init(&cur_td->td_list);
1020 if (!list_empty(&cur_td->cancelled_td_list))
1021 list_del_init(&cur_td->cancelled_td_list);
1022 xhci_giveback_urb_in_irq(xhci, cur_td,
1023 -ESHUTDOWN, "killed");
1025 while (!list_empty(&temp_ep->cancelled_td_list)) {
1026 cur_td = list_first_entry(
1027 &temp_ep->cancelled_td_list,
1030 list_del_init(&cur_td->cancelled_td_list);
1031 xhci_giveback_urb_in_irq(xhci, cur_td,
1032 -ESHUTDOWN, "killed");
1036 spin_unlock_irqrestore(&xhci->lock, flags);
1037 xhci_dbg(xhci, "Calling usb_hc_died()\n");
1038 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1039 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1043 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1044 * we need to clear the set deq pending flag in the endpoint ring state, so that
1045 * the TD queueing code can ring the doorbell again. We also need to ring the
1046 * endpoint doorbell to restart the ring, but only if there aren't more
1047 * cancellations pending.
1049 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1050 struct xhci_event_cmd *event,
1051 union xhci_trb *trb)
1053 unsigned int slot_id;
1054 unsigned int ep_index;
1055 unsigned int stream_id;
1056 struct xhci_ring *ep_ring;
1057 struct xhci_virt_device *dev;
1058 struct xhci_ep_ctx *ep_ctx;
1059 struct xhci_slot_ctx *slot_ctx;
1061 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1062 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1063 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1064 dev = xhci->devs[slot_id];
1066 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1068 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1069 "freed stream ID %u\n",
1071 /* XXX: Harmless??? */
1072 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1076 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1077 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1079 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1080 unsigned int ep_state;
1081 unsigned int slot_state;
1083 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1085 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1086 "of stream ID configuration\n");
1088 case COMP_CTX_STATE:
1089 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1090 "to incorrect slot or ep state.\n");
1091 ep_state = le32_to_cpu(ep_ctx->ep_info);
1092 ep_state &= EP_STATE_MASK;
1093 slot_state = le32_to_cpu(slot_ctx->dev_state);
1094 slot_state = GET_SLOT_STATE(slot_state);
1095 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1096 slot_state, ep_state);
1099 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1100 "slot %u was not enabled.\n", slot_id);
1103 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1104 "completion code of %u.\n",
1105 GET_COMP_CODE(le32_to_cpu(event->status)));
1108 /* OK what do we do now? The endpoint state is hosed, and we
1109 * should never get to this point if the synchronization between
1110 * queueing, and endpoint state are correct. This might happen
1111 * if the device gets disconnected after we've finished
1112 * cancelling URBs, which might not be an error...
1115 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1116 le64_to_cpu(ep_ctx->deq));
1117 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1118 dev->eps[ep_index].queued_deq_ptr) ==
1119 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1120 /* Update the ring's dequeue segment and dequeue pointer
1121 * to reflect the new position.
1123 ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
1124 ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
1126 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1127 "Ptr command & xHCI internal state.\n");
1128 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1129 dev->eps[ep_index].queued_deq_seg,
1130 dev->eps[ep_index].queued_deq_ptr);
1134 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1135 dev->eps[ep_index].queued_deq_seg = NULL;
1136 dev->eps[ep_index].queued_deq_ptr = NULL;
1137 /* Restart any rings with pending URBs */
1138 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1141 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1142 struct xhci_event_cmd *event,
1143 union xhci_trb *trb)
1146 unsigned int ep_index;
1148 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1149 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1150 /* This command will only fail if the endpoint wasn't halted,
1151 * but we don't care.
1153 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1154 GET_COMP_CODE(le32_to_cpu(event->status)));
1156 /* HW with the reset endpoint quirk needs to have a configure endpoint
1157 * command complete before the endpoint can be used. Queue that here
1158 * because the HW can't handle two commands being queued in a row.
1160 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1161 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1162 xhci_queue_configure_endpoint(xhci,
1163 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1165 xhci_ring_cmd_db(xhci);
1167 /* Clear our internal halted state */
1168 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1172 /* Complete the command and detele it from the devcie's command queue.
1174 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1175 struct xhci_command *command, u32 status)
1177 command->status = status;
1178 list_del(&command->cmd_list);
1179 if (command->completion)
1180 complete(command->completion);
1182 xhci_free_command(xhci, command);
1186 /* Check to see if a command in the device's command queue matches this one.
1187 * Signal the completion or free the command, and return 1. Return 0 if the
1188 * completed command isn't at the head of the command list.
1190 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1191 struct xhci_virt_device *virt_dev,
1192 struct xhci_event_cmd *event)
1194 struct xhci_command *command;
1196 if (list_empty(&virt_dev->cmd_list))
1199 command = list_entry(virt_dev->cmd_list.next,
1200 struct xhci_command, cmd_list);
1201 if (xhci->cmd_ring->dequeue != command->command_trb)
1204 xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1205 GET_COMP_CODE(le32_to_cpu(event->status)));
1210 * Finding the command trb need to be cancelled and modifying it to
1211 * NO OP command. And if the command is in device's command wait
1212 * list, finishing and freeing it.
1214 * If we can't find the command trb, we think it had already been
1217 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1219 struct xhci_segment *cur_seg;
1220 union xhci_trb *cmd_trb;
1223 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1226 /* find the current segment of command ring */
1227 cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1228 xhci->cmd_ring->dequeue, &cycle_state);
1231 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1232 xhci->cmd_ring->dequeue,
1233 (unsigned long long)
1234 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1235 xhci->cmd_ring->dequeue));
1236 xhci_debug_ring(xhci, xhci->cmd_ring);
1237 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1241 /* find the command trb matched by cd from command ring */
1242 for (cmd_trb = xhci->cmd_ring->dequeue;
1243 cmd_trb != xhci->cmd_ring->enqueue;
1244 next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1245 /* If the trb is link trb, continue */
1246 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1249 if (cur_cd->cmd_trb == cmd_trb) {
1251 /* If the command in device's command list, we should
1252 * finish it and free the command structure.
1254 if (cur_cd->command)
1255 xhci_complete_cmd_in_cmd_wait_list(xhci,
1256 cur_cd->command, COMP_CMD_STOP);
1258 /* get cycle state from the origin command trb */
1259 cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1262 /* modify the command trb to NO OP command */
1263 cmd_trb->generic.field[0] = 0;
1264 cmd_trb->generic.field[1] = 0;
1265 cmd_trb->generic.field[2] = 0;
1266 cmd_trb->generic.field[3] = cpu_to_le32(
1267 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1273 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1275 struct xhci_cd *cur_cd, *next_cd;
1277 if (list_empty(&xhci->cancel_cmd_list))
1280 list_for_each_entry_safe(cur_cd, next_cd,
1281 &xhci->cancel_cmd_list, cancel_cmd_list) {
1282 xhci_cmd_to_noop(xhci, cur_cd);
1283 list_del(&cur_cd->cancel_cmd_list);
1289 * traversing the cancel_cmd_list. If the command descriptor according
1290 * to cmd_trb is found, the function free it and return 1, otherwise
1293 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1294 union xhci_trb *cmd_trb)
1296 struct xhci_cd *cur_cd, *next_cd;
1298 if (list_empty(&xhci->cancel_cmd_list))
1301 list_for_each_entry_safe(cur_cd, next_cd,
1302 &xhci->cancel_cmd_list, cancel_cmd_list) {
1303 if (cur_cd->cmd_trb == cmd_trb) {
1304 if (cur_cd->command)
1305 xhci_complete_cmd_in_cmd_wait_list(xhci,
1306 cur_cd->command, COMP_CMD_STOP);
1307 list_del(&cur_cd->cancel_cmd_list);
1317 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1318 * trb pointed by the command ring dequeue pointer is the trb we want to
1319 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1320 * traverse the cancel_cmd_list to trun the all of the commands according
1321 * to command descriptor to NO-OP trb.
1323 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1324 int cmd_trb_comp_code)
1326 int cur_trb_is_good = 0;
1328 /* Searching the cmd trb pointed by the command ring dequeue
1329 * pointer in command descriptor list. If it is found, free it.
1331 cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1332 xhci->cmd_ring->dequeue);
1334 if (cmd_trb_comp_code == COMP_CMD_ABORT)
1335 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1336 else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1337 /* traversing the cancel_cmd_list and canceling
1338 * the command according to command descriptor
1340 xhci_cancel_cmd_in_cd_list(xhci);
1342 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1344 * ring command ring doorbell again to restart the
1347 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1348 xhci_ring_cmd_db(xhci);
1350 return cur_trb_is_good;
1353 static void handle_cmd_completion(struct xhci_hcd *xhci,
1354 struct xhci_event_cmd *event)
1356 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1358 dma_addr_t cmd_dequeue_dma;
1359 struct xhci_input_control_ctx *ctrl_ctx;
1360 struct xhci_virt_device *virt_dev;
1361 unsigned int ep_index;
1362 struct xhci_ring *ep_ring;
1363 unsigned int ep_state;
1365 cmd_dma = le64_to_cpu(event->cmd_trb);
1366 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1367 xhci->cmd_ring->dequeue);
1368 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1369 if (cmd_dequeue_dma == 0) {
1370 xhci->error_bitmask |= 1 << 4;
1373 /* Does the DMA address match our internal dequeue pointer address? */
1374 if (cmd_dma != (u64) cmd_dequeue_dma) {
1375 xhci->error_bitmask |= 1 << 5;
1379 if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1380 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1381 /* If the return value is 0, we think the trb pointed by
1382 * command ring dequeue pointer is a good trb. The good
1383 * trb means we don't want to cancel the trb, but it have
1384 * been stopped by host. So we should handle it normally.
1385 * Otherwise, driver should invoke inc_deq() and return.
1387 if (handle_stopped_cmd_ring(xhci,
1388 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1389 inc_deq(xhci, xhci->cmd_ring, false);
1394 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1395 & TRB_TYPE_BITMASK) {
1396 case TRB_TYPE(TRB_ENABLE_SLOT):
1397 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1398 xhci->slot_id = slot_id;
1401 complete(&xhci->addr_dev);
1403 case TRB_TYPE(TRB_DISABLE_SLOT):
1404 if (xhci->devs[slot_id]) {
1405 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1406 /* Delete default control endpoint resources */
1407 xhci_free_device_endpoint_resources(xhci,
1408 xhci->devs[slot_id], true);
1409 xhci_free_virt_device(xhci, slot_id);
1412 case TRB_TYPE(TRB_CONFIG_EP):
1413 virt_dev = xhci->devs[slot_id];
1414 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1417 * Configure endpoint commands can come from the USB core
1418 * configuration or alt setting changes, or because the HW
1419 * needed an extra configure endpoint command after a reset
1420 * endpoint command or streams were being configured.
1421 * If the command was for a halted endpoint, the xHCI driver
1422 * is not waiting on the configure endpoint command.
1424 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1426 /* Input ctx add_flags are the endpoint index plus one */
1427 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1428 /* A usb_set_interface() call directly after clearing a halted
1429 * condition may race on this quirky hardware. Not worth
1430 * worrying about, since this is prototype hardware. Not sure
1431 * if this will work for streams, but streams support was
1432 * untested on this prototype.
1434 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1435 ep_index != (unsigned int) -1 &&
1436 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1437 le32_to_cpu(ctrl_ctx->drop_flags)) {
1438 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1439 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1440 if (!(ep_state & EP_HALTED))
1441 goto bandwidth_change;
1442 xhci_dbg(xhci, "Completed config ep cmd - "
1443 "last ep index = %d, state = %d\n",
1444 ep_index, ep_state);
1445 /* Clear internal halted state and restart ring(s) */
1446 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1448 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1452 xhci_dbg(xhci, "Completed config ep cmd\n");
1453 xhci->devs[slot_id]->cmd_status =
1454 GET_COMP_CODE(le32_to_cpu(event->status));
1455 complete(&xhci->devs[slot_id]->cmd_completion);
1457 case TRB_TYPE(TRB_EVAL_CONTEXT):
1458 virt_dev = xhci->devs[slot_id];
1459 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1461 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1462 complete(&xhci->devs[slot_id]->cmd_completion);
1464 case TRB_TYPE(TRB_ADDR_DEV):
1465 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1466 complete(&xhci->addr_dev);
1468 case TRB_TYPE(TRB_STOP_RING):
1469 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1471 case TRB_TYPE(TRB_SET_DEQ):
1472 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1474 case TRB_TYPE(TRB_CMD_NOOP):
1476 case TRB_TYPE(TRB_RESET_EP):
1477 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1479 case TRB_TYPE(TRB_RESET_DEV):
1480 xhci_dbg(xhci, "Completed reset device command.\n");
1481 slot_id = TRB_TO_SLOT_ID(
1482 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1483 virt_dev = xhci->devs[slot_id];
1485 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1487 xhci_warn(xhci, "Reset device command completion "
1488 "for disabled slot %u\n", slot_id);
1490 case TRB_TYPE(TRB_NEC_GET_FW):
1491 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1492 xhci->error_bitmask |= 1 << 6;
1495 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1496 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1497 NEC_FW_MINOR(le32_to_cpu(event->status)));
1500 /* Skip over unknown commands on the event ring */
1501 xhci->error_bitmask |= 1 << 6;
1504 inc_deq(xhci, xhci->cmd_ring, false);
1507 static void handle_vendor_event(struct xhci_hcd *xhci,
1508 union xhci_trb *event)
1512 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1513 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1514 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1515 handle_cmd_completion(xhci, &event->event_cmd);
1518 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1519 * port registers -- USB 3.0 and USB 2.0).
1521 * Returns a zero-based port number, which is suitable for indexing into each of
1522 * the split roothubs' port arrays and bus state arrays.
1523 * Add one to it in order to call xhci_find_slot_id_by_port.
1525 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1526 struct xhci_hcd *xhci, u32 port_id)
1529 unsigned int num_similar_speed_ports = 0;
1531 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1532 * and usb2_ports are 0-based indexes. Count the number of similar
1533 * speed ports, up to 1 port before this port.
1535 for (i = 0; i < (port_id - 1); i++) {
1536 u8 port_speed = xhci->port_array[i];
1539 * Skip ports that don't have known speeds, or have duplicate
1540 * Extended Capabilities port speed entries.
1542 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1546 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1547 * 1.1 ports are under the USB 2.0 hub. If the port speed
1548 * matches the device speed, it's a similar speed port.
1550 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1551 num_similar_speed_ports++;
1553 return num_similar_speed_ports;
1556 static void handle_port_status(struct xhci_hcd *xhci,
1557 union xhci_trb *event)
1559 struct usb_hcd *hcd;
1564 unsigned int faked_port_index;
1566 struct xhci_bus_state *bus_state;
1567 __le32 __iomem **port_array;
1568 bool bogus_port_status = false;
1570 /* Port status change events always have a successful completion code */
1571 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1572 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1573 xhci->error_bitmask |= 1 << 8;
1575 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1576 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1578 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1579 if ((port_id <= 0) || (port_id > max_ports)) {
1580 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1581 bogus_port_status = true;
1585 /* Figure out which usb_hcd this port is attached to:
1586 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1588 major_revision = xhci->port_array[port_id - 1];
1589 if (major_revision == 0) {
1590 xhci_warn(xhci, "Event for port %u not in "
1591 "Extended Capabilities, ignoring.\n",
1593 bogus_port_status = true;
1596 if (major_revision == DUPLICATE_ENTRY) {
1597 xhci_warn(xhci, "Event for port %u duplicated in"
1598 "Extended Capabilities, ignoring.\n",
1600 bogus_port_status = true;
1605 * Hardware port IDs reported by a Port Status Change Event include USB
1606 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1607 * resume event, but we first need to translate the hardware port ID
1608 * into the index into the ports on the correct split roothub, and the
1609 * correct bus_state structure.
1611 /* Find the right roothub. */
1612 hcd = xhci_to_hcd(xhci);
1613 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1614 hcd = xhci->shared_hcd;
1615 bus_state = &xhci->bus_state[hcd_index(hcd)];
1616 if (hcd->speed == HCD_USB3)
1617 port_array = xhci->usb3_ports;
1619 port_array = xhci->usb2_ports;
1620 /* Find the faked port hub number */
1621 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1624 temp = xhci_readl(xhci, port_array[faked_port_index]);
1625 if (hcd->state == HC_STATE_SUSPENDED) {
1626 xhci_dbg(xhci, "resume root hub\n");
1627 usb_hcd_resume_root_hub(hcd);
1630 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1631 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1633 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1634 if (!(temp1 & CMD_RUN)) {
1635 xhci_warn(xhci, "xHC is not running.\n");
1639 if (DEV_SUPERSPEED(temp)) {
1640 xhci_dbg(xhci, "resume SS port %d\n", port_id);
1641 xhci_set_link_state(xhci, port_array, faked_port_index,
1643 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1644 faked_port_index + 1);
1646 xhci_dbg(xhci, "slot_id is zero\n");
1649 xhci_ring_device(xhci, slot_id);
1650 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1651 /* Clear PORT_PLC */
1652 xhci_test_and_clear_bit(xhci, port_array,
1653 faked_port_index, PORT_PLC);
1655 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1656 bus_state->resume_done[faked_port_index] = jiffies +
1657 msecs_to_jiffies(20);
1658 mod_timer(&hcd->rh_timer,
1659 bus_state->resume_done[faked_port_index]);
1660 /* Do the rest in GetPortStatus */
1664 if (hcd->speed != HCD_USB3)
1665 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1669 /* Update event ring dequeue pointer before dropping the lock */
1670 inc_deq(xhci, xhci->event_ring, true);
1672 /* Don't make the USB core poll the roothub if we got a bad port status
1673 * change event. Besides, at that point we can't tell which roothub
1674 * (USB 2.0 or USB 3.0) to kick.
1676 if (bogus_port_status)
1680 * xHCI port-status-change events occur when the "or" of all the
1681 * status-change bits in the portsc register changes from 0 to 1.
1682 * New status changes won't cause an event if any other change
1683 * bits are still set. When an event occurs, switch over to
1684 * polling to avoid losing status changes.
1686 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1687 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1688 spin_unlock(&xhci->lock);
1689 /* Pass this up to the core */
1690 usb_hcd_poll_rh_status(hcd);
1691 spin_lock(&xhci->lock);
1695 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1696 * at end_trb, which may be in another segment. If the suspect DMA address is a
1697 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1700 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1701 union xhci_trb *start_trb,
1702 union xhci_trb *end_trb,
1703 dma_addr_t suspect_dma)
1705 dma_addr_t start_dma;
1706 dma_addr_t end_seg_dma;
1707 dma_addr_t end_trb_dma;
1708 struct xhci_segment *cur_seg;
1710 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1711 cur_seg = start_seg;
1716 /* We may get an event for a Link TRB in the middle of a TD */
1717 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1718 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1719 /* If the end TRB isn't in this segment, this is set to 0 */
1720 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1722 if (end_trb_dma > 0) {
1723 /* The end TRB is in this segment, so suspect should be here */
1724 if (start_dma <= end_trb_dma) {
1725 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1728 /* Case for one segment with
1729 * a TD wrapped around to the top
1731 if ((suspect_dma >= start_dma &&
1732 suspect_dma <= end_seg_dma) ||
1733 (suspect_dma >= cur_seg->dma &&
1734 suspect_dma <= end_trb_dma))
1739 /* Might still be somewhere in this segment */
1740 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1743 cur_seg = cur_seg->next;
1744 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1745 } while (cur_seg != start_seg);
1750 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1751 unsigned int slot_id, unsigned int ep_index,
1752 unsigned int stream_id,
1753 struct xhci_td *td, union xhci_trb *event_trb)
1755 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1756 ep->ep_state |= EP_HALTED;
1757 ep->stopped_td = td;
1758 ep->stopped_stream = stream_id;
1760 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1761 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1763 ep->stopped_td = NULL;
1764 ep->stopped_stream = 0;
1766 xhci_ring_cmd_db(xhci);
1769 /* Check if an error has halted the endpoint ring. The class driver will
1770 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1771 * However, a babble and other errors also halt the endpoint ring, and the class
1772 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1773 * Ring Dequeue Pointer command manually.
1775 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1776 struct xhci_ep_ctx *ep_ctx,
1777 unsigned int trb_comp_code)
1779 /* TRB completion codes that may require a manual halt cleanup */
1780 if (trb_comp_code == COMP_TX_ERR ||
1781 trb_comp_code == COMP_BABBLE ||
1782 trb_comp_code == COMP_SPLIT_ERR)
1783 /* The 0.96 spec says a babbling control endpoint
1784 * is not halted. The 0.96 spec says it is. Some HW
1785 * claims to be 0.95 compliant, but it halts the control
1786 * endpoint anyway. Check if a babble halted the
1789 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1790 cpu_to_le32(EP_STATE_HALTED))
1796 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1798 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1799 /* Vendor defined "informational" completion code,
1800 * treat as not-an-error.
1802 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1804 xhci_dbg(xhci, "Treating code as success.\n");
1811 * Finish the td processing, remove the td from td list;
1812 * Return 1 if the urb can be given back.
1814 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1815 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1816 struct xhci_virt_ep *ep, int *status, bool skip)
1818 struct xhci_virt_device *xdev;
1819 struct xhci_ring *ep_ring;
1820 unsigned int slot_id;
1822 struct urb *urb = NULL;
1823 struct xhci_ep_ctx *ep_ctx;
1825 struct urb_priv *urb_priv;
1828 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1829 xdev = xhci->devs[slot_id];
1830 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1831 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1832 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1833 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1838 if (trb_comp_code == COMP_STOP_INVAL ||
1839 trb_comp_code == COMP_STOP) {
1840 /* The Endpoint Stop Command completion will take care of any
1841 * stopped TDs. A stopped TD may be restarted, so don't update
1842 * the ring dequeue pointer or take this TD off any lists yet.
1844 ep->stopped_td = td;
1847 if (trb_comp_code == COMP_STALL ||
1848 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1850 /* Issue a reset endpoint command to clear the host side
1851 * halt, followed by a set dequeue command to move the
1852 * dequeue pointer past the TD.
1853 * The class driver clears the device side halt later.
1855 xhci_cleanup_halted_endpoint(xhci,
1856 slot_id, ep_index, ep_ring->stream_id,
1859 /* Update ring dequeue pointer */
1860 while (ep_ring->dequeue != td->last_trb)
1861 inc_deq(xhci, ep_ring, false);
1862 inc_deq(xhci, ep_ring, false);
1866 /* Clean up the endpoint's TD list */
1868 urb_priv = urb->hcpriv;
1870 /* Do one last check of the actual transfer length.
1871 * If the host controller said we transferred more data than
1872 * the buffer length, urb->actual_length will be a very big
1873 * number (since it's unsigned). Play it safe and say we didn't
1874 * transfer anything.
1876 if (urb->actual_length > urb->transfer_buffer_length) {
1877 xhci_warn(xhci, "URB transfer length is wrong, "
1878 "xHC issue? req. len = %u, "
1880 urb->transfer_buffer_length,
1881 urb->actual_length);
1882 urb->actual_length = 0;
1883 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1884 *status = -EREMOTEIO;
1888 list_del_init(&td->td_list);
1889 /* Was this TD slated to be cancelled but completed anyway? */
1890 if (!list_empty(&td->cancelled_td_list))
1891 list_del_init(&td->cancelled_td_list);
1894 /* Giveback the urb when all the tds are completed */
1895 if (urb_priv->td_cnt == urb_priv->length) {
1897 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1898 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1899 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1901 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1902 usb_amd_quirk_pll_enable();
1912 * Process control tds, update urb status and actual_length.
1914 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1915 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1916 struct xhci_virt_ep *ep, int *status)
1918 struct xhci_virt_device *xdev;
1919 struct xhci_ring *ep_ring;
1920 unsigned int slot_id;
1922 struct xhci_ep_ctx *ep_ctx;
1925 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1926 xdev = xhci->devs[slot_id];
1927 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1928 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1929 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1930 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1932 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1933 switch (trb_comp_code) {
1935 if (event_trb == ep_ring->dequeue) {
1936 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1937 "without IOC set??\n");
1938 *status = -ESHUTDOWN;
1939 } else if (event_trb != td->last_trb) {
1940 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1941 "without IOC set??\n");
1942 *status = -ESHUTDOWN;
1948 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1949 *status = -EREMOTEIO;
1953 case COMP_STOP_INVAL:
1955 return finish_td(xhci, td, event_trb, event, ep, status, false);
1957 if (!xhci_requires_manual_halt_cleanup(xhci,
1958 ep_ctx, trb_comp_code))
1960 xhci_dbg(xhci, "TRB error code %u, "
1961 "halted endpoint index = %u\n",
1962 trb_comp_code, ep_index);
1963 /* else fall through */
1965 /* Did we transfer part of the data (middle) phase? */
1966 if (event_trb != ep_ring->dequeue &&
1967 event_trb != td->last_trb)
1968 td->urb->actual_length =
1969 td->urb->transfer_buffer_length -
1970 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1972 td->urb->actual_length = 0;
1974 return finish_td(xhci, td, event_trb, event, ep, status, false);
1977 * Did we transfer any data, despite the errors that might have
1978 * happened? I.e. did we get past the setup stage?
1980 if (event_trb != ep_ring->dequeue) {
1981 /* The event was for the status stage */
1982 if (event_trb == td->last_trb) {
1983 if (td->urb_length_set) {
1984 /* Don't overwrite a previously set error code
1986 if ((*status == -EINPROGRESS || *status == 0) &&
1987 (td->urb->transfer_flags
1988 & URB_SHORT_NOT_OK))
1989 /* Did we already see a short data
1991 *status = -EREMOTEIO;
1993 td->urb->actual_length =
1994 td->urb->transfer_buffer_length;
1998 * Maybe the event was for the data stage? If so, update
1999 * already the actual_length of the URB and flag it as
2000 * set, so that it is not overwritten in the event for
2003 td->urb_length_set = true;
2004 td->urb->actual_length =
2005 td->urb->transfer_buffer_length -
2006 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2007 xhci_dbg(xhci, "Waiting for status "
2013 return finish_td(xhci, td, event_trb, event, ep, status, false);
2017 * Process isochronous tds, update urb packet status and actual_length.
2019 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2020 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2021 struct xhci_virt_ep *ep, int *status)
2023 struct xhci_ring *ep_ring;
2024 struct urb_priv *urb_priv;
2027 union xhci_trb *cur_trb;
2028 struct xhci_segment *cur_seg;
2029 struct usb_iso_packet_descriptor *frame;
2031 bool skip_td = false;
2033 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2034 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2035 urb_priv = td->urb->hcpriv;
2036 idx = urb_priv->td_cnt;
2037 frame = &td->urb->iso_frame_desc[idx];
2039 /* handle completion code */
2040 switch (trb_comp_code) {
2042 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2046 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2047 trb_comp_code = COMP_SHORT_TX;
2049 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2053 frame->status = -ECOMM;
2056 case COMP_BUFF_OVER:
2058 frame->status = -EOVERFLOW;
2063 frame->status = -EPROTO;
2067 frame->status = -EPROTO;
2068 if (event_trb != td->last_trb)
2073 case COMP_STOP_INVAL:
2080 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2081 frame->actual_length = frame->length;
2082 td->urb->actual_length += frame->length;
2084 for (cur_trb = ep_ring->dequeue,
2085 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2086 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2087 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2088 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2089 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2091 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2092 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2094 if (trb_comp_code != COMP_STOP_INVAL) {
2095 frame->actual_length = len;
2096 td->urb->actual_length += len;
2100 return finish_td(xhci, td, event_trb, event, ep, status, false);
2103 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2104 struct xhci_transfer_event *event,
2105 struct xhci_virt_ep *ep, int *status)
2107 struct xhci_ring *ep_ring;
2108 struct urb_priv *urb_priv;
2109 struct usb_iso_packet_descriptor *frame;
2112 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2113 urb_priv = td->urb->hcpriv;
2114 idx = urb_priv->td_cnt;
2115 frame = &td->urb->iso_frame_desc[idx];
2117 /* The transfer is partly done. */
2118 frame->status = -EXDEV;
2120 /* calc actual length */
2121 frame->actual_length = 0;
2123 /* Update ring dequeue pointer */
2124 while (ep_ring->dequeue != td->last_trb)
2125 inc_deq(xhci, ep_ring, false);
2126 inc_deq(xhci, ep_ring, false);
2128 return finish_td(xhci, td, NULL, event, ep, status, true);
2132 * Process bulk and interrupt tds, update urb status and actual_length.
2134 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2135 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2136 struct xhci_virt_ep *ep, int *status)
2138 struct xhci_ring *ep_ring;
2139 union xhci_trb *cur_trb;
2140 struct xhci_segment *cur_seg;
2143 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2144 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2146 switch (trb_comp_code) {
2148 /* Double check that the HW transferred everything. */
2149 if (event_trb != td->last_trb ||
2150 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2151 xhci_warn(xhci, "WARN Successful completion "
2153 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2154 *status = -EREMOTEIO;
2157 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2158 trb_comp_code = COMP_SHORT_TX;
2164 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2165 *status = -EREMOTEIO;
2170 /* Others already handled above */
2173 if (trb_comp_code == COMP_SHORT_TX)
2174 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2175 "%d bytes untransferred\n",
2176 td->urb->ep->desc.bEndpointAddress,
2177 td->urb->transfer_buffer_length,
2178 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2179 /* Fast path - was this the last TRB in the TD for this URB? */
2180 if (event_trb == td->last_trb) {
2181 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2182 td->urb->actual_length =
2183 td->urb->transfer_buffer_length -
2184 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2185 if (td->urb->transfer_buffer_length <
2186 td->urb->actual_length) {
2187 xhci_warn(xhci, "HC gave bad length "
2188 "of %d bytes left\n",
2189 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2190 td->urb->actual_length = 0;
2191 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2192 *status = -EREMOTEIO;
2196 /* Don't overwrite a previously set error code */
2197 if (*status == -EINPROGRESS) {
2198 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2199 *status = -EREMOTEIO;
2204 td->urb->actual_length =
2205 td->urb->transfer_buffer_length;
2206 /* Ignore a short packet completion if the
2207 * untransferred length was zero.
2209 if (*status == -EREMOTEIO)
2213 /* Slow path - walk the list, starting from the dequeue
2214 * pointer, to get the actual length transferred.
2216 td->urb->actual_length = 0;
2217 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2218 cur_trb != event_trb;
2219 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2220 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2221 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2222 td->urb->actual_length +=
2223 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2225 /* If the ring didn't stop on a Link or No-op TRB, add
2226 * in the actual bytes transferred from the Normal TRB
2228 if (trb_comp_code != COMP_STOP_INVAL)
2229 td->urb->actual_length +=
2230 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2231 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2234 return finish_td(xhci, td, event_trb, event, ep, status, false);
2238 * If this function returns an error condition, it means it got a Transfer
2239 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2240 * At this point, the host controller is probably hosed and should be reset.
2242 static int handle_tx_event(struct xhci_hcd *xhci,
2243 struct xhci_transfer_event *event)
2245 struct xhci_virt_device *xdev;
2246 struct xhci_virt_ep *ep;
2247 struct xhci_ring *ep_ring;
2248 unsigned int slot_id;
2250 struct xhci_td *td = NULL;
2251 dma_addr_t event_dma;
2252 struct xhci_segment *event_seg;
2253 union xhci_trb *event_trb;
2254 struct urb *urb = NULL;
2255 int status = -EINPROGRESS;
2256 struct urb_priv *urb_priv;
2257 struct xhci_ep_ctx *ep_ctx;
2258 struct list_head *tmp;
2263 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2264 xdev = xhci->devs[slot_id];
2266 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2270 /* Endpoint ID is 1 based, our index is zero based */
2271 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2272 ep = &xdev->eps[ep_index];
2273 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2274 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2276 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2277 EP_STATE_DISABLED) {
2278 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2279 "or incorrect stream ring\n");
2283 /* Count current td numbers if ep->skip is set */
2285 list_for_each(tmp, &ep_ring->td_list)
2289 event_dma = le64_to_cpu(event->buffer);
2290 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2291 /* Look for common error cases */
2292 switch (trb_comp_code) {
2293 /* Skip codes that require special handling depending on
2297 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2299 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2300 trb_comp_code = COMP_SHORT_TX;
2302 xhci_warn(xhci, "WARN Successful completion on short TX: "
2303 "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2307 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2309 case COMP_STOP_INVAL:
2310 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2313 xhci_dbg(xhci, "Stalled endpoint\n");
2314 ep->ep_state |= EP_HALTED;
2318 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2321 case COMP_SPLIT_ERR:
2323 xhci_dbg(xhci, "Transfer error on endpoint\n");
2327 xhci_dbg(xhci, "Babble error on endpoint\n");
2328 status = -EOVERFLOW;
2331 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2335 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2337 case COMP_BUFF_OVER:
2338 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2342 * When the Isoch ring is empty, the xHC will generate
2343 * a Ring Overrun Event for IN Isoch endpoint or Ring
2344 * Underrun Event for OUT Isoch endpoint.
2346 xhci_dbg(xhci, "underrun event on endpoint\n");
2347 if (!list_empty(&ep_ring->td_list))
2348 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2349 "still with TDs queued?\n",
2350 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2354 xhci_dbg(xhci, "overrun event on endpoint\n");
2355 if (!list_empty(&ep_ring->td_list))
2356 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2357 "still with TDs queued?\n",
2358 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2362 xhci_warn(xhci, "WARN: detect an incompatible device");
2365 case COMP_MISSED_INT:
2367 * When encounter missed service error, one or more isoc tds
2368 * may be missed by xHC.
2369 * Set skip flag of the ep_ring; Complete the missed tds as
2370 * short transfer when process the ep_ring next time.
2373 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2376 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2380 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2386 /* This TRB should be in the TD at the head of this ring's
2389 if (list_empty(&ep_ring->td_list)) {
2391 * A stopped endpoint may generate an extra completion
2392 * event if the device was suspended. Don't print
2395 if (!(trb_comp_code == COMP_STOP ||
2396 trb_comp_code == COMP_STOP_INVAL)) {
2397 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2398 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2400 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2401 (le32_to_cpu(event->flags) &
2402 TRB_TYPE_BITMASK)>>10);
2403 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2407 xhci_dbg(xhci, "td_list is empty while skip "
2408 "flag set. Clear skip flag.\n");
2414 /* We've skipped all the TDs on the ep ring when ep->skip set */
2415 if (ep->skip && td_num == 0) {
2417 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2418 "Clear skip flag.\n");
2423 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2427 /* Is this a TRB in the currently executing TD? */
2428 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2429 td->last_trb, event_dma);
2432 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2433 * is not in the current TD pointed by ep_ring->dequeue because
2434 * that the hardware dequeue pointer still at the previous TRB
2435 * of the current TD. The previous TRB maybe a Link TD or the
2436 * last TRB of the previous TD. The command completion handle
2437 * will take care the rest.
2439 if (!event_seg && (trb_comp_code == COMP_STOP ||
2440 trb_comp_code == COMP_STOP_INVAL)) {
2447 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2448 /* Some host controllers give a spurious
2449 * successful event after a short transfer.
2452 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2453 ep_ring->last_td_was_short) {
2454 ep_ring->last_td_was_short = false;
2458 /* HC is busted, give up! */
2460 "ERROR Transfer event TRB DMA ptr not "
2461 "part of current TD\n");
2465 ret = skip_isoc_td(xhci, td, event, ep, &status);
2468 if (trb_comp_code == COMP_SHORT_TX)
2469 ep_ring->last_td_was_short = true;
2471 ep_ring->last_td_was_short = false;
2474 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2478 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2479 sizeof(*event_trb)];
2481 * No-op TRB should not trigger interrupts.
2482 * If event_trb is a no-op TRB, it means the
2483 * corresponding TD has been cancelled. Just ignore
2486 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2488 "event_trb is a no-op TRB. Skip it\n");
2492 /* Now update the urb's actual_length and give back to
2495 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2496 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2498 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2499 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2502 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2507 * Do not update event ring dequeue pointer if ep->skip is set.
2508 * Will roll back to continue process missed tds.
2510 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2511 inc_deq(xhci, xhci->event_ring, true);
2516 urb_priv = urb->hcpriv;
2518 xhci_urb_free_priv(xhci, urb_priv);
2520 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2521 if ((urb->actual_length != urb->transfer_buffer_length &&
2522 (urb->transfer_flags &
2523 URB_SHORT_NOT_OK)) ||
2525 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2526 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2527 "expected = %x, status = %d\n",
2528 urb, urb->actual_length,
2529 urb->transfer_buffer_length,
2531 spin_unlock(&xhci->lock);
2532 /* EHCI, UHCI, and OHCI always unconditionally set the
2533 * urb->status of an isochronous endpoint to 0.
2535 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2537 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2538 spin_lock(&xhci->lock);
2542 * If ep->skip is set, it means there are missed tds on the
2543 * endpoint ring need to take care of.
2544 * Process them as short transfer until reach the td pointed by
2547 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2553 * This function handles all OS-owned events on the event ring. It may drop
2554 * xhci->lock between event processing (e.g. to pass up port status changes).
2555 * Returns >0 for "possibly more events to process" (caller should call again),
2556 * otherwise 0 if done. In future, <0 returns should indicate error code.
2558 static int xhci_handle_event(struct xhci_hcd *xhci)
2560 union xhci_trb *event;
2561 int update_ptrs = 1;
2564 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2565 xhci->error_bitmask |= 1 << 1;
2569 event = xhci->event_ring->dequeue;
2570 /* Does the HC or OS own the TRB? */
2571 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2572 xhci->event_ring->cycle_state) {
2573 xhci->error_bitmask |= 1 << 2;
2578 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2579 * speculative reads of the event's flags/data below.
2582 /* FIXME: Handle more event types. */
2583 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2584 case TRB_TYPE(TRB_COMPLETION):
2585 handle_cmd_completion(xhci, &event->event_cmd);
2587 case TRB_TYPE(TRB_PORT_STATUS):
2588 handle_port_status(xhci, event);
2591 case TRB_TYPE(TRB_TRANSFER):
2592 ret = handle_tx_event(xhci, &event->trans_event);
2594 xhci->error_bitmask |= 1 << 9;
2599 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2601 handle_vendor_event(xhci, event);
2603 xhci->error_bitmask |= 1 << 3;
2605 /* Any of the above functions may drop and re-acquire the lock, so check
2606 * to make sure a watchdog timer didn't mark the host as non-responsive.
2608 if (xhci->xhc_state & XHCI_STATE_DYING) {
2609 xhci_dbg(xhci, "xHCI host dying, returning from "
2610 "event handler.\n");
2615 /* Update SW event ring dequeue pointer */
2616 inc_deq(xhci, xhci->event_ring, true);
2618 /* Are there more items on the event ring? Caller will call us again to
2625 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2626 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2627 * indicators of an event TRB error, but we check the status *first* to be safe.
2629 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2631 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2633 union xhci_trb *trb;
2635 union xhci_trb *event_ring_deq;
2638 spin_lock(&xhci->lock);
2639 trb = xhci->event_ring->dequeue;
2640 /* Check if the xHC generated the interrupt, or the irq is shared */
2641 status = xhci_readl(xhci, &xhci->op_regs->status);
2642 if (status == 0xffffffff)
2645 if (!(status & STS_EINT)) {
2646 spin_unlock(&xhci->lock);
2649 if (status & STS_FATAL) {
2650 xhci_warn(xhci, "WARNING: Host System Error\n");
2653 spin_unlock(&xhci->lock);
2658 * Clear the op reg interrupt status first,
2659 * so we can receive interrupts from other MSI-X interrupters.
2660 * Write 1 to clear the interrupt status.
2663 xhci_writel(xhci, status, &xhci->op_regs->status);
2664 /* FIXME when MSI-X is supported and there are multiple vectors */
2665 /* Clear the MSI-X event interrupt status */
2667 if (hcd->irq != -1) {
2669 /* Acknowledge the PCI interrupt */
2670 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2671 irq_pending |= IMAN_IP;
2672 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2675 if (xhci->xhc_state & XHCI_STATE_DYING) {
2676 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2677 "Shouldn't IRQs be disabled?\n");
2678 /* Clear the event handler busy flag (RW1C);
2679 * the event ring should be empty.
2681 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2682 xhci_write_64(xhci, temp_64 | ERST_EHB,
2683 &xhci->ir_set->erst_dequeue);
2684 spin_unlock(&xhci->lock);
2689 event_ring_deq = xhci->event_ring->dequeue;
2690 /* FIXME this should be a delayed service routine
2691 * that clears the EHB.
2693 while (xhci_handle_event(xhci) > 0) {}
2695 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2696 /* If necessary, update the HW's version of the event ring deq ptr. */
2697 if (event_ring_deq != xhci->event_ring->dequeue) {
2698 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2699 xhci->event_ring->dequeue);
2701 xhci_warn(xhci, "WARN something wrong with SW event "
2702 "ring dequeue ptr.\n");
2703 /* Update HC event ring dequeue pointer */
2704 temp_64 &= ERST_PTR_MASK;
2705 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2708 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2709 temp_64 |= ERST_EHB;
2710 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2712 spin_unlock(&xhci->lock);
2717 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2720 struct xhci_hcd *xhci;
2722 xhci = hcd_to_xhci(hcd);
2723 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2724 if (xhci->shared_hcd)
2725 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2727 ret = xhci_irq(hcd);
2732 /**** Endpoint Ring Operations ****/
2735 * Generic function for queueing a TRB on a ring.
2736 * The caller must have checked to make sure there's room on the ring.
2738 * @more_trbs_coming: Will you enqueue more TRBs before calling
2739 * prepare_transfer()?
2741 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2742 bool consumer, bool more_trbs_coming, bool isoc,
2743 u32 field1, u32 field2, u32 field3, u32 field4)
2745 struct xhci_generic_trb *trb;
2747 trb = &ring->enqueue->generic;
2748 trb->field[0] = cpu_to_le32(field1);
2749 trb->field[1] = cpu_to_le32(field2);
2750 trb->field[2] = cpu_to_le32(field3);
2751 trb->field[3] = cpu_to_le32(field4);
2752 inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2756 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2757 * FIXME allocate segments if the ring is full.
2759 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2760 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2762 /* Make sure the endpoint has been added to xHC schedule */
2764 case EP_STATE_DISABLED:
2766 * USB core changed config/interfaces without notifying us,
2767 * or hardware is reporting the wrong state.
2769 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2771 case EP_STATE_ERROR:
2772 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2773 /* FIXME event handling code for error needs to clear it */
2774 /* XXX not sure if this should be -ENOENT or not */
2776 case EP_STATE_HALTED:
2777 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2778 case EP_STATE_STOPPED:
2779 case EP_STATE_RUNNING:
2782 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2784 * FIXME issue Configure Endpoint command to try to get the HC
2785 * back into a known state.
2789 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2790 /* FIXME allocate more room */
2791 xhci_err(xhci, "ERROR no room on ep ring\n");
2795 if (enqueue_is_link_trb(ep_ring)) {
2796 struct xhci_ring *ring = ep_ring;
2797 union xhci_trb *next;
2799 next = ring->enqueue;
2801 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2802 /* If we're not dealing with 0.95 hardware or isoc rings
2803 * on AMD 0.96 host, clear the chain bit.
2805 if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2806 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2807 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2809 next->link.control |= cpu_to_le32(TRB_CHAIN);
2812 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2814 /* Toggle the cycle bit after the last ring segment. */
2815 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2816 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2817 if (!in_interrupt()) {
2818 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2819 "state for ring %p = %i\n",
2820 ring, (unsigned int)ring->cycle_state);
2823 ring->enq_seg = ring->enq_seg->next;
2824 ring->enqueue = ring->enq_seg->trbs;
2825 next = ring->enqueue;
2832 static int prepare_transfer(struct xhci_hcd *xhci,
2833 struct xhci_virt_device *xdev,
2834 unsigned int ep_index,
2835 unsigned int stream_id,
2836 unsigned int num_trbs,
2838 unsigned int td_index,
2843 struct urb_priv *urb_priv;
2845 struct xhci_ring *ep_ring;
2846 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2848 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2850 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2855 ret = prepare_ring(xhci, ep_ring,
2856 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2857 num_trbs, isoc, mem_flags);
2861 urb_priv = urb->hcpriv;
2862 td = urb_priv->td[td_index];
2864 INIT_LIST_HEAD(&td->td_list);
2865 INIT_LIST_HEAD(&td->cancelled_td_list);
2867 if (td_index == 0) {
2868 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2874 /* Add this TD to the tail of the endpoint ring's TD list */
2875 list_add_tail(&td->td_list, &ep_ring->td_list);
2876 td->start_seg = ep_ring->enq_seg;
2877 td->first_trb = ep_ring->enqueue;
2879 urb_priv->td[td_index] = td;
2884 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2886 int num_sgs, num_trbs, running_total, temp, i;
2887 struct scatterlist *sg;
2890 num_sgs = urb->num_mapped_sgs;
2891 temp = urb->transfer_buffer_length;
2893 xhci_dbg(xhci, "count sg list trbs: \n");
2895 for_each_sg(urb->sg, sg, num_sgs, i) {
2896 unsigned int previous_total_trbs = num_trbs;
2897 unsigned int len = sg_dma_len(sg);
2899 /* Scatter gather list entries may cross 64KB boundaries */
2900 running_total = TRB_MAX_BUFF_SIZE -
2901 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2902 running_total &= TRB_MAX_BUFF_SIZE - 1;
2903 if (running_total != 0)
2906 /* How many more 64KB chunks to transfer, how many more TRBs? */
2907 while (running_total < sg_dma_len(sg) && running_total < temp) {
2909 running_total += TRB_MAX_BUFF_SIZE;
2911 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2912 i, (unsigned long long)sg_dma_address(sg),
2913 len, len, num_trbs - previous_total_trbs);
2915 len = min_t(int, len, temp);
2920 xhci_dbg(xhci, "\n");
2921 if (!in_interrupt())
2922 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2924 urb->ep->desc.bEndpointAddress,
2925 urb->transfer_buffer_length,
2930 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2933 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2934 "TRBs, %d left\n", __func__,
2935 urb->ep->desc.bEndpointAddress, num_trbs);
2936 if (running_total != urb->transfer_buffer_length)
2937 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2938 "queued %#x (%d), asked for %#x (%d)\n",
2940 urb->ep->desc.bEndpointAddress,
2941 running_total, running_total,
2942 urb->transfer_buffer_length,
2943 urb->transfer_buffer_length);
2946 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2947 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2948 struct xhci_generic_trb *start_trb)
2951 * Pass all the TRBs to the hardware at once and make sure this write
2956 start_trb->field[3] |= cpu_to_le32(start_cycle);
2958 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2959 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2963 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2964 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2965 * (comprised of sg list entries) can take several service intervals to
2968 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2969 struct urb *urb, int slot_id, unsigned int ep_index)
2971 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2972 xhci->devs[slot_id]->out_ctx, ep_index);
2976 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2977 ep_interval = urb->interval;
2978 /* Convert to microframes */
2979 if (urb->dev->speed == USB_SPEED_LOW ||
2980 urb->dev->speed == USB_SPEED_FULL)
2982 /* FIXME change this to a warning and a suggestion to use the new API
2983 * to set the polling interval (once the API is added).
2985 if (xhci_interval != ep_interval) {
2986 if (printk_ratelimit())
2987 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2988 " (%d microframe%s) than xHCI "
2989 "(%d microframe%s)\n",
2991 ep_interval == 1 ? "" : "s",
2993 xhci_interval == 1 ? "" : "s");
2994 urb->interval = xhci_interval;
2995 /* Convert back to frames for LS/FS devices */
2996 if (urb->dev->speed == USB_SPEED_LOW ||
2997 urb->dev->speed == USB_SPEED_FULL)
3000 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3004 * The TD size is the number of bytes remaining in the TD (including this TRB),
3005 * right shifted by 10.
3006 * It must fit in bits 21:17, so it can't be bigger than 31.
3008 static u32 xhci_td_remainder(unsigned int remainder)
3010 u32 max = (1 << (21 - 17 + 1)) - 1;
3012 if ((remainder >> 10) >= max)
3015 return (remainder >> 10) << 17;
3019 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3020 * packets remaining in the TD (*not* including this TRB).
3022 * Total TD packet count = total_packet_count =
3023 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3025 * Packets transferred up to and including this TRB = packets_transferred =
3026 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3028 * TD size = total_packet_count - packets_transferred
3030 * It must fit in bits 21:17, so it can't be bigger than 31.
3031 * The last TRB in a TD must have the TD size set to zero.
3033 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3034 unsigned int total_packet_count, struct urb *urb,
3035 unsigned int num_trbs_left)
3037 int packets_transferred;
3039 /* One TRB with a zero-length data packet. */
3040 if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3043 /* All the TRB queueing functions don't count the current TRB in
3046 packets_transferred = (running_total + trb_buff_len) /
3047 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3049 if ((total_packet_count - packets_transferred) > 31)
3051 return (total_packet_count - packets_transferred) << 17;
3054 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3055 struct urb *urb, int slot_id, unsigned int ep_index)
3057 struct xhci_ring *ep_ring;
3058 unsigned int num_trbs;
3059 struct urb_priv *urb_priv;
3061 struct scatterlist *sg;
3063 int trb_buff_len, this_sg_len, running_total;
3064 unsigned int total_packet_count;
3067 bool more_trbs_coming;
3069 struct xhci_generic_trb *start_trb;
3072 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3076 num_trbs = count_sg_trbs_needed(xhci, urb);
3077 num_sgs = urb->num_mapped_sgs;
3078 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3079 usb_endpoint_maxp(&urb->ep->desc));
3081 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3082 ep_index, urb->stream_id,
3083 num_trbs, urb, 0, false, mem_flags);
3084 if (trb_buff_len < 0)
3085 return trb_buff_len;
3087 urb_priv = urb->hcpriv;
3088 td = urb_priv->td[0];
3091 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3092 * until we've finished creating all the other TRBs. The ring's cycle
3093 * state may change as we enqueue the other TRBs, so save it too.
3095 start_trb = &ep_ring->enqueue->generic;
3096 start_cycle = ep_ring->cycle_state;
3100 * How much data is in the first TRB?
3102 * There are three forces at work for TRB buffer pointers and lengths:
3103 * 1. We don't want to walk off the end of this sg-list entry buffer.
3104 * 2. The transfer length that the driver requested may be smaller than
3105 * the amount of memory allocated for this scatter-gather list.
3106 * 3. TRBs buffers can't cross 64KB boundaries.
3109 addr = (u64) sg_dma_address(sg);
3110 this_sg_len = sg_dma_len(sg);
3111 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3112 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3113 if (trb_buff_len > urb->transfer_buffer_length)
3114 trb_buff_len = urb->transfer_buffer_length;
3115 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
3119 /* Queue the first TRB, even if it's zero-length */
3122 u32 length_field = 0;
3125 /* Don't change the cycle bit of the first TRB until later */
3128 if (start_cycle == 0)
3131 field |= ep_ring->cycle_state;
3133 /* Chain all the TRBs together; clear the chain bit in the last
3134 * TRB to indicate it's the last TRB in the chain.
3139 /* FIXME - add check for ZERO_PACKET flag before this */
3140 td->last_trb = ep_ring->enqueue;
3144 /* Only set interrupt on short packet for IN endpoints */
3145 if (usb_urb_dir_in(urb))
3148 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
3149 "64KB boundary at %#x, end dma = %#x\n",
3150 (unsigned int) addr, trb_buff_len, trb_buff_len,
3151 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3152 (unsigned int) addr + trb_buff_len);
3153 if (TRB_MAX_BUFF_SIZE -
3154 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3155 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3156 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3157 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3158 (unsigned int) addr + trb_buff_len);
3161 /* Set the TRB length, TD size, and interrupter fields. */
3162 if (xhci->hci_version < 0x100) {
3163 remainder = xhci_td_remainder(
3164 urb->transfer_buffer_length -
3167 remainder = xhci_v1_0_td_remainder(running_total,
3168 trb_buff_len, total_packet_count, urb,
3171 length_field = TRB_LEN(trb_buff_len) |
3176 more_trbs_coming = true;
3178 more_trbs_coming = false;
3179 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3180 lower_32_bits(addr),
3181 upper_32_bits(addr),
3183 field | TRB_TYPE(TRB_NORMAL));
3185 running_total += trb_buff_len;
3187 /* Calculate length for next transfer --
3188 * Are we done queueing all the TRBs for this sg entry?
3190 this_sg_len -= trb_buff_len;
3191 if (this_sg_len == 0) {
3196 addr = (u64) sg_dma_address(sg);
3197 this_sg_len = sg_dma_len(sg);
3199 addr += trb_buff_len;
3202 trb_buff_len = TRB_MAX_BUFF_SIZE -
3203 (addr & (TRB_MAX_BUFF_SIZE - 1));
3204 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3205 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3207 urb->transfer_buffer_length - running_total;
3208 } while (running_total < urb->transfer_buffer_length);
3210 check_trb_math(urb, num_trbs, running_total);
3211 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3212 start_cycle, start_trb);
3216 /* This is very similar to what ehci-q.c qtd_fill() does */
3217 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3218 struct urb *urb, int slot_id, unsigned int ep_index)
3220 struct xhci_ring *ep_ring;
3221 struct urb_priv *urb_priv;
3224 struct xhci_generic_trb *start_trb;
3226 bool more_trbs_coming;
3228 u32 field, length_field;
3230 int running_total, trb_buff_len, ret;
3231 unsigned int total_packet_count;
3235 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3237 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3242 /* How much data is (potentially) left before the 64KB boundary? */
3243 running_total = TRB_MAX_BUFF_SIZE -
3244 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3245 running_total &= TRB_MAX_BUFF_SIZE - 1;
3247 /* If there's some data on this 64KB chunk, or we have to send a
3248 * zero-length transfer, we need at least one TRB
3250 if (running_total != 0 || urb->transfer_buffer_length == 0)
3252 /* How many more 64KB chunks to transfer, how many more TRBs? */
3253 while (running_total < urb->transfer_buffer_length) {
3255 running_total += TRB_MAX_BUFF_SIZE;
3257 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3259 if (!in_interrupt())
3260 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
3261 "addr = %#llx, num_trbs = %d\n",
3262 urb->ep->desc.bEndpointAddress,
3263 urb->transfer_buffer_length,
3264 urb->transfer_buffer_length,
3265 (unsigned long long)urb->transfer_dma,
3268 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3269 ep_index, urb->stream_id,
3270 num_trbs, urb, 0, false, mem_flags);
3274 urb_priv = urb->hcpriv;
3275 td = urb_priv->td[0];
3278 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3279 * until we've finished creating all the other TRBs. The ring's cycle
3280 * state may change as we enqueue the other TRBs, so save it too.
3282 start_trb = &ep_ring->enqueue->generic;
3283 start_cycle = ep_ring->cycle_state;
3286 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3287 usb_endpoint_maxp(&urb->ep->desc));
3288 /* How much data is in the first TRB? */
3289 addr = (u64) urb->transfer_dma;
3290 trb_buff_len = TRB_MAX_BUFF_SIZE -
3291 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3292 if (trb_buff_len > urb->transfer_buffer_length)
3293 trb_buff_len = urb->transfer_buffer_length;
3297 /* Queue the first TRB, even if it's zero-length */
3302 /* Don't change the cycle bit of the first TRB until later */
3305 if (start_cycle == 0)
3308 field |= ep_ring->cycle_state;
3310 /* Chain all the TRBs together; clear the chain bit in the last
3311 * TRB to indicate it's the last TRB in the chain.
3316 /* FIXME - add check for ZERO_PACKET flag before this */
3317 td->last_trb = ep_ring->enqueue;
3321 /* Only set interrupt on short packet for IN endpoints */
3322 if (usb_urb_dir_in(urb))
3325 /* Set the TRB length, TD size, and interrupter fields. */
3326 if (xhci->hci_version < 0x100) {
3327 remainder = xhci_td_remainder(
3328 urb->transfer_buffer_length -
3331 remainder = xhci_v1_0_td_remainder(running_total,
3332 trb_buff_len, total_packet_count, urb,
3335 length_field = TRB_LEN(trb_buff_len) |
3340 more_trbs_coming = true;
3342 more_trbs_coming = false;
3343 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3344 lower_32_bits(addr),
3345 upper_32_bits(addr),
3347 field | TRB_TYPE(TRB_NORMAL));
3349 running_total += trb_buff_len;
3351 /* Calculate length for next transfer */
3352 addr += trb_buff_len;
3353 trb_buff_len = urb->transfer_buffer_length - running_total;
3354 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3355 trb_buff_len = TRB_MAX_BUFF_SIZE;
3356 } while (running_total < urb->transfer_buffer_length);
3358 check_trb_math(urb, num_trbs, running_total);
3359 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3360 start_cycle, start_trb);
3364 /* Caller must have locked xhci->lock */
3365 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3366 struct urb *urb, int slot_id, unsigned int ep_index)
3368 struct xhci_ring *ep_ring;
3371 struct usb_ctrlrequest *setup;
3372 struct xhci_generic_trb *start_trb;
3374 u32 field, length_field;
3375 struct urb_priv *urb_priv;
3378 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3383 * Need to copy setup packet into setup TRB, so we can't use the setup
3386 if (!urb->setup_packet)
3389 if (!in_interrupt())
3390 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3392 /* 1 TRB for setup, 1 for status */
3395 * Don't need to check if we need additional event data and normal TRBs,
3396 * since data in control transfers will never get bigger than 16MB
3397 * XXX: can we get a buffer that crosses 64KB boundaries?
3399 if (urb->transfer_buffer_length > 0)
3401 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3402 ep_index, urb->stream_id,
3403 num_trbs, urb, 0, false, mem_flags);
3407 urb_priv = urb->hcpriv;
3408 td = urb_priv->td[0];
3411 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3412 * until we've finished creating all the other TRBs. The ring's cycle
3413 * state may change as we enqueue the other TRBs, so save it too.
3415 start_trb = &ep_ring->enqueue->generic;
3416 start_cycle = ep_ring->cycle_state;
3418 /* Queue setup TRB - see section 6.4.1.2.1 */
3419 /* FIXME better way to translate setup_packet into two u32 fields? */
3420 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3422 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3423 if (start_cycle == 0)
3426 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3427 if (xhci->hci_version == 0x100) {
3428 if (urb->transfer_buffer_length > 0) {
3429 if (setup->bRequestType & USB_DIR_IN)
3430 field |= TRB_TX_TYPE(TRB_DATA_IN);
3432 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3436 queue_trb(xhci, ep_ring, false, true, false,
3437 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3438 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3439 TRB_LEN(8) | TRB_INTR_TARGET(0),
3440 /* Immediate data in pointer */
3443 /* If there's data, queue data TRBs */
3444 /* Only set interrupt on short packet for IN endpoints */
3445 if (usb_urb_dir_in(urb))
3446 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3448 field = TRB_TYPE(TRB_DATA);
3450 length_field = TRB_LEN(urb->transfer_buffer_length) |
3451 xhci_td_remainder(urb->transfer_buffer_length) |
3453 if (urb->transfer_buffer_length > 0) {
3454 if (setup->bRequestType & USB_DIR_IN)
3455 field |= TRB_DIR_IN;
3456 queue_trb(xhci, ep_ring, false, true, false,
3457 lower_32_bits(urb->transfer_dma),
3458 upper_32_bits(urb->transfer_dma),
3460 field | ep_ring->cycle_state);
3463 /* Save the DMA address of the last TRB in the TD */
3464 td->last_trb = ep_ring->enqueue;
3466 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3467 /* If the device sent data, the status stage is an OUT transfer */
3468 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3472 queue_trb(xhci, ep_ring, false, false, false,
3476 /* Event on completion */
3477 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3479 giveback_first_trb(xhci, slot_id, ep_index, 0,
3480 start_cycle, start_trb);
3484 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3485 struct urb *urb, int i)
3490 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3491 td_len = urb->iso_frame_desc[i].length;
3493 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3502 * The transfer burst count field of the isochronous TRB defines the number of
3503 * bursts that are required to move all packets in this TD. Only SuperSpeed
3504 * devices can burst up to bMaxBurst number of packets per service interval.
3505 * This field is zero based, meaning a value of zero in the field means one
3506 * burst. Basically, for everything but SuperSpeed devices, this field will be
3507 * zero. Only xHCI 1.0 host controllers support this field.
3509 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3510 struct usb_device *udev,
3511 struct urb *urb, unsigned int total_packet_count)
3513 unsigned int max_burst;
3515 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3518 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3519 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3523 * Returns the number of packets in the last "burst" of packets. This field is
3524 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3525 * the last burst packet count is equal to the total number of packets in the
3526 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3527 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3528 * contain 1 to (bMaxBurst + 1) packets.
3530 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3531 struct usb_device *udev,
3532 struct urb *urb, unsigned int total_packet_count)
3534 unsigned int max_burst;
3535 unsigned int residue;
3537 if (xhci->hci_version < 0x100)
3540 switch (udev->speed) {
3541 case USB_SPEED_SUPER:
3542 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3543 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3544 residue = total_packet_count % (max_burst + 1);
3545 /* If residue is zero, the last burst contains (max_burst + 1)
3546 * number of packets, but the TLBPC field is zero-based.
3552 if (total_packet_count == 0)
3554 return total_packet_count - 1;
3558 /* This is for isoc transfer */
3559 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3560 struct urb *urb, int slot_id, unsigned int ep_index)
3562 struct xhci_ring *ep_ring;
3563 struct urb_priv *urb_priv;
3565 int num_tds, trbs_per_td;
3566 struct xhci_generic_trb *start_trb;
3569 u32 field, length_field;
3570 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3571 u64 start_addr, addr;
3573 bool more_trbs_coming;
3575 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3577 num_tds = urb->number_of_packets;
3579 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3583 if (!in_interrupt())
3584 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3585 " addr = %#llx, num_tds = %d\n",
3586 urb->ep->desc.bEndpointAddress,
3587 urb->transfer_buffer_length,
3588 urb->transfer_buffer_length,
3589 (unsigned long long)urb->transfer_dma,
3592 start_addr = (u64) urb->transfer_dma;
3593 start_trb = &ep_ring->enqueue->generic;
3594 start_cycle = ep_ring->cycle_state;
3596 urb_priv = urb->hcpriv;
3597 /* Queue the first TRB, even if it's zero-length */
3598 for (i = 0; i < num_tds; i++) {
3599 unsigned int total_packet_count;
3600 unsigned int burst_count;
3601 unsigned int residue;
3605 addr = start_addr + urb->iso_frame_desc[i].offset;
3606 td_len = urb->iso_frame_desc[i].length;
3607 td_remain_len = td_len;
3608 total_packet_count = DIV_ROUND_UP(td_len,
3610 usb_endpoint_maxp(&urb->ep->desc)));
3611 /* A zero-length transfer still involves at least one packet. */
3612 if (total_packet_count == 0)
3613 total_packet_count++;
3614 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3615 total_packet_count);
3616 residue = xhci_get_last_burst_packet_count(xhci,
3617 urb->dev, urb, total_packet_count);
3619 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3621 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3622 urb->stream_id, trbs_per_td, urb, i, true,
3630 td = urb_priv->td[i];
3631 for (j = 0; j < trbs_per_td; j++) {
3636 field = TRB_TBC(burst_count) |
3638 /* Queue the isoc TRB */
3639 field |= TRB_TYPE(TRB_ISOC);
3640 /* Assume URB_ISO_ASAP is set */
3643 if (start_cycle == 0)
3646 field |= ep_ring->cycle_state;
3649 /* Queue other normal TRBs */
3650 field |= TRB_TYPE(TRB_NORMAL);
3651 field |= ep_ring->cycle_state;
3654 /* Only set interrupt on short packet for IN EPs */
3655 if (usb_urb_dir_in(urb))
3658 /* Chain all the TRBs together; clear the chain bit in
3659 * the last TRB to indicate it's the last TRB in the
3662 if (j < trbs_per_td - 1) {
3664 more_trbs_coming = true;
3666 td->last_trb = ep_ring->enqueue;
3668 if (xhci->hci_version == 0x100 &&
3671 /* Set BEI bit except for the last td */
3672 if (i < num_tds - 1)
3675 more_trbs_coming = false;
3678 /* Calculate TRB length */
3679 trb_buff_len = TRB_MAX_BUFF_SIZE -
3680 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3681 if (trb_buff_len > td_remain_len)
3682 trb_buff_len = td_remain_len;
3684 /* Set the TRB length, TD size, & interrupter fields. */
3685 if (xhci->hci_version < 0x100) {
3686 remainder = xhci_td_remainder(
3687 td_len - running_total);
3689 remainder = xhci_v1_0_td_remainder(
3690 running_total, trb_buff_len,
3691 total_packet_count, urb,
3692 (trbs_per_td - j - 1));
3694 length_field = TRB_LEN(trb_buff_len) |
3698 queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3699 lower_32_bits(addr),
3700 upper_32_bits(addr),
3703 running_total += trb_buff_len;
3705 addr += trb_buff_len;
3706 td_remain_len -= trb_buff_len;
3709 /* Check TD length */
3710 if (running_total != td_len) {
3711 xhci_err(xhci, "ISOC TD length unmatch\n");
3717 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3718 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3719 usb_amd_quirk_pll_disable();
3721 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3723 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3724 start_cycle, start_trb);
3727 /* Clean up a partially enqueued isoc transfer. */
3729 for (i--; i >= 0; i--)
3730 list_del_init(&urb_priv->td[i]->td_list);
3732 /* Use the first TD as a temporary variable to turn the TDs we've queued
3733 * into No-ops with a software-owned cycle bit. That way the hardware
3734 * won't accidentally start executing bogus TDs when we partially
3735 * overwrite them. td->first_trb and td->start_seg are already set.
3737 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3738 /* Every TRB except the first & last will have its cycle bit flipped. */
3739 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3741 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3742 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3743 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3744 ep_ring->cycle_state = start_cycle;
3745 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3750 * Check transfer ring to guarantee there is enough room for the urb.
3751 * Update ISO URB start_frame and interval.
3752 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3753 * update the urb->start_frame by now.
3754 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3756 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3757 struct urb *urb, int slot_id, unsigned int ep_index)
3759 struct xhci_virt_device *xdev;
3760 struct xhci_ring *ep_ring;
3761 struct xhci_ep_ctx *ep_ctx;
3765 int num_tds, num_trbs, i;
3768 xdev = xhci->devs[slot_id];
3769 ep_ring = xdev->eps[ep_index].ring;
3770 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3773 num_tds = urb->number_of_packets;
3774 for (i = 0; i < num_tds; i++)
3775 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3777 /* Check the ring to guarantee there is enough room for the whole urb.
3778 * Do not insert any td of the urb to the ring if the check failed.
3780 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3781 num_trbs, true, mem_flags);
3785 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3786 start_frame &= 0x3fff;
3788 urb->start_frame = start_frame;
3789 if (urb->dev->speed == USB_SPEED_LOW ||
3790 urb->dev->speed == USB_SPEED_FULL)
3791 urb->start_frame >>= 3;
3793 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3794 ep_interval = urb->interval;
3795 /* Convert to microframes */
3796 if (urb->dev->speed == USB_SPEED_LOW ||
3797 urb->dev->speed == USB_SPEED_FULL)
3799 /* FIXME change this to a warning and a suggestion to use the new API
3800 * to set the polling interval (once the API is added).
3802 if (xhci_interval != ep_interval) {
3803 if (printk_ratelimit())
3804 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3805 " (%d microframe%s) than xHCI "
3806 "(%d microframe%s)\n",
3808 ep_interval == 1 ? "" : "s",
3810 xhci_interval == 1 ? "" : "s");
3811 urb->interval = xhci_interval;
3812 /* Convert back to frames for LS/FS devices */
3813 if (urb->dev->speed == USB_SPEED_LOW ||
3814 urb->dev->speed == USB_SPEED_FULL)
3817 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3820 /**** Command Ring Operations ****/
3822 /* Generic function for queueing a command TRB on the command ring.
3823 * Check to make sure there's room on the command ring for one command TRB.
3824 * Also check that there's room reserved for commands that must not fail.
3825 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3826 * then only check for the number of reserved spots.
3827 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3828 * because the command event handler may want to resubmit a failed command.
3830 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3831 u32 field3, u32 field4, bool command_must_succeed)
3833 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3836 if (!command_must_succeed)
3839 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3840 reserved_trbs, false, GFP_ATOMIC);
3842 xhci_err(xhci, "ERR: No room for command on command ring\n");
3843 if (command_must_succeed)
3844 xhci_err(xhci, "ERR: Reserved TRB counting for "
3845 "unfailable commands failed.\n");
3848 queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3849 field3, field4 | xhci->cmd_ring->cycle_state);
3853 /* Queue a slot enable or disable request on the command ring */
3854 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3856 return queue_command(xhci, 0, 0, 0,
3857 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3860 /* Queue an address device command TRB */
3861 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3864 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3865 upper_32_bits(in_ctx_ptr), 0,
3866 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3870 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3871 u32 field1, u32 field2, u32 field3, u32 field4)
3873 return queue_command(xhci, field1, field2, field3, field4, false);
3876 /* Queue a reset device command TRB */
3877 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3879 return queue_command(xhci, 0, 0, 0,
3880 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3884 /* Queue a configure endpoint command TRB */
3885 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3886 u32 slot_id, bool command_must_succeed)
3888 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3889 upper_32_bits(in_ctx_ptr), 0,
3890 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3891 command_must_succeed);
3894 /* Queue an evaluate context command TRB */
3895 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3898 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3899 upper_32_bits(in_ctx_ptr), 0,
3900 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3905 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3906 * activity on an endpoint that is about to be suspended.
3908 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3909 unsigned int ep_index, int suspend)
3911 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3912 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3913 u32 type = TRB_TYPE(TRB_STOP_RING);
3914 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3916 return queue_command(xhci, 0, 0, 0,
3917 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3920 /* Set Transfer Ring Dequeue Pointer command.
3921 * This should not be used for endpoints that have streams enabled.
3923 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3924 unsigned int ep_index, unsigned int stream_id,
3925 struct xhci_segment *deq_seg,
3926 union xhci_trb *deq_ptr, u32 cycle_state)
3929 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3930 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3931 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3932 u32 type = TRB_TYPE(TRB_SET_DEQ);
3933 struct xhci_virt_ep *ep;
3935 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3937 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3938 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3942 ep = &xhci->devs[slot_id]->eps[ep_index];
3943 if ((ep->ep_state & SET_DEQ_PENDING)) {
3944 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3945 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3948 ep->queued_deq_seg = deq_seg;
3949 ep->queued_deq_ptr = deq_ptr;
3950 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3951 upper_32_bits(addr), trb_stream_id,
3952 trb_slot_id | trb_ep_index | type, false);
3955 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3956 unsigned int ep_index)
3958 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3959 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3960 u32 type = TRB_TYPE(TRB_RESET_EP);
3962 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,