drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 /*
  72  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  73  * address of the TRB.
  74  */
  75 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  76                 union xhci_trb *trb)
  77 {
  78         unsigned long segment_offset;
  79
  80         if (!seg || !trb || trb < seg->trbs)
  81                 return 0;
  82         /* offset in TRBs */
  83         segment_offset = trb - seg->trbs;
  84         if (segment_offset > TRBS_PER_SEGMENT)
  85                 return 0;
  86         return seg->dma + (segment_offset * sizeof(*trb));
  87 }
  88
  89 /* Does this link TRB point to the first segment in a ring,
  90  * or was the previous TRB the last TRB on the last segment in the ERST?
  91  */
  92 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  93                 struct xhci_segment *seg, union xhci_trb *trb)
  94 {
  95         if (ring == xhci->event_ring)
  96                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
  97                         (seg->next == xhci->event_ring->first_seg);
  98         else
  99                 return trb->link.control & LINK_TOGGLE;
 100 }
 101
 102 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 103  * segment?  I.e. would the updated event TRB pointer step off the end of the
 104  * event seg?
 105  */
 106 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 107                 struct xhci_segment *seg, union xhci_trb *trb)
 108 {
 109         if (ring == xhci->event_ring)
 110                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 111         else
 112                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 113 }
 114
 115 static inline int enqueue_is_link_trb(struct xhci_ring *ring)
 116 {
 117         struct xhci_link_trb *link = &ring->enqueue->link;
 118         return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
 119 }
 120
 121 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 122  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 123  * effect the ring dequeue or enqueue pointers.
 124  */
 125 static void next_trb(struct xhci_hcd *xhci,
 126                 struct xhci_ring *ring,
 127                 struct xhci_segment **seg,
 128                 union xhci_trb **trb)
 129 {
 130         if (last_trb(xhci, ring, *seg, *trb)) {
 131                 *seg = (*seg)->next;
 132                 *trb = ((*seg)->trbs);
 133         } else {
 134                 (*trb)++;
 135         }
 136 }
 137
 138 /*
 139  * See Cycle bit rules. SW is the consumer for the event ring only.
 140  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 141  */
 142 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 143 {
 144         union xhci_trb *next = ++(ring->dequeue);
 145         unsigned long long addr;
 146
 147         ring->deq_updates++;
 148         /* Update the dequeue pointer further if that was a link TRB or we're at
 149          * the end of an event ring segment (which doesn't have link TRBS)
 150          */
 151         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 152                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 153                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 154                         if (!in_interrupt())
 155                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 156                                                 ring,
 157                                                 (unsigned int) ring->cycle_state);
 158                 }
 159                 ring->deq_seg = ring->deq_seg->next;
 160                 ring->dequeue = ring->deq_seg->trbs;
 161                 next = ring->dequeue;
 162         }
 163         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 164         if (ring == xhci->event_ring)
 165                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 166         else if (ring == xhci->cmd_ring)
 167                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 168         else
 169                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 170 }
 171
 172 /*
 173  * See Cycle bit rules. SW is the consumer for the event ring only.
 174  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 175  *
 176  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 177  * chain bit is set), then set the chain bit in all the following link TRBs.
 178  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 179  * have their chain bit cleared (so that each Link TRB is a separate TD).
 180  *
 181  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 182  * set, but other sections talk about dealing with the chain bit set.  This was
 183  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 184  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 185  *
 186  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 187  *                      prepare_transfer()?
 188  */
 189 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 190                 bool consumer, bool more_trbs_coming)
 191 {
 192         u32 chain;
 193         union xhci_trb *next;
 194         unsigned long long addr;
 195
 196         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 197         next = ++(ring->enqueue);
 198
 199         ring->enq_updates++;
 200         /* Update the dequeue pointer further if that was a link TRB or we're at
 201          * the end of an event ring segment (which doesn't have link TRBS)
 202          */
 203         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 204                 if (!consumer) {
 205                         if (ring != xhci->event_ring) {
 206                                 /*
 207                                  * If the caller doesn't plan on enqueueing more
 208                                  * TDs before ringing the doorbell, then we
 209                                  * don't want to give the link TRB to the
 210                                  * hardware just yet.  We'll give the link TRB
 211                                  * back in prepare_ring() just before we enqueue
 212                                  * the TD at the top of the ring.
 213                                  */
 214                                 if (!chain && !more_trbs_coming)
 215                                         break;
 216
 217                                 /* If we're not dealing with 0.95 hardware,
 218                                  * carry over the chain bit of the previous TRB
 219                                  * (which may mean the chain bit is cleared).
 220                                  */
 221                                 if (!xhci_link_trb_quirk(xhci)) {
 222                                         next->link.control &= ~TRB_CHAIN;
 223                                         next->link.control |= chain;
 224                                 }
 225                                 /* Give this link TRB to the hardware */
 226                                 wmb();
 227                                 next->link.control ^= TRB_CYCLE;
 228                         }
 229                         /* Toggle the cycle bit after the last ring segment. */
 230                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 231                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 232                                 if (!in_interrupt())
 233                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 234                                                         ring,
 235                                                         (unsigned int) ring->cycle_state);
 236                         }
 237                 }
 238                 ring->enq_seg = ring->enq_seg->next;
 239                 ring->enqueue = ring->enq_seg->trbs;
 240                 next = ring->enqueue;
 241         }
 242         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 243         if (ring == xhci->event_ring)
 244                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 245         else if (ring == xhci->cmd_ring)
 246                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 247         else
 248                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 249 }
 250
 251 /*
 252  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 253  * above.
 254  * FIXME: this would be simpler and faster if we just kept track of the number
 255  * of free TRBs in a ring.
 256  */
 257 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 258                 unsigned int num_trbs)
 259 {
 260         int i;
 261         union xhci_trb *enq = ring->enqueue;
 262         struct xhci_segment *enq_seg = ring->enq_seg;
 263         struct xhci_segment *cur_seg;
 264         unsigned int left_on_ring;
 265
 266         /* If we are currently pointing to a link TRB, advance the
 267          * enqueue pointer before checking for space */
 268         while (last_trb(xhci, ring, enq_seg, enq)) {
 269                 enq_seg = enq_seg->next;
 270                 enq = enq_seg->trbs;
 271         }
 272
 273         /* Check if ring is empty */
 274         if (enq == ring->dequeue) {
 275                 /* Can't use link trbs */
 276                 left_on_ring = TRBS_PER_SEGMENT - 1;
 277                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 278                                 cur_seg = cur_seg->next)
 279                         left_on_ring += TRBS_PER_SEGMENT - 1;
 280
 281                 /* Always need one TRB free in the ring. */
 282                 left_on_ring -= 1;
 283                 if (num_trbs > left_on_ring) {
 284                         xhci_warn(xhci, "Not enough room on ring; "
 285                                         "need %u TRBs, %u TRBs left\n",
 286                                         num_trbs, left_on_ring);
 287                         return 0;
 288                 }
 289                 return 1;
 290         }
 291         /* Make sure there's an extra empty TRB available */
 292         for (i = 0; i <= num_trbs; ++i) {
 293                 if (enq == ring->dequeue)
 294                         return 0;
 295                 enq++;
 296                 while (last_trb(xhci, ring, enq_seg, enq)) {
 297                         enq_seg = enq_seg->next;
 298                         enq = enq_seg->trbs;
 299                 }
 300         }
 301         return 1;
 302 }
 303
 304 /* Ring the host controller doorbell after placing a command on the ring */
 305 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 306 {
 307         u32 temp;
 308
 309         xhci_dbg(xhci, "// Ding dong!\n");
 310         temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
 311         xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
 312         /* Flush PCI posted writes */
 313         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 314 }
 315
 316 static void ring_ep_doorbell(struct xhci_hcd *xhci,
 317                 unsigned int slot_id,
 318                 unsigned int ep_index,
 319                 unsigned int stream_id)
 320 {
 321         struct xhci_virt_ep *ep;
 322         unsigned int ep_state;
 323         u32 field;
 324         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 325
 326         ep = &xhci->devs[slot_id]->eps[ep_index];
 327         ep_state = ep->ep_state;
 328         /* Don't ring the doorbell for this endpoint if there are pending
 329          * cancellations because the we don't want to interrupt processing.
 330          * We don't want to restart any stream rings if there's a set dequeue
 331          * pointer command pending because the device can choose to start any
 332          * stream once the endpoint is on the HW schedule.
 333          * FIXME - check all the stream rings for pending cancellations.
 334          */
 335         if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING)
 336                         && !(ep_state & EP_HALTED)) {
 337                 field = xhci_readl(xhci, db_addr) & DB_MASK;
 338                 field |= EPI_TO_DB(ep_index) | STREAM_ID_TO_DB(stream_id);
 339                 xhci_writel(xhci, field, db_addr);
 340         }
 341 }
 342
 343 /* Ring the doorbell for any rings with pending URBs */
 344 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 345                 unsigned int slot_id,
 346                 unsigned int ep_index)
 347 {
 348         unsigned int stream_id;
 349         struct xhci_virt_ep *ep;
 350
 351         ep = &xhci->devs[slot_id]->eps[ep_index];
 352
 353         /* A ring has pending URBs if its TD list is not empty */
 354         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 355                 if (!(list_empty(&ep->ring->td_list)))
 356                         ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 357                 return;
 358         }
 359
 360         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 361                         stream_id++) {
 362                 struct xhci_stream_info *stream_info = ep->stream_info;
 363                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 364                         ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
 365         }
 366 }
 367
 368 /*
 369  * Find the segment that trb is in.  Start searching in start_seg.
 370  * If we must move past a segment that has a link TRB with a toggle cycle state
 371  * bit set, then we will toggle the value pointed at by cycle_state.
 372  */
 373 static struct xhci_segment *find_trb_seg(
 374                 struct xhci_segment *start_seg,
 375                 union xhci_trb  *trb, int *cycle_state)
 376 {
 377         struct xhci_segment *cur_seg = start_seg;
 378         struct xhci_generic_trb *generic_trb;
 379
 380         while (cur_seg->trbs > trb ||
 381                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 382                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 383                 if ((generic_trb->field[3] & TRB_TYPE_BITMASK) ==
 384                                 TRB_TYPE(TRB_LINK) &&
 385                                 (generic_trb->field[3] & LINK_TOGGLE))
 386                         *cycle_state = ~(*cycle_state) & 0x1;
 387                 cur_seg = cur_seg->next;
 388                 if (cur_seg == start_seg)
 389                         /* Looped over the entire list.  Oops! */
 390                         return NULL;
 391         }
 392         return cur_seg;
 393 }
 394
 395
 396 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 397                 unsigned int slot_id, unsigned int ep_index,
 398                 unsigned int stream_id)
 399 {
 400         struct xhci_virt_ep *ep;
 401
 402         ep = &xhci->devs[slot_id]->eps[ep_index];
 403         /* Common case: no streams */
 404         if (!(ep->ep_state & EP_HAS_STREAMS))
 405                 return ep->ring;
 406
 407         if (stream_id == 0) {
 408                 xhci_warn(xhci,
 409                                 "WARN: Slot ID %u, ep index %u has streams, "
 410                                 "but URB has no stream ID.\n",
 411                                 slot_id, ep_index);
 412                 return NULL;
 413         }
 414
 415         if (stream_id < ep->stream_info->num_streams)
 416                 return ep->stream_info->stream_rings[stream_id];
 417
 418         xhci_warn(xhci,
 419                         "WARN: Slot ID %u, ep index %u has "
 420                         "stream IDs 1 to %u allocated, "
 421                         "but stream ID %u is requested.\n",
 422                         slot_id, ep_index,
 423                         ep->stream_info->num_streams - 1,
 424                         stream_id);
 425         return NULL;
 426 }
 427
 428 /* Get the right ring for the given URB.
 429  * If the endpoint supports streams, boundary check the URB's stream ID.
 430  * If the endpoint doesn't support streams, return the singular endpoint ring.
 431  */
 432 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 433                 struct urb *urb)
 434 {
 435         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 436                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 437 }
 438
 439 /*
 440  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 441  * Record the new state of the xHC's endpoint ring dequeue segment,
 442  * dequeue pointer, and new consumer cycle state in state.
 443  * Update our internal representation of the ring's dequeue pointer.
 444  *
 445  * We do this in three jumps:
 446  *  - First we update our new ring state to be the same as when the xHC stopped.
 447  *  - Then we traverse the ring to find the segment that contains
 448  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 449  *    any link TRBs with the toggle cycle bit set.
 450  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 451  *    if we've moved it past a link TRB with the toggle cycle bit set.
 452  */
 453 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 454                 unsigned int slot_id, unsigned int ep_index,
 455                 unsigned int stream_id, struct xhci_td *cur_td,
 456                 struct xhci_dequeue_state *state)
 457 {
 458         struct xhci_virt_device *dev = xhci->devs[slot_id];
 459         struct xhci_ring *ep_ring;
 460         struct xhci_generic_trb *trb;
 461         struct xhci_ep_ctx *ep_ctx;
 462         dma_addr_t addr;
 463
 464         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 465                         ep_index, stream_id);
 466         if (!ep_ring) {
 467                 xhci_warn(xhci, "WARN can't find new dequeue state "
 468                                 "for invalid stream ID %u.\n",
 469                                 stream_id);
 470                 return;
 471         }
 472         state->new_cycle_state = 0;
 473         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 474         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 475                         dev->eps[ep_index].stopped_trb,
 476                         &state->new_cycle_state);
 477         if (!state->new_deq_seg)
 478                 BUG();
 479         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 480         xhci_dbg(xhci, "Finding endpoint context\n");
 481         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 482         state->new_cycle_state = 0x1 & ep_ctx->deq;
 483
 484         state->new_deq_ptr = cur_td->last_trb;
 485         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 486         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 487                         state->new_deq_ptr,
 488                         &state->new_cycle_state);
 489         if (!state->new_deq_seg)
 490                 BUG();
 491
 492         trb = &state->new_deq_ptr->generic;
 493         if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
 494                                 (trb->field[3] & LINK_TOGGLE))
 495                 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
 496         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 497
 498         /* Don't update the ring cycle state for the producer (us). */
 499         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 500                         state->new_deq_seg);
 501         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 502         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 503                         (unsigned long long) addr);
 504         xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
 505         ep_ring->dequeue = state->new_deq_ptr;
 506         ep_ring->deq_seg = state->new_deq_seg;
 507 }
 508
 509 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 510                 struct xhci_td *cur_td)
 511 {
 512         struct xhci_segment *cur_seg;
 513         union xhci_trb *cur_trb;
 514
 515         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 516                         true;
 517                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 518                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 519                                 TRB_TYPE(TRB_LINK)) {
 520                         /* Unchain any chained Link TRBs, but
 521                          * leave the pointers intact.
 522                          */
 523                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 524                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 525                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 526                                         "in seg %p (0x%llx dma)\n",
 527                                         cur_trb,
 528                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 529                                         cur_seg,
 530                                         (unsigned long long)cur_seg->dma);
 531                 } else {
 532                         cur_trb->generic.field[0] = 0;
 533                         cur_trb->generic.field[1] = 0;
 534                         cur_trb->generic.field[2] = 0;
 535                         /* Preserve only the cycle bit of this TRB */
 536                         cur_trb->generic.field[3] &= TRB_CYCLE;
 537                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 538                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 539                                         "in seg %p (0x%llx dma)\n",
 540                                         cur_trb,
 541                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 542                                         cur_seg,
 543                                         (unsigned long long)cur_seg->dma);
 544                 }
 545                 if (cur_trb == cur_td->last_trb)
 546                         break;
 547         }
 548 }
 549
 550 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 551                 unsigned int ep_index, unsigned int stream_id,
 552                 struct xhci_segment *deq_seg,
 553                 union xhci_trb *deq_ptr, u32 cycle_state);
 554
 555 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 556                 unsigned int slot_id, unsigned int ep_index,
 557                 unsigned int stream_id,
 558                 struct xhci_dequeue_state *deq_state)
 559 {
 560         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 561
 562         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 563                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 564                         deq_state->new_deq_seg,
 565                         (unsigned long long)deq_state->new_deq_seg->dma,
 566                         deq_state->new_deq_ptr,
 567                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 568                         deq_state->new_cycle_state);
 569         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 570                         deq_state->new_deq_seg,
 571                         deq_state->new_deq_ptr,
 572                         (u32) deq_state->new_cycle_state);
 573         /* Stop the TD queueing code from ringing the doorbell until
 574          * this command completes.  The HC won't set the dequeue pointer
 575          * if the ring is running, and ringing the doorbell starts the
 576          * ring running.
 577          */
 578         ep->ep_state |= SET_DEQ_PENDING;
 579 }
 580
 581 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 582                 struct xhci_virt_ep *ep)
 583 {
 584         ep->ep_state &= ~EP_HALT_PENDING;
 585         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 586          * timer is running on another CPU, we don't decrement stop_cmds_pending
 587          * (since we didn't successfully stop the watchdog timer).
 588          */
 589         if (del_timer(&ep->stop_cmd_timer))
 590                 ep->stop_cmds_pending--;
 591 }
 592
 593 /* Must be called with xhci->lock held in interrupt context */
 594 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 595                 struct xhci_td *cur_td, int status, char *adjective)
 596 {
 597         struct usb_hcd *hcd = xhci_to_hcd(xhci);
 598         struct urb      *urb;
 599         struct urb_priv *urb_priv;
 600
 601         urb = cur_td->urb;
 602         urb_priv = urb->hcpriv;
 603         urb_priv->td_cnt++;
 604
 605         /* Only giveback urb when this is the last td in urb */
 606         if (urb_priv->td_cnt == urb_priv->length) {
 607                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 608                 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb);
 609
 610                 spin_unlock(&xhci->lock);
 611                 usb_hcd_giveback_urb(hcd, urb, status);
 612                 xhci_urb_free_priv(xhci, urb_priv);
 613                 spin_lock(&xhci->lock);
 614                 xhci_dbg(xhci, "%s URB given back\n", adjective);
 615         }
 616 }
 617
 618 /*
 619  * When we get a command completion for a Stop Endpoint Command, we need to
 620  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 621  *
 622  *  1. If the HW was in the middle of processing the TD that needs to be
 623  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 624  *     in the TD with a Set Dequeue Pointer Command.
 625  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 626  *     bit cleared) so that the HW will skip over them.
 627  */
 628 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 629                 union xhci_trb *trb)
 630 {
 631         unsigned int slot_id;
 632         unsigned int ep_index;
 633         struct xhci_ring *ep_ring;
 634         struct xhci_virt_ep *ep;
 635         struct list_head *entry;
 636         struct xhci_td *cur_td = NULL;
 637         struct xhci_td *last_unlinked_td;
 638
 639         struct xhci_dequeue_state deq_state;
 640
 641         memset(&deq_state, 0, sizeof(deq_state));
 642         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 643         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 644         ep = &xhci->devs[slot_id]->eps[ep_index];
 645
 646         if (list_empty(&ep->cancelled_td_list)) {
 647                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 648                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 649                 return;
 650         }
 651
 652         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 653          * We have the xHCI lock, so nothing can modify this list until we drop
 654          * it.  We're also in the event handler, so we can't get re-interrupted
 655          * if another Stop Endpoint command completes
 656          */
 657         list_for_each(entry, &ep->cancelled_td_list) {
 658                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 659                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 660                                 cur_td->first_trb,
 661                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 662                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 663                 if (!ep_ring) {
 664                         /* This shouldn't happen unless a driver is mucking
 665                          * with the stream ID after submission.  This will
 666                          * leave the TD on the hardware ring, and the hardware
 667                          * will try to execute it, and may access a buffer
 668                          * that has already been freed.  In the best case, the
 669                          * hardware will execute it, and the event handler will
 670                          * ignore the completion event for that TD, since it was
 671                          * removed from the td_list for that endpoint.  In
 672                          * short, don't muck with the stream ID after
 673                          * submission.
 674                          */
 675                         xhci_warn(xhci, "WARN Cancelled URB %p "
 676                                         "has invalid stream ID %u.\n",
 677                                         cur_td->urb,
 678                                         cur_td->urb->stream_id);
 679                         goto remove_finished_td;
 680                 }
 681                 /*
 682                  * If we stopped on the TD we need to cancel, then we have to
 683                  * move the xHC endpoint ring dequeue pointer past this TD.
 684                  */
 685                 if (cur_td == ep->stopped_td)
 686                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 687                                         cur_td->urb->stream_id,
 688                                         cur_td, &deq_state);
 689                 else
 690                         td_to_noop(xhci, ep_ring, cur_td);
 691 remove_finished_td:
 692                 /*
 693                  * The event handler won't see a completion for this TD anymore,
 694                  * so remove it from the endpoint ring's TD list.  Keep it in
 695                  * the cancelled TD list for URB completion later.
 696                  */
 697                 list_del(&cur_td->td_list);
 698         }
 699         last_unlinked_td = cur_td;
 700         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 701
 702         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 703         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 704                 xhci_queue_new_dequeue_state(xhci,
 705                                 slot_id, ep_index,
 706                                 ep->stopped_td->urb->stream_id,
 707                                 &deq_state);
 708                 xhci_ring_cmd_db(xhci);
 709         } else {
 710                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 711                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 712         }
 713         ep->stopped_td = NULL;
 714         ep->stopped_trb = NULL;
 715
 716         /*
 717          * Drop the lock and complete the URBs in the cancelled TD list.
 718          * New TDs to be cancelled might be added to the end of the list before
 719          * we can complete all the URBs for the TDs we already unlinked.
 720          * So stop when we've completed the URB for the last TD we unlinked.
 721          */
 722         do {
 723                 cur_td = list_entry(ep->cancelled_td_list.next,
 724                                 struct xhci_td, cancelled_td_list);
 725                 list_del(&cur_td->cancelled_td_list);
 726
 727                 /* Clean up the cancelled URB */
 728                 /* Doesn't matter what we pass for status, since the core will
 729                  * just overwrite it (because the URB has been unlinked).
 730                  */
 731                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 732
 733                 /* Stop processing the cancelled list if the watchdog timer is
 734                  * running.
 735                  */
 736                 if (xhci->xhc_state & XHCI_STATE_DYING)
 737                         return;
 738         } while (cur_td != last_unlinked_td);
 739
 740         /* Return to the event handler with xhci->lock re-acquired */
 741 }
 742
 743 /* Watchdog timer function for when a stop endpoint command fails to complete.
 744  * In this case, we assume the host controller is broken or dying or dead.  The
 745  * host may still be completing some other events, so we have to be careful to
 746  * let the event ring handler and the URB dequeueing/enqueueing functions know
 747  * through xhci->state.
 748  *
 749  * The timer may also fire if the host takes a very long time to respond to the
 750  * command, and the stop endpoint command completion handler cannot delete the
 751  * timer before the timer function is called.  Another endpoint cancellation may
 752  * sneak in before the timer function can grab the lock, and that may queue
 753  * another stop endpoint command and add the timer back.  So we cannot use a
 754  * simple flag to say whether there is a pending stop endpoint command for a
 755  * particular endpoint.
 756  *
 757  * Instead we use a combination of that flag and a counter for the number of
 758  * pending stop endpoint commands.  If the timer is the tail end of the last
 759  * stop endpoint command, and the endpoint's command is still pending, we assume
 760  * the host is dying.
 761  */
 762 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 763 {
 764         struct xhci_hcd *xhci;
 765         struct xhci_virt_ep *ep;
 766         struct xhci_virt_ep *temp_ep;
 767         struct xhci_ring *ring;
 768         struct xhci_td *cur_td;
 769         int ret, i, j;
 770
 771         ep = (struct xhci_virt_ep *) arg;
 772         xhci = ep->xhci;
 773
 774         spin_lock(&xhci->lock);
 775
 776         ep->stop_cmds_pending--;
 777         if (xhci->xhc_state & XHCI_STATE_DYING) {
 778                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 779                                 "xHCI as DYING, exiting.\n");
 780                 spin_unlock(&xhci->lock);
 781                 return;
 782         }
 783         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 784                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 785                                 "exiting.\n");
 786                 spin_unlock(&xhci->lock);
 787                 return;
 788         }
 789
 790         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 791         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 792         /* Oops, HC is dead or dying or at least not responding to the stop
 793          * endpoint command.
 794          */
 795         xhci->xhc_state |= XHCI_STATE_DYING;
 796         /* Disable interrupts from the host controller and start halting it */
 797         xhci_quiesce(xhci);
 798         spin_unlock(&xhci->lock);
 799
 800         ret = xhci_halt(xhci);
 801
 802         spin_lock(&xhci->lock);
 803         if (ret < 0) {
 804                 /* This is bad; the host is not responding to commands and it's
 805                  * not allowing itself to be halted.  At least interrupts are
 806                  * disabled, so we can set HC_STATE_HALT and notify the
 807                  * USB core.  But if we call usb_hc_died(), it will attempt to
 808                  * disconnect all device drivers under this host.  Those
 809                  * disconnect() methods will wait for all URBs to be unlinked,
 810                  * so we must complete them.
 811                  */
 812                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 813                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 814                 /* We could turn all TDs on the rings to no-ops.  This won't
 815                  * help if the host has cached part of the ring, and is slow if
 816                  * we want to preserve the cycle bit.  Skip it and hope the host
 817                  * doesn't touch the memory.
 818                  */
 819         }
 820         for (i = 0; i < MAX_HC_SLOTS; i++) {
 821                 if (!xhci->devs[i])
 822                         continue;
 823                 for (j = 0; j < 31; j++) {
 824                         temp_ep = &xhci->devs[i]->eps[j];
 825                         ring = temp_ep->ring;
 826                         if (!ring)
 827                                 continue;
 828                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 829                                         "ep index %u\n", i, j);
 830                         while (!list_empty(&ring->td_list)) {
 831                                 cur_td = list_first_entry(&ring->td_list,
 832                                                 struct xhci_td,
 833                                                 td_list);
 834                                 list_del(&cur_td->td_list);
 835                                 if (!list_empty(&cur_td->cancelled_td_list))
 836                                         list_del(&cur_td->cancelled_td_list);
 837                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 838                                                 -ESHUTDOWN, "killed");
 839                         }
 840                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 841                                 cur_td = list_first_entry(
 842                                                 &temp_ep->cancelled_td_list,
 843                                                 struct xhci_td,
 844                                                 cancelled_td_list);
 845                                 list_del(&cur_td->cancelled_td_list);
 846                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 847                                                 -ESHUTDOWN, "killed");
 848                         }
 849                 }
 850         }
 851         spin_unlock(&xhci->lock);
 852         xhci_to_hcd(xhci)->state = HC_STATE_HALT;
 853         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 854         usb_hc_died(xhci_to_hcd(xhci));
 855         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 856 }
 857
 858 /*
 859  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 860  * we need to clear the set deq pending flag in the endpoint ring state, so that
 861  * the TD queueing code can ring the doorbell again.  We also need to ring the
 862  * endpoint doorbell to restart the ring, but only if there aren't more
 863  * cancellations pending.
 864  */
 865 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 866                 struct xhci_event_cmd *event,
 867                 union xhci_trb *trb)
 868 {
 869         unsigned int slot_id;
 870         unsigned int ep_index;
 871         unsigned int stream_id;
 872         struct xhci_ring *ep_ring;
 873         struct xhci_virt_device *dev;
 874         struct xhci_ep_ctx *ep_ctx;
 875         struct xhci_slot_ctx *slot_ctx;
 876
 877         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 878         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 879         stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
 880         dev = xhci->devs[slot_id];
 881
 882         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 883         if (!ep_ring) {
 884                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 885                                 "freed stream ID %u\n",
 886                                 stream_id);
 887                 /* XXX: Harmless??? */
 888                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 889                 return;
 890         }
 891
 892         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 893         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 894
 895         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 896                 unsigned int ep_state;
 897                 unsigned int slot_state;
 898
 899                 switch (GET_COMP_CODE(event->status)) {
 900                 case COMP_TRB_ERR:
 901                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 902                                         "of stream ID configuration\n");
 903                         break;
 904                 case COMP_CTX_STATE:
 905                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 906                                         "to incorrect slot or ep state.\n");
 907                         ep_state = ep_ctx->ep_info;
 908                         ep_state &= EP_STATE_MASK;
 909                         slot_state = slot_ctx->dev_state;
 910                         slot_state = GET_SLOT_STATE(slot_state);
 911                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 912                                         slot_state, ep_state);
 913                         break;
 914                 case COMP_EBADSLT:
 915                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 916                                         "slot %u was not enabled.\n", slot_id);
 917                         break;
 918                 default:
 919                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 920                                         "completion code of %u.\n",
 921                                         GET_COMP_CODE(event->status));
 922                         break;
 923                 }
 924                 /* OK what do we do now?  The endpoint state is hosed, and we
 925                  * should never get to this point if the synchronization between
 926                  * queueing, and endpoint state are correct.  This might happen
 927                  * if the device gets disconnected after we've finished
 928                  * cancelling URBs, which might not be an error...
 929                  */
 930         } else {
 931                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 932                                 ep_ctx->deq);
 933         }
 934
 935         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 936         /* Restart any rings with pending URBs */
 937         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 938 }
 939
 940 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 941                 struct xhci_event_cmd *event,
 942                 union xhci_trb *trb)
 943 {
 944         int slot_id;
 945         unsigned int ep_index;
 946
 947         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 948         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 949         /* This command will only fail if the endpoint wasn't halted,
 950          * but we don't care.
 951          */
 952         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 953                         (unsigned int) GET_COMP_CODE(event->status));
 954
 955         /* HW with the reset endpoint quirk needs to have a configure endpoint
 956          * command complete before the endpoint can be used.  Queue that here
 957          * because the HW can't handle two commands being queued in a row.
 958          */
 959         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
 960                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
 961                 xhci_queue_configure_endpoint(xhci,
 962                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
 963                                 false);
 964                 xhci_ring_cmd_db(xhci);
 965         } else {
 966                 /* Clear our internal halted state and restart the ring(s) */
 967                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
 968                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 969         }
 970 }
 971
 972 /* Check to see if a command in the device's command queue matches this one.
 973  * Signal the completion or free the command, and return 1.  Return 0 if the
 974  * completed command isn't at the head of the command list.
 975  */
 976 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
 977                 struct xhci_virt_device *virt_dev,
 978                 struct xhci_event_cmd *event)
 979 {
 980         struct xhci_command *command;
 981
 982         if (list_empty(&virt_dev->cmd_list))
 983                 return 0;
 984
 985         command = list_entry(virt_dev->cmd_list.next,
 986                         struct xhci_command, cmd_list);
 987         if (xhci->cmd_ring->dequeue != command->command_trb)
 988                 return 0;
 989
 990         command->status =
 991                 GET_COMP_CODE(event->status);
 992         list_del(&command->cmd_list);
 993         if (command->completion)
 994                 complete(command->completion);
 995         else
 996                 xhci_free_command(xhci, command);
 997         return 1;
 998 }
 999
1000 static void handle_cmd_completion(struct xhci_hcd *xhci,
1001                 struct xhci_event_cmd *event)
1002 {
1003         int slot_id = TRB_TO_SLOT_ID(event->flags);
1004         u64 cmd_dma;
1005         dma_addr_t cmd_dequeue_dma;
1006         struct xhci_input_control_ctx *ctrl_ctx;
1007         struct xhci_virt_device *virt_dev;
1008         unsigned int ep_index;
1009         struct xhci_ring *ep_ring;
1010         unsigned int ep_state;
1011
1012         cmd_dma = event->cmd_trb;
1013         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1014                         xhci->cmd_ring->dequeue);
1015         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1016         if (cmd_dequeue_dma == 0) {
1017                 xhci->error_bitmask |= 1 << 4;
1018                 return;
1019         }
1020         /* Does the DMA address match our internal dequeue pointer address? */
1021         if (cmd_dma != (u64) cmd_dequeue_dma) {
1022                 xhci->error_bitmask |= 1 << 5;
1023                 return;
1024         }
1025         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
1026         case TRB_TYPE(TRB_ENABLE_SLOT):
1027                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
1028                         xhci->slot_id = slot_id;
1029                 else
1030                         xhci->slot_id = 0;
1031                 complete(&xhci->addr_dev);
1032                 break;
1033         case TRB_TYPE(TRB_DISABLE_SLOT):
1034                 if (xhci->devs[slot_id])
1035                         xhci_free_virt_device(xhci, slot_id);
1036                 break;
1037         case TRB_TYPE(TRB_CONFIG_EP):
1038                 virt_dev = xhci->devs[slot_id];
1039                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1040                         break;
1041                 /*
1042                  * Configure endpoint commands can come from the USB core
1043                  * configuration or alt setting changes, or because the HW
1044                  * needed an extra configure endpoint command after a reset
1045                  * endpoint command or streams were being configured.
1046                  * If the command was for a halted endpoint, the xHCI driver
1047                  * is not waiting on the configure endpoint command.
1048                  */
1049                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1050                                 virt_dev->in_ctx);
1051                 /* Input ctx add_flags are the endpoint index plus one */
1052                 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
1053                 /* A usb_set_interface() call directly after clearing a halted
1054                  * condition may race on this quirky hardware.  Not worth
1055                  * worrying about, since this is prototype hardware.  Not sure
1056                  * if this will work for streams, but streams support was
1057                  * untested on this prototype.
1058                  */
1059                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1060                                 ep_index != (unsigned int) -1 &&
1061                                 ctrl_ctx->add_flags - SLOT_FLAG ==
1062                                         ctrl_ctx->drop_flags) {
1063                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1064                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1065                         if (!(ep_state & EP_HALTED))
1066                                 goto bandwidth_change;
1067                         xhci_dbg(xhci, "Completed config ep cmd - "
1068                                         "last ep index = %d, state = %d\n",
1069                                         ep_index, ep_state);
1070                         /* Clear internal halted state and restart ring(s) */
1071                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1072                                 ~EP_HALTED;
1073                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1074                         break;
1075                 }
1076 bandwidth_change:
1077                 xhci_dbg(xhci, "Completed config ep cmd\n");
1078                 xhci->devs[slot_id]->cmd_status =
1079                         GET_COMP_CODE(event->status);
1080                 complete(&xhci->devs[slot_id]->cmd_completion);
1081                 break;
1082         case TRB_TYPE(TRB_EVAL_CONTEXT):
1083                 virt_dev = xhci->devs[slot_id];
1084                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1085                         break;
1086                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1087                 complete(&xhci->devs[slot_id]->cmd_completion);
1088                 break;
1089         case TRB_TYPE(TRB_ADDR_DEV):
1090                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1091                 complete(&xhci->addr_dev);
1092                 break;
1093         case TRB_TYPE(TRB_STOP_RING):
1094                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
1095                 break;
1096         case TRB_TYPE(TRB_SET_DEQ):
1097                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1098                 break;
1099         case TRB_TYPE(TRB_CMD_NOOP):
1100                 ++xhci->noops_handled;
1101                 break;
1102         case TRB_TYPE(TRB_RESET_EP):
1103                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1104                 break;
1105         case TRB_TYPE(TRB_RESET_DEV):
1106                 xhci_dbg(xhci, "Completed reset device command.\n");
1107                 slot_id = TRB_TO_SLOT_ID(
1108                                 xhci->cmd_ring->dequeue->generic.field[3]);
1109                 virt_dev = xhci->devs[slot_id];
1110                 if (virt_dev)
1111                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1112                 else
1113                         xhci_warn(xhci, "Reset device command completion "
1114                                         "for disabled slot %u\n", slot_id);
1115                 break;
1116         case TRB_TYPE(TRB_NEC_GET_FW):
1117                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1118                         xhci->error_bitmask |= 1 << 6;
1119                         break;
1120                 }
1121                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1122                                 NEC_FW_MAJOR(event->status),
1123                                 NEC_FW_MINOR(event->status));
1124                 break;
1125         default:
1126                 /* Skip over unknown commands on the event ring */
1127                 xhci->error_bitmask |= 1 << 6;
1128                 break;
1129         }
1130         inc_deq(xhci, xhci->cmd_ring, false);
1131 }
1132
1133 static void handle_vendor_event(struct xhci_hcd *xhci,
1134                 union xhci_trb *event)
1135 {
1136         u32 trb_type;
1137
1138         trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]);
1139         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1140         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1141                 handle_cmd_completion(xhci, &event->event_cmd);
1142 }
1143
1144 static void handle_port_status(struct xhci_hcd *xhci,
1145                 union xhci_trb *event)
1146 {
1147         u32 port_id;
1148
1149         /* Port status change events always have a successful completion code */
1150         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1151                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1152                 xhci->error_bitmask |= 1 << 8;
1153         }
1154         /* FIXME: core doesn't care about all port link state changes yet */
1155         port_id = GET_PORT_ID(event->generic.field[0]);
1156         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1157
1158         /* Update event ring dequeue pointer before dropping the lock */
1159         inc_deq(xhci, xhci->event_ring, true);
1160
1161         spin_unlock(&xhci->lock);
1162         /* Pass this up to the core */
1163         usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
1164         spin_lock(&xhci->lock);
1165 }
1166
1167 /*
1168  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1169  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1170  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1171  * returns 0.
1172  */
1173 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1174                 union xhci_trb  *start_trb,
1175                 union xhci_trb  *end_trb,
1176                 dma_addr_t      suspect_dma)
1177 {
1178         dma_addr_t start_dma;
1179         dma_addr_t end_seg_dma;
1180         dma_addr_t end_trb_dma;
1181         struct xhci_segment *cur_seg;
1182
1183         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1184         cur_seg = start_seg;
1185
1186         do {
1187                 if (start_dma == 0)
1188                         return NULL;
1189                 /* We may get an event for a Link TRB in the middle of a TD */
1190                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1191                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1192                 /* If the end TRB isn't in this segment, this is set to 0 */
1193                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1194
1195                 if (end_trb_dma > 0) {
1196                         /* The end TRB is in this segment, so suspect should be here */
1197                         if (start_dma <= end_trb_dma) {
1198                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1199                                         return cur_seg;
1200                         } else {
1201                                 /* Case for one segment with
1202                                  * a TD wrapped around to the top
1203                                  */
1204                                 if ((suspect_dma >= start_dma &&
1205                                                         suspect_dma <= end_seg_dma) ||
1206                                                 (suspect_dma >= cur_seg->dma &&
1207                                                  suspect_dma <= end_trb_dma))
1208                                         return cur_seg;
1209                         }
1210                         return NULL;
1211                 } else {
1212                         /* Might still be somewhere in this segment */
1213                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1214                                 return cur_seg;
1215                 }
1216                 cur_seg = cur_seg->next;
1217                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1218         } while (cur_seg != start_seg);
1219
1220         return NULL;
1221 }
1222
1223 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1224                 unsigned int slot_id, unsigned int ep_index,
1225                 unsigned int stream_id,
1226                 struct xhci_td *td, union xhci_trb *event_trb)
1227 {
1228         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1229         ep->ep_state |= EP_HALTED;
1230         ep->stopped_td = td;
1231         ep->stopped_trb = event_trb;
1232         ep->stopped_stream = stream_id;
1233
1234         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1235         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1236
1237         ep->stopped_td = NULL;
1238         ep->stopped_trb = NULL;
1239         ep->stopped_stream = 0;
1240
1241         xhci_ring_cmd_db(xhci);
1242 }
1243
1244 /* Check if an error has halted the endpoint ring.  The class driver will
1245  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1246  * However, a babble and other errors also halt the endpoint ring, and the class
1247  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1248  * Ring Dequeue Pointer command manually.
1249  */
1250 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1251                 struct xhci_ep_ctx *ep_ctx,
1252                 unsigned int trb_comp_code)
1253 {
1254         /* TRB completion codes that may require a manual halt cleanup */
1255         if (trb_comp_code == COMP_TX_ERR ||
1256                         trb_comp_code == COMP_BABBLE ||
1257                         trb_comp_code == COMP_SPLIT_ERR)
1258                 /* The 0.96 spec says a babbling control endpoint
1259                  * is not halted. The 0.96 spec says it is.  Some HW
1260                  * claims to be 0.95 compliant, but it halts the control
1261                  * endpoint anyway.  Check if a babble halted the
1262                  * endpoint.
1263                  */
1264                 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1265                         return 1;
1266
1267         return 0;
1268 }
1269
1270 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1271 {
1272         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1273                 /* Vendor defined "informational" completion code,
1274                  * treat as not-an-error.
1275                  */
1276                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1277                                 trb_comp_code);
1278                 xhci_dbg(xhci, "Treating code as success.\n");
1279                 return 1;
1280         }
1281         return 0;
1282 }
1283
1284 /*
1285  * Finish the td processing, remove the td from td list;
1286  * Return 1 if the urb can be given back.
1287  */
1288 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1289         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1290         struct xhci_virt_ep *ep, int *status, bool skip)
1291 {
1292         struct xhci_virt_device *xdev;
1293         struct xhci_ring *ep_ring;
1294         unsigned int slot_id;
1295         int ep_index;
1296         struct urb *urb = NULL;
1297         struct xhci_ep_ctx *ep_ctx;
1298         int ret = 0;
1299         struct urb_priv *urb_priv;
1300         u32 trb_comp_code;
1301
1302         slot_id = TRB_TO_SLOT_ID(event->flags);
1303         xdev = xhci->devs[slot_id];
1304         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1305         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1306         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1307         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1308
1309         if (skip)
1310                 goto td_cleanup;
1311
1312         if (trb_comp_code == COMP_STOP_INVAL ||
1313                         trb_comp_code == COMP_STOP) {
1314                 /* The Endpoint Stop Command completion will take care of any
1315                  * stopped TDs.  A stopped TD may be restarted, so don't update
1316                  * the ring dequeue pointer or take this TD off any lists yet.
1317                  */
1318                 ep->stopped_td = td;
1319                 ep->stopped_trb = event_trb;
1320                 return 0;
1321         } else {
1322                 if (trb_comp_code == COMP_STALL) {
1323                         /* The transfer is completed from the driver's
1324                          * perspective, but we need to issue a set dequeue
1325                          * command for this stalled endpoint to move the dequeue
1326                          * pointer past the TD.  We can't do that here because
1327                          * the halt condition must be cleared first.  Let the
1328                          * USB class driver clear the stall later.
1329                          */
1330                         ep->stopped_td = td;
1331                         ep->stopped_trb = event_trb;
1332                         ep->stopped_stream = ep_ring->stream_id;
1333                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1334                                         ep_ctx, trb_comp_code)) {
1335                         /* Other types of errors halt the endpoint, but the
1336                          * class driver doesn't call usb_reset_endpoint() unless
1337                          * the error is -EPIPE.  Clear the halted status in the
1338                          * xHCI hardware manually.
1339                          */
1340                         xhci_cleanup_halted_endpoint(xhci,
1341                                         slot_id, ep_index, ep_ring->stream_id,
1342                                         td, event_trb);
1343                 } else {
1344                         /* Update ring dequeue pointer */
1345                         while (ep_ring->dequeue != td->last_trb)
1346                                 inc_deq(xhci, ep_ring, false);
1347                         inc_deq(xhci, ep_ring, false);
1348                 }
1349
1350 td_cleanup:
1351                 /* Clean up the endpoint's TD list */
1352                 urb = td->urb;
1353                 urb_priv = urb->hcpriv;
1354
1355                 /* Do one last check of the actual transfer length.
1356                  * If the host controller said we transferred more data than
1357                  * the buffer length, urb->actual_length will be a very big
1358                  * number (since it's unsigned).  Play it safe and say we didn't
1359                  * transfer anything.
1360                  */
1361                 if (urb->actual_length > urb->transfer_buffer_length) {
1362                         xhci_warn(xhci, "URB transfer length is wrong, "
1363                                         "xHC issue? req. len = %u, "
1364                                         "act. len = %u\n",
1365                                         urb->transfer_buffer_length,
1366                                         urb->actual_length);
1367                         urb->actual_length = 0;
1368                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1369                                 *status = -EREMOTEIO;
1370                         else
1371                                 *status = 0;
1372                 }
1373                 list_del(&td->td_list);
1374                 /* Was this TD slated to be cancelled but completed anyway? */
1375                 if (!list_empty(&td->cancelled_td_list))
1376                         list_del(&td->cancelled_td_list);
1377
1378                 urb_priv->td_cnt++;
1379                 /* Giveback the urb when all the tds are completed */
1380                 if (urb_priv->td_cnt == urb_priv->length)
1381                         ret = 1;
1382         }
1383
1384         return ret;
1385 }
1386
1387 /*
1388  * Process control tds, update urb status and actual_length.
1389  */
1390 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1391         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1392         struct xhci_virt_ep *ep, int *status)
1393 {
1394         struct xhci_virt_device *xdev;
1395         struct xhci_ring *ep_ring;
1396         unsigned int slot_id;
1397         int ep_index;
1398         struct xhci_ep_ctx *ep_ctx;
1399         u32 trb_comp_code;
1400
1401         slot_id = TRB_TO_SLOT_ID(event->flags);
1402         xdev = xhci->devs[slot_id];
1403         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1404         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1405         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1406         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1407
1408         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1409         switch (trb_comp_code) {
1410         case COMP_SUCCESS:
1411                 if (event_trb == ep_ring->dequeue) {
1412                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1413                                         "without IOC set??\n");
1414                         *status = -ESHUTDOWN;
1415                 } else if (event_trb != td->last_trb) {
1416                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1417                                         "without IOC set??\n");
1418                         *status = -ESHUTDOWN;
1419                 } else {
1420                         xhci_dbg(xhci, "Successful control transfer!\n");
1421                         *status = 0;
1422                 }
1423                 break;
1424         case COMP_SHORT_TX:
1425                 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1426                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1427                         *status = -EREMOTEIO;
1428                 else
1429                         *status = 0;
1430                 break;
1431         default:
1432                 if (!xhci_requires_manual_halt_cleanup(xhci,
1433                                         ep_ctx, trb_comp_code))
1434                         break;
1435                 xhci_dbg(xhci, "TRB error code %u, "
1436                                 "halted endpoint index = %u\n",
1437                                 trb_comp_code, ep_index);
1438                 /* else fall through */
1439         case COMP_STALL:
1440                 /* Did we transfer part of the data (middle) phase? */
1441                 if (event_trb != ep_ring->dequeue &&
1442                                 event_trb != td->last_trb)
1443                         td->urb->actual_length =
1444                                 td->urb->transfer_buffer_length
1445                                 - TRB_LEN(event->transfer_len);
1446                 else
1447                         td->urb->actual_length = 0;
1448
1449                 xhci_cleanup_halted_endpoint(xhci,
1450                         slot_id, ep_index, 0, td, event_trb);
1451                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1452         }
1453         /*
1454          * Did we transfer any data, despite the errors that might have
1455          * happened?  I.e. did we get past the setup stage?
1456          */
1457         if (event_trb != ep_ring->dequeue) {
1458                 /* The event was for the status stage */
1459                 if (event_trb == td->last_trb) {
1460                         if (td->urb->actual_length != 0) {
1461                                 /* Don't overwrite a previously set error code
1462                                  */
1463                                 if ((*status == -EINPROGRESS || *status == 0) &&
1464                                                 (td->urb->transfer_flags
1465                                                  & URB_SHORT_NOT_OK))
1466                                         /* Did we already see a short data
1467                                          * stage? */
1468                                         *status = -EREMOTEIO;
1469                         } else {
1470                                 td->urb->actual_length =
1471                                         td->urb->transfer_buffer_length;
1472                         }
1473                 } else {
1474                 /* Maybe the event was for the data stage? */
1475                         if (trb_comp_code != COMP_STOP_INVAL) {
1476                                 /* We didn't stop on a link TRB in the middle */
1477                                 td->urb->actual_length =
1478                                         td->urb->transfer_buffer_length -
1479                                         TRB_LEN(event->transfer_len);
1480                                 xhci_dbg(xhci, "Waiting for status "
1481                                                 "stage event\n");
1482                                 return 0;
1483                         }
1484                 }
1485         }
1486
1487         return finish_td(xhci, td, event_trb, event, ep, status, false);
1488 }
1489
1490 /*
1491  * Process isochronous tds, update urb packet status and actual_length.
1492  */
1493 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1494         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1495         struct xhci_virt_ep *ep, int *status)
1496 {
1497         struct xhci_ring *ep_ring;
1498         struct urb_priv *urb_priv;
1499         int idx;
1500         int len = 0;
1501         int skip_td = 0;
1502         union xhci_trb *cur_trb;
1503         struct xhci_segment *cur_seg;
1504         u32 trb_comp_code;
1505
1506         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1507         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1508         urb_priv = td->urb->hcpriv;
1509         idx = urb_priv->td_cnt;
1510
1511         if (ep->skip) {
1512                 /* The transfer is partly done */
1513                 *status = -EXDEV;
1514                 td->urb->iso_frame_desc[idx].status = -EXDEV;
1515         } else {
1516                 /* handle completion code */
1517                 switch (trb_comp_code) {
1518                 case COMP_SUCCESS:
1519                         td->urb->iso_frame_desc[idx].status = 0;
1520                         xhci_dbg(xhci, "Successful isoc transfer!\n");
1521                         break;
1522                 case COMP_SHORT_TX:
1523                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1524                                 td->urb->iso_frame_desc[idx].status =
1525                                          -EREMOTEIO;
1526                         else
1527                                 td->urb->iso_frame_desc[idx].status = 0;
1528                         break;
1529                 case COMP_BW_OVER:
1530                         td->urb->iso_frame_desc[idx].status = -ECOMM;
1531                         skip_td = 1;
1532                         break;
1533                 case COMP_BUFF_OVER:
1534                 case COMP_BABBLE:
1535                         td->urb->iso_frame_desc[idx].status = -EOVERFLOW;
1536                         skip_td = 1;
1537                         break;
1538                 case COMP_STALL:
1539                         td->urb->iso_frame_desc[idx].status = -EPROTO;
1540                         skip_td = 1;
1541                         break;
1542                 case COMP_STOP:
1543                 case COMP_STOP_INVAL:
1544                         break;
1545                 default:
1546                         td->urb->iso_frame_desc[idx].status = -1;
1547                         break;
1548                 }
1549         }
1550
1551         /* calc actual length */
1552         if (ep->skip) {
1553                 td->urb->iso_frame_desc[idx].actual_length = 0;
1554                 /* Update ring dequeue pointer */
1555                 while (ep_ring->dequeue != td->last_trb)
1556                         inc_deq(xhci, ep_ring, false);
1557                 inc_deq(xhci, ep_ring, false);
1558                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1559         }
1560
1561         if (trb_comp_code == COMP_SUCCESS || skip_td == 1) {
1562                 td->urb->iso_frame_desc[idx].actual_length =
1563                         td->urb->iso_frame_desc[idx].length;
1564                 td->urb->actual_length +=
1565                         td->urb->iso_frame_desc[idx].length;
1566         } else {
1567                 for (cur_trb = ep_ring->dequeue,
1568                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1569                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1570                         if ((cur_trb->generic.field[3] &
1571                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1572                             (cur_trb->generic.field[3] &
1573                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1574                                 len +=
1575                                     TRB_LEN(cur_trb->generic.field[2]);
1576                 }
1577                 len += TRB_LEN(cur_trb->generic.field[2]) -
1578                         TRB_LEN(event->transfer_len);
1579
1580                 if (trb_comp_code != COMP_STOP_INVAL) {
1581                         td->urb->iso_frame_desc[idx].actual_length = len;
1582                         td->urb->actual_length += len;
1583                 }
1584         }
1585
1586         if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS)
1587                 *status = 0;
1588
1589         return finish_td(xhci, td, event_trb, event, ep, status, false);
1590 }
1591
1592 /*
1593  * Process bulk and interrupt tds, update urb status and actual_length.
1594  */
1595 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1596         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1597         struct xhci_virt_ep *ep, int *status)
1598 {
1599         struct xhci_ring *ep_ring;
1600         union xhci_trb *cur_trb;
1601         struct xhci_segment *cur_seg;
1602         u32 trb_comp_code;
1603
1604         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1605         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1606
1607         switch (trb_comp_code) {
1608         case COMP_SUCCESS:
1609                 /* Double check that the HW transferred everything. */
1610                 if (event_trb != td->last_trb) {
1611                         xhci_warn(xhci, "WARN Successful completion "
1612                                         "on short TX\n");
1613                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1614                                 *status = -EREMOTEIO;
1615                         else
1616                                 *status = 0;
1617                 } else {
1618                         if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1619                                 xhci_dbg(xhci, "Successful bulk "
1620                                                 "transfer!\n");
1621                         else
1622                                 xhci_dbg(xhci, "Successful interrupt "
1623                                                 "transfer!\n");
1624                         *status = 0;
1625                 }
1626                 break;
1627         case COMP_SHORT_TX:
1628                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1629                         *status = -EREMOTEIO;
1630                 else
1631                         *status = 0;
1632                 break;
1633         default:
1634                 /* Others already handled above */
1635                 break;
1636         }
1637         dev_dbg(&td->urb->dev->dev,
1638                         "ep %#x - asked for %d bytes, "
1639                         "%d bytes untransferred\n",
1640                         td->urb->ep->desc.bEndpointAddress,
1641                         td->urb->transfer_buffer_length,
1642                         TRB_LEN(event->transfer_len));
1643         /* Fast path - was this the last TRB in the TD for this URB? */
1644         if (event_trb == td->last_trb) {
1645                 if (TRB_LEN(event->transfer_len) != 0) {
1646                         td->urb->actual_length =
1647                                 td->urb->transfer_buffer_length -
1648                                 TRB_LEN(event->transfer_len);
1649                         if (td->urb->transfer_buffer_length <
1650                                         td->urb->actual_length) {
1651                                 xhci_warn(xhci, "HC gave bad length "
1652                                                 "of %d bytes left\n",
1653                                                 TRB_LEN(event->transfer_len));
1654                                 td->urb->actual_length = 0;
1655                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1656                                         *status = -EREMOTEIO;
1657                                 else
1658                                         *status = 0;
1659                         }
1660                         /* Don't overwrite a previously set error code */
1661                         if (*status == -EINPROGRESS) {
1662                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1663                                         *status = -EREMOTEIO;
1664                                 else
1665                                         *status = 0;
1666                         }
1667                 } else {
1668                         td->urb->actual_length =
1669                                 td->urb->transfer_buffer_length;
1670                         /* Ignore a short packet completion if the
1671                          * untransferred length was zero.
1672                          */
1673                         if (*status == -EREMOTEIO)
1674                                 *status = 0;
1675                 }
1676         } else {
1677                 /* Slow path - walk the list, starting from the dequeue
1678                  * pointer, to get the actual length transferred.
1679                  */
1680                 td->urb->actual_length = 0;
1681                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1682                                 cur_trb != event_trb;
1683                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1684                         if ((cur_trb->generic.field[3] &
1685                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1686                             (cur_trb->generic.field[3] &
1687                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1688                                 td->urb->actual_length +=
1689                                         TRB_LEN(cur_trb->generic.field[2]);
1690                 }
1691                 /* If the ring didn't stop on a Link or No-op TRB, add
1692                  * in the actual bytes transferred from the Normal TRB
1693                  */
1694                 if (trb_comp_code != COMP_STOP_INVAL)
1695                         td->urb->actual_length +=
1696                                 TRB_LEN(cur_trb->generic.field[2]) -
1697                                 TRB_LEN(event->transfer_len);
1698         }
1699
1700         return finish_td(xhci, td, event_trb, event, ep, status, false);
1701 }
1702
1703 /*
1704  * If this function returns an error condition, it means it got a Transfer
1705  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1706  * At this point, the host controller is probably hosed and should be reset.
1707  */
1708 static int handle_tx_event(struct xhci_hcd *xhci,
1709                 struct xhci_transfer_event *event)
1710 {
1711         struct xhci_virt_device *xdev;
1712         struct xhci_virt_ep *ep;
1713         struct xhci_ring *ep_ring;
1714         unsigned int slot_id;
1715         int ep_index;
1716         struct xhci_td *td = NULL;
1717         dma_addr_t event_dma;
1718         struct xhci_segment *event_seg;
1719         union xhci_trb *event_trb;
1720         struct urb *urb = NULL;
1721         int status = -EINPROGRESS;
1722         struct urb_priv *urb_priv;
1723         struct xhci_ep_ctx *ep_ctx;
1724         u32 trb_comp_code;
1725         int ret = 0;
1726
1727         slot_id = TRB_TO_SLOT_ID(event->flags);
1728         xdev = xhci->devs[slot_id];
1729         if (!xdev) {
1730                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1731                 return -ENODEV;
1732         }
1733
1734         /* Endpoint ID is 1 based, our index is zero based */
1735         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1736         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1737         ep = &xdev->eps[ep_index];
1738         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1739         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1740         if (!ep_ring ||
1741                 (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1742                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1743                                 "or incorrect stream ring\n");
1744                 return -ENODEV;
1745         }
1746
1747         event_dma = event->buffer;
1748         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1749         /* Look for common error cases */
1750         switch (trb_comp_code) {
1751         /* Skip codes that require special handling depending on
1752          * transfer type
1753          */
1754         case COMP_SUCCESS:
1755         case COMP_SHORT_TX:
1756                 break;
1757         case COMP_STOP:
1758                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1759                 break;
1760         case COMP_STOP_INVAL:
1761                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1762                 break;
1763         case COMP_STALL:
1764                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1765                 ep->ep_state |= EP_HALTED;
1766                 status = -EPIPE;
1767                 break;
1768         case COMP_TRB_ERR:
1769                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1770                 status = -EILSEQ;
1771                 break;
1772         case COMP_SPLIT_ERR:
1773         case COMP_TX_ERR:
1774                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1775                 status = -EPROTO;
1776                 break;
1777         case COMP_BABBLE:
1778                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1779                 status = -EOVERFLOW;
1780                 break;
1781         case COMP_DB_ERR:
1782                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1783                 status = -ENOSR;
1784                 break;
1785         case COMP_BW_OVER:
1786                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
1787                 break;
1788         case COMP_BUFF_OVER:
1789                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
1790                 break;
1791         case COMP_UNDERRUN:
1792                 /*
1793                  * When the Isoch ring is empty, the xHC will generate
1794                  * a Ring Overrun Event for IN Isoch endpoint or Ring
1795                  * Underrun Event for OUT Isoch endpoint.
1796                  */
1797                 xhci_dbg(xhci, "underrun event on endpoint\n");
1798                 if (!list_empty(&ep_ring->td_list))
1799                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
1800                                         "still with TDs queued?\n",
1801                                 TRB_TO_SLOT_ID(event->flags), ep_index);
1802                 goto cleanup;
1803         case COMP_OVERRUN:
1804                 xhci_dbg(xhci, "overrun event on endpoint\n");
1805                 if (!list_empty(&ep_ring->td_list))
1806                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
1807                                         "still with TDs queued?\n",
1808                                 TRB_TO_SLOT_ID(event->flags), ep_index);
1809                 goto cleanup;
1810         case COMP_MISSED_INT:
1811                 /*
1812                  * When encounter missed service error, one or more isoc tds
1813                  * may be missed by xHC.
1814                  * Set skip flag of the ep_ring; Complete the missed tds as
1815                  * short transfer when process the ep_ring next time.
1816                  */
1817                 ep->skip = true;
1818                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
1819                 goto cleanup;
1820         default:
1821                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
1822                         status = 0;
1823                         break;
1824                 }
1825                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
1826                                 "busted\n");
1827                 goto cleanup;
1828         }
1829
1830         do {
1831                 /* This TRB should be in the TD at the head of this ring's
1832                  * TD list.
1833                  */
1834                 if (list_empty(&ep_ring->td_list)) {
1835                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
1836                                         "with no TDs queued?\n",
1837                                   TRB_TO_SLOT_ID(event->flags), ep_index);
1838                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1839                           (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1840                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
1841                         if (ep->skip) {
1842                                 ep->skip = false;
1843                                 xhci_dbg(xhci, "td_list is empty while skip "
1844                                                 "flag set. Clear skip flag.\n");
1845                         }
1846                         ret = 0;
1847                         goto cleanup;
1848                 }
1849
1850                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
1851                 /* Is this a TRB in the currently executing TD? */
1852                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1853                                 td->last_trb, event_dma);
1854                 if (event_seg && ep->skip) {
1855                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
1856                         ep->skip = false;
1857                 }
1858                 if (!event_seg &&
1859                    (!ep->skip || !usb_endpoint_xfer_isoc(&td->urb->ep->desc))) {
1860                         /* HC is busted, give up! */
1861                         xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not "
1862                                         "part of current TD\n");
1863                         return -ESHUTDOWN;
1864                 }
1865
1866                 if (event_seg) {
1867                         event_trb = &event_seg->trbs[(event_dma -
1868                                          event_seg->dma) / sizeof(*event_trb)];
1869                         /*
1870                          * No-op TRB should not trigger interrupts.
1871                          * If event_trb is a no-op TRB, it means the
1872                          * corresponding TD has been cancelled. Just ignore
1873                          * the TD.
1874                          */
1875                         if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK)
1876                                          == TRB_TYPE(TRB_TR_NOOP)) {
1877                                 xhci_dbg(xhci, "event_trb is a no-op TRB. "
1878                                                 "Skip it\n");
1879                                 goto cleanup;
1880                         }
1881                 }
1882
1883                 /* Now update the urb's actual_length and give back to
1884                  * the core
1885                  */
1886                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
1887                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
1888                                                  &status);
1889                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
1890                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
1891                                                  &status);
1892                 else
1893                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
1894                                                  ep, &status);
1895
1896 cleanup:
1897                 /*
1898                  * Do not update event ring dequeue pointer if ep->skip is set.
1899                  * Will roll back to continue process missed tds.
1900                  */
1901                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
1902                         inc_deq(xhci, xhci->event_ring, true);
1903                 }
1904
1905                 if (ret) {
1906                         urb = td->urb;
1907                         urb_priv = urb->hcpriv;
1908                         /* Leave the TD around for the reset endpoint function
1909                          * to use(but only if it's not a control endpoint,
1910                          * since we already queued the Set TR dequeue pointer
1911                          * command for stalled control endpoints).
1912                          */
1913                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1914                                 (trb_comp_code != COMP_STALL &&
1915                                         trb_comp_code != COMP_BABBLE))
1916                                 xhci_urb_free_priv(xhci, urb_priv);
1917
1918                         usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1919                         xhci_dbg(xhci, "Giveback URB %p, len = %d, "
1920                                         "status = %d\n",
1921                                         urb, urb->actual_length, status);
1922                         spin_unlock(&xhci->lock);
1923                         usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1924                         spin_lock(&xhci->lock);
1925                 }
1926
1927         /*
1928          * If ep->skip is set, it means there are missed tds on the
1929          * endpoint ring need to take care of.
1930          * Process them as short transfer until reach the td pointed by
1931          * the event.
1932          */
1933         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
1934
1935         return 0;
1936 }
1937
1938 /*
1939  * This function handles all OS-owned events on the event ring.  It may drop
1940  * xhci->lock between event processing (e.g. to pass up port status changes).
1941  */
1942 static void xhci_handle_event(struct xhci_hcd *xhci)
1943 {
1944         union xhci_trb *event;
1945         int update_ptrs = 1;
1946         int ret;
1947
1948         xhci_dbg(xhci, "In %s\n", __func__);
1949         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1950                 xhci->error_bitmask |= 1 << 1;
1951                 return;
1952         }
1953
1954         event = xhci->event_ring->dequeue;
1955         /* Does the HC or OS own the TRB? */
1956         if ((event->event_cmd.flags & TRB_CYCLE) !=
1957                         xhci->event_ring->cycle_state) {
1958                 xhci->error_bitmask |= 1 << 2;
1959                 return;
1960         }
1961         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1962
1963         /* FIXME: Handle more event types. */
1964         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1965         case TRB_TYPE(TRB_COMPLETION):
1966                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1967                 handle_cmd_completion(xhci, &event->event_cmd);
1968                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1969                 break;
1970         case TRB_TYPE(TRB_PORT_STATUS):
1971                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1972                 handle_port_status(xhci, event);
1973                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1974                 update_ptrs = 0;
1975                 break;
1976         case TRB_TYPE(TRB_TRANSFER):
1977                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1978                 ret = handle_tx_event(xhci, &event->trans_event);
1979                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1980                 if (ret < 0)
1981                         xhci->error_bitmask |= 1 << 9;
1982                 else
1983                         update_ptrs = 0;
1984                 break;
1985         default:
1986                 if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48))
1987                         handle_vendor_event(xhci, event);
1988                 else
1989                         xhci->error_bitmask |= 1 << 3;
1990         }
1991         /* Any of the above functions may drop and re-acquire the lock, so check
1992          * to make sure a watchdog timer didn't mark the host as non-responsive.
1993          */
1994         if (xhci->xhc_state & XHCI_STATE_DYING) {
1995                 xhci_dbg(xhci, "xHCI host dying, returning from "
1996                                 "event handler.\n");
1997                 return;
1998         }
1999
2000         if (update_ptrs)
2001                 /* Update SW event ring dequeue pointer */
2002                 inc_deq(xhci, xhci->event_ring, true);
2003
2004         /* Are there more items on the event ring? */
2005         xhci_handle_event(xhci);
2006 }
2007
2008 /*
2009  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2010  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2011  * indicators of an event TRB error, but we check the status *first* to be safe.
2012  */
2013 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2014 {
2015         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2016         u32 status;
2017         union xhci_trb *trb;
2018         u64 temp_64;
2019         union xhci_trb *event_ring_deq;
2020         dma_addr_t deq;
2021
2022         spin_lock(&xhci->lock);
2023         trb = xhci->event_ring->dequeue;
2024         /* Check if the xHC generated the interrupt, or the irq is shared */
2025         status = xhci_readl(xhci, &xhci->op_regs->status);
2026         if (status == 0xffffffff)
2027                 goto hw_died;
2028
2029         if (!(status & STS_EINT)) {
2030                 spin_unlock(&xhci->lock);
2031                 xhci_warn(xhci, "Spurious interrupt.\n");
2032                 return IRQ_NONE;
2033         }
2034         xhci_dbg(xhci, "op reg status = %08x\n", status);
2035         xhci_dbg(xhci, "Event ring dequeue ptr:\n");
2036         xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n",
2037                         (unsigned long long)
2038                         xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
2039                         lower_32_bits(trb->link.segment_ptr),
2040                         upper_32_bits(trb->link.segment_ptr),
2041                         (unsigned int) trb->link.intr_target,
2042                         (unsigned int) trb->link.control);
2043
2044         if (status & STS_FATAL) {
2045                 xhci_warn(xhci, "WARNING: Host System Error\n");
2046                 xhci_halt(xhci);
2047 hw_died:
2048                 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
2049                 spin_unlock(&xhci->lock);
2050                 return -ESHUTDOWN;
2051         }
2052
2053         /*
2054          * Clear the op reg interrupt status first,
2055          * so we can receive interrupts from other MSI-X interrupters.
2056          * Write 1 to clear the interrupt status.
2057          */
2058         status |= STS_EINT;
2059         xhci_writel(xhci, status, &xhci->op_regs->status);
2060         /* FIXME when MSI-X is supported and there are multiple vectors */
2061         /* Clear the MSI-X event interrupt status */
2062
2063         if (hcd->irq != -1) {
2064                 u32 irq_pending;
2065                 /* Acknowledge the PCI interrupt */
2066                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2067                 irq_pending |= 0x3;
2068                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2069         }
2070
2071         if (xhci->xhc_state & XHCI_STATE_DYING) {
2072                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2073                                 "Shouldn't IRQs be disabled?\n");
2074                 /* Clear the event handler busy flag (RW1C);
2075                  * the event ring should be empty.
2076                  */
2077                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2078                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2079                                 &xhci->ir_set->erst_dequeue);
2080                 spin_unlock(&xhci->lock);
2081
2082                 return IRQ_HANDLED;
2083         }
2084
2085         event_ring_deq = xhci->event_ring->dequeue;
2086         /* FIXME this should be a delayed service routine
2087          * that clears the EHB.
2088          */
2089         xhci_handle_event(xhci);
2090
2091         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2092         /* If necessary, update the HW's version of the event ring deq ptr. */
2093         if (event_ring_deq != xhci->event_ring->dequeue) {
2094                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2095                                 xhci->event_ring->dequeue);
2096                 if (deq == 0)
2097                         xhci_warn(xhci, "WARN something wrong with SW event "
2098                                         "ring dequeue ptr.\n");
2099                 /* Update HC event ring dequeue pointer */
2100                 temp_64 &= ERST_PTR_MASK;
2101                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2102         }
2103
2104         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2105         temp_64 |= ERST_EHB;
2106         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2107
2108         spin_unlock(&xhci->lock);
2109
2110         return IRQ_HANDLED;
2111 }
2112
2113 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2114 {
2115         irqreturn_t ret;
2116
2117         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2118
2119         ret = xhci_irq(hcd);
2120
2121         return ret;
2122 }
2123
2124 /****           Endpoint Ring Operations        ****/
2125
2126 /*
2127  * Generic function for queueing a TRB on a ring.
2128  * The caller must have checked to make sure there's room on the ring.
2129  *
2130  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2131  *                      prepare_transfer()?
2132  */
2133 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2134                 bool consumer, bool more_trbs_coming,
2135                 u32 field1, u32 field2, u32 field3, u32 field4)
2136 {
2137         struct xhci_generic_trb *trb;
2138
2139         trb = &ring->enqueue->generic;
2140         trb->field[0] = field1;
2141         trb->field[1] = field2;
2142         trb->field[2] = field3;
2143         trb->field[3] = field4;
2144         inc_enq(xhci, ring, consumer, more_trbs_coming);
2145 }
2146
2147 /*
2148  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2149  * FIXME allocate segments if the ring is full.
2150  */
2151 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2152                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2153 {
2154         /* Make sure the endpoint has been added to xHC schedule */
2155         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
2156         switch (ep_state) {
2157         case EP_STATE_DISABLED:
2158                 /*
2159                  * USB core changed config/interfaces without notifying us,
2160                  * or hardware is reporting the wrong state.
2161                  */
2162                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2163                 return -ENOENT;
2164         case EP_STATE_ERROR:
2165                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2166                 /* FIXME event handling code for error needs to clear it */
2167                 /* XXX not sure if this should be -ENOENT or not */
2168                 return -EINVAL;
2169         case EP_STATE_HALTED:
2170                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2171         case EP_STATE_STOPPED:
2172         case EP_STATE_RUNNING:
2173                 break;
2174         default:
2175                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2176                 /*
2177                  * FIXME issue Configure Endpoint command to try to get the HC
2178                  * back into a known state.
2179                  */
2180                 return -EINVAL;
2181         }
2182         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2183                 /* FIXME allocate more room */
2184                 xhci_err(xhci, "ERROR no room on ep ring\n");
2185                 return -ENOMEM;
2186         }
2187
2188         if (enqueue_is_link_trb(ep_ring)) {
2189                 struct xhci_ring *ring = ep_ring;
2190                 union xhci_trb *next;
2191
2192                 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
2193                 next = ring->enqueue;
2194
2195                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2196
2197                         /* If we're not dealing with 0.95 hardware,
2198                          * clear the chain bit.
2199                          */
2200                         if (!xhci_link_trb_quirk(xhci))
2201                                 next->link.control &= ~TRB_CHAIN;
2202                         else
2203                                 next->link.control |= TRB_CHAIN;
2204
2205                         wmb();
2206                         next->link.control ^= (u32) TRB_CYCLE;
2207
2208                         /* Toggle the cycle bit after the last ring segment. */
2209                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2210                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2211                                 if (!in_interrupt()) {
2212                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2213                                                 "state for ring %p = %i\n",
2214                                                 ring, (unsigned int)ring->cycle_state);
2215                                 }
2216                         }
2217                         ring->enq_seg = ring->enq_seg->next;
2218                         ring->enqueue = ring->enq_seg->trbs;
2219                         next = ring->enqueue;
2220                 }
2221         }
2222
2223         return 0;
2224 }
2225
2226 static int prepare_transfer(struct xhci_hcd *xhci,
2227                 struct xhci_virt_device *xdev,
2228                 unsigned int ep_index,
2229                 unsigned int stream_id,
2230                 unsigned int num_trbs,
2231                 struct urb *urb,
2232                 unsigned int td_index,
2233                 gfp_t mem_flags)
2234 {
2235         int ret;
2236         struct urb_priv *urb_priv;
2237         struct xhci_td  *td;
2238         struct xhci_ring *ep_ring;
2239         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2240
2241         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2242         if (!ep_ring) {
2243                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2244                                 stream_id);
2245                 return -EINVAL;
2246         }
2247
2248         ret = prepare_ring(xhci, ep_ring,
2249                         ep_ctx->ep_info & EP_STATE_MASK,
2250                         num_trbs, mem_flags);
2251         if (ret)
2252                 return ret;
2253
2254         urb_priv = urb->hcpriv;
2255         td = urb_priv->td[td_index];
2256
2257         INIT_LIST_HEAD(&td->td_list);
2258         INIT_LIST_HEAD(&td->cancelled_td_list);
2259
2260         if (td_index == 0) {
2261                 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
2262                 if (unlikely(ret)) {
2263                         xhci_urb_free_priv(xhci, urb_priv);
2264                         urb->hcpriv = NULL;
2265                         return ret;
2266                 }
2267         }
2268
2269         td->urb = urb;
2270         /* Add this TD to the tail of the endpoint ring's TD list */
2271         list_add_tail(&td->td_list, &ep_ring->td_list);
2272         td->start_seg = ep_ring->enq_seg;
2273         td->first_trb = ep_ring->enqueue;
2274
2275         urb_priv->td[td_index] = td;
2276
2277         return 0;
2278 }
2279
2280 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2281 {
2282         int num_sgs, num_trbs, running_total, temp, i;
2283         struct scatterlist *sg;
2284
2285         sg = NULL;
2286         num_sgs = urb->num_sgs;
2287         temp = urb->transfer_buffer_length;
2288
2289         xhci_dbg(xhci, "count sg list trbs: \n");
2290         num_trbs = 0;
2291         for_each_sg(urb->sg, sg, num_sgs, i) {
2292                 unsigned int previous_total_trbs = num_trbs;
2293                 unsigned int len = sg_dma_len(sg);
2294
2295                 /* Scatter gather list entries may cross 64KB boundaries */
2296                 running_total = TRB_MAX_BUFF_SIZE -
2297                         (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2298                 if (running_total != 0)
2299                         num_trbs++;
2300
2301                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2302                 while (running_total < sg_dma_len(sg)) {
2303                         num_trbs++;
2304                         running_total += TRB_MAX_BUFF_SIZE;
2305                 }
2306                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2307                                 i, (unsigned long long)sg_dma_address(sg),
2308                                 len, len, num_trbs - previous_total_trbs);
2309
2310                 len = min_t(int, len, temp);
2311                 temp -= len;
2312                 if (temp == 0)
2313                         break;
2314         }
2315         xhci_dbg(xhci, "\n");
2316         if (!in_interrupt())
2317                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
2318                                 urb->ep->desc.bEndpointAddress,
2319                                 urb->transfer_buffer_length,
2320                                 num_trbs);
2321         return num_trbs;
2322 }
2323
2324 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2325 {
2326         if (num_trbs != 0)
2327                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2328                                 "TRBs, %d left\n", __func__,
2329                                 urb->ep->desc.bEndpointAddress, num_trbs);
2330         if (running_total != urb->transfer_buffer_length)
2331                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2332                                 "queued %#x (%d), asked for %#x (%d)\n",
2333                                 __func__,
2334                                 urb->ep->desc.bEndpointAddress,
2335                                 running_total, running_total,
2336                                 urb->transfer_buffer_length,
2337                                 urb->transfer_buffer_length);
2338 }
2339
2340 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2341                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2342                 struct xhci_generic_trb *start_trb, struct xhci_td *td)
2343 {
2344         /*
2345          * Pass all the TRBs to the hardware at once and make sure this write
2346          * isn't reordered.
2347          */
2348         wmb();
2349         start_trb->field[3] |= start_cycle;
2350         ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2351 }
2352
2353 /*
2354  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2355  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2356  * (comprised of sg list entries) can take several service intervals to
2357  * transmit.
2358  */
2359 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2360                 struct urb *urb, int slot_id, unsigned int ep_index)
2361 {
2362         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2363                         xhci->devs[slot_id]->out_ctx, ep_index);
2364         int xhci_interval;
2365         int ep_interval;
2366
2367         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2368         ep_interval = urb->interval;
2369         /* Convert to microframes */
2370         if (urb->dev->speed == USB_SPEED_LOW ||
2371                         urb->dev->speed == USB_SPEED_FULL)
2372                 ep_interval *= 8;
2373         /* FIXME change this to a warning and a suggestion to use the new API
2374          * to set the polling interval (once the API is added).
2375          */
2376         if (xhci_interval != ep_interval) {
2377                 if (!printk_ratelimit())
2378                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2379                                         " (%d microframe%s) than xHCI "
2380                                         "(%d microframe%s)\n",
2381                                         ep_interval,
2382                                         ep_interval == 1 ? "" : "s",
2383                                         xhci_interval,
2384                                         xhci_interval == 1 ? "" : "s");
2385                 urb->interval = xhci_interval;
2386                 /* Convert back to frames for LS/FS devices */
2387                 if (urb->dev->speed == USB_SPEED_LOW ||
2388                                 urb->dev->speed == USB_SPEED_FULL)
2389                         urb->interval /= 8;
2390         }
2391         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2392 }
2393
2394 /*
2395  * The TD size is the number of bytes remaining in the TD (including this TRB),
2396  * right shifted by 10.
2397  * It must fit in bits 21:17, so it can't be bigger than 31.
2398  */
2399 static u32 xhci_td_remainder(unsigned int remainder)
2400 {
2401         u32 max = (1 << (21 - 17 + 1)) - 1;
2402
2403         if ((remainder >> 10) >= max)
2404                 return max << 17;
2405         else
2406                 return (remainder >> 10) << 17;
2407 }
2408
2409 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2410                 struct urb *urb, int slot_id, unsigned int ep_index)
2411 {
2412         struct xhci_ring *ep_ring;
2413         unsigned int num_trbs;
2414         struct urb_priv *urb_priv;
2415         struct xhci_td *td;
2416         struct scatterlist *sg;
2417         int num_sgs;
2418         int trb_buff_len, this_sg_len, running_total;
2419         bool first_trb;
2420         u64 addr;
2421         bool more_trbs_coming;
2422
2423         struct xhci_generic_trb *start_trb;
2424         int start_cycle;
2425
2426         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2427         if (!ep_ring)
2428                 return -EINVAL;
2429
2430         num_trbs = count_sg_trbs_needed(xhci, urb);
2431         num_sgs = urb->num_sgs;
2432
2433         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2434                         ep_index, urb->stream_id,
2435                         num_trbs, urb, 0, mem_flags);
2436         if (trb_buff_len < 0)
2437                 return trb_buff_len;
2438
2439         urb_priv = urb->hcpriv;
2440         td = urb_priv->td[0];
2441
2442         /*
2443          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2444          * until we've finished creating all the other TRBs.  The ring's cycle
2445          * state may change as we enqueue the other TRBs, so save it too.
2446          */
2447         start_trb = &ep_ring->enqueue->generic;
2448         start_cycle = ep_ring->cycle_state;
2449
2450         running_total = 0;
2451         /*
2452          * How much data is in the first TRB?
2453          *
2454          * There are three forces at work for TRB buffer pointers and lengths:
2455          * 1. We don't want to walk off the end of this sg-list entry buffer.
2456          * 2. The transfer length that the driver requested may be smaller than
2457          *    the amount of memory allocated for this scatter-gather list.
2458          * 3. TRBs buffers can't cross 64KB boundaries.
2459          */
2460         sg = urb->sg;
2461         addr = (u64) sg_dma_address(sg);
2462         this_sg_len = sg_dma_len(sg);
2463         trb_buff_len = TRB_MAX_BUFF_SIZE -
2464                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2465         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2466         if (trb_buff_len > urb->transfer_buffer_length)
2467                 trb_buff_len = urb->transfer_buffer_length;
2468         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2469                         trb_buff_len);
2470
2471         first_trb = true;
2472         /* Queue the first TRB, even if it's zero-length */
2473         do {
2474                 u32 field = 0;
2475                 u32 length_field = 0;
2476                 u32 remainder = 0;
2477
2478                 /* Don't change the cycle bit of the first TRB until later */
2479                 if (first_trb)
2480                         first_trb = false;
2481                 else
2482                         field |= ep_ring->cycle_state;
2483
2484                 /* Chain all the TRBs together; clear the chain bit in the last
2485                  * TRB to indicate it's the last TRB in the chain.
2486                  */
2487                 if (num_trbs > 1) {
2488                         field |= TRB_CHAIN;
2489                 } else {
2490                         /* FIXME - add check for ZERO_PACKET flag before this */
2491                         td->last_trb = ep_ring->enqueue;
2492                         field |= TRB_IOC;
2493                 }
2494                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2495                                 "64KB boundary at %#x, end dma = %#x\n",
2496                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
2497                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2498                                 (unsigned int) addr + trb_buff_len);
2499                 if (TRB_MAX_BUFF_SIZE -
2500                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
2501                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2502                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2503                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2504                                         (unsigned int) addr + trb_buff_len);
2505                 }
2506                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2507                                 running_total) ;
2508                 length_field = TRB_LEN(trb_buff_len) |
2509                         remainder |
2510                         TRB_INTR_TARGET(0);
2511                 if (num_trbs > 1)
2512                         more_trbs_coming = true;
2513                 else
2514                         more_trbs_coming = false;
2515                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2516                                 lower_32_bits(addr),
2517                                 upper_32_bits(addr),
2518                                 length_field,
2519                                 /* We always want to know if the TRB was short,
2520                                  * or we won't get an event when it completes.
2521                                  * (Unless we use event data TRBs, which are a
2522                                  * waste of space and HC resources.)
2523                                  */
2524                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2525                 --num_trbs;
2526                 running_total += trb_buff_len;
2527
2528                 /* Calculate length for next transfer --
2529                  * Are we done queueing all the TRBs for this sg entry?
2530                  */
2531                 this_sg_len -= trb_buff_len;
2532                 if (this_sg_len == 0) {
2533                         --num_sgs;
2534                         if (num_sgs == 0)
2535                                 break;
2536                         sg = sg_next(sg);
2537                         addr = (u64) sg_dma_address(sg);
2538                         this_sg_len = sg_dma_len(sg);
2539                 } else {
2540                         addr += trb_buff_len;
2541                 }
2542
2543                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2544                         (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2545                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2546                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2547                         trb_buff_len =
2548                                 urb->transfer_buffer_length - running_total;
2549         } while (running_total < urb->transfer_buffer_length);
2550
2551         check_trb_math(urb, num_trbs, running_total);
2552         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2553                         start_cycle, start_trb, td);
2554         return 0;
2555 }
2556
2557 /* This is very similar to what ehci-q.c qtd_fill() does */
2558 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2559                 struct urb *urb, int slot_id, unsigned int ep_index)
2560 {
2561         struct xhci_ring *ep_ring;
2562         struct urb_priv *urb_priv;
2563         struct xhci_td *td;
2564         int num_trbs;
2565         struct xhci_generic_trb *start_trb;
2566         bool first_trb;
2567         bool more_trbs_coming;
2568         int start_cycle;
2569         u32 field, length_field;
2570
2571         int running_total, trb_buff_len, ret;
2572         u64 addr;
2573
2574         if (urb->num_sgs)
2575                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2576
2577         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2578         if (!ep_ring)
2579                 return -EINVAL;
2580
2581         num_trbs = 0;
2582         /* How much data is (potentially) left before the 64KB boundary? */
2583         running_total = TRB_MAX_BUFF_SIZE -
2584                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2585
2586         /* If there's some data on this 64KB chunk, or we have to send a
2587          * zero-length transfer, we need at least one TRB
2588          */
2589         if (running_total != 0 || urb->transfer_buffer_length == 0)
2590                 num_trbs++;
2591         /* How many more 64KB chunks to transfer, how many more TRBs? */
2592         while (running_total < urb->transfer_buffer_length) {
2593                 num_trbs++;
2594                 running_total += TRB_MAX_BUFF_SIZE;
2595         }
2596         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2597
2598         if (!in_interrupt())
2599                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
2600                                 urb->ep->desc.bEndpointAddress,
2601                                 urb->transfer_buffer_length,
2602                                 urb->transfer_buffer_length,
2603                                 (unsigned long long)urb->transfer_dma,
2604                                 num_trbs);
2605
2606         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2607                         ep_index, urb->stream_id,
2608                         num_trbs, urb, 0, mem_flags);
2609         if (ret < 0)
2610                 return ret;
2611
2612         urb_priv = urb->hcpriv;
2613         td = urb_priv->td[0];
2614
2615         /*
2616          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2617          * until we've finished creating all the other TRBs.  The ring's cycle
2618          * state may change as we enqueue the other TRBs, so save it too.
2619          */
2620         start_trb = &ep_ring->enqueue->generic;
2621         start_cycle = ep_ring->cycle_state;
2622
2623         running_total = 0;
2624         /* How much data is in the first TRB? */
2625         addr = (u64) urb->transfer_dma;
2626         trb_buff_len = TRB_MAX_BUFF_SIZE -
2627                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2628         if (urb->transfer_buffer_length < trb_buff_len)
2629                 trb_buff_len = urb->transfer_buffer_length;
2630
2631         first_trb = true;
2632
2633         /* Queue the first TRB, even if it's zero-length */
2634         do {
2635                 u32 remainder = 0;
2636                 field = 0;
2637
2638                 /* Don't change the cycle bit of the first TRB until later */
2639                 if (first_trb)
2640                         first_trb = false;
2641                 else
2642                         field |= ep_ring->cycle_state;
2643
2644                 /* Chain all the TRBs together; clear the chain bit in the last
2645                  * TRB to indicate it's the last TRB in the chain.
2646                  */
2647                 if (num_trbs > 1) {
2648                         field |= TRB_CHAIN;
2649                 } else {
2650                         /* FIXME - add check for ZERO_PACKET flag before this */
2651                         td->last_trb = ep_ring->enqueue;
2652                         field |= TRB_IOC;
2653                 }
2654                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2655                                 running_total);
2656                 length_field = TRB_LEN(trb_buff_len) |
2657                         remainder |
2658                         TRB_INTR_TARGET(0);
2659                 if (num_trbs > 1)
2660                         more_trbs_coming = true;
2661                 else
2662                         more_trbs_coming = false;
2663                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2664                                 lower_32_bits(addr),
2665                                 upper_32_bits(addr),
2666                                 length_field,
2667                                 /* We always want to know if the TRB was short,
2668                                  * or we won't get an event when it completes.
2669                                  * (Unless we use event data TRBs, which are a
2670                                  * waste of space and HC resources.)
2671                                  */
2672                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2673                 --num_trbs;
2674                 running_total += trb_buff_len;
2675
2676                 /* Calculate length for next transfer */
2677                 addr += trb_buff_len;
2678                 trb_buff_len = urb->transfer_buffer_length - running_total;
2679                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2680                         trb_buff_len = TRB_MAX_BUFF_SIZE;
2681         } while (running_total < urb->transfer_buffer_length);
2682
2683         check_trb_math(urb, num_trbs, running_total);
2684         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2685                         start_cycle, start_trb, td);
2686         return 0;
2687 }
2688
2689 /* Caller must have locked xhci->lock */
2690 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2691                 struct urb *urb, int slot_id, unsigned int ep_index)
2692 {
2693         struct xhci_ring *ep_ring;
2694         int num_trbs;
2695         int ret;
2696         struct usb_ctrlrequest *setup;
2697         struct xhci_generic_trb *start_trb;
2698         int start_cycle;
2699         u32 field, length_field;
2700         struct urb_priv *urb_priv;
2701         struct xhci_td *td;
2702
2703         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2704         if (!ep_ring)
2705                 return -EINVAL;
2706
2707         /*
2708          * Need to copy setup packet into setup TRB, so we can't use the setup
2709          * DMA address.
2710          */
2711         if (!urb->setup_packet)
2712                 return -EINVAL;
2713
2714         if (!in_interrupt())
2715                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2716                                 slot_id, ep_index);
2717         /* 1 TRB for setup, 1 for status */
2718         num_trbs = 2;
2719         /*
2720          * Don't need to check if we need additional event data and normal TRBs,
2721          * since data in control transfers will never get bigger than 16MB
2722          * XXX: can we get a buffer that crosses 64KB boundaries?
2723          */
2724         if (urb->transfer_buffer_length > 0)
2725                 num_trbs++;
2726         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2727                         ep_index, urb->stream_id,
2728                         num_trbs, urb, 0, mem_flags);
2729         if (ret < 0)
2730                 return ret;
2731
2732         urb_priv = urb->hcpriv;
2733         td = urb_priv->td[0];
2734
2735         /*
2736          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2737          * until we've finished creating all the other TRBs.  The ring's cycle
2738          * state may change as we enqueue the other TRBs, so save it too.
2739          */
2740         start_trb = &ep_ring->enqueue->generic;
2741         start_cycle = ep_ring->cycle_state;
2742
2743         /* Queue setup TRB - see section 6.4.1.2.1 */
2744         /* FIXME better way to translate setup_packet into two u32 fields? */
2745         setup = (struct usb_ctrlrequest *) urb->setup_packet;
2746         queue_trb(xhci, ep_ring, false, true,
2747                         /* FIXME endianness is probably going to bite my ass here. */
2748                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2749                         setup->wIndex | setup->wLength << 16,
2750                         TRB_LEN(8) | TRB_INTR_TARGET(0),
2751                         /* Immediate data in pointer */
2752                         TRB_IDT | TRB_TYPE(TRB_SETUP));
2753
2754         /* If there's data, queue data TRBs */
2755         field = 0;
2756         length_field = TRB_LEN(urb->transfer_buffer_length) |
2757                 xhci_td_remainder(urb->transfer_buffer_length) |
2758                 TRB_INTR_TARGET(0);
2759         if (urb->transfer_buffer_length > 0) {
2760                 if (setup->bRequestType & USB_DIR_IN)
2761                         field |= TRB_DIR_IN;
2762                 queue_trb(xhci, ep_ring, false, true,
2763                                 lower_32_bits(urb->transfer_dma),
2764                                 upper_32_bits(urb->transfer_dma),
2765                                 length_field,
2766                                 /* Event on short tx */
2767                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2768         }
2769
2770         /* Save the DMA address of the last TRB in the TD */
2771         td->last_trb = ep_ring->enqueue;
2772
2773         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2774         /* If the device sent data, the status stage is an OUT transfer */
2775         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2776                 field = 0;
2777         else
2778                 field = TRB_DIR_IN;
2779         queue_trb(xhci, ep_ring, false, false,
2780                         0,
2781                         0,
2782                         TRB_INTR_TARGET(0),
2783                         /* Event on completion */
2784                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2785
2786         giveback_first_trb(xhci, slot_id, ep_index, 0,
2787                         start_cycle, start_trb, td);
2788         return 0;
2789 }
2790
2791 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
2792                 struct urb *urb, int i)
2793 {
2794         int num_trbs = 0;
2795         u64 addr, td_len, running_total;
2796
2797         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
2798         td_len = urb->iso_frame_desc[i].length;
2799
2800         running_total = TRB_MAX_BUFF_SIZE -
2801                         (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2802         if (running_total != 0)
2803                 num_trbs++;
2804
2805         while (running_total < td_len) {
2806                 num_trbs++;
2807                 running_total += TRB_MAX_BUFF_SIZE;
2808         }
2809
2810         return num_trbs;
2811 }
2812
2813 /* This is for isoc transfer */
2814 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2815                 struct urb *urb, int slot_id, unsigned int ep_index)
2816 {
2817         struct xhci_ring *ep_ring;
2818         struct urb_priv *urb_priv;
2819         struct xhci_td *td;
2820         int num_tds, trbs_per_td;
2821         struct xhci_generic_trb *start_trb;
2822         bool first_trb;
2823         int start_cycle;
2824         u32 field, length_field;
2825         int running_total, trb_buff_len, td_len, td_remain_len, ret;
2826         u64 start_addr, addr;
2827         int i, j;
2828
2829         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
2830
2831         num_tds = urb->number_of_packets;
2832         if (num_tds < 1) {
2833                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
2834                 return -EINVAL;
2835         }
2836
2837         if (!in_interrupt())
2838                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d),"
2839                                 " addr = %#llx, num_tds = %d\n",
2840                                 urb->ep->desc.bEndpointAddress,
2841                                 urb->transfer_buffer_length,
2842                                 urb->transfer_buffer_length,
2843                                 (unsigned long long)urb->transfer_dma,
2844                                 num_tds);
2845
2846         start_addr = (u64) urb->transfer_dma;
2847         start_trb = &ep_ring->enqueue->generic;
2848         start_cycle = ep_ring->cycle_state;
2849
2850         /* Queue the first TRB, even if it's zero-length */
2851         for (i = 0; i < num_tds; i++) {
2852                 first_trb = true;
2853
2854                 running_total = 0;
2855                 addr = start_addr + urb->iso_frame_desc[i].offset;
2856                 td_len = urb->iso_frame_desc[i].length;
2857                 td_remain_len = td_len;
2858
2859                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
2860
2861                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
2862                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
2863                 if (ret < 0)
2864                         return ret;
2865
2866                 urb_priv = urb->hcpriv;
2867                 td = urb_priv->td[i];
2868
2869                 for (j = 0; j < trbs_per_td; j++) {
2870                         u32 remainder = 0;
2871                         field = 0;
2872
2873                         if (first_trb) {
2874                                 /* Queue the isoc TRB */
2875                                 field |= TRB_TYPE(TRB_ISOC);
2876                                 /* Assume URB_ISO_ASAP is set */
2877                                 field |= TRB_SIA;
2878                                 if (i > 0)
2879                                         field |= ep_ring->cycle_state;
2880                                 first_trb = false;
2881                         } else {
2882                                 /* Queue other normal TRBs */
2883                                 field |= TRB_TYPE(TRB_NORMAL);
2884                                 field |= ep_ring->cycle_state;
2885                         }
2886
2887                         /* Chain all the TRBs together; clear the chain bit in
2888                          * the last TRB to indicate it's the last TRB in the
2889                          * chain.
2890                          */
2891                         if (j < trbs_per_td - 1) {
2892                                 field |= TRB_CHAIN;
2893                         } else {
2894                                 td->last_trb = ep_ring->enqueue;
2895                                 field |= TRB_IOC;
2896                         }
2897
2898                         /* Calculate TRB length */
2899                         trb_buff_len = TRB_MAX_BUFF_SIZE -
2900                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2901                         if (trb_buff_len > td_remain_len)
2902                                 trb_buff_len = td_remain_len;
2903
2904                         remainder = xhci_td_remainder(td_len - running_total);
2905                         length_field = TRB_LEN(trb_buff_len) |
2906                                 remainder |
2907                                 TRB_INTR_TARGET(0);
2908                         queue_trb(xhci, ep_ring, false, false,
2909                                 lower_32_bits(addr),
2910                                 upper_32_bits(addr),
2911                                 length_field,
2912                                 /* We always want to know if the TRB was short,
2913                                  * or we won't get an event when it completes.
2914                                  * (Unless we use event data TRBs, which are a
2915                                  * waste of space and HC resources.)
2916                                  */
2917                                 field | TRB_ISP);
2918                         running_total += trb_buff_len;
2919
2920                         addr += trb_buff_len;
2921                         td_remain_len -= trb_buff_len;
2922                 }
2923
2924                 /* Check TD length */
2925                 if (running_total != td_len) {
2926                         xhci_err(xhci, "ISOC TD length unmatch\n");
2927                         return -EINVAL;
2928                 }
2929         }
2930
2931         wmb();
2932         start_trb->field[3] |= start_cycle;
2933
2934         ring_ep_doorbell(xhci, slot_id, ep_index, urb->stream_id);
2935         return 0;
2936 }
2937
2938 /*
2939  * Check transfer ring to guarantee there is enough room for the urb.
2940  * Update ISO URB start_frame and interval.
2941  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
2942  * update the urb->start_frame by now.
2943  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
2944  */
2945 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2946                 struct urb *urb, int slot_id, unsigned int ep_index)
2947 {
2948         struct xhci_virt_device *xdev;
2949         struct xhci_ring *ep_ring;
2950         struct xhci_ep_ctx *ep_ctx;
2951         int start_frame;
2952         int xhci_interval;
2953         int ep_interval;
2954         int num_tds, num_trbs, i;
2955         int ret;
2956
2957         xdev = xhci->devs[slot_id];
2958         ep_ring = xdev->eps[ep_index].ring;
2959         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2960
2961         num_trbs = 0;
2962         num_tds = urb->number_of_packets;
2963         for (i = 0; i < num_tds; i++)
2964                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
2965
2966         /* Check the ring to guarantee there is enough room for the whole urb.
2967          * Do not insert any td of the urb to the ring if the check failed.
2968          */
2969         ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK,
2970                                 num_trbs, mem_flags);
2971         if (ret)
2972                 return ret;
2973
2974         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
2975         start_frame &= 0x3fff;
2976
2977         urb->start_frame = start_frame;
2978         if (urb->dev->speed == USB_SPEED_LOW ||
2979                         urb->dev->speed == USB_SPEED_FULL)
2980                 urb->start_frame >>= 3;
2981
2982         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2983         ep_interval = urb->interval;
2984         /* Convert to microframes */
2985         if (urb->dev->speed == USB_SPEED_LOW ||
2986                         urb->dev->speed == USB_SPEED_FULL)
2987                 ep_interval *= 8;
2988         /* FIXME change this to a warning and a suggestion to use the new API
2989          * to set the polling interval (once the API is added).
2990          */
2991         if (xhci_interval != ep_interval) {
2992                 if (!printk_ratelimit())
2993                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2994                                         " (%d microframe%s) than xHCI "
2995                                         "(%d microframe%s)\n",
2996                                         ep_interval,
2997                                         ep_interval == 1 ? "" : "s",
2998                                         xhci_interval,
2999                                         xhci_interval == 1 ? "" : "s");
3000                 urb->interval = xhci_interval;
3001                 /* Convert back to frames for LS/FS devices */
3002                 if (urb->dev->speed == USB_SPEED_LOW ||
3003                                 urb->dev->speed == USB_SPEED_FULL)
3004                         urb->interval /= 8;
3005         }
3006         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3007 }
3008
3009 /****           Command Ring Operations         ****/
3010
3011 /* Generic function for queueing a command TRB on the command ring.
3012  * Check to make sure there's room on the command ring for one command TRB.
3013  * Also check that there's room reserved for commands that must not fail.
3014  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3015  * then only check for the number of reserved spots.
3016  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3017  * because the command event handler may want to resubmit a failed command.
3018  */
3019 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3020                 u32 field3, u32 field4, bool command_must_succeed)
3021 {
3022         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3023         int ret;
3024
3025         if (!command_must_succeed)
3026                 reserved_trbs++;
3027
3028         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3029                         reserved_trbs, GFP_ATOMIC);
3030         if (ret < 0) {
3031                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3032                 if (command_must_succeed)
3033                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3034                                         "unfailable commands failed.\n");
3035                 return ret;
3036         }
3037         queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3038                         field4 | xhci->cmd_ring->cycle_state);
3039         return 0;
3040 }
3041
3042 /* Queue a no-op command on the command ring */
3043 static int queue_cmd_noop(struct xhci_hcd *xhci)
3044 {
3045         return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
3046 }
3047
3048 /*
3049  * Place a no-op command on the command ring to test the command and
3050  * event ring.
3051  */
3052 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
3053 {
3054         if (queue_cmd_noop(xhci) < 0)
3055                 return NULL;
3056         xhci->noops_submitted++;
3057         return xhci_ring_cmd_db;
3058 }
3059
3060 /* Queue a slot enable or disable request on the command ring */
3061 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3062 {
3063         return queue_command(xhci, 0, 0, 0,
3064                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3065 }
3066
3067 /* Queue an address device command TRB */
3068 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3069                 u32 slot_id)
3070 {
3071         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3072                         upper_32_bits(in_ctx_ptr), 0,
3073                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3074                         false);
3075 }
3076
3077 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3078                 u32 field1, u32 field2, u32 field3, u32 field4)
3079 {
3080         return queue_command(xhci, field1, field2, field3, field4, false);
3081 }
3082
3083 /* Queue a reset device command TRB */
3084 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3085 {
3086         return queue_command(xhci, 0, 0, 0,
3087                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3088                         false);
3089 }
3090
3091 /* Queue a configure endpoint command TRB */
3092 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3093                 u32 slot_id, bool command_must_succeed)
3094 {
3095         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3096                         upper_32_bits(in_ctx_ptr), 0,
3097                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3098                         command_must_succeed);
3099 }
3100
3101 /* Queue an evaluate context command TRB */
3102 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3103                 u32 slot_id)
3104 {
3105         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3106                         upper_32_bits(in_ctx_ptr), 0,
3107                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3108                         false);
3109 }
3110
3111 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3112                 unsigned int ep_index)
3113 {
3114         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3115         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3116         u32 type = TRB_TYPE(TRB_STOP_RING);
3117
3118         return queue_command(xhci, 0, 0, 0,
3119                         trb_slot_id | trb_ep_index | type, false);
3120 }
3121
3122 /* Set Transfer Ring Dequeue Pointer command.
3123  * This should not be used for endpoints that have streams enabled.
3124  */
3125 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3126                 unsigned int ep_index, unsigned int stream_id,
3127                 struct xhci_segment *deq_seg,
3128                 union xhci_trb *deq_ptr, u32 cycle_state)
3129 {
3130         dma_addr_t addr;
3131         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3132         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3133         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3134         u32 type = TRB_TYPE(TRB_SET_DEQ);
3135
3136         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3137         if (addr == 0) {
3138                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3139                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3140                                 deq_seg, deq_ptr);
3141                 return 0;
3142         }
3143         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3144                         upper_32_bits(addr), trb_stream_id,
3145                         trb_slot_id | trb_ep_index | type, false);
3146 }
3147
3148 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3149                 unsigned int ep_index)
3150 {
3151         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3152         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3153         u32 type = TRB_TYPE(TRB_RESET_EP);
3154
3155         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3156                         false);
3157 }