drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         unsigned long long addr;
 149
 150         ring->deq_updates++;
 151
 152         do {
 153                 /*
 154                  * Update the dequeue pointer further if that was a link TRB or
 155                  * we're at the end of an event ring segment (which doesn't have
 156                  * link TRBS)
 157                  */
 158                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 159                         if (consumer && last_trb_on_last_seg(xhci, ring,
 160                                                 ring->deq_seg, ring->dequeue)) {
 161                                 if (!in_interrupt())
 162                                         xhci_dbg(xhci, "Toggle cycle state "
 163                                                         "for ring %p = %i\n",
 164                                                         ring,
 165                                                         (unsigned int)
 166                                                         ring->cycle_state);
 167                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 168                         }
 169                         ring->deq_seg = ring->deq_seg->next;
 170                         ring->dequeue = ring->deq_seg->trbs;
 171                 } else {
 172                         ring->dequeue++;
 173                 }
 174         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 175
 176         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 177 }
 178
 179 /*
 180  * See Cycle bit rules. SW is the consumer for the event ring only.
 181  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 182  *
 183  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 184  * chain bit is set), then set the chain bit in all the following link TRBs.
 185  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 186  * have their chain bit cleared (so that each Link TRB is a separate TD).
 187  *
 188  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 189  * set, but other sections talk about dealing with the chain bit set.  This was
 190  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 191  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 192  *
 193  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 194  *                      prepare_transfer()?
 195  */
 196 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 197                 bool consumer, bool more_trbs_coming, bool isoc)
 198 {
 199         u32 chain;
 200         union xhci_trb *next;
 201         unsigned long long addr;
 202
 203         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 204         next = ++(ring->enqueue);
 205
 206         ring->enq_updates++;
 207         /* Update the dequeue pointer further if that was a link TRB or we're at
 208          * the end of an event ring segment (which doesn't have link TRBS)
 209          */
 210         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 211                 if (!consumer) {
 212                         if (ring != xhci->event_ring) {
 213                                 /*
 214                                  * If the caller doesn't plan on enqueueing more
 215                                  * TDs before ringing the doorbell, then we
 216                                  * don't want to give the link TRB to the
 217                                  * hardware just yet.  We'll give the link TRB
 218                                  * back in prepare_ring() just before we enqueue
 219                                  * the TD at the top of the ring.
 220                                  */
 221                                 if (!chain && !more_trbs_coming)
 222                                         break;
 223
 224                                 /* If we're not dealing with 0.95 hardware or
 225                                  * isoc rings on AMD 0.96 host,
 226                                  * carry over the chain bit of the previous TRB
 227                                  * (which may mean the chain bit is cleared).
 228                                  */
 229                                 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
 230                                                 && !xhci_link_trb_quirk(xhci)) {
 231                                         next->link.control &=
 232                                                 cpu_to_le32(~TRB_CHAIN);
 233                                         next->link.control |=
 234                                                 cpu_to_le32(chain);
 235                                 }
 236                                 /* Give this link TRB to the hardware */
 237                                 wmb();
 238                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 239                         }
 240                         /* Toggle the cycle bit after the last ring segment. */
 241                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 242                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 243                                 if (!in_interrupt())
 244                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 245                                                         ring,
 246                                                         (unsigned int) ring->cycle_state);
 247                         }
 248                 }
 249                 ring->enq_seg = ring->enq_seg->next;
 250                 ring->enqueue = ring->enq_seg->trbs;
 251                 next = ring->enqueue;
 252         }
 253         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 254 }
 255
 256 /*
 257  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 258  * above.
 259  * FIXME: this would be simpler and faster if we just kept track of the number
 260  * of free TRBs in a ring.
 261  */
 262 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 263                 unsigned int num_trbs)
 264 {
 265         int i;
 266         union xhci_trb *enq = ring->enqueue;
 267         struct xhci_segment *enq_seg = ring->enq_seg;
 268         struct xhci_segment *cur_seg;
 269         unsigned int left_on_ring;
 270
 271         /* If we are currently pointing to a link TRB, advance the
 272          * enqueue pointer before checking for space */
 273         while (last_trb(xhci, ring, enq_seg, enq)) {
 274                 enq_seg = enq_seg->next;
 275                 enq = enq_seg->trbs;
 276         }
 277
 278         /* Check if ring is empty */
 279         if (enq == ring->dequeue) {
 280                 /* Can't use link trbs */
 281                 left_on_ring = TRBS_PER_SEGMENT - 1;
 282                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 283                                 cur_seg = cur_seg->next)
 284                         left_on_ring += TRBS_PER_SEGMENT - 1;
 285
 286                 /* Always need one TRB free in the ring. */
 287                 left_on_ring -= 1;
 288                 if (num_trbs > left_on_ring) {
 289                         xhci_warn(xhci, "Not enough room on ring; "
 290                                         "need %u TRBs, %u TRBs left\n",
 291                                         num_trbs, left_on_ring);
 292                         return 0;
 293                 }
 294                 return 1;
 295         }
 296         /* Make sure there's an extra empty TRB available */
 297         for (i = 0; i <= num_trbs; ++i) {
 298                 if (enq == ring->dequeue)
 299                         return 0;
 300                 enq++;
 301                 while (last_trb(xhci, ring, enq_seg, enq)) {
 302                         enq_seg = enq_seg->next;
 303                         enq = enq_seg->trbs;
 304                 }
 305         }
 306         return 1;
 307 }
 308
 309 /* Ring the host controller doorbell after placing a command on the ring */
 310 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 311 {
 312         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 313                 return;
 314
 315         xhci_dbg(xhci, "// Ding dong!\n");
 316         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 317         /* Flush PCI posted writes */
 318         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 319 }
 320
 321 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 322 {
 323         u64 temp_64;
 324         int ret;
 325
 326         xhci_dbg(xhci, "Abort command ring\n");
 327
 328         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 329                 xhci_dbg(xhci, "The command ring isn't running, "
 330                                 "Have the command ring been stopped?\n");
 331                 return 0;
 332         }
 333
 334         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 335         if (!(temp_64 & CMD_RING_RUNNING)) {
 336                 xhci_dbg(xhci, "Command ring had been stopped\n");
 337                 return 0;
 338         }
 339         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 340         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 341                         &xhci->op_regs->cmd_ring);
 342
 343         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 344          * time the completion od all xHCI commands, including
 345          * the Command Abort operation. If software doesn't see
 346          * CRR negated in a timely manner (e.g. longer than 5
 347          * seconds), then it should assume that the there are
 348          * larger problems with the xHC and assert HCRST.
 349          */
 350         ret = handshake(xhci, &xhci->op_regs->cmd_ring,
 351                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 352         if (ret < 0) {
 353                 xhci_err(xhci, "Stopped the command ring failed, "
 354                                 "maybe the host is dead\n");
 355                 xhci->xhc_state |= XHCI_STATE_DYING;
 356                 xhci_quiesce(xhci);
 357                 xhci_halt(xhci);
 358                 return -ESHUTDOWN;
 359         }
 360
 361         return 0;
 362 }
 363
 364 static int xhci_queue_cd(struct xhci_hcd *xhci,
 365                 struct xhci_command *command,
 366                 union xhci_trb *cmd_trb)
 367 {
 368         struct xhci_cd *cd;
 369         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 370         if (!cd)
 371                 return -ENOMEM;
 372         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 373
 374         cd->command = command;
 375         cd->cmd_trb = cmd_trb;
 376         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 377
 378         return 0;
 379 }
 380
 381 /*
 382  * Cancel the command which has issue.
 383  *
 384  * Some commands may hang due to waiting for acknowledgement from
 385  * usb device. It is outside of the xHC's ability to control and
 386  * will cause the command ring is blocked. When it occurs software
 387  * should intervene to recover the command ring.
 388  * See Section 4.6.1.1 and 4.6.1.2
 389  */
 390 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 391                 union xhci_trb *cmd_trb)
 392 {
 393         int retval = 0;
 394         unsigned long flags;
 395
 396         spin_lock_irqsave(&xhci->lock, flags);
 397
 398         if (xhci->xhc_state & XHCI_STATE_DYING) {
 399                 xhci_warn(xhci, "Abort the command ring,"
 400                                 " but the xHCI is dead.\n");
 401                 retval = -ESHUTDOWN;
 402                 goto fail;
 403         }
 404
 405         /* queue the cmd desriptor to cancel_cmd_list */
 406         retval = xhci_queue_cd(xhci, command, cmd_trb);
 407         if (retval) {
 408                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 409                 goto fail;
 410         }
 411
 412         /* abort command ring */
 413         retval = xhci_abort_cmd_ring(xhci);
 414         if (retval) {
 415                 xhci_err(xhci, "Abort command ring failed\n");
 416                 if (unlikely(retval == -ESHUTDOWN)) {
 417                         spin_unlock_irqrestore(&xhci->lock, flags);
 418                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 419                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 420                         return retval;
 421                 }
 422         }
 423
 424 fail:
 425         spin_unlock_irqrestore(&xhci->lock, flags);
 426         return retval;
 427 }
 428
 429 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 430                 unsigned int slot_id,
 431                 unsigned int ep_index,
 432                 unsigned int stream_id)
 433 {
 434         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 435         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 436         unsigned int ep_state = ep->ep_state;
 437
 438         /* Don't ring the doorbell for this endpoint if there are pending
 439          * cancellations because we don't want to interrupt processing.
 440          * We don't want to restart any stream rings if there's a set dequeue
 441          * pointer command pending because the device can choose to start any
 442          * stream once the endpoint is on the HW schedule.
 443          * FIXME - check all the stream rings for pending cancellations.
 444          */
 445         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 446             (ep_state & EP_HALTED))
 447                 return;
 448         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 449         /* The CPU has better things to do at this point than wait for a
 450          * write-posting flush.  It'll get there soon enough.
 451          */
 452 }
 453
 454 /* Ring the doorbell for any rings with pending URBs */
 455 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 456                 unsigned int slot_id,
 457                 unsigned int ep_index)
 458 {
 459         unsigned int stream_id;
 460         struct xhci_virt_ep *ep;
 461
 462         ep = &xhci->devs[slot_id]->eps[ep_index];
 463
 464         /* A ring has pending URBs if its TD list is not empty */
 465         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 466                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 467                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 468                 return;
 469         }
 470
 471         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 472                         stream_id++) {
 473                 struct xhci_stream_info *stream_info = ep->stream_info;
 474                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 475                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 476                                                 stream_id);
 477         }
 478 }
 479
 480 /*
 481  * Find the segment that trb is in.  Start searching in start_seg.
 482  * If we must move past a segment that has a link TRB with a toggle cycle state
 483  * bit set, then we will toggle the value pointed at by cycle_state.
 484  */
 485 static struct xhci_segment *find_trb_seg(
 486                 struct xhci_segment *start_seg,
 487                 union xhci_trb  *trb, int *cycle_state)
 488 {
 489         struct xhci_segment *cur_seg = start_seg;
 490         struct xhci_generic_trb *generic_trb;
 491
 492         while (cur_seg->trbs > trb ||
 493                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 494                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 495                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 496                         *cycle_state ^= 0x1;
 497                 cur_seg = cur_seg->next;
 498                 if (cur_seg == start_seg)
 499                         /* Looped over the entire list.  Oops! */
 500                         return NULL;
 501         }
 502         return cur_seg;
 503 }
 504
 505
 506 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 507                 unsigned int slot_id, unsigned int ep_index,
 508                 unsigned int stream_id)
 509 {
 510         struct xhci_virt_ep *ep;
 511
 512         ep = &xhci->devs[slot_id]->eps[ep_index];
 513         /* Common case: no streams */
 514         if (!(ep->ep_state & EP_HAS_STREAMS))
 515                 return ep->ring;
 516
 517         if (stream_id == 0) {
 518                 xhci_warn(xhci,
 519                                 "WARN: Slot ID %u, ep index %u has streams, "
 520                                 "but URB has no stream ID.\n",
 521                                 slot_id, ep_index);
 522                 return NULL;
 523         }
 524
 525         if (stream_id < ep->stream_info->num_streams)
 526                 return ep->stream_info->stream_rings[stream_id];
 527
 528         xhci_warn(xhci,
 529                         "WARN: Slot ID %u, ep index %u has "
 530                         "stream IDs 1 to %u allocated, "
 531                         "but stream ID %u is requested.\n",
 532                         slot_id, ep_index,
 533                         ep->stream_info->num_streams - 1,
 534                         stream_id);
 535         return NULL;
 536 }
 537
 538 /* Get the right ring for the given URB.
 539  * If the endpoint supports streams, boundary check the URB's stream ID.
 540  * If the endpoint doesn't support streams, return the singular endpoint ring.
 541  */
 542 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 543                 struct urb *urb)
 544 {
 545         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 546                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 547 }
 548
 549 /*
 550  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 551  * Record the new state of the xHC's endpoint ring dequeue segment,
 552  * dequeue pointer, and new consumer cycle state in state.
 553  * Update our internal representation of the ring's dequeue pointer.
 554  *
 555  * We do this in three jumps:
 556  *  - First we update our new ring state to be the same as when the xHC stopped.
 557  *  - Then we traverse the ring to find the segment that contains
 558  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 559  *    any link TRBs with the toggle cycle bit set.
 560  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 561  *    if we've moved it past a link TRB with the toggle cycle bit set.
 562  *
 563  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 564  * with correct __le32 accesses they should work fine.  Only users of this are
 565  * in here.
 566  */
 567 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 568                 unsigned int slot_id, unsigned int ep_index,
 569                 unsigned int stream_id, struct xhci_td *cur_td,
 570                 struct xhci_dequeue_state *state)
 571 {
 572         struct xhci_virt_device *dev = xhci->devs[slot_id];
 573         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 574         struct xhci_ring *ep_ring;
 575         struct xhci_segment *new_seg;
 576         union xhci_trb *new_deq;
 577         dma_addr_t addr;
 578         u64 hw_dequeue;
 579         bool cycle_found = false;
 580         bool td_last_trb_found = false;
 581
 582         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 583                         ep_index, stream_id);
 584         if (!ep_ring) {
 585                 xhci_warn(xhci, "WARN can't find new dequeue state "
 586                                 "for invalid stream ID %u.\n",
 587                                 stream_id);
 588                 return;
 589         }
 590
 591         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 592         xhci_dbg(xhci, "Finding endpoint context\n");
 593         /* 4.6.9 the css flag is written to the stream context for streams */
 594         if (ep->ep_state & EP_HAS_STREAMS) {
 595                 struct xhci_stream_ctx *ctx =
 596                         &ep->stream_info->stream_ctx_array[stream_id];
 597                 hw_dequeue = le64_to_cpu(ctx->stream_ring);
 598         } else {
 599                 struct xhci_ep_ctx *ep_ctx
 600                         = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 601                 hw_dequeue = le64_to_cpu(ep_ctx->deq);
 602         }
 603
 604         new_seg = ep_ring->deq_seg;
 605         new_deq = ep_ring->dequeue;
 606         state->new_cycle_state = hw_dequeue & 0x1;
 607
 608         /*
 609          * We want to find the pointer, segment and cycle state of the new trb
 610          * (the one after current TD's last_trb). We know the cycle state at
 611          * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
 612          * found.
 613          */
 614         do {
 615                 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
 616                     == (dma_addr_t)(hw_dequeue & ~0xf)) {
 617                         cycle_found = true;
 618                         if (td_last_trb_found)
 619                                 break;
 620                 }
 621                 if (new_deq == cur_td->last_trb)
 622                         td_last_trb_found = true;
 623
 624                 if (cycle_found &&
 625                     TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
 626                     new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
 627                         state->new_cycle_state ^= 0x1;
 628
 629                 next_trb(xhci, ep_ring, &new_seg, &new_deq);
 630
 631                 /* Search wrapped around, bail out */
 632                 if (new_deq == ep->ring->dequeue) {
 633                         xhci_err(xhci, "Error: Failed finding new dequeue state\n");
 634                         state->new_deq_seg = NULL;
 635                         state->new_deq_ptr = NULL;
 636                         return;
 637                 }
 638
 639         } while (!cycle_found || !td_last_trb_found);
 640
 641         state->new_deq_seg = new_seg;
 642         state->new_deq_ptr = new_deq;
 643
 644         /* Don't update the ring cycle state for the producer (us). */
 645         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 646
 647         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 648                         state->new_deq_seg);
 649         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 650         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 651                         (unsigned long long) addr);
 652 }
 653
 654 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 655  * (The last TRB actually points to the ring enqueue pointer, which is not part
 656  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 657  */
 658 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 659                 struct xhci_td *cur_td, bool flip_cycle)
 660 {
 661         struct xhci_segment *cur_seg;
 662         union xhci_trb *cur_trb;
 663
 664         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 665                         true;
 666                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 667                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 668                         /* Unchain any chained Link TRBs, but
 669                          * leave the pointers intact.
 670                          */
 671                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 672                         /* Flip the cycle bit (link TRBs can't be the first
 673                          * or last TRB).
 674                          */
 675                         if (flip_cycle)
 676                                 cur_trb->generic.field[3] ^=
 677                                         cpu_to_le32(TRB_CYCLE);
 678                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 679                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 680                                         "in seg %p (0x%llx dma)\n",
 681                                         cur_trb,
 682                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 683                                         cur_seg,
 684                                         (unsigned long long)cur_seg->dma);
 685                 } else {
 686                         cur_trb->generic.field[0] = 0;
 687                         cur_trb->generic.field[1] = 0;
 688                         cur_trb->generic.field[2] = 0;
 689                         /* Preserve only the cycle bit of this TRB */
 690                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 691                         /* Flip the cycle bit except on the first or last TRB */
 692                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 693                                         cur_trb != cur_td->last_trb)
 694                                 cur_trb->generic.field[3] ^=
 695                                         cpu_to_le32(TRB_CYCLE);
 696                         cur_trb->generic.field[3] |= cpu_to_le32(
 697                                 TRB_TYPE(TRB_TR_NOOP));
 698                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 699                                         "in seg %p (0x%llx dma)\n",
 700                                         cur_trb,
 701                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 702                                         cur_seg,
 703                                         (unsigned long long)cur_seg->dma);
 704                 }
 705                 if (cur_trb == cur_td->last_trb)
 706                         break;
 707         }
 708 }
 709
 710 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 711                 unsigned int ep_index, unsigned int stream_id,
 712                 struct xhci_segment *deq_seg,
 713                 union xhci_trb *deq_ptr, u32 cycle_state);
 714
 715 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 716                 unsigned int slot_id, unsigned int ep_index,
 717                 unsigned int stream_id,
 718                 struct xhci_dequeue_state *deq_state)
 719 {
 720         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 721
 722         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 723                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 724                         deq_state->new_deq_seg,
 725                         (unsigned long long)deq_state->new_deq_seg->dma,
 726                         deq_state->new_deq_ptr,
 727                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 728                         deq_state->new_cycle_state);
 729         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 730                         deq_state->new_deq_seg,
 731                         deq_state->new_deq_ptr,
 732                         (u32) deq_state->new_cycle_state);
 733         /* Stop the TD queueing code from ringing the doorbell until
 734          * this command completes.  The HC won't set the dequeue pointer
 735          * if the ring is running, and ringing the doorbell starts the
 736          * ring running.
 737          */
 738         ep->ep_state |= SET_DEQ_PENDING;
 739 }
 740
 741 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 742                 struct xhci_virt_ep *ep)
 743 {
 744         ep->ep_state &= ~EP_HALT_PENDING;
 745         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 746          * timer is running on another CPU, we don't decrement stop_cmds_pending
 747          * (since we didn't successfully stop the watchdog timer).
 748          */
 749         if (del_timer(&ep->stop_cmd_timer))
 750                 ep->stop_cmds_pending--;
 751 }
 752
 753 /* Must be called with xhci->lock held in interrupt context */
 754 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 755                 struct xhci_td *cur_td, int status, char *adjective)
 756 {
 757         struct usb_hcd *hcd;
 758         struct urb      *urb;
 759         struct urb_priv *urb_priv;
 760
 761         urb = cur_td->urb;
 762         urb_priv = urb->hcpriv;
 763         urb_priv->td_cnt++;
 764         hcd = bus_to_hcd(urb->dev->bus);
 765
 766         /* Only giveback urb when this is the last td in urb */
 767         if (urb_priv->td_cnt == urb_priv->length) {
 768                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 769                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 770                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 771                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 772                                         usb_amd_quirk_pll_enable();
 773                         }
 774                 }
 775                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 776
 777                 spin_unlock(&xhci->lock);
 778                 usb_hcd_giveback_urb(hcd, urb, status);
 779                 xhci_urb_free_priv(xhci, urb_priv);
 780                 spin_lock(&xhci->lock);
 781         }
 782 }
 783
 784 /*
 785  * When we get a command completion for a Stop Endpoint Command, we need to
 786  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 787  *
 788  *  1. If the HW was in the middle of processing the TD that needs to be
 789  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 790  *     in the TD with a Set Dequeue Pointer Command.
 791  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 792  *     bit cleared) so that the HW will skip over them.
 793  */
 794 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 795                 union xhci_trb *trb, struct xhci_event_cmd *event)
 796 {
 797         unsigned int slot_id;
 798         unsigned int ep_index;
 799         struct xhci_virt_device *virt_dev;
 800         struct xhci_ring *ep_ring;
 801         struct xhci_virt_ep *ep;
 802         struct list_head *entry;
 803         struct xhci_td *cur_td = NULL;
 804         struct xhci_td *last_unlinked_td;
 805
 806         struct xhci_dequeue_state deq_state;
 807
 808         if (unlikely(TRB_TO_SUSPEND_PORT(
 809                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 810                 slot_id = TRB_TO_SLOT_ID(
 811                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 812                 virt_dev = xhci->devs[slot_id];
 813                 if (virt_dev)
 814                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 815                                 event);
 816                 else
 817                         xhci_warn(xhci, "Stop endpoint command "
 818                                 "completion for disabled slot %u\n",
 819                                 slot_id);
 820                 return;
 821         }
 822
 823         memset(&deq_state, 0, sizeof(deq_state));
 824         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 825         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 826         ep = &xhci->devs[slot_id]->eps[ep_index];
 827
 828         if (list_empty(&ep->cancelled_td_list)) {
 829                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 830                 ep->stopped_td = NULL;
 831                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 832                 return;
 833         }
 834
 835         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 836          * We have the xHCI lock, so nothing can modify this list until we drop
 837          * it.  We're also in the event handler, so we can't get re-interrupted
 838          * if another Stop Endpoint command completes
 839          */
 840         list_for_each(entry, &ep->cancelled_td_list) {
 841                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 842                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 843                                 cur_td->first_trb,
 844                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 845                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 846                 if (!ep_ring) {
 847                         /* This shouldn't happen unless a driver is mucking
 848                          * with the stream ID after submission.  This will
 849                          * leave the TD on the hardware ring, and the hardware
 850                          * will try to execute it, and may access a buffer
 851                          * that has already been freed.  In the best case, the
 852                          * hardware will execute it, and the event handler will
 853                          * ignore the completion event for that TD, since it was
 854                          * removed from the td_list for that endpoint.  In
 855                          * short, don't muck with the stream ID after
 856                          * submission.
 857                          */
 858                         xhci_warn(xhci, "WARN Cancelled URB %p "
 859                                         "has invalid stream ID %u.\n",
 860                                         cur_td->urb,
 861                                         cur_td->urb->stream_id);
 862                         goto remove_finished_td;
 863                 }
 864                 /*
 865                  * If we stopped on the TD we need to cancel, then we have to
 866                  * move the xHC endpoint ring dequeue pointer past this TD.
 867                  */
 868                 if (cur_td == ep->stopped_td)
 869                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 870                                         cur_td->urb->stream_id,
 871                                         cur_td, &deq_state);
 872                 else
 873                         td_to_noop(xhci, ep_ring, cur_td, false);
 874 remove_finished_td:
 875                 /*
 876                  * The event handler won't see a completion for this TD anymore,
 877                  * so remove it from the endpoint ring's TD list.  Keep it in
 878                  * the cancelled TD list for URB completion later.
 879                  */
 880                 list_del_init(&cur_td->td_list);
 881         }
 882         last_unlinked_td = cur_td;
 883         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 884
 885         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 886         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 887                 xhci_queue_new_dequeue_state(xhci,
 888                                 slot_id, ep_index,
 889                                 ep->stopped_td->urb->stream_id,
 890                                 &deq_state);
 891                 xhci_ring_cmd_db(xhci);
 892         } else {
 893                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 894                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 895         }
 896
 897         /* Clear stopped_td if endpoint is not halted */
 898         if (!(ep->ep_state & EP_HALTED))
 899                 ep->stopped_td = NULL;
 900
 901         /*
 902          * Drop the lock and complete the URBs in the cancelled TD list.
 903          * New TDs to be cancelled might be added to the end of the list before
 904          * we can complete all the URBs for the TDs we already unlinked.
 905          * So stop when we've completed the URB for the last TD we unlinked.
 906          */
 907         do {
 908                 cur_td = list_entry(ep->cancelled_td_list.next,
 909                                 struct xhci_td, cancelled_td_list);
 910                 list_del_init(&cur_td->cancelled_td_list);
 911
 912                 /* Clean up the cancelled URB */
 913                 /* Doesn't matter what we pass for status, since the core will
 914                  * just overwrite it (because the URB has been unlinked).
 915                  */
 916                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 917
 918                 /* Stop processing the cancelled list if the watchdog timer is
 919                  * running.
 920                  */
 921                 if (xhci->xhc_state & XHCI_STATE_DYING)
 922                         return;
 923         } while (cur_td != last_unlinked_td);
 924
 925         /* Return to the event handler with xhci->lock re-acquired */
 926 }
 927
 928 /* Watchdog timer function for when a stop endpoint command fails to complete.
 929  * In this case, we assume the host controller is broken or dying or dead.  The
 930  * host may still be completing some other events, so we have to be careful to
 931  * let the event ring handler and the URB dequeueing/enqueueing functions know
 932  * through xhci->state.
 933  *
 934  * The timer may also fire if the host takes a very long time to respond to the
 935  * command, and the stop endpoint command completion handler cannot delete the
 936  * timer before the timer function is called.  Another endpoint cancellation may
 937  * sneak in before the timer function can grab the lock, and that may queue
 938  * another stop endpoint command and add the timer back.  So we cannot use a
 939  * simple flag to say whether there is a pending stop endpoint command for a
 940  * particular endpoint.
 941  *
 942  * Instead we use a combination of that flag and a counter for the number of
 943  * pending stop endpoint commands.  If the timer is the tail end of the last
 944  * stop endpoint command, and the endpoint's command is still pending, we assume
 945  * the host is dying.
 946  */
 947 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 948 {
 949         struct xhci_hcd *xhci;
 950         struct xhci_virt_ep *ep;
 951         struct xhci_virt_ep *temp_ep;
 952         struct xhci_ring *ring;
 953         struct xhci_td *cur_td;
 954         int ret, i, j;
 955         unsigned long flags;
 956
 957         ep = (struct xhci_virt_ep *) arg;
 958         xhci = ep->xhci;
 959
 960         spin_lock_irqsave(&xhci->lock, flags);
 961
 962         ep->stop_cmds_pending--;
 963         if (xhci->xhc_state & XHCI_STATE_DYING) {
 964                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 965                                 "xHCI as DYING, exiting.\n");
 966                 spin_unlock_irqrestore(&xhci->lock, flags);
 967                 return;
 968         }
 969         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 970                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 971                                 "exiting.\n");
 972                 spin_unlock_irqrestore(&xhci->lock, flags);
 973                 return;
 974         }
 975
 976         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 977         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 978         /* Oops, HC is dead or dying or at least not responding to the stop
 979          * endpoint command.
 980          */
 981         xhci->xhc_state |= XHCI_STATE_DYING;
 982         /* Disable interrupts from the host controller and start halting it */
 983         xhci_quiesce(xhci);
 984         spin_unlock_irqrestore(&xhci->lock, flags);
 985
 986         ret = xhci_halt(xhci);
 987
 988         spin_lock_irqsave(&xhci->lock, flags);
 989         if (ret < 0) {
 990                 /* This is bad; the host is not responding to commands and it's
 991                  * not allowing itself to be halted.  At least interrupts are
 992                  * disabled. If we call usb_hc_died(), it will attempt to
 993                  * disconnect all device drivers under this host.  Those
 994                  * disconnect() methods will wait for all URBs to be unlinked,
 995                  * so we must complete them.
 996                  */
 997                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 998                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 999                 /* We could turn all TDs on the rings to no-ops.  This won't
1000                  * help if the host has cached part of the ring, and is slow if
1001                  * we want to preserve the cycle bit.  Skip it and hope the host
1002                  * doesn't touch the memory.
1003                  */
1004         }
1005         for (i = 0; i < MAX_HC_SLOTS; i++) {
1006                 if (!xhci->devs[i])
1007                         continue;
1008                 for (j = 0; j < 31; j++) {
1009                         temp_ep = &xhci->devs[i]->eps[j];
1010                         ring = temp_ep->ring;
1011                         if (!ring)
1012                                 continue;
1013                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
1014                                         "ep index %u\n", i, j);
1015                         while (!list_empty(&ring->td_list)) {
1016                                 cur_td = list_first_entry(&ring->td_list,
1017                                                 struct xhci_td,
1018                                                 td_list);
1019                                 list_del_init(&cur_td->td_list);
1020                                 if (!list_empty(&cur_td->cancelled_td_list))
1021                                         list_del_init(&cur_td->cancelled_td_list);
1022                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1023                                                 -ESHUTDOWN, "killed");
1024                         }
1025                         while (!list_empty(&temp_ep->cancelled_td_list)) {
1026                                 cur_td = list_first_entry(
1027                                                 &temp_ep->cancelled_td_list,
1028                                                 struct xhci_td,
1029                                                 cancelled_td_list);
1030                                 list_del_init(&cur_td->cancelled_td_list);
1031                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1032                                                 -ESHUTDOWN, "killed");
1033                         }
1034                 }
1035         }
1036         spin_unlock_irqrestore(&xhci->lock, flags);
1037         xhci_dbg(xhci, "Calling usb_hc_died()\n");
1038         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1039         xhci_dbg(xhci, "xHCI host controller is dead.\n");
1040 }
1041
1042 /*
1043  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1044  * we need to clear the set deq pending flag in the endpoint ring state, so that
1045  * the TD queueing code can ring the doorbell again.  We also need to ring the
1046  * endpoint doorbell to restart the ring, but only if there aren't more
1047  * cancellations pending.
1048  */
1049 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1050                 struct xhci_event_cmd *event,
1051                 union xhci_trb *trb)
1052 {
1053         unsigned int slot_id;
1054         unsigned int ep_index;
1055         unsigned int stream_id;
1056         struct xhci_ring *ep_ring;
1057         struct xhci_virt_device *dev;
1058         struct xhci_ep_ctx *ep_ctx;
1059         struct xhci_slot_ctx *slot_ctx;
1060
1061         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1062         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1063         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1064         dev = xhci->devs[slot_id];
1065
1066         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1067         if (!ep_ring) {
1068                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1069                                 "freed stream ID %u\n",
1070                                 stream_id);
1071                 /* XXX: Harmless??? */
1072                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1073                 return;
1074         }
1075
1076         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1077         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1078
1079         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1080                 unsigned int ep_state;
1081                 unsigned int slot_state;
1082
1083                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1084                 case COMP_TRB_ERR:
1085                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1086                                         "of stream ID configuration\n");
1087                         break;
1088                 case COMP_CTX_STATE:
1089                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1090                                         "to incorrect slot or ep state.\n");
1091                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1092                         ep_state &= EP_STATE_MASK;
1093                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1094                         slot_state = GET_SLOT_STATE(slot_state);
1095                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1096                                         slot_state, ep_state);
1097                         break;
1098                 case COMP_EBADSLT:
1099                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1100                                         "slot %u was not enabled.\n", slot_id);
1101                         break;
1102                 default:
1103                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1104                                         "completion code of %u.\n",
1105                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1106                         break;
1107                 }
1108                 /* OK what do we do now?  The endpoint state is hosed, and we
1109                  * should never get to this point if the synchronization between
1110                  * queueing, and endpoint state are correct.  This might happen
1111                  * if the device gets disconnected after we've finished
1112                  * cancelling URBs, which might not be an error...
1113                  */
1114         } else {
1115                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1116                          le64_to_cpu(ep_ctx->deq));
1117                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1118                                          dev->eps[ep_index].queued_deq_ptr) ==
1119                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1120                         /* Update the ring's dequeue segment and dequeue pointer
1121                          * to reflect the new position.
1122                          */
1123                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
1124                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
1125                 } else {
1126                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1127                                         "Ptr command & xHCI internal state.\n");
1128                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1129                                         dev->eps[ep_index].queued_deq_seg,
1130                                         dev->eps[ep_index].queued_deq_ptr);
1131                 }
1132         }
1133
1134         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1135         dev->eps[ep_index].queued_deq_seg = NULL;
1136         dev->eps[ep_index].queued_deq_ptr = NULL;
1137         /* Restart any rings with pending URBs */
1138         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1139 }
1140
1141 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1142                 struct xhci_event_cmd *event,
1143                 union xhci_trb *trb)
1144 {
1145         int slot_id;
1146         unsigned int ep_index;
1147
1148         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1149         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1150         /* This command will only fail if the endpoint wasn't halted,
1151          * but we don't care.
1152          */
1153         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1154                  GET_COMP_CODE(le32_to_cpu(event->status)));
1155
1156         /* HW with the reset endpoint quirk needs to have a configure endpoint
1157          * command complete before the endpoint can be used.  Queue that here
1158          * because the HW can't handle two commands being queued in a row.
1159          */
1160         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1161                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1162                 xhci_queue_configure_endpoint(xhci,
1163                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1164                                 false);
1165                 xhci_ring_cmd_db(xhci);
1166         } else {
1167                 /* Clear our internal halted state */
1168                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1169         }
1170 }
1171
1172 /* Complete the command and detele it from the devcie's command queue.
1173  */
1174 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1175                 struct xhci_command *command, u32 status)
1176 {
1177         command->status = status;
1178         list_del(&command->cmd_list);
1179         if (command->completion)
1180                 complete(command->completion);
1181         else
1182                 xhci_free_command(xhci, command);
1183 }
1184
1185
1186 /* Check to see if a command in the device's command queue matches this one.
1187  * Signal the completion or free the command, and return 1.  Return 0 if the
1188  * completed command isn't at the head of the command list.
1189  */
1190 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1191                 struct xhci_virt_device *virt_dev,
1192                 struct xhci_event_cmd *event)
1193 {
1194         struct xhci_command *command;
1195
1196         if (list_empty(&virt_dev->cmd_list))
1197                 return 0;
1198
1199         command = list_entry(virt_dev->cmd_list.next,
1200                         struct xhci_command, cmd_list);
1201         if (xhci->cmd_ring->dequeue != command->command_trb)
1202                 return 0;
1203
1204         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1205                         GET_COMP_CODE(le32_to_cpu(event->status)));
1206         return 1;
1207 }
1208
1209 /*
1210  * Finding the command trb need to be cancelled and modifying it to
1211  * NO OP command. And if the command is in device's command wait
1212  * list, finishing and freeing it.
1213  *
1214  * If we can't find the command trb, we think it had already been
1215  * executed.
1216  */
1217 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1218 {
1219         struct xhci_segment *cur_seg;
1220         union xhci_trb *cmd_trb;
1221         u32 cycle_state;
1222
1223         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1224                 return;
1225
1226         /* find the current segment of command ring */
1227         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1228                         xhci->cmd_ring->dequeue, &cycle_state);
1229
1230         if (!cur_seg) {
1231                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1232                                 xhci->cmd_ring->dequeue,
1233                                 (unsigned long long)
1234                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1235                                         xhci->cmd_ring->dequeue));
1236                 xhci_debug_ring(xhci, xhci->cmd_ring);
1237                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1238                 return;
1239         }
1240
1241         /* find the command trb matched by cd from command ring */
1242         for (cmd_trb = xhci->cmd_ring->dequeue;
1243                         cmd_trb != xhci->cmd_ring->enqueue;
1244                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1245                 /* If the trb is link trb, continue */
1246                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1247                         continue;
1248
1249                 if (cur_cd->cmd_trb == cmd_trb) {
1250
1251                         /* If the command in device's command list, we should
1252                          * finish it and free the command structure.
1253                          */
1254                         if (cur_cd->command)
1255                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1256                                         cur_cd->command, COMP_CMD_STOP);
1257
1258                         /* get cycle state from the origin command trb */
1259                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1260                                 & TRB_CYCLE;
1261
1262                         /* modify the command trb to NO OP command */
1263                         cmd_trb->generic.field[0] = 0;
1264                         cmd_trb->generic.field[1] = 0;
1265                         cmd_trb->generic.field[2] = 0;
1266                         cmd_trb->generic.field[3] = cpu_to_le32(
1267                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1268                         break;
1269                 }
1270         }
1271 }
1272
1273 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1274 {
1275         struct xhci_cd *cur_cd, *next_cd;
1276
1277         if (list_empty(&xhci->cancel_cmd_list))
1278                 return;
1279
1280         list_for_each_entry_safe(cur_cd, next_cd,
1281                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1282                 xhci_cmd_to_noop(xhci, cur_cd);
1283                 list_del(&cur_cd->cancel_cmd_list);
1284                 kfree(cur_cd);
1285         }
1286 }
1287
1288 /*
1289  * traversing the cancel_cmd_list. If the command descriptor according
1290  * to cmd_trb is found, the function free it and return 1, otherwise
1291  * return 0.
1292  */
1293 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1294                 union xhci_trb *cmd_trb)
1295 {
1296         struct xhci_cd *cur_cd, *next_cd;
1297
1298         if (list_empty(&xhci->cancel_cmd_list))
1299                 return 0;
1300
1301         list_for_each_entry_safe(cur_cd, next_cd,
1302                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1303                 if (cur_cd->cmd_trb == cmd_trb) {
1304                         if (cur_cd->command)
1305                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1306                                         cur_cd->command, COMP_CMD_STOP);
1307                         list_del(&cur_cd->cancel_cmd_list);
1308                         kfree(cur_cd);
1309                         return 1;
1310                 }
1311         }
1312
1313         return 0;
1314 }
1315
1316 /*
1317  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1318  * trb pointed by the command ring dequeue pointer is the trb we want to
1319  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1320  * traverse the cancel_cmd_list to trun the all of the commands according
1321  * to command descriptor to NO-OP trb.
1322  */
1323 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1324                 int cmd_trb_comp_code)
1325 {
1326         int cur_trb_is_good = 0;
1327
1328         /* Searching the cmd trb pointed by the command ring dequeue
1329          * pointer in command descriptor list. If it is found, free it.
1330          */
1331         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1332                         xhci->cmd_ring->dequeue);
1333
1334         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1335                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1336         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1337                 /* traversing the cancel_cmd_list and canceling
1338                  * the command according to command descriptor
1339                  */
1340                 xhci_cancel_cmd_in_cd_list(xhci);
1341
1342                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1343                 /*
1344                  * ring command ring doorbell again to restart the
1345                  * command ring
1346                  */
1347                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1348                         xhci_ring_cmd_db(xhci);
1349         }
1350         return cur_trb_is_good;
1351 }
1352
1353 static void handle_cmd_completion(struct xhci_hcd *xhci,
1354                 struct xhci_event_cmd *event)
1355 {
1356         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1357         u64 cmd_dma;
1358         dma_addr_t cmd_dequeue_dma;
1359         struct xhci_input_control_ctx *ctrl_ctx;
1360         struct xhci_virt_device *virt_dev;
1361         unsigned int ep_index;
1362         struct xhci_ring *ep_ring;
1363         unsigned int ep_state;
1364
1365         cmd_dma = le64_to_cpu(event->cmd_trb);
1366         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1367                         xhci->cmd_ring->dequeue);
1368         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1369         if (cmd_dequeue_dma == 0) {
1370                 xhci->error_bitmask |= 1 << 4;
1371                 return;
1372         }
1373         /* Does the DMA address match our internal dequeue pointer address? */
1374         if (cmd_dma != (u64) cmd_dequeue_dma) {
1375                 xhci->error_bitmask |= 1 << 5;
1376                 return;
1377         }
1378
1379         if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1380                 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1381                 /* If the return value is 0, we think the trb pointed by
1382                  * command ring dequeue pointer is a good trb. The good
1383                  * trb means we don't want to cancel the trb, but it have
1384                  * been stopped by host. So we should handle it normally.
1385                  * Otherwise, driver should invoke inc_deq() and return.
1386                  */
1387                 if (handle_stopped_cmd_ring(xhci,
1388                                 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1389                         inc_deq(xhci, xhci->cmd_ring, false);
1390                         return;
1391                 }
1392         }
1393
1394         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1395                 & TRB_TYPE_BITMASK) {
1396         case TRB_TYPE(TRB_ENABLE_SLOT):
1397                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1398                         xhci->slot_id = slot_id;
1399                 else
1400                         xhci->slot_id = 0;
1401                 complete(&xhci->addr_dev);
1402                 break;
1403         case TRB_TYPE(TRB_DISABLE_SLOT):
1404                 if (xhci->devs[slot_id]) {
1405                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1406                                 /* Delete default control endpoint resources */
1407                                 xhci_free_device_endpoint_resources(xhci,
1408                                                 xhci->devs[slot_id], true);
1409                         xhci_free_virt_device(xhci, slot_id);
1410                 }
1411                 break;
1412         case TRB_TYPE(TRB_CONFIG_EP):
1413                 virt_dev = xhci->devs[slot_id];
1414                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1415                         break;
1416                 /*
1417                  * Configure endpoint commands can come from the USB core
1418                  * configuration or alt setting changes, or because the HW
1419                  * needed an extra configure endpoint command after a reset
1420                  * endpoint command or streams were being configured.
1421                  * If the command was for a halted endpoint, the xHCI driver
1422                  * is not waiting on the configure endpoint command.
1423                  */
1424                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1425                                 virt_dev->in_ctx);
1426                 /* Input ctx add_flags are the endpoint index plus one */
1427                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1428                 /* A usb_set_interface() call directly after clearing a halted
1429                  * condition may race on this quirky hardware.  Not worth
1430                  * worrying about, since this is prototype hardware.  Not sure
1431                  * if this will work for streams, but streams support was
1432                  * untested on this prototype.
1433                  */
1434                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1435                                 ep_index != (unsigned int) -1 &&
1436                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1437                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1438                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1439                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1440                         if (!(ep_state & EP_HALTED))
1441                                 goto bandwidth_change;
1442                         xhci_dbg(xhci, "Completed config ep cmd - "
1443                                         "last ep index = %d, state = %d\n",
1444                                         ep_index, ep_state);
1445                         /* Clear internal halted state and restart ring(s) */
1446                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1447                                 ~EP_HALTED;
1448                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1449                         break;
1450                 }
1451 bandwidth_change:
1452                 xhci_dbg(xhci, "Completed config ep cmd\n");
1453                 xhci->devs[slot_id]->cmd_status =
1454                         GET_COMP_CODE(le32_to_cpu(event->status));
1455                 complete(&xhci->devs[slot_id]->cmd_completion);
1456                 break;
1457         case TRB_TYPE(TRB_EVAL_CONTEXT):
1458                 virt_dev = xhci->devs[slot_id];
1459                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1460                         break;
1461                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1462                 complete(&xhci->devs[slot_id]->cmd_completion);
1463                 break;
1464         case TRB_TYPE(TRB_ADDR_DEV):
1465                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1466                 complete(&xhci->addr_dev);
1467                 break;
1468         case TRB_TYPE(TRB_STOP_RING):
1469                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1470                 break;
1471         case TRB_TYPE(TRB_SET_DEQ):
1472                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1473                 break;
1474         case TRB_TYPE(TRB_CMD_NOOP):
1475                 break;
1476         case TRB_TYPE(TRB_RESET_EP):
1477                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1478                 break;
1479         case TRB_TYPE(TRB_RESET_DEV):
1480                 xhci_dbg(xhci, "Completed reset device command.\n");
1481                 slot_id = TRB_TO_SLOT_ID(
1482                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1483                 virt_dev = xhci->devs[slot_id];
1484                 if (virt_dev)
1485                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1486                 else
1487                         xhci_warn(xhci, "Reset device command completion "
1488                                         "for disabled slot %u\n", slot_id);
1489                 break;
1490         case TRB_TYPE(TRB_NEC_GET_FW):
1491                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1492                         xhci->error_bitmask |= 1 << 6;
1493                         break;
1494                 }
1495                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1496                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1497                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1498                 break;
1499         default:
1500                 /* Skip over unknown commands on the event ring */
1501                 xhci->error_bitmask |= 1 << 6;
1502                 break;
1503         }
1504         inc_deq(xhci, xhci->cmd_ring, false);
1505 }
1506
1507 static void handle_vendor_event(struct xhci_hcd *xhci,
1508                 union xhci_trb *event)
1509 {
1510         u32 trb_type;
1511
1512         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1513         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1514         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1515                 handle_cmd_completion(xhci, &event->event_cmd);
1516 }
1517
1518 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1519  * port registers -- USB 3.0 and USB 2.0).
1520  *
1521  * Returns a zero-based port number, which is suitable for indexing into each of
1522  * the split roothubs' port arrays and bus state arrays.
1523  * Add one to it in order to call xhci_find_slot_id_by_port.
1524  */
1525 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1526                 struct xhci_hcd *xhci, u32 port_id)
1527 {
1528         unsigned int i;
1529         unsigned int num_similar_speed_ports = 0;
1530
1531         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1532          * and usb2_ports are 0-based indexes.  Count the number of similar
1533          * speed ports, up to 1 port before this port.
1534          */
1535         for (i = 0; i < (port_id - 1); i++) {
1536                 u8 port_speed = xhci->port_array[i];
1537
1538                 /*
1539                  * Skip ports that don't have known speeds, or have duplicate
1540                  * Extended Capabilities port speed entries.
1541                  */
1542                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1543                         continue;
1544
1545                 /*
1546                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1547                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1548                  * matches the device speed, it's a similar speed port.
1549                  */
1550                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1551                         num_similar_speed_ports++;
1552         }
1553         return num_similar_speed_ports;
1554 }
1555
1556 static void handle_port_status(struct xhci_hcd *xhci,
1557                 union xhci_trb *event)
1558 {
1559         struct usb_hcd *hcd;
1560         u32 port_id;
1561         u32 temp, temp1;
1562         int max_ports;
1563         int slot_id;
1564         unsigned int faked_port_index;
1565         u8 major_revision;
1566         struct xhci_bus_state *bus_state;
1567         __le32 __iomem **port_array;
1568         bool bogus_port_status = false;
1569
1570         /* Port status change events always have a successful completion code */
1571         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1572                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1573                 xhci->error_bitmask |= 1 << 8;
1574         }
1575         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1576         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1577
1578         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1579         if ((port_id <= 0) || (port_id > max_ports)) {
1580                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1581                 bogus_port_status = true;
1582                 goto cleanup;
1583         }
1584
1585         /* Figure out which usb_hcd this port is attached to:
1586          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1587          */
1588         major_revision = xhci->port_array[port_id - 1];
1589         if (major_revision == 0) {
1590                 xhci_warn(xhci, "Event for port %u not in "
1591                                 "Extended Capabilities, ignoring.\n",
1592                                 port_id);
1593                 bogus_port_status = true;
1594                 goto cleanup;
1595         }
1596         if (major_revision == DUPLICATE_ENTRY) {
1597                 xhci_warn(xhci, "Event for port %u duplicated in"
1598                                 "Extended Capabilities, ignoring.\n",
1599                                 port_id);
1600                 bogus_port_status = true;
1601                 goto cleanup;
1602         }
1603
1604         /*
1605          * Hardware port IDs reported by a Port Status Change Event include USB
1606          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1607          * resume event, but we first need to translate the hardware port ID
1608          * into the index into the ports on the correct split roothub, and the
1609          * correct bus_state structure.
1610          */
1611         /* Find the right roothub. */
1612         hcd = xhci_to_hcd(xhci);
1613         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1614                 hcd = xhci->shared_hcd;
1615         bus_state = &xhci->bus_state[hcd_index(hcd)];
1616         if (hcd->speed == HCD_USB3)
1617                 port_array = xhci->usb3_ports;
1618         else
1619                 port_array = xhci->usb2_ports;
1620         /* Find the faked port hub number */
1621         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1622                         port_id);
1623
1624         temp = xhci_readl(xhci, port_array[faked_port_index]);
1625         if (hcd->state == HC_STATE_SUSPENDED) {
1626                 xhci_dbg(xhci, "resume root hub\n");
1627                 usb_hcd_resume_root_hub(hcd);
1628         }
1629
1630         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1631                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1632
1633                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1634                 if (!(temp1 & CMD_RUN)) {
1635                         xhci_warn(xhci, "xHC is not running.\n");
1636                         goto cleanup;
1637                 }
1638
1639                 if (DEV_SUPERSPEED(temp)) {
1640                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1641                         xhci_set_link_state(xhci, port_array, faked_port_index,
1642                                                 XDEV_U0);
1643                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1644                                         faked_port_index + 1);
1645                         if (!slot_id) {
1646                                 xhci_dbg(xhci, "slot_id is zero\n");
1647                                 goto cleanup;
1648                         }
1649                         xhci_ring_device(xhci, slot_id);
1650                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1651                         /* Clear PORT_PLC */
1652                         xhci_test_and_clear_bit(xhci, port_array,
1653                                                 faked_port_index, PORT_PLC);
1654                 } else {
1655                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1656                         bus_state->resume_done[faked_port_index] = jiffies +
1657                                 msecs_to_jiffies(20);
1658                         mod_timer(&hcd->rh_timer,
1659                                   bus_state->resume_done[faked_port_index]);
1660                         /* Do the rest in GetPortStatus */
1661                 }
1662         }
1663
1664         if (hcd->speed != HCD_USB3)
1665                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1666                                         PORT_PLC);
1667
1668 cleanup:
1669         /* Update event ring dequeue pointer before dropping the lock */
1670         inc_deq(xhci, xhci->event_ring, true);
1671
1672         /* Don't make the USB core poll the roothub if we got a bad port status
1673          * change event.  Besides, at that point we can't tell which roothub
1674          * (USB 2.0 or USB 3.0) to kick.
1675          */
1676         if (bogus_port_status)
1677                 return;
1678
1679         /*
1680          * xHCI port-status-change events occur when the "or" of all the
1681          * status-change bits in the portsc register changes from 0 to 1.
1682          * New status changes won't cause an event if any other change
1683          * bits are still set.  When an event occurs, switch over to
1684          * polling to avoid losing status changes.
1685          */
1686         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1687         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1688         spin_unlock(&xhci->lock);
1689         /* Pass this up to the core */
1690         usb_hcd_poll_rh_status(hcd);
1691         spin_lock(&xhci->lock);
1692 }
1693
1694 /*
1695  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1696  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1697  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1698  * returns 0.
1699  */
1700 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1701                 union xhci_trb  *start_trb,
1702                 union xhci_trb  *end_trb,
1703                 dma_addr_t      suspect_dma)
1704 {
1705         dma_addr_t start_dma;
1706         dma_addr_t end_seg_dma;
1707         dma_addr_t end_trb_dma;
1708         struct xhci_segment *cur_seg;
1709
1710         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1711         cur_seg = start_seg;
1712
1713         do {
1714                 if (start_dma == 0)
1715                         return NULL;
1716                 /* We may get an event for a Link TRB in the middle of a TD */
1717                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1718                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1719                 /* If the end TRB isn't in this segment, this is set to 0 */
1720                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1721
1722                 if (end_trb_dma > 0) {
1723                         /* The end TRB is in this segment, so suspect should be here */
1724                         if (start_dma <= end_trb_dma) {
1725                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1726                                         return cur_seg;
1727                         } else {
1728                                 /* Case for one segment with
1729                                  * a TD wrapped around to the top
1730                                  */
1731                                 if ((suspect_dma >= start_dma &&
1732                                                         suspect_dma <= end_seg_dma) ||
1733                                                 (suspect_dma >= cur_seg->dma &&
1734                                                  suspect_dma <= end_trb_dma))
1735                                         return cur_seg;
1736                         }
1737                         return NULL;
1738                 } else {
1739                         /* Might still be somewhere in this segment */
1740                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1741                                 return cur_seg;
1742                 }
1743                 cur_seg = cur_seg->next;
1744                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1745         } while (cur_seg != start_seg);
1746
1747         return NULL;
1748 }
1749
1750 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1751                 unsigned int slot_id, unsigned int ep_index,
1752                 unsigned int stream_id,
1753                 struct xhci_td *td, union xhci_trb *event_trb)
1754 {
1755         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1756         ep->ep_state |= EP_HALTED;
1757         ep->stopped_td = td;
1758         ep->stopped_stream = stream_id;
1759
1760         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1761         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1762
1763         ep->stopped_td = NULL;
1764         ep->stopped_stream = 0;
1765
1766         xhci_ring_cmd_db(xhci);
1767 }
1768
1769 /* Check if an error has halted the endpoint ring.  The class driver will
1770  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1771  * However, a babble and other errors also halt the endpoint ring, and the class
1772  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1773  * Ring Dequeue Pointer command manually.
1774  */
1775 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1776                 struct xhci_ep_ctx *ep_ctx,
1777                 unsigned int trb_comp_code)
1778 {
1779         /* TRB completion codes that may require a manual halt cleanup */
1780         if (trb_comp_code == COMP_TX_ERR ||
1781                         trb_comp_code == COMP_BABBLE ||
1782                         trb_comp_code == COMP_SPLIT_ERR)
1783                 /* The 0.96 spec says a babbling control endpoint
1784                  * is not halted. The 0.96 spec says it is.  Some HW
1785                  * claims to be 0.95 compliant, but it halts the control
1786                  * endpoint anyway.  Check if a babble halted the
1787                  * endpoint.
1788                  */
1789                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1790                     cpu_to_le32(EP_STATE_HALTED))
1791                         return 1;
1792
1793         return 0;
1794 }
1795
1796 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1797 {
1798         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1799                 /* Vendor defined "informational" completion code,
1800                  * treat as not-an-error.
1801                  */
1802                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1803                                 trb_comp_code);
1804                 xhci_dbg(xhci, "Treating code as success.\n");
1805                 return 1;
1806         }
1807         return 0;
1808 }
1809
1810 /*
1811  * Finish the td processing, remove the td from td list;
1812  * Return 1 if the urb can be given back.
1813  */
1814 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1815         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1816         struct xhci_virt_ep *ep, int *status, bool skip)
1817 {
1818         struct xhci_virt_device *xdev;
1819         struct xhci_ring *ep_ring;
1820         unsigned int slot_id;
1821         int ep_index;
1822         struct urb *urb = NULL;
1823         struct xhci_ep_ctx *ep_ctx;
1824         int ret = 0;
1825         struct urb_priv *urb_priv;
1826         u32 trb_comp_code;
1827
1828         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1829         xdev = xhci->devs[slot_id];
1830         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1831         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1832         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1833         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1834
1835         if (skip)
1836                 goto td_cleanup;
1837
1838         if (trb_comp_code == COMP_STOP_INVAL ||
1839                         trb_comp_code == COMP_STOP) {
1840                 /* The Endpoint Stop Command completion will take care of any
1841                  * stopped TDs.  A stopped TD may be restarted, so don't update
1842                  * the ring dequeue pointer or take this TD off any lists yet.
1843                  */
1844                 ep->stopped_td = td;
1845                 return 0;
1846         } else {
1847                 if (trb_comp_code == COMP_STALL ||
1848                     xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1849                                                       trb_comp_code)) {
1850                         /* Issue a reset endpoint command to clear the host side
1851                          * halt, followed by a set dequeue command to move the
1852                          * dequeue pointer past the TD.
1853                          * The class driver clears the device side halt later.
1854                          */
1855                         xhci_cleanup_halted_endpoint(xhci,
1856                                         slot_id, ep_index, ep_ring->stream_id,
1857                                         td, event_trb);
1858                 } else {
1859                         /* Update ring dequeue pointer */
1860                         while (ep_ring->dequeue != td->last_trb)
1861                                 inc_deq(xhci, ep_ring, false);
1862                         inc_deq(xhci, ep_ring, false);
1863                 }
1864
1865 td_cleanup:
1866                 /* Clean up the endpoint's TD list */
1867                 urb = td->urb;
1868                 urb_priv = urb->hcpriv;
1869
1870                 /* Do one last check of the actual transfer length.
1871                  * If the host controller said we transferred more data than
1872                  * the buffer length, urb->actual_length will be a very big
1873                  * number (since it's unsigned).  Play it safe and say we didn't
1874                  * transfer anything.
1875                  */
1876                 if (urb->actual_length > urb->transfer_buffer_length) {
1877                         xhci_warn(xhci, "URB transfer length is wrong, "
1878                                         "xHC issue? req. len = %u, "
1879                                         "act. len = %u\n",
1880                                         urb->transfer_buffer_length,
1881                                         urb->actual_length);
1882                         urb->actual_length = 0;
1883                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1884                                 *status = -EREMOTEIO;
1885                         else
1886                                 *status = 0;
1887                 }
1888                 list_del_init(&td->td_list);
1889                 /* Was this TD slated to be cancelled but completed anyway? */
1890                 if (!list_empty(&td->cancelled_td_list))
1891                         list_del_init(&td->cancelled_td_list);
1892
1893                 urb_priv->td_cnt++;
1894                 /* Giveback the urb when all the tds are completed */
1895                 if (urb_priv->td_cnt == urb_priv->length) {
1896                         ret = 1;
1897                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1898                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1899                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1900                                         == 0) {
1901                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1902                                                 usb_amd_quirk_pll_enable();
1903                                 }
1904                         }
1905                 }
1906         }
1907
1908         return ret;
1909 }
1910
1911 /*
1912  * Process control tds, update urb status and actual_length.
1913  */
1914 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1915         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1916         struct xhci_virt_ep *ep, int *status)
1917 {
1918         struct xhci_virt_device *xdev;
1919         struct xhci_ring *ep_ring;
1920         unsigned int slot_id;
1921         int ep_index;
1922         struct xhci_ep_ctx *ep_ctx;
1923         u32 trb_comp_code;
1924
1925         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1926         xdev = xhci->devs[slot_id];
1927         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1928         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1929         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1930         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1931
1932         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1933         switch (trb_comp_code) {
1934         case COMP_SUCCESS:
1935                 if (event_trb == ep_ring->dequeue) {
1936                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1937                                         "without IOC set??\n");
1938                         *status = -ESHUTDOWN;
1939                 } else if (event_trb != td->last_trb) {
1940                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1941                                         "without IOC set??\n");
1942                         *status = -ESHUTDOWN;
1943                 } else {
1944                         *status = 0;
1945                 }
1946                 break;
1947         case COMP_SHORT_TX:
1948                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1949                         *status = -EREMOTEIO;
1950                 else
1951                         *status = 0;
1952                 break;
1953         case COMP_STOP_INVAL:
1954         case COMP_STOP:
1955                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1956         default:
1957                 if (!xhci_requires_manual_halt_cleanup(xhci,
1958                                         ep_ctx, trb_comp_code))
1959                         break;
1960                 xhci_dbg(xhci, "TRB error code %u, "
1961                                 "halted endpoint index = %u\n",
1962                                 trb_comp_code, ep_index);
1963                 /* else fall through */
1964         case COMP_STALL:
1965                 /* Did we transfer part of the data (middle) phase? */
1966                 if (event_trb != ep_ring->dequeue &&
1967                                 event_trb != td->last_trb)
1968                         td->urb->actual_length =
1969                                 td->urb->transfer_buffer_length -
1970                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1971                 else
1972                         td->urb->actual_length = 0;
1973
1974                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1975         }
1976         /*
1977          * Did we transfer any data, despite the errors that might have
1978          * happened?  I.e. did we get past the setup stage?
1979          */
1980         if (event_trb != ep_ring->dequeue) {
1981                 /* The event was for the status stage */
1982                 if (event_trb == td->last_trb) {
1983                         if (td->urb->actual_length != 0) {
1984                                 /* Don't overwrite a previously set error code
1985                                  */
1986                                 if ((*status == -EINPROGRESS || *status == 0) &&
1987                                                 (td->urb->transfer_flags
1988                                                  & URB_SHORT_NOT_OK))
1989                                         /* Did we already see a short data
1990                                          * stage? */
1991                                         *status = -EREMOTEIO;
1992                         } else {
1993                                 td->urb->actual_length =
1994                                         td->urb->transfer_buffer_length;
1995                         }
1996                 } else {
1997                 /* Maybe the event was for the data stage? */
1998                         td->urb->actual_length =
1999                                 td->urb->transfer_buffer_length -
2000                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2001                         xhci_dbg(xhci, "Waiting for status "
2002                                         "stage event\n");
2003                         return 0;
2004                 }
2005         }
2006
2007         return finish_td(xhci, td, event_trb, event, ep, status, false);
2008 }
2009
2010 /*
2011  * Process isochronous tds, update urb packet status and actual_length.
2012  */
2013 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2014         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2015         struct xhci_virt_ep *ep, int *status)
2016 {
2017         struct xhci_ring *ep_ring;
2018         struct urb_priv *urb_priv;
2019         int idx;
2020         int len = 0;
2021         union xhci_trb *cur_trb;
2022         struct xhci_segment *cur_seg;
2023         struct usb_iso_packet_descriptor *frame;
2024         u32 trb_comp_code;
2025         bool skip_td = false;
2026
2027         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2028         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2029         urb_priv = td->urb->hcpriv;
2030         idx = urb_priv->td_cnt;
2031         frame = &td->urb->iso_frame_desc[idx];
2032
2033         /* handle completion code */
2034         switch (trb_comp_code) {
2035         case COMP_SUCCESS:
2036                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2037                         frame->status = 0;
2038                         break;
2039                 }
2040                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2041                         trb_comp_code = COMP_SHORT_TX;
2042         case COMP_SHORT_TX:
2043                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2044                                 -EREMOTEIO : 0;
2045                 break;
2046         case COMP_BW_OVER:
2047                 frame->status = -ECOMM;
2048                 skip_td = true;
2049                 break;
2050         case COMP_BUFF_OVER:
2051         case COMP_BABBLE:
2052                 frame->status = -EOVERFLOW;
2053                 skip_td = true;
2054                 break;
2055         case COMP_DEV_ERR:
2056         case COMP_STALL:
2057         case COMP_TX_ERR:
2058                 frame->status = -EPROTO;
2059                 skip_td = true;
2060                 break;
2061         case COMP_STOP:
2062         case COMP_STOP_INVAL:
2063                 break;
2064         default:
2065                 frame->status = -1;
2066                 break;
2067         }
2068
2069         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2070                 frame->actual_length = frame->length;
2071                 td->urb->actual_length += frame->length;
2072         } else {
2073                 for (cur_trb = ep_ring->dequeue,
2074                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2075                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2076                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2077                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2078                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2079                 }
2080                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2081                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2082
2083                 if (trb_comp_code != COMP_STOP_INVAL) {
2084                         frame->actual_length = len;
2085                         td->urb->actual_length += len;
2086                 }
2087         }
2088
2089         return finish_td(xhci, td, event_trb, event, ep, status, false);
2090 }
2091
2092 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2093                         struct xhci_transfer_event *event,
2094                         struct xhci_virt_ep *ep, int *status)
2095 {
2096         struct xhci_ring *ep_ring;
2097         struct urb_priv *urb_priv;
2098         struct usb_iso_packet_descriptor *frame;
2099         int idx;
2100
2101         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2102         urb_priv = td->urb->hcpriv;
2103         idx = urb_priv->td_cnt;
2104         frame = &td->urb->iso_frame_desc[idx];
2105
2106         /* The transfer is partly done. */
2107         frame->status = -EXDEV;
2108
2109         /* calc actual length */
2110         frame->actual_length = 0;
2111
2112         /* Update ring dequeue pointer */
2113         while (ep_ring->dequeue != td->last_trb)
2114                 inc_deq(xhci, ep_ring, false);
2115         inc_deq(xhci, ep_ring, false);
2116
2117         return finish_td(xhci, td, NULL, event, ep, status, true);
2118 }
2119
2120 /*
2121  * Process bulk and interrupt tds, update urb status and actual_length.
2122  */
2123 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2124         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2125         struct xhci_virt_ep *ep, int *status)
2126 {
2127         struct xhci_ring *ep_ring;
2128         union xhci_trb *cur_trb;
2129         struct xhci_segment *cur_seg;
2130         u32 trb_comp_code;
2131
2132         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2133         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2134
2135         switch (trb_comp_code) {
2136         case COMP_SUCCESS:
2137                 /* Double check that the HW transferred everything. */
2138                 if (event_trb != td->last_trb ||
2139                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2140                         xhci_warn(xhci, "WARN Successful completion "
2141                                         "on short TX\n");
2142                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2143                                 *status = -EREMOTEIO;
2144                         else
2145                                 *status = 0;
2146                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2147                                 trb_comp_code = COMP_SHORT_TX;
2148                 } else {
2149                         *status = 0;
2150                 }
2151                 break;
2152         case COMP_SHORT_TX:
2153                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2154                         *status = -EREMOTEIO;
2155                 else
2156                         *status = 0;
2157                 break;
2158         default:
2159                 /* Others already handled above */
2160                 break;
2161         }
2162         if (trb_comp_code == COMP_SHORT_TX)
2163                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2164                                 "%d bytes untransferred\n",
2165                                 td->urb->ep->desc.bEndpointAddress,
2166                                 td->urb->transfer_buffer_length,
2167                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2168         /* Fast path - was this the last TRB in the TD for this URB? */
2169         if (event_trb == td->last_trb) {
2170                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2171                         td->urb->actual_length =
2172                                 td->urb->transfer_buffer_length -
2173                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2174                         if (td->urb->transfer_buffer_length <
2175                                         td->urb->actual_length) {
2176                                 xhci_warn(xhci, "HC gave bad length "
2177                                                 "of %d bytes left\n",
2178                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2179                                 td->urb->actual_length = 0;
2180                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2181                                         *status = -EREMOTEIO;
2182                                 else
2183                                         *status = 0;
2184                         }
2185                         /* Don't overwrite a previously set error code */
2186                         if (*status == -EINPROGRESS) {
2187                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2188                                         *status = -EREMOTEIO;
2189                                 else
2190                                         *status = 0;
2191                         }
2192                 } else {
2193                         td->urb->actual_length =
2194                                 td->urb->transfer_buffer_length;
2195                         /* Ignore a short packet completion if the
2196                          * untransferred length was zero.
2197                          */
2198                         if (*status == -EREMOTEIO)
2199                                 *status = 0;
2200                 }
2201         } else {
2202                 /* Slow path - walk the list, starting from the dequeue
2203                  * pointer, to get the actual length transferred.
2204                  */
2205                 td->urb->actual_length = 0;
2206                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2207                                 cur_trb != event_trb;
2208                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2209                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2210                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2211                                 td->urb->actual_length +=
2212                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2213                 }
2214                 /* If the ring didn't stop on a Link or No-op TRB, add
2215                  * in the actual bytes transferred from the Normal TRB
2216                  */
2217                 if (trb_comp_code != COMP_STOP_INVAL)
2218                         td->urb->actual_length +=
2219                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2220                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2221         }
2222
2223         return finish_td(xhci, td, event_trb, event, ep, status, false);
2224 }
2225
2226 /*
2227  * If this function returns an error condition, it means it got a Transfer
2228  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2229  * At this point, the host controller is probably hosed and should be reset.
2230  */
2231 static int handle_tx_event(struct xhci_hcd *xhci,
2232                 struct xhci_transfer_event *event)
2233 {
2234         struct xhci_virt_device *xdev;
2235         struct xhci_virt_ep *ep;
2236         struct xhci_ring *ep_ring;
2237         unsigned int slot_id;
2238         int ep_index;
2239         struct xhci_td *td = NULL;
2240         dma_addr_t event_dma;
2241         struct xhci_segment *event_seg;
2242         union xhci_trb *event_trb;
2243         struct urb *urb = NULL;
2244         int status = -EINPROGRESS;
2245         struct urb_priv *urb_priv;
2246         struct xhci_ep_ctx *ep_ctx;
2247         struct list_head *tmp;
2248         u32 trb_comp_code;
2249         int ret = 0;
2250         int td_num = 0;
2251
2252         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2253         xdev = xhci->devs[slot_id];
2254         if (!xdev) {
2255                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2256                 return -ENODEV;
2257         }
2258
2259         /* Endpoint ID is 1 based, our index is zero based */
2260         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2261         ep = &xdev->eps[ep_index];
2262         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2263         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2264         if (!ep_ring ||
2265             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2266             EP_STATE_DISABLED) {
2267                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2268                                 "or incorrect stream ring\n");
2269                 return -ENODEV;
2270         }
2271
2272         /* Count current td numbers if ep->skip is set */
2273         if (ep->skip) {
2274                 list_for_each(tmp, &ep_ring->td_list)
2275                         td_num++;
2276         }
2277
2278         event_dma = le64_to_cpu(event->buffer);
2279         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2280         /* Look for common error cases */
2281         switch (trb_comp_code) {
2282         /* Skip codes that require special handling depending on
2283          * transfer type
2284          */
2285         case COMP_SUCCESS:
2286                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2287                         break;
2288                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2289                         trb_comp_code = COMP_SHORT_TX;
2290                 else
2291                         xhci_warn(xhci, "WARN Successful completion on short TX: "
2292                                         "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2293         case COMP_SHORT_TX:
2294                 break;
2295         case COMP_STOP:
2296                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2297                 break;
2298         case COMP_STOP_INVAL:
2299                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2300                 break;
2301         case COMP_STALL:
2302                 xhci_dbg(xhci, "Stalled endpoint\n");
2303                 ep->ep_state |= EP_HALTED;
2304                 status = -EPIPE;
2305                 break;
2306         case COMP_TRB_ERR:
2307                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2308                 status = -EILSEQ;
2309                 break;
2310         case COMP_SPLIT_ERR:
2311         case COMP_TX_ERR:
2312                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2313                 status = -EPROTO;
2314                 break;
2315         case COMP_BABBLE:
2316                 xhci_dbg(xhci, "Babble error on endpoint\n");
2317                 status = -EOVERFLOW;
2318                 break;
2319         case COMP_DB_ERR:
2320                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2321                 status = -ENOSR;
2322                 break;
2323         case COMP_BW_OVER:
2324                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2325                 break;
2326         case COMP_BUFF_OVER:
2327                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2328                 break;
2329         case COMP_UNDERRUN:
2330                 /*
2331                  * When the Isoch ring is empty, the xHC will generate
2332                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2333                  * Underrun Event for OUT Isoch endpoint.
2334                  */
2335                 xhci_dbg(xhci, "underrun event on endpoint\n");
2336                 if (!list_empty(&ep_ring->td_list))
2337                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2338                                         "still with TDs queued?\n",
2339                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2340                                  ep_index);
2341                 goto cleanup;
2342         case COMP_OVERRUN:
2343                 xhci_dbg(xhci, "overrun event on endpoint\n");
2344                 if (!list_empty(&ep_ring->td_list))
2345                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2346                                         "still with TDs queued?\n",
2347                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2348                                  ep_index);
2349                 goto cleanup;
2350         case COMP_DEV_ERR:
2351                 xhci_warn(xhci, "WARN: detect an incompatible device");
2352                 status = -EPROTO;
2353                 break;
2354         case COMP_MISSED_INT:
2355                 /*
2356                  * When encounter missed service error, one or more isoc tds
2357                  * may be missed by xHC.
2358                  * Set skip flag of the ep_ring; Complete the missed tds as
2359                  * short transfer when process the ep_ring next time.
2360                  */
2361                 ep->skip = true;
2362                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2363                 goto cleanup;
2364         default:
2365                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2366                         status = 0;
2367                         break;
2368                 }
2369                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2370                                 "busted\n");
2371                 goto cleanup;
2372         }
2373
2374         do {
2375                 /* This TRB should be in the TD at the head of this ring's
2376                  * TD list.
2377                  */
2378                 if (list_empty(&ep_ring->td_list)) {
2379                         /*
2380                          * A stopped endpoint may generate an extra completion
2381                          * event if the device was suspended.  Don't print
2382                          * warnings.
2383                          */
2384                         if (!(trb_comp_code == COMP_STOP ||
2385                                                 trb_comp_code == COMP_STOP_INVAL)) {
2386                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2387                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2388                                                 ep_index);
2389                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2390                                                 (le32_to_cpu(event->flags) &
2391                                                  TRB_TYPE_BITMASK)>>10);
2392                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2393                         }
2394                         if (ep->skip) {
2395                                 ep->skip = false;
2396                                 xhci_dbg(xhci, "td_list is empty while skip "
2397                                                 "flag set. Clear skip flag.\n");
2398                         }
2399                         ret = 0;
2400                         goto cleanup;
2401                 }
2402
2403                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2404                 if (ep->skip && td_num == 0) {
2405                         ep->skip = false;
2406                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2407                                                 "Clear skip flag.\n");
2408                         ret = 0;
2409                         goto cleanup;
2410                 }
2411
2412                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2413                 if (ep->skip)
2414                         td_num--;
2415
2416                 /* Is this a TRB in the currently executing TD? */
2417                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2418                                 td->last_trb, event_dma);
2419
2420                 /*
2421                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2422                  * is not in the current TD pointed by ep_ring->dequeue because
2423                  * that the hardware dequeue pointer still at the previous TRB
2424                  * of the current TD. The previous TRB maybe a Link TD or the
2425                  * last TRB of the previous TD. The command completion handle
2426                  * will take care the rest.
2427                  */
2428                 if (!event_seg && (trb_comp_code == COMP_STOP ||
2429                                    trb_comp_code == COMP_STOP_INVAL)) {
2430                         ret = 0;
2431                         goto cleanup;
2432                 }
2433
2434                 if (!event_seg) {
2435                         if (!ep->skip ||
2436                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2437                                 /* Some host controllers give a spurious
2438                                  * successful event after a short transfer.
2439                                  * Ignore it.
2440                                  */
2441                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2442                                                 ep_ring->last_td_was_short) {
2443                                         ep_ring->last_td_was_short = false;
2444                                         ret = 0;
2445                                         goto cleanup;
2446                                 }
2447                                 /* HC is busted, give up! */
2448                                 xhci_err(xhci,
2449                                         "ERROR Transfer event TRB DMA ptr not "
2450                                         "part of current TD\n");
2451                                 return -ESHUTDOWN;
2452                         }
2453
2454                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2455                         goto cleanup;
2456                 }
2457                 if (trb_comp_code == COMP_SHORT_TX)
2458                         ep_ring->last_td_was_short = true;
2459                 else
2460                         ep_ring->last_td_was_short = false;
2461
2462                 if (ep->skip) {
2463                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2464                         ep->skip = false;
2465                 }
2466
2467                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2468                                                 sizeof(*event_trb)];
2469                 /*
2470                  * No-op TRB should not trigger interrupts.
2471                  * If event_trb is a no-op TRB, it means the
2472                  * corresponding TD has been cancelled. Just ignore
2473                  * the TD.
2474                  */
2475                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2476                         xhci_dbg(xhci,
2477                                  "event_trb is a no-op TRB. Skip it\n");
2478                         goto cleanup;
2479                 }
2480
2481                 /* Now update the urb's actual_length and give back to
2482                  * the core
2483                  */
2484                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2485                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2486                                                  &status);
2487                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2488                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2489                                                  &status);
2490                 else
2491                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2492                                                  ep, &status);
2493
2494 cleanup:
2495                 /*
2496                  * Do not update event ring dequeue pointer if ep->skip is set.
2497                  * Will roll back to continue process missed tds.
2498                  */
2499                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2500                         inc_deq(xhci, xhci->event_ring, true);
2501                 }
2502
2503                 if (ret) {
2504                         urb = td->urb;
2505                         urb_priv = urb->hcpriv;
2506
2507                         xhci_urb_free_priv(xhci, urb_priv);
2508
2509                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2510                         if ((urb->actual_length != urb->transfer_buffer_length &&
2511                                                 (urb->transfer_flags &
2512                                                  URB_SHORT_NOT_OK)) ||
2513                                         (status != 0 &&
2514                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2515                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2516                                                 "expected = %x, status = %d\n",
2517                                                 urb, urb->actual_length,
2518                                                 urb->transfer_buffer_length,
2519                                                 status);
2520                         spin_unlock(&xhci->lock);
2521                         /* EHCI, UHCI, and OHCI always unconditionally set the
2522                          * urb->status of an isochronous endpoint to 0.
2523                          */
2524                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2525                                 status = 0;
2526                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2527                         spin_lock(&xhci->lock);
2528                 }
2529
2530         /*
2531          * If ep->skip is set, it means there are missed tds on the
2532          * endpoint ring need to take care of.
2533          * Process them as short transfer until reach the td pointed by
2534          * the event.
2535          */
2536         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2537
2538         return 0;
2539 }
2540
2541 /*
2542  * This function handles all OS-owned events on the event ring.  It may drop
2543  * xhci->lock between event processing (e.g. to pass up port status changes).
2544  * Returns >0 for "possibly more events to process" (caller should call again),
2545  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2546  */
2547 static int xhci_handle_event(struct xhci_hcd *xhci)
2548 {
2549         union xhci_trb *event;
2550         int update_ptrs = 1;
2551         int ret;
2552
2553         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2554                 xhci->error_bitmask |= 1 << 1;
2555                 return 0;
2556         }
2557
2558         event = xhci->event_ring->dequeue;
2559         /* Does the HC or OS own the TRB? */
2560         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2561             xhci->event_ring->cycle_state) {
2562                 xhci->error_bitmask |= 1 << 2;
2563                 return 0;
2564         }
2565
2566         /*
2567          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2568          * speculative reads of the event's flags/data below.
2569          */
2570         rmb();
2571         /* FIXME: Handle more event types. */
2572         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2573         case TRB_TYPE(TRB_COMPLETION):
2574                 handle_cmd_completion(xhci, &event->event_cmd);
2575                 break;
2576         case TRB_TYPE(TRB_PORT_STATUS):
2577                 handle_port_status(xhci, event);
2578                 update_ptrs = 0;
2579                 break;
2580         case TRB_TYPE(TRB_TRANSFER):
2581                 ret = handle_tx_event(xhci, &event->trans_event);
2582                 if (ret < 0)
2583                         xhci->error_bitmask |= 1 << 9;
2584                 else
2585                         update_ptrs = 0;
2586                 break;
2587         default:
2588                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2589                     TRB_TYPE(48))
2590                         handle_vendor_event(xhci, event);
2591                 else
2592                         xhci->error_bitmask |= 1 << 3;
2593         }
2594         /* Any of the above functions may drop and re-acquire the lock, so check
2595          * to make sure a watchdog timer didn't mark the host as non-responsive.
2596          */
2597         if (xhci->xhc_state & XHCI_STATE_DYING) {
2598                 xhci_dbg(xhci, "xHCI host dying, returning from "
2599                                 "event handler.\n");
2600                 return 0;
2601         }
2602
2603         if (update_ptrs)
2604                 /* Update SW event ring dequeue pointer */
2605                 inc_deq(xhci, xhci->event_ring, true);
2606
2607         /* Are there more items on the event ring?  Caller will call us again to
2608          * check.
2609          */
2610         return 1;
2611 }
2612
2613 /*
2614  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2615  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2616  * indicators of an event TRB error, but we check the status *first* to be safe.
2617  */
2618 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2619 {
2620         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2621         u32 status;
2622         union xhci_trb *trb;
2623         u64 temp_64;
2624         union xhci_trb *event_ring_deq;
2625         dma_addr_t deq;
2626
2627         spin_lock(&xhci->lock);
2628         trb = xhci->event_ring->dequeue;
2629         /* Check if the xHC generated the interrupt, or the irq is shared */
2630         status = xhci_readl(xhci, &xhci->op_regs->status);
2631         if (status == 0xffffffff)
2632                 goto hw_died;
2633
2634         if (!(status & STS_EINT)) {
2635                 spin_unlock(&xhci->lock);
2636                 return IRQ_NONE;
2637         }
2638         if (status & STS_FATAL) {
2639                 xhci_warn(xhci, "WARNING: Host System Error\n");
2640                 xhci_halt(xhci);
2641 hw_died:
2642                 spin_unlock(&xhci->lock);
2643                 return -ESHUTDOWN;
2644         }
2645
2646         /*
2647          * Clear the op reg interrupt status first,
2648          * so we can receive interrupts from other MSI-X interrupters.
2649          * Write 1 to clear the interrupt status.
2650          */
2651         status |= STS_EINT;
2652         xhci_writel(xhci, status, &xhci->op_regs->status);
2653         /* FIXME when MSI-X is supported and there are multiple vectors */
2654         /* Clear the MSI-X event interrupt status */
2655
2656         if (hcd->irq != -1) {
2657                 u32 irq_pending;
2658                 /* Acknowledge the PCI interrupt */
2659                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2660                 irq_pending |= IMAN_IP;
2661                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2662         }
2663
2664         if (xhci->xhc_state & XHCI_STATE_DYING) {
2665                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2666                                 "Shouldn't IRQs be disabled?\n");
2667                 /* Clear the event handler busy flag (RW1C);
2668                  * the event ring should be empty.
2669                  */
2670                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2671                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2672                                 &xhci->ir_set->erst_dequeue);
2673                 spin_unlock(&xhci->lock);
2674
2675                 return IRQ_HANDLED;
2676         }
2677
2678         event_ring_deq = xhci->event_ring->dequeue;
2679         /* FIXME this should be a delayed service routine
2680          * that clears the EHB.
2681          */
2682         while (xhci_handle_event(xhci) > 0) {}
2683
2684         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2685         /* If necessary, update the HW's version of the event ring deq ptr. */
2686         if (event_ring_deq != xhci->event_ring->dequeue) {
2687                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2688                                 xhci->event_ring->dequeue);
2689                 if (deq == 0)
2690                         xhci_warn(xhci, "WARN something wrong with SW event "
2691                                         "ring dequeue ptr.\n");
2692                 /* Update HC event ring dequeue pointer */
2693                 temp_64 &= ERST_PTR_MASK;
2694                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2695         }
2696
2697         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2698         temp_64 |= ERST_EHB;
2699         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2700
2701         spin_unlock(&xhci->lock);
2702
2703         return IRQ_HANDLED;
2704 }
2705
2706 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2707 {
2708         irqreturn_t ret;
2709         struct xhci_hcd *xhci;
2710
2711         xhci = hcd_to_xhci(hcd);
2712         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2713         if (xhci->shared_hcd)
2714                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2715
2716         ret = xhci_irq(hcd);
2717
2718         return ret;
2719 }
2720
2721 /****           Endpoint Ring Operations        ****/
2722
2723 /*
2724  * Generic function for queueing a TRB on a ring.
2725  * The caller must have checked to make sure there's room on the ring.
2726  *
2727  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2728  *                      prepare_transfer()?
2729  */
2730 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2731                 bool consumer, bool more_trbs_coming, bool isoc,
2732                 u32 field1, u32 field2, u32 field3, u32 field4)
2733 {
2734         struct xhci_generic_trb *trb;
2735
2736         trb = &ring->enqueue->generic;
2737         trb->field[0] = cpu_to_le32(field1);
2738         trb->field[1] = cpu_to_le32(field2);
2739         trb->field[2] = cpu_to_le32(field3);
2740         trb->field[3] = cpu_to_le32(field4);
2741         inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2742 }
2743
2744 /*
2745  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2746  * FIXME allocate segments if the ring is full.
2747  */
2748 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2749                 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2750 {
2751         /* Make sure the endpoint has been added to xHC schedule */
2752         switch (ep_state) {
2753         case EP_STATE_DISABLED:
2754                 /*
2755                  * USB core changed config/interfaces without notifying us,
2756                  * or hardware is reporting the wrong state.
2757                  */
2758                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2759                 return -ENOENT;
2760         case EP_STATE_ERROR:
2761                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2762                 /* FIXME event handling code for error needs to clear it */
2763                 /* XXX not sure if this should be -ENOENT or not */
2764                 return -EINVAL;
2765         case EP_STATE_HALTED:
2766                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2767         case EP_STATE_STOPPED:
2768         case EP_STATE_RUNNING:
2769                 break;
2770         default:
2771                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2772                 /*
2773                  * FIXME issue Configure Endpoint command to try to get the HC
2774                  * back into a known state.
2775                  */
2776                 return -EINVAL;
2777         }
2778         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2779                 /* FIXME allocate more room */
2780                 xhci_err(xhci, "ERROR no room on ep ring\n");
2781                 return -ENOMEM;
2782         }
2783
2784         if (enqueue_is_link_trb(ep_ring)) {
2785                 struct xhci_ring *ring = ep_ring;
2786                 union xhci_trb *next;
2787
2788                 next = ring->enqueue;
2789
2790                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2791                         /* If we're not dealing with 0.95 hardware or isoc rings
2792                          * on AMD 0.96 host, clear the chain bit.
2793                          */
2794                         if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2795                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2796                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2797                         else
2798                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2799
2800                         wmb();
2801                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2802
2803                         /* Toggle the cycle bit after the last ring segment. */
2804                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2805                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2806                                 if (!in_interrupt()) {
2807                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2808                                                 "state for ring %p = %i\n",
2809                                                 ring, (unsigned int)ring->cycle_state);
2810                                 }
2811                         }
2812                         ring->enq_seg = ring->enq_seg->next;
2813                         ring->enqueue = ring->enq_seg->trbs;
2814                         next = ring->enqueue;
2815                 }
2816         }
2817
2818         return 0;
2819 }
2820
2821 static int prepare_transfer(struct xhci_hcd *xhci,
2822                 struct xhci_virt_device *xdev,
2823                 unsigned int ep_index,
2824                 unsigned int stream_id,
2825                 unsigned int num_trbs,
2826                 struct urb *urb,
2827                 unsigned int td_index,
2828                 bool isoc,
2829                 gfp_t mem_flags)
2830 {
2831         int ret;
2832         struct urb_priv *urb_priv;
2833         struct xhci_td  *td;
2834         struct xhci_ring *ep_ring;
2835         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2836
2837         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2838         if (!ep_ring) {
2839                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2840                                 stream_id);
2841                 return -EINVAL;
2842         }
2843
2844         ret = prepare_ring(xhci, ep_ring,
2845                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2846                            num_trbs, isoc, mem_flags);
2847         if (ret)
2848                 return ret;
2849
2850         urb_priv = urb->hcpriv;
2851         td = urb_priv->td[td_index];
2852
2853         INIT_LIST_HEAD(&td->td_list);
2854         INIT_LIST_HEAD(&td->cancelled_td_list);
2855
2856         if (td_index == 0) {
2857                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2858                 if (unlikely(ret))
2859                         return ret;
2860         }
2861
2862         td->urb = urb;
2863         /* Add this TD to the tail of the endpoint ring's TD list */
2864         list_add_tail(&td->td_list, &ep_ring->td_list);
2865         td->start_seg = ep_ring->enq_seg;
2866         td->first_trb = ep_ring->enqueue;
2867
2868         urb_priv->td[td_index] = td;
2869
2870         return 0;
2871 }
2872
2873 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2874 {
2875         int num_sgs, num_trbs, running_total, temp, i;
2876         struct scatterlist *sg;
2877
2878         sg = NULL;
2879         num_sgs = urb->num_mapped_sgs;
2880         temp = urb->transfer_buffer_length;
2881
2882         xhci_dbg(xhci, "count sg list trbs: \n");
2883         num_trbs = 0;
2884         for_each_sg(urb->sg, sg, num_sgs, i) {
2885                 unsigned int previous_total_trbs = num_trbs;
2886                 unsigned int len = sg_dma_len(sg);
2887
2888                 /* Scatter gather list entries may cross 64KB boundaries */
2889                 running_total = TRB_MAX_BUFF_SIZE -
2890                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2891                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2892                 if (running_total != 0)
2893                         num_trbs++;
2894
2895                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2896                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2897                         num_trbs++;
2898                         running_total += TRB_MAX_BUFF_SIZE;
2899                 }
2900                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2901                                 i, (unsigned long long)sg_dma_address(sg),
2902                                 len, len, num_trbs - previous_total_trbs);
2903
2904                 len = min_t(int, len, temp);
2905                 temp -= len;
2906                 if (temp == 0)
2907                         break;
2908         }
2909         xhci_dbg(xhci, "\n");
2910         if (!in_interrupt())
2911                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2912                                 "num_trbs = %d\n",
2913                                 urb->ep->desc.bEndpointAddress,
2914                                 urb->transfer_buffer_length,
2915                                 num_trbs);
2916         return num_trbs;
2917 }
2918
2919 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2920 {
2921         if (num_trbs != 0)
2922                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2923                                 "TRBs, %d left\n", __func__,
2924                                 urb->ep->desc.bEndpointAddress, num_trbs);
2925         if (running_total != urb->transfer_buffer_length)
2926                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2927                                 "queued %#x (%d), asked for %#x (%d)\n",
2928                                 __func__,
2929                                 urb->ep->desc.bEndpointAddress,
2930                                 running_total, running_total,
2931                                 urb->transfer_buffer_length,
2932                                 urb->transfer_buffer_length);
2933 }
2934
2935 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2936                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2937                 struct xhci_generic_trb *start_trb)
2938 {
2939         /*
2940          * Pass all the TRBs to the hardware at once and make sure this write
2941          * isn't reordered.
2942          */
2943         wmb();
2944         if (start_cycle)
2945                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2946         else
2947                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2948         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2949 }
2950
2951 /*
2952  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2953  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2954  * (comprised of sg list entries) can take several service intervals to
2955  * transmit.
2956  */
2957 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2958                 struct urb *urb, int slot_id, unsigned int ep_index)
2959 {
2960         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2961                         xhci->devs[slot_id]->out_ctx, ep_index);
2962         int xhci_interval;
2963         int ep_interval;
2964
2965         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2966         ep_interval = urb->interval;
2967         /* Convert to microframes */
2968         if (urb->dev->speed == USB_SPEED_LOW ||
2969                         urb->dev->speed == USB_SPEED_FULL)
2970                 ep_interval *= 8;
2971         /* FIXME change this to a warning and a suggestion to use the new API
2972          * to set the polling interval (once the API is added).
2973          */
2974         if (xhci_interval != ep_interval) {
2975                 if (printk_ratelimit())
2976                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2977                                         " (%d microframe%s) than xHCI "
2978                                         "(%d microframe%s)\n",
2979                                         ep_interval,
2980                                         ep_interval == 1 ? "" : "s",
2981                                         xhci_interval,
2982                                         xhci_interval == 1 ? "" : "s");
2983                 urb->interval = xhci_interval;
2984                 /* Convert back to frames for LS/FS devices */
2985                 if (urb->dev->speed == USB_SPEED_LOW ||
2986                                 urb->dev->speed == USB_SPEED_FULL)
2987                         urb->interval /= 8;
2988         }
2989         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2990 }
2991
2992 /*
2993  * The TD size is the number of bytes remaining in the TD (including this TRB),
2994  * right shifted by 10.
2995  * It must fit in bits 21:17, so it can't be bigger than 31.
2996  */
2997 static u32 xhci_td_remainder(unsigned int remainder)
2998 {
2999         u32 max = (1 << (21 - 17 + 1)) - 1;
3000
3001         if ((remainder >> 10) >= max)
3002                 return max << 17;
3003         else
3004                 return (remainder >> 10) << 17;
3005 }
3006
3007 /*
3008  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3009  * packets remaining in the TD (*not* including this TRB).
3010  *
3011  * Total TD packet count = total_packet_count =
3012  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3013  *
3014  * Packets transferred up to and including this TRB = packets_transferred =
3015  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3016  *
3017  * TD size = total_packet_count - packets_transferred
3018  *
3019  * It must fit in bits 21:17, so it can't be bigger than 31.
3020  * The last TRB in a TD must have the TD size set to zero.
3021  */
3022 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3023                 unsigned int total_packet_count, struct urb *urb,
3024                 unsigned int num_trbs_left)
3025 {
3026         int packets_transferred;
3027
3028         /* One TRB with a zero-length data packet. */
3029         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3030                 return 0;
3031
3032         /* All the TRB queueing functions don't count the current TRB in
3033          * running_total.
3034          */
3035         packets_transferred = (running_total + trb_buff_len) /
3036                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3037
3038         if ((total_packet_count - packets_transferred) > 31)
3039                 return 31 << 17;
3040         return (total_packet_count - packets_transferred) << 17;
3041 }
3042
3043 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3044                 struct urb *urb, int slot_id, unsigned int ep_index)
3045 {
3046         struct xhci_ring *ep_ring;
3047         unsigned int num_trbs;
3048         struct urb_priv *urb_priv;
3049         struct xhci_td *td;
3050         struct scatterlist *sg;
3051         int num_sgs;
3052         int trb_buff_len, this_sg_len, running_total;
3053         unsigned int total_packet_count;
3054         bool first_trb;
3055         u64 addr;
3056         bool more_trbs_coming;
3057
3058         struct xhci_generic_trb *start_trb;
3059         int start_cycle;
3060
3061         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3062         if (!ep_ring)
3063                 return -EINVAL;
3064
3065         num_trbs = count_sg_trbs_needed(xhci, urb);
3066         num_sgs = urb->num_mapped_sgs;
3067         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3068                         usb_endpoint_maxp(&urb->ep->desc));
3069
3070         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3071                         ep_index, urb->stream_id,
3072                         num_trbs, urb, 0, false, mem_flags);
3073         if (trb_buff_len < 0)
3074                 return trb_buff_len;
3075
3076         urb_priv = urb->hcpriv;
3077         td = urb_priv->td[0];
3078
3079         /*
3080          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3081          * until we've finished creating all the other TRBs.  The ring's cycle
3082          * state may change as we enqueue the other TRBs, so save it too.
3083          */
3084         start_trb = &ep_ring->enqueue->generic;
3085         start_cycle = ep_ring->cycle_state;
3086
3087         running_total = 0;
3088         /*
3089          * How much data is in the first TRB?
3090          *
3091          * There are three forces at work for TRB buffer pointers and lengths:
3092          * 1. We don't want to walk off the end of this sg-list entry buffer.
3093          * 2. The transfer length that the driver requested may be smaller than
3094          *    the amount of memory allocated for this scatter-gather list.
3095          * 3. TRBs buffers can't cross 64KB boundaries.
3096          */
3097         sg = urb->sg;
3098         addr = (u64) sg_dma_address(sg);
3099         this_sg_len = sg_dma_len(sg);
3100         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3101         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3102         if (trb_buff_len > urb->transfer_buffer_length)
3103                 trb_buff_len = urb->transfer_buffer_length;
3104         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
3105                         trb_buff_len);
3106
3107         first_trb = true;
3108         /* Queue the first TRB, even if it's zero-length */
3109         do {
3110                 u32 field = 0;
3111                 u32 length_field = 0;
3112                 u32 remainder = 0;
3113
3114                 /* Don't change the cycle bit of the first TRB until later */
3115                 if (first_trb) {
3116                         first_trb = false;
3117                         if (start_cycle == 0)
3118                                 field |= 0x1;
3119                 } else
3120                         field |= ep_ring->cycle_state;
3121
3122                 /* Chain all the TRBs together; clear the chain bit in the last
3123                  * TRB to indicate it's the last TRB in the chain.
3124                  */
3125                 if (num_trbs > 1) {
3126                         field |= TRB_CHAIN;
3127                 } else {
3128                         /* FIXME - add check for ZERO_PACKET flag before this */
3129                         td->last_trb = ep_ring->enqueue;
3130                         field |= TRB_IOC;
3131                 }
3132
3133                 /* Only set interrupt on short packet for IN endpoints */
3134                 if (usb_urb_dir_in(urb))
3135                         field |= TRB_ISP;
3136
3137                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
3138                                 "64KB boundary at %#x, end dma = %#x\n",
3139                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
3140                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3141                                 (unsigned int) addr + trb_buff_len);
3142                 if (TRB_MAX_BUFF_SIZE -
3143                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3144                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3145                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3146                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3147                                         (unsigned int) addr + trb_buff_len);
3148                 }
3149
3150                 /* Set the TRB length, TD size, and interrupter fields. */
3151                 if (xhci->hci_version < 0x100) {
3152                         remainder = xhci_td_remainder(
3153                                         urb->transfer_buffer_length -
3154                                         running_total);
3155                 } else {
3156                         remainder = xhci_v1_0_td_remainder(running_total,
3157                                         trb_buff_len, total_packet_count, urb,
3158                                         num_trbs - 1);
3159                 }
3160                 length_field = TRB_LEN(trb_buff_len) |
3161                         remainder |
3162                         TRB_INTR_TARGET(0);
3163
3164                 if (num_trbs > 1)
3165                         more_trbs_coming = true;
3166                 else
3167                         more_trbs_coming = false;
3168                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3169                                 lower_32_bits(addr),
3170                                 upper_32_bits(addr),
3171                                 length_field,
3172                                 field | TRB_TYPE(TRB_NORMAL));
3173                 --num_trbs;
3174                 running_total += trb_buff_len;
3175
3176                 /* Calculate length for next transfer --
3177                  * Are we done queueing all the TRBs for this sg entry?
3178                  */
3179                 this_sg_len -= trb_buff_len;
3180                 if (this_sg_len == 0) {
3181                         --num_sgs;
3182                         if (num_sgs == 0)
3183                                 break;
3184                         sg = sg_next(sg);
3185                         addr = (u64) sg_dma_address(sg);
3186                         this_sg_len = sg_dma_len(sg);
3187                 } else {
3188                         addr += trb_buff_len;
3189                 }
3190
3191                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3192                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3193                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3194                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3195                         trb_buff_len =
3196                                 urb->transfer_buffer_length - running_total;
3197         } while (running_total < urb->transfer_buffer_length);
3198
3199         check_trb_math(urb, num_trbs, running_total);
3200         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3201                         start_cycle, start_trb);
3202         return 0;
3203 }
3204
3205 /* This is very similar to what ehci-q.c qtd_fill() does */
3206 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3207                 struct urb *urb, int slot_id, unsigned int ep_index)
3208 {
3209         struct xhci_ring *ep_ring;
3210         struct urb_priv *urb_priv;
3211         struct xhci_td *td;
3212         int num_trbs;
3213         struct xhci_generic_trb *start_trb;
3214         bool first_trb;
3215         bool more_trbs_coming;
3216         int start_cycle;
3217         u32 field, length_field;
3218
3219         int running_total, trb_buff_len, ret;
3220         unsigned int total_packet_count;
3221         u64 addr;
3222
3223         if (urb->num_sgs)
3224                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3225
3226         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3227         if (!ep_ring)
3228                 return -EINVAL;
3229
3230         num_trbs = 0;
3231         /* How much data is (potentially) left before the 64KB boundary? */
3232         running_total = TRB_MAX_BUFF_SIZE -
3233                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3234         running_total &= TRB_MAX_BUFF_SIZE - 1;
3235
3236         /* If there's some data on this 64KB chunk, or we have to send a
3237          * zero-length transfer, we need at least one TRB
3238          */
3239         if (running_total != 0 || urb->transfer_buffer_length == 0)
3240                 num_trbs++;
3241         /* How many more 64KB chunks to transfer, how many more TRBs? */
3242         while (running_total < urb->transfer_buffer_length) {
3243                 num_trbs++;
3244                 running_total += TRB_MAX_BUFF_SIZE;
3245         }
3246         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3247
3248         if (!in_interrupt())
3249                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
3250                                 "addr = %#llx, num_trbs = %d\n",
3251                                 urb->ep->desc.bEndpointAddress,
3252                                 urb->transfer_buffer_length,
3253                                 urb->transfer_buffer_length,
3254                                 (unsigned long long)urb->transfer_dma,
3255                                 num_trbs);
3256
3257         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3258                         ep_index, urb->stream_id,
3259                         num_trbs, urb, 0, false, mem_flags);
3260         if (ret < 0)
3261                 return ret;
3262
3263         urb_priv = urb->hcpriv;
3264         td = urb_priv->td[0];
3265
3266         /*
3267          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3268          * until we've finished creating all the other TRBs.  The ring's cycle
3269          * state may change as we enqueue the other TRBs, so save it too.
3270          */
3271         start_trb = &ep_ring->enqueue->generic;
3272         start_cycle = ep_ring->cycle_state;
3273
3274         running_total = 0;
3275         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3276                         usb_endpoint_maxp(&urb->ep->desc));
3277         /* How much data is in the first TRB? */
3278         addr = (u64) urb->transfer_dma;
3279         trb_buff_len = TRB_MAX_BUFF_SIZE -
3280                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3281         if (trb_buff_len > urb->transfer_buffer_length)
3282                 trb_buff_len = urb->transfer_buffer_length;
3283
3284         first_trb = true;
3285
3286         /* Queue the first TRB, even if it's zero-length */
3287         do {
3288                 u32 remainder = 0;
3289                 field = 0;
3290
3291                 /* Don't change the cycle bit of the first TRB until later */
3292                 if (first_trb) {
3293                         first_trb = false;
3294                         if (start_cycle == 0)
3295                                 field |= 0x1;
3296                 } else
3297                         field |= ep_ring->cycle_state;
3298
3299                 /* Chain all the TRBs together; clear the chain bit in the last
3300                  * TRB to indicate it's the last TRB in the chain.
3301                  */
3302                 if (num_trbs > 1) {
3303                         field |= TRB_CHAIN;
3304                 } else {
3305                         /* FIXME - add check for ZERO_PACKET flag before this */
3306                         td->last_trb = ep_ring->enqueue;
3307                         field |= TRB_IOC;
3308                 }
3309
3310                 /* Only set interrupt on short packet for IN endpoints */
3311                 if (usb_urb_dir_in(urb))
3312                         field |= TRB_ISP;
3313
3314                 /* Set the TRB length, TD size, and interrupter fields. */
3315                 if (xhci->hci_version < 0x100) {
3316                         remainder = xhci_td_remainder(
3317                                         urb->transfer_buffer_length -
3318                                         running_total);
3319                 } else {
3320                         remainder = xhci_v1_0_td_remainder(running_total,
3321                                         trb_buff_len, total_packet_count, urb,
3322                                         num_trbs - 1);
3323                 }
3324                 length_field = TRB_LEN(trb_buff_len) |
3325                         remainder |
3326                         TRB_INTR_TARGET(0);
3327
3328                 if (num_trbs > 1)
3329                         more_trbs_coming = true;
3330                 else
3331                         more_trbs_coming = false;
3332                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3333                                 lower_32_bits(addr),
3334                                 upper_32_bits(addr),
3335                                 length_field,
3336                                 field | TRB_TYPE(TRB_NORMAL));
3337                 --num_trbs;
3338                 running_total += trb_buff_len;
3339
3340                 /* Calculate length for next transfer */
3341                 addr += trb_buff_len;
3342                 trb_buff_len = urb->transfer_buffer_length - running_total;
3343                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3344                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3345         } while (running_total < urb->transfer_buffer_length);
3346
3347         check_trb_math(urb, num_trbs, running_total);
3348         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3349                         start_cycle, start_trb);
3350         return 0;
3351 }
3352
3353 /* Caller must have locked xhci->lock */
3354 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3355                 struct urb *urb, int slot_id, unsigned int ep_index)
3356 {
3357         struct xhci_ring *ep_ring;
3358         int num_trbs;
3359         int ret;
3360         struct usb_ctrlrequest *setup;
3361         struct xhci_generic_trb *start_trb;
3362         int start_cycle;
3363         u32 field, length_field;
3364         struct urb_priv *urb_priv;
3365         struct xhci_td *td;
3366
3367         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3368         if (!ep_ring)
3369                 return -EINVAL;
3370
3371         /*
3372          * Need to copy setup packet into setup TRB, so we can't use the setup
3373          * DMA address.
3374          */
3375         if (!urb->setup_packet)
3376                 return -EINVAL;
3377
3378         if (!in_interrupt())
3379                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3380                                 slot_id, ep_index);
3381         /* 1 TRB for setup, 1 for status */
3382         num_trbs = 2;
3383         /*
3384          * Don't need to check if we need additional event data and normal TRBs,
3385          * since data in control transfers will never get bigger than 16MB
3386          * XXX: can we get a buffer that crosses 64KB boundaries?
3387          */
3388         if (urb->transfer_buffer_length > 0)
3389                 num_trbs++;
3390         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3391                         ep_index, urb->stream_id,
3392                         num_trbs, urb, 0, false, mem_flags);
3393         if (ret < 0)
3394                 return ret;
3395
3396         urb_priv = urb->hcpriv;
3397         td = urb_priv->td[0];
3398
3399         /*
3400          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3401          * until we've finished creating all the other TRBs.  The ring's cycle
3402          * state may change as we enqueue the other TRBs, so save it too.
3403          */
3404         start_trb = &ep_ring->enqueue->generic;
3405         start_cycle = ep_ring->cycle_state;
3406
3407         /* Queue setup TRB - see section 6.4.1.2.1 */
3408         /* FIXME better way to translate setup_packet into two u32 fields? */
3409         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3410         field = 0;
3411         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3412         if (start_cycle == 0)
3413                 field |= 0x1;
3414
3415         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3416         if (xhci->hci_version == 0x100) {
3417                 if (urb->transfer_buffer_length > 0) {
3418                         if (setup->bRequestType & USB_DIR_IN)
3419                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3420                         else
3421                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3422                 }
3423         }
3424
3425         queue_trb(xhci, ep_ring, false, true, false,
3426                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3427                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3428                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3429                   /* Immediate data in pointer */
3430                   field);
3431
3432         /* If there's data, queue data TRBs */
3433         /* Only set interrupt on short packet for IN endpoints */
3434         if (usb_urb_dir_in(urb))
3435                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3436         else
3437                 field = TRB_TYPE(TRB_DATA);
3438
3439         length_field = TRB_LEN(urb->transfer_buffer_length) |
3440                 xhci_td_remainder(urb->transfer_buffer_length) |
3441                 TRB_INTR_TARGET(0);
3442         if (urb->transfer_buffer_length > 0) {
3443                 if (setup->bRequestType & USB_DIR_IN)
3444                         field |= TRB_DIR_IN;
3445                 queue_trb(xhci, ep_ring, false, true, false,
3446                                 lower_32_bits(urb->transfer_dma),
3447                                 upper_32_bits(urb->transfer_dma),
3448                                 length_field,
3449                                 field | ep_ring->cycle_state);
3450         }
3451
3452         /* Save the DMA address of the last TRB in the TD */
3453         td->last_trb = ep_ring->enqueue;
3454
3455         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3456         /* If the device sent data, the status stage is an OUT transfer */
3457         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3458                 field = 0;
3459         else
3460                 field = TRB_DIR_IN;
3461         queue_trb(xhci, ep_ring, false, false, false,
3462                         0,
3463                         0,
3464                         TRB_INTR_TARGET(0),
3465                         /* Event on completion */
3466                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3467
3468         giveback_first_trb(xhci, slot_id, ep_index, 0,
3469                         start_cycle, start_trb);
3470         return 0;
3471 }
3472
3473 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3474                 struct urb *urb, int i)
3475 {
3476         int num_trbs = 0;
3477         u64 addr, td_len;
3478
3479         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3480         td_len = urb->iso_frame_desc[i].length;
3481
3482         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3483                         TRB_MAX_BUFF_SIZE);
3484         if (num_trbs == 0)
3485                 num_trbs++;
3486
3487         return num_trbs;
3488 }
3489
3490 /*
3491  * The transfer burst count field of the isochronous TRB defines the number of
3492  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3493  * devices can burst up to bMaxBurst number of packets per service interval.
3494  * This field is zero based, meaning a value of zero in the field means one
3495  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3496  * zero.  Only xHCI 1.0 host controllers support this field.
3497  */
3498 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3499                 struct usb_device *udev,
3500                 struct urb *urb, unsigned int total_packet_count)
3501 {
3502         unsigned int max_burst;
3503
3504         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3505                 return 0;
3506
3507         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3508         return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3509 }
3510
3511 /*
3512  * Returns the number of packets in the last "burst" of packets.  This field is
3513  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3514  * the last burst packet count is equal to the total number of packets in the
3515  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3516  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3517  * contain 1 to (bMaxBurst + 1) packets.
3518  */
3519 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3520                 struct usb_device *udev,
3521                 struct urb *urb, unsigned int total_packet_count)
3522 {
3523         unsigned int max_burst;
3524         unsigned int residue;
3525
3526         if (xhci->hci_version < 0x100)
3527                 return 0;
3528
3529         switch (udev->speed) {
3530         case USB_SPEED_SUPER:
3531                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3532                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3533                 residue = total_packet_count % (max_burst + 1);
3534                 /* If residue is zero, the last burst contains (max_burst + 1)
3535                  * number of packets, but the TLBPC field is zero-based.
3536                  */
3537                 if (residue == 0)
3538                         return max_burst;
3539                 return residue - 1;
3540         default:
3541                 if (total_packet_count == 0)
3542                         return 0;
3543                 return total_packet_count - 1;
3544         }
3545 }
3546
3547 /* This is for isoc transfer */
3548 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3549                 struct urb *urb, int slot_id, unsigned int ep_index)
3550 {
3551         struct xhci_ring *ep_ring;
3552         struct urb_priv *urb_priv;
3553         struct xhci_td *td;
3554         int num_tds, trbs_per_td;
3555         struct xhci_generic_trb *start_trb;
3556         bool first_trb;
3557         int start_cycle;
3558         u32 field, length_field;
3559         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3560         u64 start_addr, addr;
3561         int i, j;
3562         bool more_trbs_coming;
3563
3564         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3565
3566         num_tds = urb->number_of_packets;
3567         if (num_tds < 1) {
3568                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3569                 return -EINVAL;
3570         }
3571
3572         if (!in_interrupt())
3573                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3574                                 " addr = %#llx, num_tds = %d\n",
3575                                 urb->ep->desc.bEndpointAddress,
3576                                 urb->transfer_buffer_length,
3577                                 urb->transfer_buffer_length,
3578                                 (unsigned long long)urb->transfer_dma,
3579                                 num_tds);
3580
3581         start_addr = (u64) urb->transfer_dma;
3582         start_trb = &ep_ring->enqueue->generic;
3583         start_cycle = ep_ring->cycle_state;
3584
3585         urb_priv = urb->hcpriv;
3586         /* Queue the first TRB, even if it's zero-length */
3587         for (i = 0; i < num_tds; i++) {
3588                 unsigned int total_packet_count;
3589                 unsigned int burst_count;
3590                 unsigned int residue;
3591
3592                 first_trb = true;
3593                 running_total = 0;
3594                 addr = start_addr + urb->iso_frame_desc[i].offset;
3595                 td_len = urb->iso_frame_desc[i].length;
3596                 td_remain_len = td_len;
3597                 total_packet_count = DIV_ROUND_UP(td_len,
3598                                 GET_MAX_PACKET(
3599                                         usb_endpoint_maxp(&urb->ep->desc)));
3600                 /* A zero-length transfer still involves at least one packet. */
3601                 if (total_packet_count == 0)
3602                         total_packet_count++;
3603                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3604                                 total_packet_count);
3605                 residue = xhci_get_last_burst_packet_count(xhci,
3606                                 urb->dev, urb, total_packet_count);
3607
3608                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3609
3610                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3611                                 urb->stream_id, trbs_per_td, urb, i, true,
3612                                 mem_flags);
3613                 if (ret < 0) {
3614                         if (i == 0)
3615                                 return ret;
3616                         goto cleanup;
3617                 }
3618
3619                 td = urb_priv->td[i];
3620                 for (j = 0; j < trbs_per_td; j++) {
3621                         u32 remainder = 0;
3622                         field = 0;
3623
3624                         if (first_trb) {
3625                                 field = TRB_TBC(burst_count) |
3626                                         TRB_TLBPC(residue);
3627                                 /* Queue the isoc TRB */
3628                                 field |= TRB_TYPE(TRB_ISOC);
3629                                 /* Assume URB_ISO_ASAP is set */
3630                                 field |= TRB_SIA;
3631                                 if (i == 0) {
3632                                         if (start_cycle == 0)
3633                                                 field |= 0x1;
3634                                 } else
3635                                         field |= ep_ring->cycle_state;
3636                                 first_trb = false;
3637                         } else {
3638                                 /* Queue other normal TRBs */
3639                                 field |= TRB_TYPE(TRB_NORMAL);
3640                                 field |= ep_ring->cycle_state;
3641                         }
3642
3643                         /* Only set interrupt on short packet for IN EPs */
3644                         if (usb_urb_dir_in(urb))
3645                                 field |= TRB_ISP;
3646
3647                         /* Chain all the TRBs together; clear the chain bit in
3648                          * the last TRB to indicate it's the last TRB in the
3649                          * chain.
3650                          */
3651                         if (j < trbs_per_td - 1) {
3652                                 field |= TRB_CHAIN;
3653                                 more_trbs_coming = true;
3654                         } else {
3655                                 td->last_trb = ep_ring->enqueue;
3656                                 field |= TRB_IOC;
3657                                 if (xhci->hci_version == 0x100 &&
3658                                                 !(xhci->quirks &
3659                                                         XHCI_AVOID_BEI)) {
3660                                         /* Set BEI bit except for the last td */
3661                                         if (i < num_tds - 1)
3662                                                 field |= TRB_BEI;
3663                                 }
3664                                 more_trbs_coming = false;
3665                         }
3666
3667                         /* Calculate TRB length */
3668                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3669                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3670                         if (trb_buff_len > td_remain_len)
3671                                 trb_buff_len = td_remain_len;
3672
3673                         /* Set the TRB length, TD size, & interrupter fields. */
3674                         if (xhci->hci_version < 0x100) {
3675                                 remainder = xhci_td_remainder(
3676                                                 td_len - running_total);
3677                         } else {
3678                                 remainder = xhci_v1_0_td_remainder(
3679                                                 running_total, trb_buff_len,
3680                                                 total_packet_count, urb,
3681                                                 (trbs_per_td - j - 1));
3682                         }
3683                         length_field = TRB_LEN(trb_buff_len) |
3684                                 remainder |
3685                                 TRB_INTR_TARGET(0);
3686
3687                         queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3688                                 lower_32_bits(addr),
3689                                 upper_32_bits(addr),
3690                                 length_field,
3691                                 field);
3692                         running_total += trb_buff_len;
3693
3694                         addr += trb_buff_len;
3695                         td_remain_len -= trb_buff_len;
3696                 }
3697
3698                 /* Check TD length */
3699                 if (running_total != td_len) {
3700                         xhci_err(xhci, "ISOC TD length unmatch\n");
3701                         ret = -EINVAL;
3702                         goto cleanup;
3703                 }
3704         }
3705
3706         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3707                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3708                         usb_amd_quirk_pll_disable();
3709         }
3710         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3711
3712         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3713                         start_cycle, start_trb);
3714         return 0;
3715 cleanup:
3716         /* Clean up a partially enqueued isoc transfer. */
3717
3718         for (i--; i >= 0; i--)
3719                 list_del_init(&urb_priv->td[i]->td_list);
3720
3721         /* Use the first TD as a temporary variable to turn the TDs we've queued
3722          * into No-ops with a software-owned cycle bit. That way the hardware
3723          * won't accidentally start executing bogus TDs when we partially
3724          * overwrite them.  td->first_trb and td->start_seg are already set.
3725          */
3726         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3727         /* Every TRB except the first & last will have its cycle bit flipped. */
3728         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3729
3730         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3731         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3732         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3733         ep_ring->cycle_state = start_cycle;
3734         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3735         return ret;
3736 }
3737
3738 /*
3739  * Check transfer ring to guarantee there is enough room for the urb.
3740  * Update ISO URB start_frame and interval.
3741  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3742  * update the urb->start_frame by now.
3743  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3744  */
3745 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3746                 struct urb *urb, int slot_id, unsigned int ep_index)
3747 {
3748         struct xhci_virt_device *xdev;
3749         struct xhci_ring *ep_ring;
3750         struct xhci_ep_ctx *ep_ctx;
3751         int start_frame;
3752         int xhci_interval;
3753         int ep_interval;
3754         int num_tds, num_trbs, i;
3755         int ret;
3756
3757         xdev = xhci->devs[slot_id];
3758         ep_ring = xdev->eps[ep_index].ring;
3759         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3760
3761         num_trbs = 0;
3762         num_tds = urb->number_of_packets;
3763         for (i = 0; i < num_tds; i++)
3764                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3765
3766         /* Check the ring to guarantee there is enough room for the whole urb.
3767          * Do not insert any td of the urb to the ring if the check failed.
3768          */
3769         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3770                            num_trbs, true, mem_flags);
3771         if (ret)
3772                 return ret;
3773
3774         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3775         start_frame &= 0x3fff;
3776
3777         urb->start_frame = start_frame;
3778         if (urb->dev->speed == USB_SPEED_LOW ||
3779                         urb->dev->speed == USB_SPEED_FULL)
3780                 urb->start_frame >>= 3;
3781
3782         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3783         ep_interval = urb->interval;
3784         /* Convert to microframes */
3785         if (urb->dev->speed == USB_SPEED_LOW ||
3786                         urb->dev->speed == USB_SPEED_FULL)
3787                 ep_interval *= 8;
3788         /* FIXME change this to a warning and a suggestion to use the new API
3789          * to set the polling interval (once the API is added).
3790          */
3791         if (xhci_interval != ep_interval) {
3792                 if (printk_ratelimit())
3793                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3794                                         " (%d microframe%s) than xHCI "
3795                                         "(%d microframe%s)\n",
3796                                         ep_interval,
3797                                         ep_interval == 1 ? "" : "s",
3798                                         xhci_interval,
3799                                         xhci_interval == 1 ? "" : "s");
3800                 urb->interval = xhci_interval;
3801                 /* Convert back to frames for LS/FS devices */
3802                 if (urb->dev->speed == USB_SPEED_LOW ||
3803                                 urb->dev->speed == USB_SPEED_FULL)
3804                         urb->interval /= 8;
3805         }
3806         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3807 }
3808
3809 /****           Command Ring Operations         ****/
3810
3811 /* Generic function for queueing a command TRB on the command ring.
3812  * Check to make sure there's room on the command ring for one command TRB.
3813  * Also check that there's room reserved for commands that must not fail.
3814  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3815  * then only check for the number of reserved spots.
3816  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3817  * because the command event handler may want to resubmit a failed command.
3818  */
3819 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3820                 u32 field3, u32 field4, bool command_must_succeed)
3821 {
3822         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3823         int ret;
3824
3825         if (!command_must_succeed)
3826                 reserved_trbs++;
3827
3828         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3829                         reserved_trbs, false, GFP_ATOMIC);
3830         if (ret < 0) {
3831                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3832                 if (command_must_succeed)
3833                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3834                                         "unfailable commands failed.\n");
3835                 return ret;
3836         }
3837         queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3838                         field3, field4 | xhci->cmd_ring->cycle_state);
3839         return 0;
3840 }
3841
3842 /* Queue a slot enable or disable request on the command ring */
3843 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3844 {
3845         return queue_command(xhci, 0, 0, 0,
3846                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3847 }
3848
3849 /* Queue an address device command TRB */
3850 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3851                 u32 slot_id)
3852 {
3853         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3854                         upper_32_bits(in_ctx_ptr), 0,
3855                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3856                         false);
3857 }
3858
3859 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3860                 u32 field1, u32 field2, u32 field3, u32 field4)
3861 {
3862         return queue_command(xhci, field1, field2, field3, field4, false);
3863 }
3864
3865 /* Queue a reset device command TRB */
3866 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3867 {
3868         return queue_command(xhci, 0, 0, 0,
3869                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3870                         false);
3871 }
3872
3873 /* Queue a configure endpoint command TRB */
3874 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3875                 u32 slot_id, bool command_must_succeed)
3876 {
3877         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3878                         upper_32_bits(in_ctx_ptr), 0,
3879                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3880                         command_must_succeed);
3881 }
3882
3883 /* Queue an evaluate context command TRB */
3884 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3885                 u32 slot_id)
3886 {
3887         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3888                         upper_32_bits(in_ctx_ptr), 0,
3889                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3890                         false);
3891 }
3892
3893 /*
3894  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3895  * activity on an endpoint that is about to be suspended.
3896  */
3897 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3898                 unsigned int ep_index, int suspend)
3899 {
3900         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3901         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3902         u32 type = TRB_TYPE(TRB_STOP_RING);
3903         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3904
3905         return queue_command(xhci, 0, 0, 0,
3906                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3907 }
3908
3909 /* Set Transfer Ring Dequeue Pointer command.
3910  * This should not be used for endpoints that have streams enabled.
3911  */
3912 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3913                 unsigned int ep_index, unsigned int stream_id,
3914                 struct xhci_segment *deq_seg,
3915                 union xhci_trb *deq_ptr, u32 cycle_state)
3916 {
3917         dma_addr_t addr;
3918         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3919         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3920         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3921         u32 type = TRB_TYPE(TRB_SET_DEQ);
3922         struct xhci_virt_ep *ep;
3923
3924         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3925         if (addr == 0) {
3926                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3927                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3928                                 deq_seg, deq_ptr);
3929                 return 0;
3930         }
3931         ep = &xhci->devs[slot_id]->eps[ep_index];
3932         if ((ep->ep_state & SET_DEQ_PENDING)) {
3933                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3934                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3935                 return 0;
3936         }
3937         ep->queued_deq_seg = deq_seg;
3938         ep->queued_deq_ptr = deq_ptr;
3939         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3940                         upper_32_bits(addr), trb_stream_id,
3941                         trb_slot_id | trb_ep_index | type, false);
3942 }
3943
3944 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3945                 unsigned int ep_index)
3946 {
3947         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3948         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3949         u32 type = TRB_TYPE(TRB_RESET_EP);
3950
3951         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3952                         false);
3953 }