2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
82 unsigned long segment_offset;
84 if (!seg || !trb || trb < seg->trbs)
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
90 return seg->dma + (segment_offset * sizeof(*trb));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
103 return trb->link.control & LINK_TOGGLE;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
116 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
119 static int enqueue_is_link_trb(struct xhci_ring *ring)
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
129 static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
134 if (last_trb(xhci, ring, *seg, *trb)) {
136 *trb = ((*seg)->trbs);
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
148 union xhci_trb *next = ++(ring->dequeue);
149 unsigned long long addr;
152 /* Update the dequeue pointer further if that was a link TRB or we're at
153 * the end of an event ring segment (which doesn't have link TRBS)
155 while (last_trb(xhci, ring, ring->deq_seg, next)) {
156 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
157 ring->cycle_state = (ring->cycle_state ? 0 : 1);
159 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
161 (unsigned int) ring->cycle_state);
163 ring->deq_seg = ring->deq_seg->next;
164 ring->dequeue = ring->deq_seg->trbs;
165 next = ring->dequeue;
167 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
168 if (ring == xhci->event_ring)
169 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
170 else if (ring == xhci->cmd_ring)
171 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
173 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
177 * See Cycle bit rules. SW is the consumer for the event ring only.
178 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
180 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
181 * chain bit is set), then set the chain bit in all the following link TRBs.
182 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
183 * have their chain bit cleared (so that each Link TRB is a separate TD).
185 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
186 * set, but other sections talk about dealing with the chain bit set. This was
187 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
188 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
190 * @more_trbs_coming: Will you enqueue more TRBs before calling
191 * prepare_transfer()?
193 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
194 bool consumer, bool more_trbs_coming)
197 union xhci_trb *next;
198 unsigned long long addr;
200 chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
201 next = ++(ring->enqueue);
204 /* Update the dequeue pointer further if that was a link TRB or we're at
205 * the end of an event ring segment (which doesn't have link TRBS)
207 while (last_trb(xhci, ring, ring->enq_seg, next)) {
209 if (ring != xhci->event_ring) {
211 * If the caller doesn't plan on enqueueing more
212 * TDs before ringing the doorbell, then we
213 * don't want to give the link TRB to the
214 * hardware just yet. We'll give the link TRB
215 * back in prepare_ring() just before we enqueue
216 * the TD at the top of the ring.
218 if (!chain && !more_trbs_coming)
221 /* If we're not dealing with 0.95 hardware,
222 * carry over the chain bit of the previous TRB
223 * (which may mean the chain bit is cleared).
225 if (!xhci_link_trb_quirk(xhci)) {
226 next->link.control &= ~TRB_CHAIN;
227 next->link.control |= chain;
229 /* Give this link TRB to the hardware */
231 next->link.control ^= TRB_CYCLE;
233 /* Toggle the cycle bit after the last ring segment. */
234 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
235 ring->cycle_state = (ring->cycle_state ? 0 : 1);
237 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
239 (unsigned int) ring->cycle_state);
242 ring->enq_seg = ring->enq_seg->next;
243 ring->enqueue = ring->enq_seg->trbs;
244 next = ring->enqueue;
246 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
247 if (ring == xhci->event_ring)
248 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
249 else if (ring == xhci->cmd_ring)
250 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
252 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
256 * Check to see if there's room to enqueue num_trbs on the ring. See rules
258 * FIXME: this would be simpler and faster if we just kept track of the number
259 * of free TRBs in a ring.
261 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
262 unsigned int num_trbs)
265 union xhci_trb *enq = ring->enqueue;
266 struct xhci_segment *enq_seg = ring->enq_seg;
267 struct xhci_segment *cur_seg;
268 unsigned int left_on_ring;
270 /* If we are currently pointing to a link TRB, advance the
271 * enqueue pointer before checking for space */
272 while (last_trb(xhci, ring, enq_seg, enq)) {
273 enq_seg = enq_seg->next;
277 /* Check if ring is empty */
278 if (enq == ring->dequeue) {
279 /* Can't use link trbs */
280 left_on_ring = TRBS_PER_SEGMENT - 1;
281 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
282 cur_seg = cur_seg->next)
283 left_on_ring += TRBS_PER_SEGMENT - 1;
285 /* Always need one TRB free in the ring. */
287 if (num_trbs > left_on_ring) {
288 xhci_warn(xhci, "Not enough room on ring; "
289 "need %u TRBs, %u TRBs left\n",
290 num_trbs, left_on_ring);
295 /* Make sure there's an extra empty TRB available */
296 for (i = 0; i <= num_trbs; ++i) {
297 if (enq == ring->dequeue)
300 while (last_trb(xhci, ring, enq_seg, enq)) {
301 enq_seg = enq_seg->next;
308 /* Ring the host controller doorbell after placing a command on the ring */
309 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
311 xhci_dbg(xhci, "// Ding dong!\n");
312 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
313 /* Flush PCI posted writes */
314 xhci_readl(xhci, &xhci->dba->doorbell[0]);
317 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
318 unsigned int slot_id,
319 unsigned int ep_index,
320 unsigned int stream_id)
322 __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
323 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
324 unsigned int ep_state = ep->ep_state;
326 /* Don't ring the doorbell for this endpoint if there are pending
327 * cancellations because we don't want to interrupt processing.
328 * We don't want to restart any stream rings if there's a set dequeue
329 * pointer command pending because the device can choose to start any
330 * stream once the endpoint is on the HW schedule.
331 * FIXME - check all the stream rings for pending cancellations.
333 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
334 (ep_state & EP_HALTED))
336 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
337 /* The CPU has better things to do at this point than wait for a
338 * write-posting flush. It'll get there soon enough.
342 /* Ring the doorbell for any rings with pending URBs */
343 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
344 unsigned int slot_id,
345 unsigned int ep_index)
347 unsigned int stream_id;
348 struct xhci_virt_ep *ep;
350 ep = &xhci->devs[slot_id]->eps[ep_index];
352 /* A ring has pending URBs if its TD list is not empty */
353 if (!(ep->ep_state & EP_HAS_STREAMS)) {
354 if (!(list_empty(&ep->ring->td_list)))
355 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
359 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
361 struct xhci_stream_info *stream_info = ep->stream_info;
362 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
363 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
369 * Find the segment that trb is in. Start searching in start_seg.
370 * If we must move past a segment that has a link TRB with a toggle cycle state
371 * bit set, then we will toggle the value pointed at by cycle_state.
373 static struct xhci_segment *find_trb_seg(
374 struct xhci_segment *start_seg,
375 union xhci_trb *trb, int *cycle_state)
377 struct xhci_segment *cur_seg = start_seg;
378 struct xhci_generic_trb *generic_trb;
380 while (cur_seg->trbs > trb ||
381 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
382 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
383 if (generic_trb->field[3] & LINK_TOGGLE)
385 cur_seg = cur_seg->next;
386 if (cur_seg == start_seg)
387 /* Looped over the entire list. Oops! */
394 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
395 unsigned int slot_id, unsigned int ep_index,
396 unsigned int stream_id)
398 struct xhci_virt_ep *ep;
400 ep = &xhci->devs[slot_id]->eps[ep_index];
401 /* Common case: no streams */
402 if (!(ep->ep_state & EP_HAS_STREAMS))
405 if (stream_id == 0) {
407 "WARN: Slot ID %u, ep index %u has streams, "
408 "but URB has no stream ID.\n",
413 if (stream_id < ep->stream_info->num_streams)
414 return ep->stream_info->stream_rings[stream_id];
417 "WARN: Slot ID %u, ep index %u has "
418 "stream IDs 1 to %u allocated, "
419 "but stream ID %u is requested.\n",
421 ep->stream_info->num_streams - 1,
426 /* Get the right ring for the given URB.
427 * If the endpoint supports streams, boundary check the URB's stream ID.
428 * If the endpoint doesn't support streams, return the singular endpoint ring.
430 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
433 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
434 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
438 * Move the xHC's endpoint ring dequeue pointer past cur_td.
439 * Record the new state of the xHC's endpoint ring dequeue segment,
440 * dequeue pointer, and new consumer cycle state in state.
441 * Update our internal representation of the ring's dequeue pointer.
443 * We do this in three jumps:
444 * - First we update our new ring state to be the same as when the xHC stopped.
445 * - Then we traverse the ring to find the segment that contains
446 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
447 * any link TRBs with the toggle cycle bit set.
448 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
449 * if we've moved it past a link TRB with the toggle cycle bit set.
451 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
452 unsigned int slot_id, unsigned int ep_index,
453 unsigned int stream_id, struct xhci_td *cur_td,
454 struct xhci_dequeue_state *state)
456 struct xhci_virt_device *dev = xhci->devs[slot_id];
457 struct xhci_ring *ep_ring;
458 struct xhci_generic_trb *trb;
459 struct xhci_ep_ctx *ep_ctx;
462 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
463 ep_index, stream_id);
465 xhci_warn(xhci, "WARN can't find new dequeue state "
466 "for invalid stream ID %u.\n",
470 state->new_cycle_state = 0;
471 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
472 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
473 dev->eps[ep_index].stopped_trb,
474 &state->new_cycle_state);
475 if (!state->new_deq_seg) {
480 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
481 xhci_dbg(xhci, "Finding endpoint context\n");
482 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
483 state->new_cycle_state = 0x1 & ep_ctx->deq;
485 state->new_deq_ptr = cur_td->last_trb;
486 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
487 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
489 &state->new_cycle_state);
490 if (!state->new_deq_seg) {
495 trb = &state->new_deq_ptr->generic;
496 if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
497 (trb->field[3] & LINK_TOGGLE))
498 state->new_cycle_state ^= 0x1;
499 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
502 * If there is only one segment in a ring, find_trb_seg()'s while loop
503 * will not run, and it will return before it has a chance to see if it
504 * needs to toggle the cycle bit. It can't tell if the stalled transfer
505 * ended just before the link TRB on a one-segment ring, or if the TD
506 * wrapped around the top of the ring, because it doesn't have the TD in
507 * question. Look for the one-segment case where stalled TRB's address
508 * is greater than the new dequeue pointer address.
510 if (ep_ring->first_seg == ep_ring->first_seg->next &&
511 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
512 state->new_cycle_state ^= 0x1;
513 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
515 /* Don't update the ring cycle state for the producer (us). */
516 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
518 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
519 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
520 (unsigned long long) addr);
523 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
524 struct xhci_td *cur_td)
526 struct xhci_segment *cur_seg;
527 union xhci_trb *cur_trb;
529 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
531 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
532 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
533 TRB_TYPE(TRB_LINK)) {
534 /* Unchain any chained Link TRBs, but
535 * leave the pointers intact.
537 cur_trb->generic.field[3] &= ~TRB_CHAIN;
538 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
539 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
540 "in seg %p (0x%llx dma)\n",
542 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
544 (unsigned long long)cur_seg->dma);
546 cur_trb->generic.field[0] = 0;
547 cur_trb->generic.field[1] = 0;
548 cur_trb->generic.field[2] = 0;
549 /* Preserve only the cycle bit of this TRB */
550 cur_trb->generic.field[3] &= TRB_CYCLE;
551 cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
552 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
553 "in seg %p (0x%llx dma)\n",
555 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
557 (unsigned long long)cur_seg->dma);
559 if (cur_trb == cur_td->last_trb)
564 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
565 unsigned int ep_index, unsigned int stream_id,
566 struct xhci_segment *deq_seg,
567 union xhci_trb *deq_ptr, u32 cycle_state);
569 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
570 unsigned int slot_id, unsigned int ep_index,
571 unsigned int stream_id,
572 struct xhci_dequeue_state *deq_state)
574 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
576 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
577 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
578 deq_state->new_deq_seg,
579 (unsigned long long)deq_state->new_deq_seg->dma,
580 deq_state->new_deq_ptr,
581 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
582 deq_state->new_cycle_state);
583 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
584 deq_state->new_deq_seg,
585 deq_state->new_deq_ptr,
586 (u32) deq_state->new_cycle_state);
587 /* Stop the TD queueing code from ringing the doorbell until
588 * this command completes. The HC won't set the dequeue pointer
589 * if the ring is running, and ringing the doorbell starts the
592 ep->ep_state |= SET_DEQ_PENDING;
595 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
596 struct xhci_virt_ep *ep)
598 ep->ep_state &= ~EP_HALT_PENDING;
599 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
600 * timer is running on another CPU, we don't decrement stop_cmds_pending
601 * (since we didn't successfully stop the watchdog timer).
603 if (del_timer(&ep->stop_cmd_timer))
604 ep->stop_cmds_pending--;
607 /* Must be called with xhci->lock held in interrupt context */
608 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
609 struct xhci_td *cur_td, int status, char *adjective)
613 struct urb_priv *urb_priv;
616 urb_priv = urb->hcpriv;
618 hcd = bus_to_hcd(urb->dev->bus);
620 /* Only giveback urb when this is the last td in urb */
621 if (urb_priv->td_cnt == urb_priv->length) {
622 usb_hcd_unlink_urb_from_ep(hcd, urb);
623 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb);
625 spin_unlock(&xhci->lock);
626 usb_hcd_giveback_urb(hcd, urb, status);
627 xhci_urb_free_priv(xhci, urb_priv);
628 spin_lock(&xhci->lock);
629 xhci_dbg(xhci, "%s URB given back\n", adjective);
634 * When we get a command completion for a Stop Endpoint Command, we need to
635 * unlink any cancelled TDs from the ring. There are two ways to do that:
637 * 1. If the HW was in the middle of processing the TD that needs to be
638 * cancelled, then we must move the ring's dequeue pointer past the last TRB
639 * in the TD with a Set Dequeue Pointer Command.
640 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
641 * bit cleared) so that the HW will skip over them.
643 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
644 union xhci_trb *trb, struct xhci_event_cmd *event)
646 unsigned int slot_id;
647 unsigned int ep_index;
648 struct xhci_virt_device *virt_dev;
649 struct xhci_ring *ep_ring;
650 struct xhci_virt_ep *ep;
651 struct list_head *entry;
652 struct xhci_td *cur_td = NULL;
653 struct xhci_td *last_unlinked_td;
655 struct xhci_dequeue_state deq_state;
657 if (unlikely(TRB_TO_SUSPEND_PORT(
658 xhci->cmd_ring->dequeue->generic.field[3]))) {
659 slot_id = TRB_TO_SLOT_ID(
660 xhci->cmd_ring->dequeue->generic.field[3]);
661 virt_dev = xhci->devs[slot_id];
663 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
666 xhci_warn(xhci, "Stop endpoint command "
667 "completion for disabled slot %u\n",
672 memset(&deq_state, 0, sizeof(deq_state));
673 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
674 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
675 ep = &xhci->devs[slot_id]->eps[ep_index];
677 if (list_empty(&ep->cancelled_td_list)) {
678 xhci_stop_watchdog_timer_in_irq(xhci, ep);
679 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
683 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
684 * We have the xHCI lock, so nothing can modify this list until we drop
685 * it. We're also in the event handler, so we can't get re-interrupted
686 * if another Stop Endpoint command completes
688 list_for_each(entry, &ep->cancelled_td_list) {
689 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
690 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
692 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
693 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
695 /* This shouldn't happen unless a driver is mucking
696 * with the stream ID after submission. This will
697 * leave the TD on the hardware ring, and the hardware
698 * will try to execute it, and may access a buffer
699 * that has already been freed. In the best case, the
700 * hardware will execute it, and the event handler will
701 * ignore the completion event for that TD, since it was
702 * removed from the td_list for that endpoint. In
703 * short, don't muck with the stream ID after
706 xhci_warn(xhci, "WARN Cancelled URB %p "
707 "has invalid stream ID %u.\n",
709 cur_td->urb->stream_id);
710 goto remove_finished_td;
713 * If we stopped on the TD we need to cancel, then we have to
714 * move the xHC endpoint ring dequeue pointer past this TD.
716 if (cur_td == ep->stopped_td)
717 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
718 cur_td->urb->stream_id,
721 td_to_noop(xhci, ep_ring, cur_td);
724 * The event handler won't see a completion for this TD anymore,
725 * so remove it from the endpoint ring's TD list. Keep it in
726 * the cancelled TD list for URB completion later.
728 list_del(&cur_td->td_list);
730 last_unlinked_td = cur_td;
731 xhci_stop_watchdog_timer_in_irq(xhci, ep);
733 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
734 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
735 xhci_queue_new_dequeue_state(xhci,
737 ep->stopped_td->urb->stream_id,
739 xhci_ring_cmd_db(xhci);
741 /* Otherwise ring the doorbell(s) to restart queued transfers */
742 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
744 ep->stopped_td = NULL;
745 ep->stopped_trb = NULL;
748 * Drop the lock and complete the URBs in the cancelled TD list.
749 * New TDs to be cancelled might be added to the end of the list before
750 * we can complete all the URBs for the TDs we already unlinked.
751 * So stop when we've completed the URB for the last TD we unlinked.
754 cur_td = list_entry(ep->cancelled_td_list.next,
755 struct xhci_td, cancelled_td_list);
756 list_del(&cur_td->cancelled_td_list);
758 /* Clean up the cancelled URB */
759 /* Doesn't matter what we pass for status, since the core will
760 * just overwrite it (because the URB has been unlinked).
762 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
764 /* Stop processing the cancelled list if the watchdog timer is
767 if (xhci->xhc_state & XHCI_STATE_DYING)
769 } while (cur_td != last_unlinked_td);
771 /* Return to the event handler with xhci->lock re-acquired */
774 /* Watchdog timer function for when a stop endpoint command fails to complete.
775 * In this case, we assume the host controller is broken or dying or dead. The
776 * host may still be completing some other events, so we have to be careful to
777 * let the event ring handler and the URB dequeueing/enqueueing functions know
778 * through xhci->state.
780 * The timer may also fire if the host takes a very long time to respond to the
781 * command, and the stop endpoint command completion handler cannot delete the
782 * timer before the timer function is called. Another endpoint cancellation may
783 * sneak in before the timer function can grab the lock, and that may queue
784 * another stop endpoint command and add the timer back. So we cannot use a
785 * simple flag to say whether there is a pending stop endpoint command for a
786 * particular endpoint.
788 * Instead we use a combination of that flag and a counter for the number of
789 * pending stop endpoint commands. If the timer is the tail end of the last
790 * stop endpoint command, and the endpoint's command is still pending, we assume
793 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
795 struct xhci_hcd *xhci;
796 struct xhci_virt_ep *ep;
797 struct xhci_virt_ep *temp_ep;
798 struct xhci_ring *ring;
799 struct xhci_td *cur_td;
802 ep = (struct xhci_virt_ep *) arg;
805 spin_lock(&xhci->lock);
807 ep->stop_cmds_pending--;
808 if (xhci->xhc_state & XHCI_STATE_DYING) {
809 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
810 "xHCI as DYING, exiting.\n");
811 spin_unlock(&xhci->lock);
814 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
815 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
817 spin_unlock(&xhci->lock);
821 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
822 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
823 /* Oops, HC is dead or dying or at least not responding to the stop
826 xhci->xhc_state |= XHCI_STATE_DYING;
827 /* Disable interrupts from the host controller and start halting it */
829 spin_unlock(&xhci->lock);
831 ret = xhci_halt(xhci);
833 spin_lock(&xhci->lock);
835 /* This is bad; the host is not responding to commands and it's
836 * not allowing itself to be halted. At least interrupts are
837 * disabled. If we call usb_hc_died(), it will attempt to
838 * disconnect all device drivers under this host. Those
839 * disconnect() methods will wait for all URBs to be unlinked,
840 * so we must complete them.
842 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
843 xhci_warn(xhci, "Completing active URBs anyway.\n");
844 /* We could turn all TDs on the rings to no-ops. This won't
845 * help if the host has cached part of the ring, and is slow if
846 * we want to preserve the cycle bit. Skip it and hope the host
847 * doesn't touch the memory.
850 for (i = 0; i < MAX_HC_SLOTS; i++) {
853 for (j = 0; j < 31; j++) {
854 temp_ep = &xhci->devs[i]->eps[j];
855 ring = temp_ep->ring;
858 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
859 "ep index %u\n", i, j);
860 while (!list_empty(&ring->td_list)) {
861 cur_td = list_first_entry(&ring->td_list,
864 list_del(&cur_td->td_list);
865 if (!list_empty(&cur_td->cancelled_td_list))
866 list_del(&cur_td->cancelled_td_list);
867 xhci_giveback_urb_in_irq(xhci, cur_td,
868 -ESHUTDOWN, "killed");
870 while (!list_empty(&temp_ep->cancelled_td_list)) {
871 cur_td = list_first_entry(
872 &temp_ep->cancelled_td_list,
875 list_del(&cur_td->cancelled_td_list);
876 xhci_giveback_urb_in_irq(xhci, cur_td,
877 -ESHUTDOWN, "killed");
881 spin_unlock(&xhci->lock);
882 xhci_dbg(xhci, "Calling usb_hc_died()\n");
883 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
884 xhci_dbg(xhci, "xHCI host controller is dead.\n");
888 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
889 * we need to clear the set deq pending flag in the endpoint ring state, so that
890 * the TD queueing code can ring the doorbell again. We also need to ring the
891 * endpoint doorbell to restart the ring, but only if there aren't more
892 * cancellations pending.
894 static void handle_set_deq_completion(struct xhci_hcd *xhci,
895 struct xhci_event_cmd *event,
898 unsigned int slot_id;
899 unsigned int ep_index;
900 unsigned int stream_id;
901 struct xhci_ring *ep_ring;
902 struct xhci_virt_device *dev;
903 struct xhci_ep_ctx *ep_ctx;
904 struct xhci_slot_ctx *slot_ctx;
906 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
907 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
908 stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
909 dev = xhci->devs[slot_id];
911 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
913 xhci_warn(xhci, "WARN Set TR deq ptr command for "
914 "freed stream ID %u\n",
916 /* XXX: Harmless??? */
917 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
921 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
922 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
924 if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
925 unsigned int ep_state;
926 unsigned int slot_state;
928 switch (GET_COMP_CODE(event->status)) {
930 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
931 "of stream ID configuration\n");
934 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
935 "to incorrect slot or ep state.\n");
936 ep_state = ep_ctx->ep_info;
937 ep_state &= EP_STATE_MASK;
938 slot_state = slot_ctx->dev_state;
939 slot_state = GET_SLOT_STATE(slot_state);
940 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
941 slot_state, ep_state);
944 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
945 "slot %u was not enabled.\n", slot_id);
948 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
949 "completion code of %u.\n",
950 GET_COMP_CODE(event->status));
953 /* OK what do we do now? The endpoint state is hosed, and we
954 * should never get to this point if the synchronization between
955 * queueing, and endpoint state are correct. This might happen
956 * if the device gets disconnected after we've finished
957 * cancelling URBs, which might not be an error...
960 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
962 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
963 dev->eps[ep_index].queued_deq_ptr) ==
964 (ep_ctx->deq & ~(EP_CTX_CYCLE_MASK))) {
965 /* Update the ring's dequeue segment and dequeue pointer
966 * to reflect the new position.
968 ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
969 ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
971 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
972 "Ptr command & xHCI internal state.\n");
973 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
974 dev->eps[ep_index].queued_deq_seg,
975 dev->eps[ep_index].queued_deq_ptr);
979 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
980 dev->eps[ep_index].queued_deq_seg = NULL;
981 dev->eps[ep_index].queued_deq_ptr = NULL;
982 /* Restart any rings with pending URBs */
983 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
986 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
987 struct xhci_event_cmd *event,
991 unsigned int ep_index;
993 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
994 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
995 /* This command will only fail if the endpoint wasn't halted,
998 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
999 (unsigned int) GET_COMP_CODE(event->status));
1001 /* HW with the reset endpoint quirk needs to have a configure endpoint
1002 * command complete before the endpoint can be used. Queue that here
1003 * because the HW can't handle two commands being queued in a row.
1005 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1006 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1007 xhci_queue_configure_endpoint(xhci,
1008 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1010 xhci_ring_cmd_db(xhci);
1012 /* Clear our internal halted state and restart the ring(s) */
1013 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1014 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1018 /* Check to see if a command in the device's command queue matches this one.
1019 * Signal the completion or free the command, and return 1. Return 0 if the
1020 * completed command isn't at the head of the command list.
1022 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1023 struct xhci_virt_device *virt_dev,
1024 struct xhci_event_cmd *event)
1026 struct xhci_command *command;
1028 if (list_empty(&virt_dev->cmd_list))
1031 command = list_entry(virt_dev->cmd_list.next,
1032 struct xhci_command, cmd_list);
1033 if (xhci->cmd_ring->dequeue != command->command_trb)
1037 GET_COMP_CODE(event->status);
1038 list_del(&command->cmd_list);
1039 if (command->completion)
1040 complete(command->completion);
1042 xhci_free_command(xhci, command);
1046 static void handle_cmd_completion(struct xhci_hcd *xhci,
1047 struct xhci_event_cmd *event)
1049 int slot_id = TRB_TO_SLOT_ID(event->flags);
1051 dma_addr_t cmd_dequeue_dma;
1052 struct xhci_input_control_ctx *ctrl_ctx;
1053 struct xhci_virt_device *virt_dev;
1054 unsigned int ep_index;
1055 struct xhci_ring *ep_ring;
1056 unsigned int ep_state;
1058 cmd_dma = event->cmd_trb;
1059 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1060 xhci->cmd_ring->dequeue);
1061 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1062 if (cmd_dequeue_dma == 0) {
1063 xhci->error_bitmask |= 1 << 4;
1066 /* Does the DMA address match our internal dequeue pointer address? */
1067 if (cmd_dma != (u64) cmd_dequeue_dma) {
1068 xhci->error_bitmask |= 1 << 5;
1071 switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
1072 case TRB_TYPE(TRB_ENABLE_SLOT):
1073 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
1074 xhci->slot_id = slot_id;
1077 complete(&xhci->addr_dev);
1079 case TRB_TYPE(TRB_DISABLE_SLOT):
1080 if (xhci->devs[slot_id])
1081 xhci_free_virt_device(xhci, slot_id);
1083 case TRB_TYPE(TRB_CONFIG_EP):
1084 virt_dev = xhci->devs[slot_id];
1085 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1088 * Configure endpoint commands can come from the USB core
1089 * configuration or alt setting changes, or because the HW
1090 * needed an extra configure endpoint command after a reset
1091 * endpoint command or streams were being configured.
1092 * If the command was for a halted endpoint, the xHCI driver
1093 * is not waiting on the configure endpoint command.
1095 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1097 /* Input ctx add_flags are the endpoint index plus one */
1098 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
1099 /* A usb_set_interface() call directly after clearing a halted
1100 * condition may race on this quirky hardware. Not worth
1101 * worrying about, since this is prototype hardware. Not sure
1102 * if this will work for streams, but streams support was
1103 * untested on this prototype.
1105 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1106 ep_index != (unsigned int) -1 &&
1107 ctrl_ctx->add_flags - SLOT_FLAG ==
1108 ctrl_ctx->drop_flags) {
1109 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1110 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1111 if (!(ep_state & EP_HALTED))
1112 goto bandwidth_change;
1113 xhci_dbg(xhci, "Completed config ep cmd - "
1114 "last ep index = %d, state = %d\n",
1115 ep_index, ep_state);
1116 /* Clear internal halted state and restart ring(s) */
1117 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1119 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1123 xhci_dbg(xhci, "Completed config ep cmd\n");
1124 xhci->devs[slot_id]->cmd_status =
1125 GET_COMP_CODE(event->status);
1126 complete(&xhci->devs[slot_id]->cmd_completion);
1128 case TRB_TYPE(TRB_EVAL_CONTEXT):
1129 virt_dev = xhci->devs[slot_id];
1130 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1132 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1133 complete(&xhci->devs[slot_id]->cmd_completion);
1135 case TRB_TYPE(TRB_ADDR_DEV):
1136 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1137 complete(&xhci->addr_dev);
1139 case TRB_TYPE(TRB_STOP_RING):
1140 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1142 case TRB_TYPE(TRB_SET_DEQ):
1143 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1145 case TRB_TYPE(TRB_CMD_NOOP):
1147 case TRB_TYPE(TRB_RESET_EP):
1148 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1150 case TRB_TYPE(TRB_RESET_DEV):
1151 xhci_dbg(xhci, "Completed reset device command.\n");
1152 slot_id = TRB_TO_SLOT_ID(
1153 xhci->cmd_ring->dequeue->generic.field[3]);
1154 virt_dev = xhci->devs[slot_id];
1156 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1158 xhci_warn(xhci, "Reset device command completion "
1159 "for disabled slot %u\n", slot_id);
1161 case TRB_TYPE(TRB_NEC_GET_FW):
1162 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1163 xhci->error_bitmask |= 1 << 6;
1166 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1167 NEC_FW_MAJOR(event->status),
1168 NEC_FW_MINOR(event->status));
1171 /* Skip over unknown commands on the event ring */
1172 xhci->error_bitmask |= 1 << 6;
1175 inc_deq(xhci, xhci->cmd_ring, false);
1178 static void handle_vendor_event(struct xhci_hcd *xhci,
1179 union xhci_trb *event)
1183 trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]);
1184 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1185 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1186 handle_cmd_completion(xhci, &event->event_cmd);
1189 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1190 * port registers -- USB 3.0 and USB 2.0).
1192 * Returns a zero-based port number, which is suitable for indexing into each of
1193 * the split roothubs' port arrays and bus state arrays.
1195 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1196 struct xhci_hcd *xhci, u32 port_id)
1199 unsigned int num_similar_speed_ports = 0;
1201 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1202 * and usb2_ports are 0-based indexes. Count the number of similar
1203 * speed ports, up to 1 port before this port.
1205 for (i = 0; i < (port_id - 1); i++) {
1206 u8 port_speed = xhci->port_array[i];
1209 * Skip ports that don't have known speeds, or have duplicate
1210 * Extended Capabilities port speed entries.
1212 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1216 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1217 * 1.1 ports are under the USB 2.0 hub. If the port speed
1218 * matches the device speed, it's a similar speed port.
1220 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1221 num_similar_speed_ports++;
1223 return num_similar_speed_ports;
1226 static void handle_port_status(struct xhci_hcd *xhci,
1227 union xhci_trb *event)
1229 struct usb_hcd *hcd;
1234 unsigned int faked_port_index;
1236 struct xhci_bus_state *bus_state;
1237 u32 __iomem **port_array;
1238 bool bogus_port_status = false;
1240 /* Port status change events always have a successful completion code */
1241 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1242 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1243 xhci->error_bitmask |= 1 << 8;
1245 port_id = GET_PORT_ID(event->generic.field[0]);
1246 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1248 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1249 if ((port_id <= 0) || (port_id > max_ports)) {
1250 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1251 bogus_port_status = true;
1255 /* Figure out which usb_hcd this port is attached to:
1256 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1258 major_revision = xhci->port_array[port_id - 1];
1259 if (major_revision == 0) {
1260 xhci_warn(xhci, "Event for port %u not in "
1261 "Extended Capabilities, ignoring.\n",
1263 bogus_port_status = true;
1266 if (major_revision == DUPLICATE_ENTRY) {
1267 xhci_warn(xhci, "Event for port %u duplicated in"
1268 "Extended Capabilities, ignoring.\n",
1270 bogus_port_status = true;
1275 * Hardware port IDs reported by a Port Status Change Event include USB
1276 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1277 * resume event, but we first need to translate the hardware port ID
1278 * into the index into the ports on the correct split roothub, and the
1279 * correct bus_state structure.
1281 /* Find the right roothub. */
1282 hcd = xhci_to_hcd(xhci);
1283 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1284 hcd = xhci->shared_hcd;
1285 bus_state = &xhci->bus_state[hcd_index(hcd)];
1286 if (hcd->speed == HCD_USB3)
1287 port_array = xhci->usb3_ports;
1289 port_array = xhci->usb2_ports;
1290 /* Find the faked port hub number */
1291 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1294 temp = xhci_readl(xhci, port_array[faked_port_index]);
1295 if (hcd->state == HC_STATE_SUSPENDED) {
1296 xhci_dbg(xhci, "resume root hub\n");
1297 usb_hcd_resume_root_hub(hcd);
1300 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1301 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1303 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1304 if (!(temp1 & CMD_RUN)) {
1305 xhci_warn(xhci, "xHC is not running.\n");
1309 if (DEV_SUPERSPEED(temp)) {
1310 xhci_dbg(xhci, "resume SS port %d\n", port_id);
1311 temp = xhci_port_state_to_neutral(temp);
1312 temp &= ~PORT_PLS_MASK;
1313 temp |= PORT_LINK_STROBE | XDEV_U0;
1314 xhci_writel(xhci, temp, port_array[faked_port_index]);
1315 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1318 xhci_dbg(xhci, "slot_id is zero\n");
1321 xhci_ring_device(xhci, slot_id);
1322 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1323 /* Clear PORT_PLC */
1324 temp = xhci_readl(xhci, port_array[faked_port_index]);
1325 temp = xhci_port_state_to_neutral(temp);
1327 xhci_writel(xhci, temp, port_array[faked_port_index]);
1329 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1330 bus_state->resume_done[faked_port_index] = jiffies +
1331 msecs_to_jiffies(20);
1332 mod_timer(&hcd->rh_timer,
1333 bus_state->resume_done[faked_port_index]);
1334 /* Do the rest in GetPortStatus */
1339 /* Update event ring dequeue pointer before dropping the lock */
1340 inc_deq(xhci, xhci->event_ring, true);
1342 /* Don't make the USB core poll the roothub if we got a bad port status
1343 * change event. Besides, at that point we can't tell which roothub
1344 * (USB 2.0 or USB 3.0) to kick.
1346 if (bogus_port_status)
1349 spin_unlock(&xhci->lock);
1350 /* Pass this up to the core */
1351 usb_hcd_poll_rh_status(hcd);
1352 spin_lock(&xhci->lock);
1356 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1357 * at end_trb, which may be in another segment. If the suspect DMA address is a
1358 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1361 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1362 union xhci_trb *start_trb,
1363 union xhci_trb *end_trb,
1364 dma_addr_t suspect_dma)
1366 dma_addr_t start_dma;
1367 dma_addr_t end_seg_dma;
1368 dma_addr_t end_trb_dma;
1369 struct xhci_segment *cur_seg;
1371 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1372 cur_seg = start_seg;
1377 /* We may get an event for a Link TRB in the middle of a TD */
1378 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1379 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1380 /* If the end TRB isn't in this segment, this is set to 0 */
1381 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1383 if (end_trb_dma > 0) {
1384 /* The end TRB is in this segment, so suspect should be here */
1385 if (start_dma <= end_trb_dma) {
1386 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1389 /* Case for one segment with
1390 * a TD wrapped around to the top
1392 if ((suspect_dma >= start_dma &&
1393 suspect_dma <= end_seg_dma) ||
1394 (suspect_dma >= cur_seg->dma &&
1395 suspect_dma <= end_trb_dma))
1400 /* Might still be somewhere in this segment */
1401 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1404 cur_seg = cur_seg->next;
1405 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1406 } while (cur_seg != start_seg);
1411 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1412 unsigned int slot_id, unsigned int ep_index,
1413 unsigned int stream_id,
1414 struct xhci_td *td, union xhci_trb *event_trb)
1416 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1417 ep->ep_state |= EP_HALTED;
1418 ep->stopped_td = td;
1419 ep->stopped_trb = event_trb;
1420 ep->stopped_stream = stream_id;
1422 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1423 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1425 ep->stopped_td = NULL;
1426 ep->stopped_trb = NULL;
1427 ep->stopped_stream = 0;
1429 xhci_ring_cmd_db(xhci);
1432 /* Check if an error has halted the endpoint ring. The class driver will
1433 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1434 * However, a babble and other errors also halt the endpoint ring, and the class
1435 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1436 * Ring Dequeue Pointer command manually.
1438 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1439 struct xhci_ep_ctx *ep_ctx,
1440 unsigned int trb_comp_code)
1442 /* TRB completion codes that may require a manual halt cleanup */
1443 if (trb_comp_code == COMP_TX_ERR ||
1444 trb_comp_code == COMP_BABBLE ||
1445 trb_comp_code == COMP_SPLIT_ERR)
1446 /* The 0.96 spec says a babbling control endpoint
1447 * is not halted. The 0.96 spec says it is. Some HW
1448 * claims to be 0.95 compliant, but it halts the control
1449 * endpoint anyway. Check if a babble halted the
1452 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1458 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1460 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1461 /* Vendor defined "informational" completion code,
1462 * treat as not-an-error.
1464 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1466 xhci_dbg(xhci, "Treating code as success.\n");
1473 * Finish the td processing, remove the td from td list;
1474 * Return 1 if the urb can be given back.
1476 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1477 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1478 struct xhci_virt_ep *ep, int *status, bool skip)
1480 struct xhci_virt_device *xdev;
1481 struct xhci_ring *ep_ring;
1482 unsigned int slot_id;
1484 struct urb *urb = NULL;
1485 struct xhci_ep_ctx *ep_ctx;
1487 struct urb_priv *urb_priv;
1490 slot_id = TRB_TO_SLOT_ID(event->flags);
1491 xdev = xhci->devs[slot_id];
1492 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1493 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1494 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1495 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1500 if (trb_comp_code == COMP_STOP_INVAL ||
1501 trb_comp_code == COMP_STOP) {
1502 /* The Endpoint Stop Command completion will take care of any
1503 * stopped TDs. A stopped TD may be restarted, so don't update
1504 * the ring dequeue pointer or take this TD off any lists yet.
1506 ep->stopped_td = td;
1507 ep->stopped_trb = event_trb;
1510 if (trb_comp_code == COMP_STALL) {
1511 /* The transfer is completed from the driver's
1512 * perspective, but we need to issue a set dequeue
1513 * command for this stalled endpoint to move the dequeue
1514 * pointer past the TD. We can't do that here because
1515 * the halt condition must be cleared first. Let the
1516 * USB class driver clear the stall later.
1518 ep->stopped_td = td;
1519 ep->stopped_trb = event_trb;
1520 ep->stopped_stream = ep_ring->stream_id;
1521 } else if (xhci_requires_manual_halt_cleanup(xhci,
1522 ep_ctx, trb_comp_code)) {
1523 /* Other types of errors halt the endpoint, but the
1524 * class driver doesn't call usb_reset_endpoint() unless
1525 * the error is -EPIPE. Clear the halted status in the
1526 * xHCI hardware manually.
1528 xhci_cleanup_halted_endpoint(xhci,
1529 slot_id, ep_index, ep_ring->stream_id,
1532 /* Update ring dequeue pointer */
1533 while (ep_ring->dequeue != td->last_trb)
1534 inc_deq(xhci, ep_ring, false);
1535 inc_deq(xhci, ep_ring, false);
1539 /* Clean up the endpoint's TD list */
1541 urb_priv = urb->hcpriv;
1543 /* Do one last check of the actual transfer length.
1544 * If the host controller said we transferred more data than
1545 * the buffer length, urb->actual_length will be a very big
1546 * number (since it's unsigned). Play it safe and say we didn't
1547 * transfer anything.
1549 if (urb->actual_length > urb->transfer_buffer_length) {
1550 xhci_warn(xhci, "URB transfer length is wrong, "
1551 "xHC issue? req. len = %u, "
1553 urb->transfer_buffer_length,
1554 urb->actual_length);
1555 urb->actual_length = 0;
1556 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1557 *status = -EREMOTEIO;
1561 list_del(&td->td_list);
1562 /* Was this TD slated to be cancelled but completed anyway? */
1563 if (!list_empty(&td->cancelled_td_list))
1564 list_del(&td->cancelled_td_list);
1567 /* Giveback the urb when all the tds are completed */
1568 if (urb_priv->td_cnt == urb_priv->length)
1576 * Process control tds, update urb status and actual_length.
1578 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1579 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1580 struct xhci_virt_ep *ep, int *status)
1582 struct xhci_virt_device *xdev;
1583 struct xhci_ring *ep_ring;
1584 unsigned int slot_id;
1586 struct xhci_ep_ctx *ep_ctx;
1589 slot_id = TRB_TO_SLOT_ID(event->flags);
1590 xdev = xhci->devs[slot_id];
1591 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1592 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1593 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1594 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1596 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1597 switch (trb_comp_code) {
1599 if (event_trb == ep_ring->dequeue) {
1600 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1601 "without IOC set??\n");
1602 *status = -ESHUTDOWN;
1603 } else if (event_trb != td->last_trb) {
1604 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1605 "without IOC set??\n");
1606 *status = -ESHUTDOWN;
1608 xhci_dbg(xhci, "Successful control transfer!\n");
1613 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1614 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1615 *status = -EREMOTEIO;
1620 if (!xhci_requires_manual_halt_cleanup(xhci,
1621 ep_ctx, trb_comp_code))
1623 xhci_dbg(xhci, "TRB error code %u, "
1624 "halted endpoint index = %u\n",
1625 trb_comp_code, ep_index);
1626 /* else fall through */
1628 /* Did we transfer part of the data (middle) phase? */
1629 if (event_trb != ep_ring->dequeue &&
1630 event_trb != td->last_trb)
1631 td->urb->actual_length =
1632 td->urb->transfer_buffer_length
1633 - TRB_LEN(event->transfer_len);
1635 td->urb->actual_length = 0;
1637 xhci_cleanup_halted_endpoint(xhci,
1638 slot_id, ep_index, 0, td, event_trb);
1639 return finish_td(xhci, td, event_trb, event, ep, status, true);
1642 * Did we transfer any data, despite the errors that might have
1643 * happened? I.e. did we get past the setup stage?
1645 if (event_trb != ep_ring->dequeue) {
1646 /* The event was for the status stage */
1647 if (event_trb == td->last_trb) {
1648 if (td->urb->actual_length != 0) {
1649 /* Don't overwrite a previously set error code
1651 if ((*status == -EINPROGRESS || *status == 0) &&
1652 (td->urb->transfer_flags
1653 & URB_SHORT_NOT_OK))
1654 /* Did we already see a short data
1656 *status = -EREMOTEIO;
1658 td->urb->actual_length =
1659 td->urb->transfer_buffer_length;
1662 /* Maybe the event was for the data stage? */
1663 if (trb_comp_code != COMP_STOP_INVAL) {
1664 /* We didn't stop on a link TRB in the middle */
1665 td->urb->actual_length =
1666 td->urb->transfer_buffer_length -
1667 TRB_LEN(event->transfer_len);
1668 xhci_dbg(xhci, "Waiting for status "
1675 return finish_td(xhci, td, event_trb, event, ep, status, false);
1679 * Process isochronous tds, update urb packet status and actual_length.
1681 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1682 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1683 struct xhci_virt_ep *ep, int *status)
1685 struct xhci_ring *ep_ring;
1686 struct urb_priv *urb_priv;
1689 union xhci_trb *cur_trb;
1690 struct xhci_segment *cur_seg;
1691 struct usb_iso_packet_descriptor *frame;
1693 bool skip_td = false;
1695 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1696 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1697 urb_priv = td->urb->hcpriv;
1698 idx = urb_priv->td_cnt;
1699 frame = &td->urb->iso_frame_desc[idx];
1701 /* handle completion code */
1702 switch (trb_comp_code) {
1705 xhci_dbg(xhci, "Successful isoc transfer!\n");
1708 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1712 frame->status = -ECOMM;
1715 case COMP_BUFF_OVER:
1717 frame->status = -EOVERFLOW;
1721 frame->status = -EPROTO;
1725 case COMP_STOP_INVAL:
1732 if (trb_comp_code == COMP_SUCCESS || skip_td) {
1733 frame->actual_length = frame->length;
1734 td->urb->actual_length += frame->length;
1736 for (cur_trb = ep_ring->dequeue,
1737 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1738 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1739 if ((cur_trb->generic.field[3] &
1740 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1741 (cur_trb->generic.field[3] &
1742 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1744 TRB_LEN(cur_trb->generic.field[2]);
1746 len += TRB_LEN(cur_trb->generic.field[2]) -
1747 TRB_LEN(event->transfer_len);
1749 if (trb_comp_code != COMP_STOP_INVAL) {
1750 frame->actual_length = len;
1751 td->urb->actual_length += len;
1755 if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS)
1758 return finish_td(xhci, td, event_trb, event, ep, status, false);
1761 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1762 struct xhci_transfer_event *event,
1763 struct xhci_virt_ep *ep, int *status)
1765 struct xhci_ring *ep_ring;
1766 struct urb_priv *urb_priv;
1767 struct usb_iso_packet_descriptor *frame;
1770 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1771 urb_priv = td->urb->hcpriv;
1772 idx = urb_priv->td_cnt;
1773 frame = &td->urb->iso_frame_desc[idx];
1775 /* The transfer is partly done */
1777 frame->status = -EXDEV;
1779 /* calc actual length */
1780 frame->actual_length = 0;
1782 /* Update ring dequeue pointer */
1783 while (ep_ring->dequeue != td->last_trb)
1784 inc_deq(xhci, ep_ring, false);
1785 inc_deq(xhci, ep_ring, false);
1787 return finish_td(xhci, td, NULL, event, ep, status, true);
1791 * Process bulk and interrupt tds, update urb status and actual_length.
1793 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1794 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1795 struct xhci_virt_ep *ep, int *status)
1797 struct xhci_ring *ep_ring;
1798 union xhci_trb *cur_trb;
1799 struct xhci_segment *cur_seg;
1802 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1803 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1805 switch (trb_comp_code) {
1807 /* Double check that the HW transferred everything. */
1808 if (event_trb != td->last_trb) {
1809 xhci_warn(xhci, "WARN Successful completion "
1811 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1812 *status = -EREMOTEIO;
1816 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1817 xhci_dbg(xhci, "Successful bulk "
1820 xhci_dbg(xhci, "Successful interrupt "
1826 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1827 *status = -EREMOTEIO;
1832 /* Others already handled above */
1835 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1836 "%d bytes untransferred\n",
1837 td->urb->ep->desc.bEndpointAddress,
1838 td->urb->transfer_buffer_length,
1839 TRB_LEN(event->transfer_len));
1840 /* Fast path - was this the last TRB in the TD for this URB? */
1841 if (event_trb == td->last_trb) {
1842 if (TRB_LEN(event->transfer_len) != 0) {
1843 td->urb->actual_length =
1844 td->urb->transfer_buffer_length -
1845 TRB_LEN(event->transfer_len);
1846 if (td->urb->transfer_buffer_length <
1847 td->urb->actual_length) {
1848 xhci_warn(xhci, "HC gave bad length "
1849 "of %d bytes left\n",
1850 TRB_LEN(event->transfer_len));
1851 td->urb->actual_length = 0;
1852 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1853 *status = -EREMOTEIO;
1857 /* Don't overwrite a previously set error code */
1858 if (*status == -EINPROGRESS) {
1859 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1860 *status = -EREMOTEIO;
1865 td->urb->actual_length =
1866 td->urb->transfer_buffer_length;
1867 /* Ignore a short packet completion if the
1868 * untransferred length was zero.
1870 if (*status == -EREMOTEIO)
1874 /* Slow path - walk the list, starting from the dequeue
1875 * pointer, to get the actual length transferred.
1877 td->urb->actual_length = 0;
1878 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1879 cur_trb != event_trb;
1880 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1881 if ((cur_trb->generic.field[3] &
1882 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1883 (cur_trb->generic.field[3] &
1884 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1885 td->urb->actual_length +=
1886 TRB_LEN(cur_trb->generic.field[2]);
1888 /* If the ring didn't stop on a Link or No-op TRB, add
1889 * in the actual bytes transferred from the Normal TRB
1891 if (trb_comp_code != COMP_STOP_INVAL)
1892 td->urb->actual_length +=
1893 TRB_LEN(cur_trb->generic.field[2]) -
1894 TRB_LEN(event->transfer_len);
1897 return finish_td(xhci, td, event_trb, event, ep, status, false);
1901 * If this function returns an error condition, it means it got a Transfer
1902 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1903 * At this point, the host controller is probably hosed and should be reset.
1905 static int handle_tx_event(struct xhci_hcd *xhci,
1906 struct xhci_transfer_event *event)
1908 struct xhci_virt_device *xdev;
1909 struct xhci_virt_ep *ep;
1910 struct xhci_ring *ep_ring;
1911 unsigned int slot_id;
1913 struct xhci_td *td = NULL;
1914 dma_addr_t event_dma;
1915 struct xhci_segment *event_seg;
1916 union xhci_trb *event_trb;
1917 struct urb *urb = NULL;
1918 int status = -EINPROGRESS;
1919 struct urb_priv *urb_priv;
1920 struct xhci_ep_ctx *ep_ctx;
1924 slot_id = TRB_TO_SLOT_ID(event->flags);
1925 xdev = xhci->devs[slot_id];
1927 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1931 /* Endpoint ID is 1 based, our index is zero based */
1932 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1933 xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1934 ep = &xdev->eps[ep_index];
1935 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1936 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1938 (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1939 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1940 "or incorrect stream ring\n");
1944 event_dma = event->buffer;
1945 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1946 /* Look for common error cases */
1947 switch (trb_comp_code) {
1948 /* Skip codes that require special handling depending on
1955 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1957 case COMP_STOP_INVAL:
1958 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1961 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1962 ep->ep_state |= EP_HALTED;
1966 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1969 case COMP_SPLIT_ERR:
1971 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1975 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1976 status = -EOVERFLOW;
1979 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1983 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
1985 case COMP_BUFF_OVER:
1986 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
1990 * When the Isoch ring is empty, the xHC will generate
1991 * a Ring Overrun Event for IN Isoch endpoint or Ring
1992 * Underrun Event for OUT Isoch endpoint.
1994 xhci_dbg(xhci, "underrun event on endpoint\n");
1995 if (!list_empty(&ep_ring->td_list))
1996 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
1997 "still with TDs queued?\n",
1998 TRB_TO_SLOT_ID(event->flags), ep_index);
2001 xhci_dbg(xhci, "overrun event on endpoint\n");
2002 if (!list_empty(&ep_ring->td_list))
2003 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2004 "still with TDs queued?\n",
2005 TRB_TO_SLOT_ID(event->flags), ep_index);
2007 case COMP_MISSED_INT:
2009 * When encounter missed service error, one or more isoc tds
2010 * may be missed by xHC.
2011 * Set skip flag of the ep_ring; Complete the missed tds as
2012 * short transfer when process the ep_ring next time.
2015 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2018 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2022 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2028 /* This TRB should be in the TD at the head of this ring's
2031 if (list_empty(&ep_ring->td_list)) {
2032 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2033 "with no TDs queued?\n",
2034 TRB_TO_SLOT_ID(event->flags), ep_index);
2035 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2036 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
2037 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2040 xhci_dbg(xhci, "td_list is empty while skip "
2041 "flag set. Clear skip flag.\n");
2047 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2049 /* Is this a TRB in the currently executing TD? */
2050 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2051 td->last_trb, event_dma);
2054 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2055 /* HC is busted, give up! */
2057 "ERROR Transfer event TRB DMA ptr not "
2058 "part of current TD\n");
2062 ret = skip_isoc_td(xhci, td, event, ep, &status);
2067 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2071 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2072 sizeof(*event_trb)];
2074 * No-op TRB should not trigger interrupts.
2075 * If event_trb is a no-op TRB, it means the
2076 * corresponding TD has been cancelled. Just ignore
2079 if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK)
2080 == TRB_TYPE(TRB_TR_NOOP)) {
2082 "event_trb is a no-op TRB. Skip it\n");
2086 /* Now update the urb's actual_length and give back to
2089 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2090 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2092 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2093 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2096 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2101 * Do not update event ring dequeue pointer if ep->skip is set.
2102 * Will roll back to continue process missed tds.
2104 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2105 inc_deq(xhci, xhci->event_ring, true);
2110 urb_priv = urb->hcpriv;
2111 /* Leave the TD around for the reset endpoint function
2112 * to use(but only if it's not a control endpoint,
2113 * since we already queued the Set TR dequeue pointer
2114 * command for stalled control endpoints).
2116 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2117 (trb_comp_code != COMP_STALL &&
2118 trb_comp_code != COMP_BABBLE))
2119 xhci_urb_free_priv(xhci, urb_priv);
2121 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2122 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2124 urb, urb->actual_length, status);
2125 spin_unlock(&xhci->lock);
2126 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2127 spin_lock(&xhci->lock);
2131 * If ep->skip is set, it means there are missed tds on the
2132 * endpoint ring need to take care of.
2133 * Process them as short transfer until reach the td pointed by
2136 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2142 * This function handles all OS-owned events on the event ring. It may drop
2143 * xhci->lock between event processing (e.g. to pass up port status changes).
2145 static void xhci_handle_event(struct xhci_hcd *xhci)
2147 union xhci_trb *event;
2148 int update_ptrs = 1;
2151 xhci_dbg(xhci, "In %s\n", __func__);
2152 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2153 xhci->error_bitmask |= 1 << 1;
2157 event = xhci->event_ring->dequeue;
2158 /* Does the HC or OS own the TRB? */
2159 if ((event->event_cmd.flags & TRB_CYCLE) !=
2160 xhci->event_ring->cycle_state) {
2161 xhci->error_bitmask |= 1 << 2;
2164 xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
2166 /* FIXME: Handle more event types. */
2167 switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
2168 case TRB_TYPE(TRB_COMPLETION):
2169 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
2170 handle_cmd_completion(xhci, &event->event_cmd);
2171 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
2173 case TRB_TYPE(TRB_PORT_STATUS):
2174 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
2175 handle_port_status(xhci, event);
2176 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
2179 case TRB_TYPE(TRB_TRANSFER):
2180 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
2181 ret = handle_tx_event(xhci, &event->trans_event);
2182 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
2184 xhci->error_bitmask |= 1 << 9;
2189 if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48))
2190 handle_vendor_event(xhci, event);
2192 xhci->error_bitmask |= 1 << 3;
2194 /* Any of the above functions may drop and re-acquire the lock, so check
2195 * to make sure a watchdog timer didn't mark the host as non-responsive.
2197 if (xhci->xhc_state & XHCI_STATE_DYING) {
2198 xhci_dbg(xhci, "xHCI host dying, returning from "
2199 "event handler.\n");
2204 /* Update SW event ring dequeue pointer */
2205 inc_deq(xhci, xhci->event_ring, true);
2207 /* Are there more items on the event ring? */
2208 xhci_handle_event(xhci);
2212 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2213 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2214 * indicators of an event TRB error, but we check the status *first* to be safe.
2216 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2218 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2220 union xhci_trb *trb;
2222 union xhci_trb *event_ring_deq;
2225 spin_lock(&xhci->lock);
2226 trb = xhci->event_ring->dequeue;
2227 /* Check if the xHC generated the interrupt, or the irq is shared */
2228 status = xhci_readl(xhci, &xhci->op_regs->status);
2229 if (status == 0xffffffff)
2232 if (!(status & STS_EINT)) {
2233 spin_unlock(&xhci->lock);
2236 xhci_dbg(xhci, "op reg status = %08x\n", status);
2237 xhci_dbg(xhci, "Event ring dequeue ptr:\n");
2238 xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n",
2239 (unsigned long long)
2240 xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
2241 lower_32_bits(trb->link.segment_ptr),
2242 upper_32_bits(trb->link.segment_ptr),
2243 (unsigned int) trb->link.intr_target,
2244 (unsigned int) trb->link.control);
2246 if (status & STS_FATAL) {
2247 xhci_warn(xhci, "WARNING: Host System Error\n");
2250 spin_unlock(&xhci->lock);
2255 * Clear the op reg interrupt status first,
2256 * so we can receive interrupts from other MSI-X interrupters.
2257 * Write 1 to clear the interrupt status.
2260 xhci_writel(xhci, status, &xhci->op_regs->status);
2261 /* FIXME when MSI-X is supported and there are multiple vectors */
2262 /* Clear the MSI-X event interrupt status */
2264 if (hcd->irq != -1) {
2266 /* Acknowledge the PCI interrupt */
2267 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2269 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2272 if (xhci->xhc_state & XHCI_STATE_DYING) {
2273 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2274 "Shouldn't IRQs be disabled?\n");
2275 /* Clear the event handler busy flag (RW1C);
2276 * the event ring should be empty.
2278 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2279 xhci_write_64(xhci, temp_64 | ERST_EHB,
2280 &xhci->ir_set->erst_dequeue);
2281 spin_unlock(&xhci->lock);
2286 event_ring_deq = xhci->event_ring->dequeue;
2287 /* FIXME this should be a delayed service routine
2288 * that clears the EHB.
2290 xhci_handle_event(xhci);
2292 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2293 /* If necessary, update the HW's version of the event ring deq ptr. */
2294 if (event_ring_deq != xhci->event_ring->dequeue) {
2295 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2296 xhci->event_ring->dequeue);
2298 xhci_warn(xhci, "WARN something wrong with SW event "
2299 "ring dequeue ptr.\n");
2300 /* Update HC event ring dequeue pointer */
2301 temp_64 &= ERST_PTR_MASK;
2302 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2305 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2306 temp_64 |= ERST_EHB;
2307 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2309 spin_unlock(&xhci->lock);
2314 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2317 struct xhci_hcd *xhci;
2319 xhci = hcd_to_xhci(hcd);
2320 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2321 if (xhci->shared_hcd)
2322 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2324 ret = xhci_irq(hcd);
2329 /**** Endpoint Ring Operations ****/
2332 * Generic function for queueing a TRB on a ring.
2333 * The caller must have checked to make sure there's room on the ring.
2335 * @more_trbs_coming: Will you enqueue more TRBs before calling
2336 * prepare_transfer()?
2338 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2339 bool consumer, bool more_trbs_coming,
2340 u32 field1, u32 field2, u32 field3, u32 field4)
2342 struct xhci_generic_trb *trb;
2344 trb = &ring->enqueue->generic;
2345 trb->field[0] = field1;
2346 trb->field[1] = field2;
2347 trb->field[2] = field3;
2348 trb->field[3] = field4;
2349 inc_enq(xhci, ring, consumer, more_trbs_coming);
2353 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2354 * FIXME allocate segments if the ring is full.
2356 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2357 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2359 /* Make sure the endpoint has been added to xHC schedule */
2360 xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
2362 case EP_STATE_DISABLED:
2364 * USB core changed config/interfaces without notifying us,
2365 * or hardware is reporting the wrong state.
2367 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2369 case EP_STATE_ERROR:
2370 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2371 /* FIXME event handling code for error needs to clear it */
2372 /* XXX not sure if this should be -ENOENT or not */
2374 case EP_STATE_HALTED:
2375 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2376 case EP_STATE_STOPPED:
2377 case EP_STATE_RUNNING:
2380 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2382 * FIXME issue Configure Endpoint command to try to get the HC
2383 * back into a known state.
2387 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2388 /* FIXME allocate more room */
2389 xhci_err(xhci, "ERROR no room on ep ring\n");
2393 if (enqueue_is_link_trb(ep_ring)) {
2394 struct xhci_ring *ring = ep_ring;
2395 union xhci_trb *next;
2397 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
2398 next = ring->enqueue;
2400 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2402 /* If we're not dealing with 0.95 hardware,
2403 * clear the chain bit.
2405 if (!xhci_link_trb_quirk(xhci))
2406 next->link.control &= ~TRB_CHAIN;
2408 next->link.control |= TRB_CHAIN;
2411 next->link.control ^= (u32) TRB_CYCLE;
2413 /* Toggle the cycle bit after the last ring segment. */
2414 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2415 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2416 if (!in_interrupt()) {
2417 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2418 "state for ring %p = %i\n",
2419 ring, (unsigned int)ring->cycle_state);
2422 ring->enq_seg = ring->enq_seg->next;
2423 ring->enqueue = ring->enq_seg->trbs;
2424 next = ring->enqueue;
2431 static int prepare_transfer(struct xhci_hcd *xhci,
2432 struct xhci_virt_device *xdev,
2433 unsigned int ep_index,
2434 unsigned int stream_id,
2435 unsigned int num_trbs,
2437 unsigned int td_index,
2441 struct urb_priv *urb_priv;
2443 struct xhci_ring *ep_ring;
2444 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2446 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2448 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2453 ret = prepare_ring(xhci, ep_ring,
2454 ep_ctx->ep_info & EP_STATE_MASK,
2455 num_trbs, mem_flags);
2459 urb_priv = urb->hcpriv;
2460 td = urb_priv->td[td_index];
2462 INIT_LIST_HEAD(&td->td_list);
2463 INIT_LIST_HEAD(&td->cancelled_td_list);
2465 if (td_index == 0) {
2466 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2467 if (unlikely(ret)) {
2468 xhci_urb_free_priv(xhci, urb_priv);
2475 /* Add this TD to the tail of the endpoint ring's TD list */
2476 list_add_tail(&td->td_list, &ep_ring->td_list);
2477 td->start_seg = ep_ring->enq_seg;
2478 td->first_trb = ep_ring->enqueue;
2480 urb_priv->td[td_index] = td;
2485 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2487 int num_sgs, num_trbs, running_total, temp, i;
2488 struct scatterlist *sg;
2491 num_sgs = urb->num_sgs;
2492 temp = urb->transfer_buffer_length;
2494 xhci_dbg(xhci, "count sg list trbs: \n");
2496 for_each_sg(urb->sg, sg, num_sgs, i) {
2497 unsigned int previous_total_trbs = num_trbs;
2498 unsigned int len = sg_dma_len(sg);
2500 /* Scatter gather list entries may cross 64KB boundaries */
2501 running_total = TRB_MAX_BUFF_SIZE -
2502 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2503 running_total &= TRB_MAX_BUFF_SIZE - 1;
2504 if (running_total != 0)
2507 /* How many more 64KB chunks to transfer, how many more TRBs? */
2508 while (running_total < sg_dma_len(sg) && running_total < temp) {
2510 running_total += TRB_MAX_BUFF_SIZE;
2512 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2513 i, (unsigned long long)sg_dma_address(sg),
2514 len, len, num_trbs - previous_total_trbs);
2516 len = min_t(int, len, temp);
2521 xhci_dbg(xhci, "\n");
2522 if (!in_interrupt())
2523 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2525 urb->ep->desc.bEndpointAddress,
2526 urb->transfer_buffer_length,
2531 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2534 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2535 "TRBs, %d left\n", __func__,
2536 urb->ep->desc.bEndpointAddress, num_trbs);
2537 if (running_total != urb->transfer_buffer_length)
2538 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2539 "queued %#x (%d), asked for %#x (%d)\n",
2541 urb->ep->desc.bEndpointAddress,
2542 running_total, running_total,
2543 urb->transfer_buffer_length,
2544 urb->transfer_buffer_length);
2547 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2548 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2549 struct xhci_generic_trb *start_trb)
2552 * Pass all the TRBs to the hardware at once and make sure this write
2557 start_trb->field[3] |= start_cycle;
2559 start_trb->field[3] &= ~0x1;
2560 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2564 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2565 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2566 * (comprised of sg list entries) can take several service intervals to
2569 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2570 struct urb *urb, int slot_id, unsigned int ep_index)
2572 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2573 xhci->devs[slot_id]->out_ctx, ep_index);
2577 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2578 ep_interval = urb->interval;
2579 /* Convert to microframes */
2580 if (urb->dev->speed == USB_SPEED_LOW ||
2581 urb->dev->speed == USB_SPEED_FULL)
2583 /* FIXME change this to a warning and a suggestion to use the new API
2584 * to set the polling interval (once the API is added).
2586 if (xhci_interval != ep_interval) {
2587 if (printk_ratelimit())
2588 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2589 " (%d microframe%s) than xHCI "
2590 "(%d microframe%s)\n",
2592 ep_interval == 1 ? "" : "s",
2594 xhci_interval == 1 ? "" : "s");
2595 urb->interval = xhci_interval;
2596 /* Convert back to frames for LS/FS devices */
2597 if (urb->dev->speed == USB_SPEED_LOW ||
2598 urb->dev->speed == USB_SPEED_FULL)
2601 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2605 * The TD size is the number of bytes remaining in the TD (including this TRB),
2606 * right shifted by 10.
2607 * It must fit in bits 21:17, so it can't be bigger than 31.
2609 static u32 xhci_td_remainder(unsigned int remainder)
2611 u32 max = (1 << (21 - 17 + 1)) - 1;
2613 if ((remainder >> 10) >= max)
2616 return (remainder >> 10) << 17;
2619 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2620 struct urb *urb, int slot_id, unsigned int ep_index)
2622 struct xhci_ring *ep_ring;
2623 unsigned int num_trbs;
2624 struct urb_priv *urb_priv;
2626 struct scatterlist *sg;
2628 int trb_buff_len, this_sg_len, running_total;
2631 bool more_trbs_coming;
2633 struct xhci_generic_trb *start_trb;
2636 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2640 num_trbs = count_sg_trbs_needed(xhci, urb);
2641 num_sgs = urb->num_sgs;
2643 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2644 ep_index, urb->stream_id,
2645 num_trbs, urb, 0, mem_flags);
2646 if (trb_buff_len < 0)
2647 return trb_buff_len;
2649 urb_priv = urb->hcpriv;
2650 td = urb_priv->td[0];
2653 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2654 * until we've finished creating all the other TRBs. The ring's cycle
2655 * state may change as we enqueue the other TRBs, so save it too.
2657 start_trb = &ep_ring->enqueue->generic;
2658 start_cycle = ep_ring->cycle_state;
2662 * How much data is in the first TRB?
2664 * There are three forces at work for TRB buffer pointers and lengths:
2665 * 1. We don't want to walk off the end of this sg-list entry buffer.
2666 * 2. The transfer length that the driver requested may be smaller than
2667 * the amount of memory allocated for this scatter-gather list.
2668 * 3. TRBs buffers can't cross 64KB boundaries.
2671 addr = (u64) sg_dma_address(sg);
2672 this_sg_len = sg_dma_len(sg);
2673 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2674 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2675 if (trb_buff_len > urb->transfer_buffer_length)
2676 trb_buff_len = urb->transfer_buffer_length;
2677 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2681 /* Queue the first TRB, even if it's zero-length */
2684 u32 length_field = 0;
2687 /* Don't change the cycle bit of the first TRB until later */
2690 if (start_cycle == 0)
2693 field |= ep_ring->cycle_state;
2695 /* Chain all the TRBs together; clear the chain bit in the last
2696 * TRB to indicate it's the last TRB in the chain.
2701 /* FIXME - add check for ZERO_PACKET flag before this */
2702 td->last_trb = ep_ring->enqueue;
2705 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2706 "64KB boundary at %#x, end dma = %#x\n",
2707 (unsigned int) addr, trb_buff_len, trb_buff_len,
2708 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2709 (unsigned int) addr + trb_buff_len);
2710 if (TRB_MAX_BUFF_SIZE -
2711 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2712 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2713 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2714 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2715 (unsigned int) addr + trb_buff_len);
2717 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2719 length_field = TRB_LEN(trb_buff_len) |
2723 more_trbs_coming = true;
2725 more_trbs_coming = false;
2726 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2727 lower_32_bits(addr),
2728 upper_32_bits(addr),
2730 /* We always want to know if the TRB was short,
2731 * or we won't get an event when it completes.
2732 * (Unless we use event data TRBs, which are a
2733 * waste of space and HC resources.)
2735 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2737 running_total += trb_buff_len;
2739 /* Calculate length for next transfer --
2740 * Are we done queueing all the TRBs for this sg entry?
2742 this_sg_len -= trb_buff_len;
2743 if (this_sg_len == 0) {
2748 addr = (u64) sg_dma_address(sg);
2749 this_sg_len = sg_dma_len(sg);
2751 addr += trb_buff_len;
2754 trb_buff_len = TRB_MAX_BUFF_SIZE -
2755 (addr & (TRB_MAX_BUFF_SIZE - 1));
2756 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2757 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2759 urb->transfer_buffer_length - running_total;
2760 } while (running_total < urb->transfer_buffer_length);
2762 check_trb_math(urb, num_trbs, running_total);
2763 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2764 start_cycle, start_trb);
2768 /* This is very similar to what ehci-q.c qtd_fill() does */
2769 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2770 struct urb *urb, int slot_id, unsigned int ep_index)
2772 struct xhci_ring *ep_ring;
2773 struct urb_priv *urb_priv;
2776 struct xhci_generic_trb *start_trb;
2778 bool more_trbs_coming;
2780 u32 field, length_field;
2782 int running_total, trb_buff_len, ret;
2786 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2788 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2793 /* How much data is (potentially) left before the 64KB boundary? */
2794 running_total = TRB_MAX_BUFF_SIZE -
2795 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2796 running_total &= TRB_MAX_BUFF_SIZE - 1;
2798 /* If there's some data on this 64KB chunk, or we have to send a
2799 * zero-length transfer, we need at least one TRB
2801 if (running_total != 0 || urb->transfer_buffer_length == 0)
2803 /* How many more 64KB chunks to transfer, how many more TRBs? */
2804 while (running_total < urb->transfer_buffer_length) {
2806 running_total += TRB_MAX_BUFF_SIZE;
2808 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2810 if (!in_interrupt())
2811 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2812 "addr = %#llx, num_trbs = %d\n",
2813 urb->ep->desc.bEndpointAddress,
2814 urb->transfer_buffer_length,
2815 urb->transfer_buffer_length,
2816 (unsigned long long)urb->transfer_dma,
2819 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2820 ep_index, urb->stream_id,
2821 num_trbs, urb, 0, mem_flags);
2825 urb_priv = urb->hcpriv;
2826 td = urb_priv->td[0];
2829 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2830 * until we've finished creating all the other TRBs. The ring's cycle
2831 * state may change as we enqueue the other TRBs, so save it too.
2833 start_trb = &ep_ring->enqueue->generic;
2834 start_cycle = ep_ring->cycle_state;
2837 /* How much data is in the first TRB? */
2838 addr = (u64) urb->transfer_dma;
2839 trb_buff_len = TRB_MAX_BUFF_SIZE -
2840 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2841 if (trb_buff_len > urb->transfer_buffer_length)
2842 trb_buff_len = urb->transfer_buffer_length;
2846 /* Queue the first TRB, even if it's zero-length */
2851 /* Don't change the cycle bit of the first TRB until later */
2854 if (start_cycle == 0)
2857 field |= ep_ring->cycle_state;
2859 /* Chain all the TRBs together; clear the chain bit in the last
2860 * TRB to indicate it's the last TRB in the chain.
2865 /* FIXME - add check for ZERO_PACKET flag before this */
2866 td->last_trb = ep_ring->enqueue;
2869 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2871 length_field = TRB_LEN(trb_buff_len) |
2875 more_trbs_coming = true;
2877 more_trbs_coming = false;
2878 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2879 lower_32_bits(addr),
2880 upper_32_bits(addr),
2882 /* We always want to know if the TRB was short,
2883 * or we won't get an event when it completes.
2884 * (Unless we use event data TRBs, which are a
2885 * waste of space and HC resources.)
2887 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2889 running_total += trb_buff_len;
2891 /* Calculate length for next transfer */
2892 addr += trb_buff_len;
2893 trb_buff_len = urb->transfer_buffer_length - running_total;
2894 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2895 trb_buff_len = TRB_MAX_BUFF_SIZE;
2896 } while (running_total < urb->transfer_buffer_length);
2898 check_trb_math(urb, num_trbs, running_total);
2899 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2900 start_cycle, start_trb);
2904 /* Caller must have locked xhci->lock */
2905 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2906 struct urb *urb, int slot_id, unsigned int ep_index)
2908 struct xhci_ring *ep_ring;
2911 struct usb_ctrlrequest *setup;
2912 struct xhci_generic_trb *start_trb;
2914 u32 field, length_field;
2915 struct urb_priv *urb_priv;
2918 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2923 * Need to copy setup packet into setup TRB, so we can't use the setup
2926 if (!urb->setup_packet)
2929 if (!in_interrupt())
2930 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2932 /* 1 TRB for setup, 1 for status */
2935 * Don't need to check if we need additional event data and normal TRBs,
2936 * since data in control transfers will never get bigger than 16MB
2937 * XXX: can we get a buffer that crosses 64KB boundaries?
2939 if (urb->transfer_buffer_length > 0)
2941 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2942 ep_index, urb->stream_id,
2943 num_trbs, urb, 0, mem_flags);
2947 urb_priv = urb->hcpriv;
2948 td = urb_priv->td[0];
2951 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2952 * until we've finished creating all the other TRBs. The ring's cycle
2953 * state may change as we enqueue the other TRBs, so save it too.
2955 start_trb = &ep_ring->enqueue->generic;
2956 start_cycle = ep_ring->cycle_state;
2958 /* Queue setup TRB - see section 6.4.1.2.1 */
2959 /* FIXME better way to translate setup_packet into two u32 fields? */
2960 setup = (struct usb_ctrlrequest *) urb->setup_packet;
2962 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
2963 if (start_cycle == 0)
2965 queue_trb(xhci, ep_ring, false, true,
2966 /* FIXME endianness is probably going to bite my ass here. */
2967 setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2968 setup->wIndex | setup->wLength << 16,
2969 TRB_LEN(8) | TRB_INTR_TARGET(0),
2970 /* Immediate data in pointer */
2973 /* If there's data, queue data TRBs */
2975 length_field = TRB_LEN(urb->transfer_buffer_length) |
2976 xhci_td_remainder(urb->transfer_buffer_length) |
2978 if (urb->transfer_buffer_length > 0) {
2979 if (setup->bRequestType & USB_DIR_IN)
2980 field |= TRB_DIR_IN;
2981 queue_trb(xhci, ep_ring, false, true,
2982 lower_32_bits(urb->transfer_dma),
2983 upper_32_bits(urb->transfer_dma),
2985 /* Event on short tx */
2986 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2989 /* Save the DMA address of the last TRB in the TD */
2990 td->last_trb = ep_ring->enqueue;
2992 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2993 /* If the device sent data, the status stage is an OUT transfer */
2994 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2998 queue_trb(xhci, ep_ring, false, false,
3002 /* Event on completion */
3003 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3005 giveback_first_trb(xhci, slot_id, ep_index, 0,
3006 start_cycle, start_trb);
3010 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3011 struct urb *urb, int i)
3014 u64 addr, td_len, running_total;
3016 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3017 td_len = urb->iso_frame_desc[i].length;
3019 running_total = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3020 running_total &= TRB_MAX_BUFF_SIZE - 1;
3021 if (running_total != 0)
3024 while (running_total < td_len) {
3026 running_total += TRB_MAX_BUFF_SIZE;
3032 /* This is for isoc transfer */
3033 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3034 struct urb *urb, int slot_id, unsigned int ep_index)
3036 struct xhci_ring *ep_ring;
3037 struct urb_priv *urb_priv;
3039 int num_tds, trbs_per_td;
3040 struct xhci_generic_trb *start_trb;
3043 u32 field, length_field;
3044 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3045 u64 start_addr, addr;
3047 bool more_trbs_coming;
3049 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3051 num_tds = urb->number_of_packets;
3053 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3057 if (!in_interrupt())
3058 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3059 " addr = %#llx, num_tds = %d\n",
3060 urb->ep->desc.bEndpointAddress,
3061 urb->transfer_buffer_length,
3062 urb->transfer_buffer_length,
3063 (unsigned long long)urb->transfer_dma,
3066 start_addr = (u64) urb->transfer_dma;
3067 start_trb = &ep_ring->enqueue->generic;
3068 start_cycle = ep_ring->cycle_state;
3070 /* Queue the first TRB, even if it's zero-length */
3071 for (i = 0; i < num_tds; i++) {
3075 addr = start_addr + urb->iso_frame_desc[i].offset;
3076 td_len = urb->iso_frame_desc[i].length;
3077 td_remain_len = td_len;
3079 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3081 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3082 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3086 urb_priv = urb->hcpriv;
3087 td = urb_priv->td[i];
3089 for (j = 0; j < trbs_per_td; j++) {
3094 /* Queue the isoc TRB */
3095 field |= TRB_TYPE(TRB_ISOC);
3096 /* Assume URB_ISO_ASAP is set */
3099 if (start_cycle == 0)
3102 field |= ep_ring->cycle_state;
3105 /* Queue other normal TRBs */
3106 field |= TRB_TYPE(TRB_NORMAL);
3107 field |= ep_ring->cycle_state;
3110 /* Chain all the TRBs together; clear the chain bit in
3111 * the last TRB to indicate it's the last TRB in the
3114 if (j < trbs_per_td - 1) {
3116 more_trbs_coming = true;
3118 td->last_trb = ep_ring->enqueue;
3120 more_trbs_coming = false;
3123 /* Calculate TRB length */
3124 trb_buff_len = TRB_MAX_BUFF_SIZE -
3125 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3126 if (trb_buff_len > td_remain_len)
3127 trb_buff_len = td_remain_len;
3129 remainder = xhci_td_remainder(td_len - running_total);
3130 length_field = TRB_LEN(trb_buff_len) |
3133 queue_trb(xhci, ep_ring, false, more_trbs_coming,
3134 lower_32_bits(addr),
3135 upper_32_bits(addr),
3137 /* We always want to know if the TRB was short,
3138 * or we won't get an event when it completes.
3139 * (Unless we use event data TRBs, which are a
3140 * waste of space and HC resources.)
3143 running_total += trb_buff_len;
3145 addr += trb_buff_len;
3146 td_remain_len -= trb_buff_len;
3149 /* Check TD length */
3150 if (running_total != td_len) {
3151 xhci_err(xhci, "ISOC TD length unmatch\n");
3156 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3157 start_cycle, start_trb);
3162 * Check transfer ring to guarantee there is enough room for the urb.
3163 * Update ISO URB start_frame and interval.
3164 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3165 * update the urb->start_frame by now.
3166 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3168 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3169 struct urb *urb, int slot_id, unsigned int ep_index)
3171 struct xhci_virt_device *xdev;
3172 struct xhci_ring *ep_ring;
3173 struct xhci_ep_ctx *ep_ctx;
3177 int num_tds, num_trbs, i;
3180 xdev = xhci->devs[slot_id];
3181 ep_ring = xdev->eps[ep_index].ring;
3182 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3185 num_tds = urb->number_of_packets;
3186 for (i = 0; i < num_tds; i++)
3187 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3189 /* Check the ring to guarantee there is enough room for the whole urb.
3190 * Do not insert any td of the urb to the ring if the check failed.
3192 ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK,
3193 num_trbs, mem_flags);
3197 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3198 start_frame &= 0x3fff;
3200 urb->start_frame = start_frame;
3201 if (urb->dev->speed == USB_SPEED_LOW ||
3202 urb->dev->speed == USB_SPEED_FULL)
3203 urb->start_frame >>= 3;
3205 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
3206 ep_interval = urb->interval;
3207 /* Convert to microframes */
3208 if (urb->dev->speed == USB_SPEED_LOW ||
3209 urb->dev->speed == USB_SPEED_FULL)
3211 /* FIXME change this to a warning and a suggestion to use the new API
3212 * to set the polling interval (once the API is added).
3214 if (xhci_interval != ep_interval) {
3215 if (printk_ratelimit())
3216 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3217 " (%d microframe%s) than xHCI "
3218 "(%d microframe%s)\n",
3220 ep_interval == 1 ? "" : "s",
3222 xhci_interval == 1 ? "" : "s");
3223 urb->interval = xhci_interval;
3224 /* Convert back to frames for LS/FS devices */
3225 if (urb->dev->speed == USB_SPEED_LOW ||
3226 urb->dev->speed == USB_SPEED_FULL)
3229 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3232 /**** Command Ring Operations ****/
3234 /* Generic function for queueing a command TRB on the command ring.
3235 * Check to make sure there's room on the command ring for one command TRB.
3236 * Also check that there's room reserved for commands that must not fail.
3237 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3238 * then only check for the number of reserved spots.
3239 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3240 * because the command event handler may want to resubmit a failed command.
3242 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3243 u32 field3, u32 field4, bool command_must_succeed)
3245 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3248 if (!command_must_succeed)
3251 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3252 reserved_trbs, GFP_ATOMIC);
3254 xhci_err(xhci, "ERR: No room for command on command ring\n");
3255 if (command_must_succeed)
3256 xhci_err(xhci, "ERR: Reserved TRB counting for "
3257 "unfailable commands failed.\n");
3260 queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3261 field4 | xhci->cmd_ring->cycle_state);
3265 /* Queue a slot enable or disable request on the command ring */
3266 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3268 return queue_command(xhci, 0, 0, 0,
3269 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3272 /* Queue an address device command TRB */
3273 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3276 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3277 upper_32_bits(in_ctx_ptr), 0,
3278 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3282 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3283 u32 field1, u32 field2, u32 field3, u32 field4)
3285 return queue_command(xhci, field1, field2, field3, field4, false);
3288 /* Queue a reset device command TRB */
3289 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3291 return queue_command(xhci, 0, 0, 0,
3292 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3296 /* Queue a configure endpoint command TRB */
3297 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3298 u32 slot_id, bool command_must_succeed)
3300 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3301 upper_32_bits(in_ctx_ptr), 0,
3302 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3303 command_must_succeed);
3306 /* Queue an evaluate context command TRB */
3307 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3310 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3311 upper_32_bits(in_ctx_ptr), 0,
3312 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3317 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3318 * activity on an endpoint that is about to be suspended.
3320 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3321 unsigned int ep_index, int suspend)
3323 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3324 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3325 u32 type = TRB_TYPE(TRB_STOP_RING);
3326 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3328 return queue_command(xhci, 0, 0, 0,
3329 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3332 /* Set Transfer Ring Dequeue Pointer command.
3333 * This should not be used for endpoints that have streams enabled.
3335 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3336 unsigned int ep_index, unsigned int stream_id,
3337 struct xhci_segment *deq_seg,
3338 union xhci_trb *deq_ptr, u32 cycle_state)
3341 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3342 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3343 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3344 u32 type = TRB_TYPE(TRB_SET_DEQ);
3345 struct xhci_virt_ep *ep;
3347 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3349 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3350 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3354 ep = &xhci->devs[slot_id]->eps[ep_index];
3355 if ((ep->ep_state & SET_DEQ_PENDING)) {
3356 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3357 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3360 ep->queued_deq_seg = deq_seg;
3361 ep->queued_deq_ptr = deq_ptr;
3362 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3363 upper_32_bits(addr), trb_stream_id,
3364 trb_slot_id | trb_ep_index | type, false);
3367 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3368 unsigned int ep_index)
3370 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3371 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3372 u32 type = TRB_TYPE(TRB_RESET_EP);
3374 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,