drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         unsigned long long addr;
 149
 150         ring->deq_updates++;
 151
 152         do {
 153                 /*
 154                  * Update the dequeue pointer further if that was a link TRB or
 155                  * we're at the end of an event ring segment (which doesn't have
 156                  * link TRBS)
 157                  */
 158                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 159                         if (consumer && last_trb_on_last_seg(xhci, ring,
 160                                                 ring->deq_seg, ring->dequeue)) {
 161                                 if (!in_interrupt())
 162                                         xhci_dbg(xhci, "Toggle cycle state "
 163                                                         "for ring %p = %i\n",
 164                                                         ring,
 165                                                         (unsigned int)
 166                                                         ring->cycle_state);
 167                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 168                         }
 169                         ring->deq_seg = ring->deq_seg->next;
 170                         ring->dequeue = ring->deq_seg->trbs;
 171                 } else {
 172                         ring->dequeue++;
 173                 }
 174         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 175
 176         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 177 }
 178
 179 /*
 180  * See Cycle bit rules. SW is the consumer for the event ring only.
 181  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 182  *
 183  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 184  * chain bit is set), then set the chain bit in all the following link TRBs.
 185  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 186  * have their chain bit cleared (so that each Link TRB is a separate TD).
 187  *
 188  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 189  * set, but other sections talk about dealing with the chain bit set.  This was
 190  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 191  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 192  *
 193  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 194  *                      prepare_transfer()?
 195  */
 196 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 197                 bool consumer, bool more_trbs_coming, bool isoc)
 198 {
 199         u32 chain;
 200         union xhci_trb *next;
 201         unsigned long long addr;
 202
 203         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 204         next = ++(ring->enqueue);
 205
 206         ring->enq_updates++;
 207         /* Update the dequeue pointer further if that was a link TRB or we're at
 208          * the end of an event ring segment (which doesn't have link TRBS)
 209          */
 210         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 211                 if (!consumer) {
 212                         if (ring != xhci->event_ring) {
 213                                 /*
 214                                  * If the caller doesn't plan on enqueueing more
 215                                  * TDs before ringing the doorbell, then we
 216                                  * don't want to give the link TRB to the
 217                                  * hardware just yet.  We'll give the link TRB
 218                                  * back in prepare_ring() just before we enqueue
 219                                  * the TD at the top of the ring.
 220                                  */
 221                                 if (!chain && !more_trbs_coming)
 222                                         break;
 223
 224                                 /* If we're not dealing with 0.95 hardware or
 225                                  * isoc rings on AMD 0.96 host,
 226                                  * carry over the chain bit of the previous TRB
 227                                  * (which may mean the chain bit is cleared).
 228                                  */
 229                                 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
 230                                                 && !xhci_link_trb_quirk(xhci)) {
 231                                         next->link.control &=
 232                                                 cpu_to_le32(~TRB_CHAIN);
 233                                         next->link.control |=
 234                                                 cpu_to_le32(chain);
 235                                 }
 236                                 /* Give this link TRB to the hardware */
 237                                 wmb();
 238                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 239                         }
 240                         /* Toggle the cycle bit after the last ring segment. */
 241                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 242                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 243                                 if (!in_interrupt())
 244                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 245                                                         ring,
 246                                                         (unsigned int) ring->cycle_state);
 247                         }
 248                 }
 249                 ring->enq_seg = ring->enq_seg->next;
 250                 ring->enqueue = ring->enq_seg->trbs;
 251                 next = ring->enqueue;
 252         }
 253         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 254 }
 255
 256 /*
 257  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 258  * above.
 259  * FIXME: this would be simpler and faster if we just kept track of the number
 260  * of free TRBs in a ring.
 261  */
 262 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 263                 unsigned int num_trbs)
 264 {
 265         int i;
 266         union xhci_trb *enq = ring->enqueue;
 267         struct xhci_segment *enq_seg = ring->enq_seg;
 268         struct xhci_segment *cur_seg;
 269         unsigned int left_on_ring;
 270
 271         /* If we are currently pointing to a link TRB, advance the
 272          * enqueue pointer before checking for space */
 273         while (last_trb(xhci, ring, enq_seg, enq)) {
 274                 enq_seg = enq_seg->next;
 275                 enq = enq_seg->trbs;
 276         }
 277
 278         /* Check if ring is empty */
 279         if (enq == ring->dequeue) {
 280                 /* Can't use link trbs */
 281                 left_on_ring = TRBS_PER_SEGMENT - 1;
 282                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 283                                 cur_seg = cur_seg->next)
 284                         left_on_ring += TRBS_PER_SEGMENT - 1;
 285
 286                 /* Always need one TRB free in the ring. */
 287                 left_on_ring -= 1;
 288                 if (num_trbs > left_on_ring) {
 289                         xhci_warn(xhci, "Not enough room on ring; "
 290                                         "need %u TRBs, %u TRBs left\n",
 291                                         num_trbs, left_on_ring);
 292                         return 0;
 293                 }
 294                 return 1;
 295         }
 296         /* Make sure there's an extra empty TRB available */
 297         for (i = 0; i <= num_trbs; ++i) {
 298                 if (enq == ring->dequeue)
 299                         return 0;
 300                 enq++;
 301                 while (last_trb(xhci, ring, enq_seg, enq)) {
 302                         enq_seg = enq_seg->next;
 303                         enq = enq_seg->trbs;
 304                 }
 305         }
 306         return 1;
 307 }
 308
 309 /* Ring the host controller doorbell after placing a command on the ring */
 310 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 311 {
 312         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 313                 return;
 314
 315         xhci_dbg(xhci, "// Ding dong!\n");
 316         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 317         /* Flush PCI posted writes */
 318         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 319 }
 320
 321 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 322                 unsigned int slot_id,
 323                 unsigned int ep_index,
 324                 unsigned int stream_id)
 325 {
 326         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 327         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 328         unsigned int ep_state = ep->ep_state;
 329
 330         /* Don't ring the doorbell for this endpoint if there are pending
 331          * cancellations because we don't want to interrupt processing.
 332          * We don't want to restart any stream rings if there's a set dequeue
 333          * pointer command pending because the device can choose to start any
 334          * stream once the endpoint is on the HW schedule.
 335          * FIXME - check all the stream rings for pending cancellations.
 336          */
 337         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 338             (ep_state & EP_HALTED))
 339                 return;
 340         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 341         /* The CPU has better things to do at this point than wait for a
 342          * write-posting flush.  It'll get there soon enough.
 343          */
 344 }
 345
 346 /* Ring the doorbell for any rings with pending URBs */
 347 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 348                 unsigned int slot_id,
 349                 unsigned int ep_index)
 350 {
 351         unsigned int stream_id;
 352         struct xhci_virt_ep *ep;
 353
 354         ep = &xhci->devs[slot_id]->eps[ep_index];
 355
 356         /* A ring has pending URBs if its TD list is not empty */
 357         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 358                 if (!(list_empty(&ep->ring->td_list)))
 359                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 360                 return;
 361         }
 362
 363         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 364                         stream_id++) {
 365                 struct xhci_stream_info *stream_info = ep->stream_info;
 366                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 367                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 368                                                 stream_id);
 369         }
 370 }
 371
 372 /*
 373  * Find the segment that trb is in.  Start searching in start_seg.
 374  * If we must move past a segment that has a link TRB with a toggle cycle state
 375  * bit set, then we will toggle the value pointed at by cycle_state.
 376  */
 377 static struct xhci_segment *find_trb_seg(
 378                 struct xhci_segment *start_seg,
 379                 union xhci_trb  *trb, int *cycle_state)
 380 {
 381         struct xhci_segment *cur_seg = start_seg;
 382         struct xhci_generic_trb *generic_trb;
 383
 384         while (cur_seg->trbs > trb ||
 385                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 386                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 387                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 388                         *cycle_state ^= 0x1;
 389                 cur_seg = cur_seg->next;
 390                 if (cur_seg == start_seg)
 391                         /* Looped over the entire list.  Oops! */
 392                         return NULL;
 393         }
 394         return cur_seg;
 395 }
 396
 397
 398 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 399                 unsigned int slot_id, unsigned int ep_index,
 400                 unsigned int stream_id)
 401 {
 402         struct xhci_virt_ep *ep;
 403
 404         ep = &xhci->devs[slot_id]->eps[ep_index];
 405         /* Common case: no streams */
 406         if (!(ep->ep_state & EP_HAS_STREAMS))
 407                 return ep->ring;
 408
 409         if (stream_id == 0) {
 410                 xhci_warn(xhci,
 411                                 "WARN: Slot ID %u, ep index %u has streams, "
 412                                 "but URB has no stream ID.\n",
 413                                 slot_id, ep_index);
 414                 return NULL;
 415         }
 416
 417         if (stream_id < ep->stream_info->num_streams)
 418                 return ep->stream_info->stream_rings[stream_id];
 419
 420         xhci_warn(xhci,
 421                         "WARN: Slot ID %u, ep index %u has "
 422                         "stream IDs 1 to %u allocated, "
 423                         "but stream ID %u is requested.\n",
 424                         slot_id, ep_index,
 425                         ep->stream_info->num_streams - 1,
 426                         stream_id);
 427         return NULL;
 428 }
 429
 430 /* Get the right ring for the given URB.
 431  * If the endpoint supports streams, boundary check the URB's stream ID.
 432  * If the endpoint doesn't support streams, return the singular endpoint ring.
 433  */
 434 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 435                 struct urb *urb)
 436 {
 437         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 438                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 439 }
 440
 441 /*
 442  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 443  * Record the new state of the xHC's endpoint ring dequeue segment,
 444  * dequeue pointer, and new consumer cycle state in state.
 445  * Update our internal representation of the ring's dequeue pointer.
 446  *
 447  * We do this in three jumps:
 448  *  - First we update our new ring state to be the same as when the xHC stopped.
 449  *  - Then we traverse the ring to find the segment that contains
 450  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 451  *    any link TRBs with the toggle cycle bit set.
 452  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 453  *    if we've moved it past a link TRB with the toggle cycle bit set.
 454  *
 455  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 456  * with correct __le32 accesses they should work fine.  Only users of this are
 457  * in here.
 458  */
 459 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 460                 unsigned int slot_id, unsigned int ep_index,
 461                 unsigned int stream_id, struct xhci_td *cur_td,
 462                 struct xhci_dequeue_state *state)
 463 {
 464         struct xhci_virt_device *dev = xhci->devs[slot_id];
 465         struct xhci_ring *ep_ring;
 466         struct xhci_generic_trb *trb;
 467         struct xhci_ep_ctx *ep_ctx;
 468         dma_addr_t addr;
 469
 470         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 471                         ep_index, stream_id);
 472         if (!ep_ring) {
 473                 xhci_warn(xhci, "WARN can't find new dequeue state "
 474                                 "for invalid stream ID %u.\n",
 475                                 stream_id);
 476                 return;
 477         }
 478         state->new_cycle_state = 0;
 479         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 480         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 481                         dev->eps[ep_index].stopped_trb,
 482                         &state->new_cycle_state);
 483         if (!state->new_deq_seg) {
 484                 WARN_ON(1);
 485                 return;
 486         }
 487
 488         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 489         xhci_dbg(xhci, "Finding endpoint context\n");
 490         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 491         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 492
 493         state->new_deq_ptr = cur_td->last_trb;
 494         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 495         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 496                         state->new_deq_ptr,
 497                         &state->new_cycle_state);
 498         if (!state->new_deq_seg) {
 499                 WARN_ON(1);
 500                 return;
 501         }
 502
 503         trb = &state->new_deq_ptr->generic;
 504         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 505             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 506                 state->new_cycle_state ^= 0x1;
 507         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 508
 509         /*
 510          * If there is only one segment in a ring, find_trb_seg()'s while loop
 511          * will not run, and it will return before it has a chance to see if it
 512          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 513          * ended just before the link TRB on a one-segment ring, or if the TD
 514          * wrapped around the top of the ring, because it doesn't have the TD in
 515          * question.  Look for the one-segment case where stalled TRB's address
 516          * is greater than the new dequeue pointer address.
 517          */
 518         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 519                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 520                 state->new_cycle_state ^= 0x1;
 521         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 522
 523         /* Don't update the ring cycle state for the producer (us). */
 524         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 525                         state->new_deq_seg);
 526         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 527         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 528                         (unsigned long long) addr);
 529 }
 530
 531 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 532  * (The last TRB actually points to the ring enqueue pointer, which is not part
 533  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 534  */
 535 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 536                 struct xhci_td *cur_td, bool flip_cycle)
 537 {
 538         struct xhci_segment *cur_seg;
 539         union xhci_trb *cur_trb;
 540
 541         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 542                         true;
 543                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 544                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 545                         /* Unchain any chained Link TRBs, but
 546                          * leave the pointers intact.
 547                          */
 548                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 549                         /* Flip the cycle bit (link TRBs can't be the first
 550                          * or last TRB).
 551                          */
 552                         if (flip_cycle)
 553                                 cur_trb->generic.field[3] ^=
 554                                         cpu_to_le32(TRB_CYCLE);
 555                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 556                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 557                                         "in seg %p (0x%llx dma)\n",
 558                                         cur_trb,
 559                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 560                                         cur_seg,
 561                                         (unsigned long long)cur_seg->dma);
 562                 } else {
 563                         cur_trb->generic.field[0] = 0;
 564                         cur_trb->generic.field[1] = 0;
 565                         cur_trb->generic.field[2] = 0;
 566                         /* Preserve only the cycle bit of this TRB */
 567                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 568                         /* Flip the cycle bit except on the first or last TRB */
 569                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 570                                         cur_trb != cur_td->last_trb)
 571                                 cur_trb->generic.field[3] ^=
 572                                         cpu_to_le32(TRB_CYCLE);
 573                         cur_trb->generic.field[3] |= cpu_to_le32(
 574                                 TRB_TYPE(TRB_TR_NOOP));
 575                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 576                                         "in seg %p (0x%llx dma)\n",
 577                                         cur_trb,
 578                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 579                                         cur_seg,
 580                                         (unsigned long long)cur_seg->dma);
 581                 }
 582                 if (cur_trb == cur_td->last_trb)
 583                         break;
 584         }
 585 }
 586
 587 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 588                 unsigned int ep_index, unsigned int stream_id,
 589                 struct xhci_segment *deq_seg,
 590                 union xhci_trb *deq_ptr, u32 cycle_state);
 591
 592 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 593                 unsigned int slot_id, unsigned int ep_index,
 594                 unsigned int stream_id,
 595                 struct xhci_dequeue_state *deq_state)
 596 {
 597         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 598
 599         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 600                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 601                         deq_state->new_deq_seg,
 602                         (unsigned long long)deq_state->new_deq_seg->dma,
 603                         deq_state->new_deq_ptr,
 604                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 605                         deq_state->new_cycle_state);
 606         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 607                         deq_state->new_deq_seg,
 608                         deq_state->new_deq_ptr,
 609                         (u32) deq_state->new_cycle_state);
 610         /* Stop the TD queueing code from ringing the doorbell until
 611          * this command completes.  The HC won't set the dequeue pointer
 612          * if the ring is running, and ringing the doorbell starts the
 613          * ring running.
 614          */
 615         ep->ep_state |= SET_DEQ_PENDING;
 616 }
 617
 618 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 619                 struct xhci_virt_ep *ep)
 620 {
 621         ep->ep_state &= ~EP_HALT_PENDING;
 622         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 623          * timer is running on another CPU, we don't decrement stop_cmds_pending
 624          * (since we didn't successfully stop the watchdog timer).
 625          */
 626         if (del_timer(&ep->stop_cmd_timer))
 627                 ep->stop_cmds_pending--;
 628 }
 629
 630 /* Must be called with xhci->lock held in interrupt context */
 631 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 632                 struct xhci_td *cur_td, int status, char *adjective)
 633 {
 634         struct usb_hcd *hcd;
 635         struct urb      *urb;
 636         struct urb_priv *urb_priv;
 637
 638         urb = cur_td->urb;
 639         urb_priv = urb->hcpriv;
 640         urb_priv->td_cnt++;
 641         hcd = bus_to_hcd(urb->dev->bus);
 642
 643         /* Only giveback urb when this is the last td in urb */
 644         if (urb_priv->td_cnt == urb_priv->length) {
 645                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 646                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 647                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 648                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 649                                         usb_amd_quirk_pll_enable();
 650                         }
 651                 }
 652                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 653
 654                 spin_unlock(&xhci->lock);
 655                 usb_hcd_giveback_urb(hcd, urb, status);
 656                 xhci_urb_free_priv(xhci, urb_priv);
 657                 spin_lock(&xhci->lock);
 658         }
 659 }
 660
 661 /*
 662  * When we get a command completion for a Stop Endpoint Command, we need to
 663  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 664  *
 665  *  1. If the HW was in the middle of processing the TD that needs to be
 666  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 667  *     in the TD with a Set Dequeue Pointer Command.
 668  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 669  *     bit cleared) so that the HW will skip over them.
 670  */
 671 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 672                 union xhci_trb *trb, struct xhci_event_cmd *event)
 673 {
 674         unsigned int slot_id;
 675         unsigned int ep_index;
 676         struct xhci_virt_device *virt_dev;
 677         struct xhci_ring *ep_ring;
 678         struct xhci_virt_ep *ep;
 679         struct list_head *entry;
 680         struct xhci_td *cur_td = NULL;
 681         struct xhci_td *last_unlinked_td;
 682
 683         struct xhci_dequeue_state deq_state;
 684
 685         if (unlikely(TRB_TO_SUSPEND_PORT(
 686                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 687                 slot_id = TRB_TO_SLOT_ID(
 688                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 689                 virt_dev = xhci->devs[slot_id];
 690                 if (virt_dev)
 691                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 692                                 event);
 693                 else
 694                         xhci_warn(xhci, "Stop endpoint command "
 695                                 "completion for disabled slot %u\n",
 696                                 slot_id);
 697                 return;
 698         }
 699
 700         memset(&deq_state, 0, sizeof(deq_state));
 701         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 702         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 703         ep = &xhci->devs[slot_id]->eps[ep_index];
 704
 705         if (list_empty(&ep->cancelled_td_list)) {
 706                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 707                 ep->stopped_td = NULL;
 708                 ep->stopped_trb = NULL;
 709                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 710                 return;
 711         }
 712
 713         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 714          * We have the xHCI lock, so nothing can modify this list until we drop
 715          * it.  We're also in the event handler, so we can't get re-interrupted
 716          * if another Stop Endpoint command completes
 717          */
 718         list_for_each(entry, &ep->cancelled_td_list) {
 719                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 720                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 721                                 cur_td->first_trb,
 722                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 723                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 724                 if (!ep_ring) {
 725                         /* This shouldn't happen unless a driver is mucking
 726                          * with the stream ID after submission.  This will
 727                          * leave the TD on the hardware ring, and the hardware
 728                          * will try to execute it, and may access a buffer
 729                          * that has already been freed.  In the best case, the
 730                          * hardware will execute it, and the event handler will
 731                          * ignore the completion event for that TD, since it was
 732                          * removed from the td_list for that endpoint.  In
 733                          * short, don't muck with the stream ID after
 734                          * submission.
 735                          */
 736                         xhci_warn(xhci, "WARN Cancelled URB %p "
 737                                         "has invalid stream ID %u.\n",
 738                                         cur_td->urb,
 739                                         cur_td->urb->stream_id);
 740                         goto remove_finished_td;
 741                 }
 742                 /*
 743                  * If we stopped on the TD we need to cancel, then we have to
 744                  * move the xHC endpoint ring dequeue pointer past this TD.
 745                  */
 746                 if (cur_td == ep->stopped_td)
 747                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 748                                         cur_td->urb->stream_id,
 749                                         cur_td, &deq_state);
 750                 else
 751                         td_to_noop(xhci, ep_ring, cur_td, false);
 752 remove_finished_td:
 753                 /*
 754                  * The event handler won't see a completion for this TD anymore,
 755                  * so remove it from the endpoint ring's TD list.  Keep it in
 756                  * the cancelled TD list for URB completion later.
 757                  */
 758                 list_del_init(&cur_td->td_list);
 759         }
 760         last_unlinked_td = cur_td;
 761         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 762
 763         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 764         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 765                 xhci_queue_new_dequeue_state(xhci,
 766                                 slot_id, ep_index,
 767                                 ep->stopped_td->urb->stream_id,
 768                                 &deq_state);
 769                 xhci_ring_cmd_db(xhci);
 770         } else {
 771                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 772                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 773         }
 774         ep->stopped_td = NULL;
 775         ep->stopped_trb = NULL;
 776
 777         /*
 778          * Drop the lock and complete the URBs in the cancelled TD list.
 779          * New TDs to be cancelled might be added to the end of the list before
 780          * we can complete all the URBs for the TDs we already unlinked.
 781          * So stop when we've completed the URB for the last TD we unlinked.
 782          */
 783         do {
 784                 cur_td = list_entry(ep->cancelled_td_list.next,
 785                                 struct xhci_td, cancelled_td_list);
 786                 list_del_init(&cur_td->cancelled_td_list);
 787
 788                 /* Clean up the cancelled URB */
 789                 /* Doesn't matter what we pass for status, since the core will
 790                  * just overwrite it (because the URB has been unlinked).
 791                  */
 792                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 793
 794                 /* Stop processing the cancelled list if the watchdog timer is
 795                  * running.
 796                  */
 797                 if (xhci->xhc_state & XHCI_STATE_DYING)
 798                         return;
 799         } while (cur_td != last_unlinked_td);
 800
 801         /* Return to the event handler with xhci->lock re-acquired */
 802 }
 803
 804 /* Watchdog timer function for when a stop endpoint command fails to complete.
 805  * In this case, we assume the host controller is broken or dying or dead.  The
 806  * host may still be completing some other events, so we have to be careful to
 807  * let the event ring handler and the URB dequeueing/enqueueing functions know
 808  * through xhci->state.
 809  *
 810  * The timer may also fire if the host takes a very long time to respond to the
 811  * command, and the stop endpoint command completion handler cannot delete the
 812  * timer before the timer function is called.  Another endpoint cancellation may
 813  * sneak in before the timer function can grab the lock, and that may queue
 814  * another stop endpoint command and add the timer back.  So we cannot use a
 815  * simple flag to say whether there is a pending stop endpoint command for a
 816  * particular endpoint.
 817  *
 818  * Instead we use a combination of that flag and a counter for the number of
 819  * pending stop endpoint commands.  If the timer is the tail end of the last
 820  * stop endpoint command, and the endpoint's command is still pending, we assume
 821  * the host is dying.
 822  */
 823 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 824 {
 825         struct xhci_hcd *xhci;
 826         struct xhci_virt_ep *ep;
 827         struct xhci_virt_ep *temp_ep;
 828         struct xhci_ring *ring;
 829         struct xhci_td *cur_td;
 830         int ret, i, j;
 831         unsigned long flags;
 832
 833         ep = (struct xhci_virt_ep *) arg;
 834         xhci = ep->xhci;
 835
 836         spin_lock_irqsave(&xhci->lock, flags);
 837
 838         ep->stop_cmds_pending--;
 839         if (xhci->xhc_state & XHCI_STATE_DYING) {
 840                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 841                                 "xHCI as DYING, exiting.\n");
 842                 spin_unlock_irqrestore(&xhci->lock, flags);
 843                 return;
 844         }
 845         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 846                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 847                                 "exiting.\n");
 848                 spin_unlock_irqrestore(&xhci->lock, flags);
 849                 return;
 850         }
 851
 852         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 853         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 854         /* Oops, HC is dead or dying or at least not responding to the stop
 855          * endpoint command.
 856          */
 857         xhci->xhc_state |= XHCI_STATE_DYING;
 858         /* Disable interrupts from the host controller and start halting it */
 859         xhci_quiesce(xhci);
 860         spin_unlock_irqrestore(&xhci->lock, flags);
 861
 862         ret = xhci_halt(xhci);
 863
 864         spin_lock_irqsave(&xhci->lock, flags);
 865         if (ret < 0) {
 866                 /* This is bad; the host is not responding to commands and it's
 867                  * not allowing itself to be halted.  At least interrupts are
 868                  * disabled. If we call usb_hc_died(), it will attempt to
 869                  * disconnect all device drivers under this host.  Those
 870                  * disconnect() methods will wait for all URBs to be unlinked,
 871                  * so we must complete them.
 872                  */
 873                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 874                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 875                 /* We could turn all TDs on the rings to no-ops.  This won't
 876                  * help if the host has cached part of the ring, and is slow if
 877                  * we want to preserve the cycle bit.  Skip it and hope the host
 878                  * doesn't touch the memory.
 879                  */
 880         }
 881         for (i = 0; i < MAX_HC_SLOTS; i++) {
 882                 if (!xhci->devs[i])
 883                         continue;
 884                 for (j = 0; j < 31; j++) {
 885                         temp_ep = &xhci->devs[i]->eps[j];
 886                         ring = temp_ep->ring;
 887                         if (!ring)
 888                                 continue;
 889                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 890                                         "ep index %u\n", i, j);
 891                         while (!list_empty(&ring->td_list)) {
 892                                 cur_td = list_first_entry(&ring->td_list,
 893                                                 struct xhci_td,
 894                                                 td_list);
 895                                 list_del_init(&cur_td->td_list);
 896                                 if (!list_empty(&cur_td->cancelled_td_list))
 897                                         list_del_init(&cur_td->cancelled_td_list);
 898                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 899                                                 -ESHUTDOWN, "killed");
 900                         }
 901                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 902                                 cur_td = list_first_entry(
 903                                                 &temp_ep->cancelled_td_list,
 904                                                 struct xhci_td,
 905                                                 cancelled_td_list);
 906                                 list_del_init(&cur_td->cancelled_td_list);
 907                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 908                                                 -ESHUTDOWN, "killed");
 909                         }
 910                 }
 911         }
 912         spin_unlock_irqrestore(&xhci->lock, flags);
 913         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 914         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 915         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 916 }
 917
 918 /*
 919  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 920  * we need to clear the set deq pending flag in the endpoint ring state, so that
 921  * the TD queueing code can ring the doorbell again.  We also need to ring the
 922  * endpoint doorbell to restart the ring, but only if there aren't more
 923  * cancellations pending.
 924  */
 925 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 926                 struct xhci_event_cmd *event,
 927                 union xhci_trb *trb)
 928 {
 929         unsigned int slot_id;
 930         unsigned int ep_index;
 931         unsigned int stream_id;
 932         struct xhci_ring *ep_ring;
 933         struct xhci_virt_device *dev;
 934         struct xhci_ep_ctx *ep_ctx;
 935         struct xhci_slot_ctx *slot_ctx;
 936
 937         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 938         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 939         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
 940         dev = xhci->devs[slot_id];
 941
 942         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 943         if (!ep_ring) {
 944                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 945                                 "freed stream ID %u\n",
 946                                 stream_id);
 947                 /* XXX: Harmless??? */
 948                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 949                 return;
 950         }
 951
 952         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 953         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 954
 955         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
 956                 unsigned int ep_state;
 957                 unsigned int slot_state;
 958
 959                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
 960                 case COMP_TRB_ERR:
 961                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 962                                         "of stream ID configuration\n");
 963                         break;
 964                 case COMP_CTX_STATE:
 965                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 966                                         "to incorrect slot or ep state.\n");
 967                         ep_state = le32_to_cpu(ep_ctx->ep_info);
 968                         ep_state &= EP_STATE_MASK;
 969                         slot_state = le32_to_cpu(slot_ctx->dev_state);
 970                         slot_state = GET_SLOT_STATE(slot_state);
 971                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 972                                         slot_state, ep_state);
 973                         break;
 974                 case COMP_EBADSLT:
 975                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 976                                         "slot %u was not enabled.\n", slot_id);
 977                         break;
 978                 default:
 979                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 980                                         "completion code of %u.\n",
 981                                   GET_COMP_CODE(le32_to_cpu(event->status)));
 982                         break;
 983                 }
 984                 /* OK what do we do now?  The endpoint state is hosed, and we
 985                  * should never get to this point if the synchronization between
 986                  * queueing, and endpoint state are correct.  This might happen
 987                  * if the device gets disconnected after we've finished
 988                  * cancelling URBs, which might not be an error...
 989                  */
 990         } else {
 991                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 992                          le64_to_cpu(ep_ctx->deq));
 993                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
 994                                          dev->eps[ep_index].queued_deq_ptr) ==
 995                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
 996                         /* Update the ring's dequeue segment and dequeue pointer
 997                          * to reflect the new position.
 998                          */
 999                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
1000                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
1001                 } else {
1002                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1003                                         "Ptr command & xHCI internal state.\n");
1004                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1005                                         dev->eps[ep_index].queued_deq_seg,
1006                                         dev->eps[ep_index].queued_deq_ptr);
1007                 }
1008         }
1009
1010         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1011         dev->eps[ep_index].queued_deq_seg = NULL;
1012         dev->eps[ep_index].queued_deq_ptr = NULL;
1013         /* Restart any rings with pending URBs */
1014         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1015 }
1016
1017 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1018                 struct xhci_event_cmd *event,
1019                 union xhci_trb *trb)
1020 {
1021         int slot_id;
1022         unsigned int ep_index;
1023
1024         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1025         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1026         /* This command will only fail if the endpoint wasn't halted,
1027          * but we don't care.
1028          */
1029         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1030                  GET_COMP_CODE(le32_to_cpu(event->status)));
1031
1032         /* HW with the reset endpoint quirk needs to have a configure endpoint
1033          * command complete before the endpoint can be used.  Queue that here
1034          * because the HW can't handle two commands being queued in a row.
1035          */
1036         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1037                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1038                 xhci_queue_configure_endpoint(xhci,
1039                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1040                                 false);
1041                 xhci_ring_cmd_db(xhci);
1042         } else {
1043                 /* Clear our internal halted state and restart the ring(s) */
1044                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1045                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1046         }
1047 }
1048
1049 /* Check to see if a command in the device's command queue matches this one.
1050  * Signal the completion or free the command, and return 1.  Return 0 if the
1051  * completed command isn't at the head of the command list.
1052  */
1053 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1054                 struct xhci_virt_device *virt_dev,
1055                 struct xhci_event_cmd *event)
1056 {
1057         struct xhci_command *command;
1058
1059         if (list_empty(&virt_dev->cmd_list))
1060                 return 0;
1061
1062         command = list_entry(virt_dev->cmd_list.next,
1063                         struct xhci_command, cmd_list);
1064         if (xhci->cmd_ring->dequeue != command->command_trb)
1065                 return 0;
1066
1067         command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1068         list_del(&command->cmd_list);
1069         if (command->completion)
1070                 complete(command->completion);
1071         else
1072                 xhci_free_command(xhci, command);
1073         return 1;
1074 }
1075
1076 static void handle_cmd_completion(struct xhci_hcd *xhci,
1077                 struct xhci_event_cmd *event)
1078 {
1079         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1080         u64 cmd_dma;
1081         dma_addr_t cmd_dequeue_dma;
1082         struct xhci_input_control_ctx *ctrl_ctx;
1083         struct xhci_virt_device *virt_dev;
1084         unsigned int ep_index;
1085         struct xhci_ring *ep_ring;
1086         unsigned int ep_state;
1087
1088         cmd_dma = le64_to_cpu(event->cmd_trb);
1089         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1090                         xhci->cmd_ring->dequeue);
1091         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1092         if (cmd_dequeue_dma == 0) {
1093                 xhci->error_bitmask |= 1 << 4;
1094                 return;
1095         }
1096         /* Does the DMA address match our internal dequeue pointer address? */
1097         if (cmd_dma != (u64) cmd_dequeue_dma) {
1098                 xhci->error_bitmask |= 1 << 5;
1099                 return;
1100         }
1101         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1102                 & TRB_TYPE_BITMASK) {
1103         case TRB_TYPE(TRB_ENABLE_SLOT):
1104                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1105                         xhci->slot_id = slot_id;
1106                 else
1107                         xhci->slot_id = 0;
1108                 complete(&xhci->addr_dev);
1109                 break;
1110         case TRB_TYPE(TRB_DISABLE_SLOT):
1111                 if (xhci->devs[slot_id]) {
1112                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1113                                 /* Delete default control endpoint resources */
1114                                 xhci_free_device_endpoint_resources(xhci,
1115                                                 xhci->devs[slot_id], true);
1116                         xhci_free_virt_device(xhci, slot_id);
1117                 }
1118                 break;
1119         case TRB_TYPE(TRB_CONFIG_EP):
1120                 virt_dev = xhci->devs[slot_id];
1121                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1122                         break;
1123                 /*
1124                  * Configure endpoint commands can come from the USB core
1125                  * configuration or alt setting changes, or because the HW
1126                  * needed an extra configure endpoint command after a reset
1127                  * endpoint command or streams were being configured.
1128                  * If the command was for a halted endpoint, the xHCI driver
1129                  * is not waiting on the configure endpoint command.
1130                  */
1131                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1132                                 virt_dev->in_ctx);
1133                 /* Input ctx add_flags are the endpoint index plus one */
1134                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1135                 /* A usb_set_interface() call directly after clearing a halted
1136                  * condition may race on this quirky hardware.  Not worth
1137                  * worrying about, since this is prototype hardware.  Not sure
1138                  * if this will work for streams, but streams support was
1139                  * untested on this prototype.
1140                  */
1141                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1142                                 ep_index != (unsigned int) -1 &&
1143                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1144                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1145                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1146                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1147                         if (!(ep_state & EP_HALTED))
1148                                 goto bandwidth_change;
1149                         xhci_dbg(xhci, "Completed config ep cmd - "
1150                                         "last ep index = %d, state = %d\n",
1151                                         ep_index, ep_state);
1152                         /* Clear internal halted state and restart ring(s) */
1153                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1154                                 ~EP_HALTED;
1155                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1156                         break;
1157                 }
1158 bandwidth_change:
1159                 xhci_dbg(xhci, "Completed config ep cmd\n");
1160                 xhci->devs[slot_id]->cmd_status =
1161                         GET_COMP_CODE(le32_to_cpu(event->status));
1162                 complete(&xhci->devs[slot_id]->cmd_completion);
1163                 break;
1164         case TRB_TYPE(TRB_EVAL_CONTEXT):
1165                 virt_dev = xhci->devs[slot_id];
1166                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1167                         break;
1168                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1169                 complete(&xhci->devs[slot_id]->cmd_completion);
1170                 break;
1171         case TRB_TYPE(TRB_ADDR_DEV):
1172                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1173                 complete(&xhci->addr_dev);
1174                 break;
1175         case TRB_TYPE(TRB_STOP_RING):
1176                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1177                 break;
1178         case TRB_TYPE(TRB_SET_DEQ):
1179                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1180                 break;
1181         case TRB_TYPE(TRB_CMD_NOOP):
1182                 break;
1183         case TRB_TYPE(TRB_RESET_EP):
1184                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1185                 break;
1186         case TRB_TYPE(TRB_RESET_DEV):
1187                 xhci_dbg(xhci, "Completed reset device command.\n");
1188                 slot_id = TRB_TO_SLOT_ID(
1189                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1190                 virt_dev = xhci->devs[slot_id];
1191                 if (virt_dev)
1192                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1193                 else
1194                         xhci_warn(xhci, "Reset device command completion "
1195                                         "for disabled slot %u\n", slot_id);
1196                 break;
1197         case TRB_TYPE(TRB_NEC_GET_FW):
1198                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1199                         xhci->error_bitmask |= 1 << 6;
1200                         break;
1201                 }
1202                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1203                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1204                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1205                 break;
1206         default:
1207                 /* Skip over unknown commands on the event ring */
1208                 xhci->error_bitmask |= 1 << 6;
1209                 break;
1210         }
1211         inc_deq(xhci, xhci->cmd_ring, false);
1212 }
1213
1214 static void handle_vendor_event(struct xhci_hcd *xhci,
1215                 union xhci_trb *event)
1216 {
1217         u32 trb_type;
1218
1219         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1220         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1221         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1222                 handle_cmd_completion(xhci, &event->event_cmd);
1223 }
1224
1225 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1226  * port registers -- USB 3.0 and USB 2.0).
1227  *
1228  * Returns a zero-based port number, which is suitable for indexing into each of
1229  * the split roothubs' port arrays and bus state arrays.
1230  * Add one to it in order to call xhci_find_slot_id_by_port.
1231  */
1232 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1233                 struct xhci_hcd *xhci, u32 port_id)
1234 {
1235         unsigned int i;
1236         unsigned int num_similar_speed_ports = 0;
1237
1238         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1239          * and usb2_ports are 0-based indexes.  Count the number of similar
1240          * speed ports, up to 1 port before this port.
1241          */
1242         for (i = 0; i < (port_id - 1); i++) {
1243                 u8 port_speed = xhci->port_array[i];
1244
1245                 /*
1246                  * Skip ports that don't have known speeds, or have duplicate
1247                  * Extended Capabilities port speed entries.
1248                  */
1249                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1250                         continue;
1251
1252                 /*
1253                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1254                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1255                  * matches the device speed, it's a similar speed port.
1256                  */
1257                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1258                         num_similar_speed_ports++;
1259         }
1260         return num_similar_speed_ports;
1261 }
1262
1263 static void handle_port_status(struct xhci_hcd *xhci,
1264                 union xhci_trb *event)
1265 {
1266         struct usb_hcd *hcd;
1267         u32 port_id;
1268         u32 temp, temp1;
1269         int max_ports;
1270         int slot_id;
1271         unsigned int faked_port_index;
1272         u8 major_revision;
1273         struct xhci_bus_state *bus_state;
1274         __le32 __iomem **port_array;
1275         bool bogus_port_status = false;
1276
1277         /* Port status change events always have a successful completion code */
1278         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1279                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1280                 xhci->error_bitmask |= 1 << 8;
1281         }
1282         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1283         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1284
1285         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1286         if ((port_id <= 0) || (port_id > max_ports)) {
1287                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1288                 bogus_port_status = true;
1289                 goto cleanup;
1290         }
1291
1292         /* Figure out which usb_hcd this port is attached to:
1293          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1294          */
1295         major_revision = xhci->port_array[port_id - 1];
1296         if (major_revision == 0) {
1297                 xhci_warn(xhci, "Event for port %u not in "
1298                                 "Extended Capabilities, ignoring.\n",
1299                                 port_id);
1300                 bogus_port_status = true;
1301                 goto cleanup;
1302         }
1303         if (major_revision == DUPLICATE_ENTRY) {
1304                 xhci_warn(xhci, "Event for port %u duplicated in"
1305                                 "Extended Capabilities, ignoring.\n",
1306                                 port_id);
1307                 bogus_port_status = true;
1308                 goto cleanup;
1309         }
1310
1311         /*
1312          * Hardware port IDs reported by a Port Status Change Event include USB
1313          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1314          * resume event, but we first need to translate the hardware port ID
1315          * into the index into the ports on the correct split roothub, and the
1316          * correct bus_state structure.
1317          */
1318         /* Find the right roothub. */
1319         hcd = xhci_to_hcd(xhci);
1320         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1321                 hcd = xhci->shared_hcd;
1322         bus_state = &xhci->bus_state[hcd_index(hcd)];
1323         if (hcd->speed == HCD_USB3)
1324                 port_array = xhci->usb3_ports;
1325         else
1326                 port_array = xhci->usb2_ports;
1327         /* Find the faked port hub number */
1328         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1329                         port_id);
1330
1331         temp = xhci_readl(xhci, port_array[faked_port_index]);
1332         if (hcd->state == HC_STATE_SUSPENDED) {
1333                 xhci_dbg(xhci, "resume root hub\n");
1334                 usb_hcd_resume_root_hub(hcd);
1335         }
1336
1337         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1338                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1339
1340                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1341                 if (!(temp1 & CMD_RUN)) {
1342                         xhci_warn(xhci, "xHC is not running.\n");
1343                         goto cleanup;
1344                 }
1345
1346                 if (DEV_SUPERSPEED(temp)) {
1347                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1348                         xhci_set_link_state(xhci, port_array, faked_port_index,
1349                                                 XDEV_U0);
1350                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1351                                         faked_port_index + 1);
1352                         if (!slot_id) {
1353                                 xhci_dbg(xhci, "slot_id is zero\n");
1354                                 goto cleanup;
1355                         }
1356                         xhci_ring_device(xhci, slot_id);
1357                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1358                         /* Clear PORT_PLC */
1359                         xhci_test_and_clear_bit(xhci, port_array,
1360                                                 faked_port_index, PORT_PLC);
1361                 } else {
1362                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1363                         bus_state->resume_done[faked_port_index] = jiffies +
1364                                 msecs_to_jiffies(20);
1365                         mod_timer(&hcd->rh_timer,
1366                                   bus_state->resume_done[faked_port_index]);
1367                         /* Do the rest in GetPortStatus */
1368                 }
1369         }
1370
1371         if (hcd->speed != HCD_USB3)
1372                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1373                                         PORT_PLC);
1374
1375 cleanup:
1376         /* Update event ring dequeue pointer before dropping the lock */
1377         inc_deq(xhci, xhci->event_ring, true);
1378
1379         /* Don't make the USB core poll the roothub if we got a bad port status
1380          * change event.  Besides, at that point we can't tell which roothub
1381          * (USB 2.0 or USB 3.0) to kick.
1382          */
1383         if (bogus_port_status)
1384                 return;
1385
1386         spin_unlock(&xhci->lock);
1387         /* Pass this up to the core */
1388         usb_hcd_poll_rh_status(hcd);
1389         spin_lock(&xhci->lock);
1390 }
1391
1392 /*
1393  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1394  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1395  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1396  * returns 0.
1397  */
1398 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1399                 union xhci_trb  *start_trb,
1400                 union xhci_trb  *end_trb,
1401                 dma_addr_t      suspect_dma)
1402 {
1403         dma_addr_t start_dma;
1404         dma_addr_t end_seg_dma;
1405         dma_addr_t end_trb_dma;
1406         struct xhci_segment *cur_seg;
1407
1408         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1409         cur_seg = start_seg;
1410
1411         do {
1412                 if (start_dma == 0)
1413                         return NULL;
1414                 /* We may get an event for a Link TRB in the middle of a TD */
1415                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1416                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1417                 /* If the end TRB isn't in this segment, this is set to 0 */
1418                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1419
1420                 if (end_trb_dma > 0) {
1421                         /* The end TRB is in this segment, so suspect should be here */
1422                         if (start_dma <= end_trb_dma) {
1423                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1424                                         return cur_seg;
1425                         } else {
1426                                 /* Case for one segment with
1427                                  * a TD wrapped around to the top
1428                                  */
1429                                 if ((suspect_dma >= start_dma &&
1430                                                         suspect_dma <= end_seg_dma) ||
1431                                                 (suspect_dma >= cur_seg->dma &&
1432                                                  suspect_dma <= end_trb_dma))
1433                                         return cur_seg;
1434                         }
1435                         return NULL;
1436                 } else {
1437                         /* Might still be somewhere in this segment */
1438                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1439                                 return cur_seg;
1440                 }
1441                 cur_seg = cur_seg->next;
1442                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1443         } while (cur_seg != start_seg);
1444
1445         return NULL;
1446 }
1447
1448 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1449                 unsigned int slot_id, unsigned int ep_index,
1450                 unsigned int stream_id,
1451                 struct xhci_td *td, union xhci_trb *event_trb)
1452 {
1453         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1454         ep->ep_state |= EP_HALTED;
1455         ep->stopped_td = td;
1456         ep->stopped_trb = event_trb;
1457         ep->stopped_stream = stream_id;
1458
1459         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1460         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1461
1462         ep->stopped_td = NULL;
1463         ep->stopped_trb = NULL;
1464         ep->stopped_stream = 0;
1465
1466         xhci_ring_cmd_db(xhci);
1467 }
1468
1469 /* Check if an error has halted the endpoint ring.  The class driver will
1470  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1471  * However, a babble and other errors also halt the endpoint ring, and the class
1472  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1473  * Ring Dequeue Pointer command manually.
1474  */
1475 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1476                 struct xhci_ep_ctx *ep_ctx,
1477                 unsigned int trb_comp_code)
1478 {
1479         /* TRB completion codes that may require a manual halt cleanup */
1480         if (trb_comp_code == COMP_TX_ERR ||
1481                         trb_comp_code == COMP_BABBLE ||
1482                         trb_comp_code == COMP_SPLIT_ERR)
1483                 /* The 0.96 spec says a babbling control endpoint
1484                  * is not halted. The 0.96 spec says it is.  Some HW
1485                  * claims to be 0.95 compliant, but it halts the control
1486                  * endpoint anyway.  Check if a babble halted the
1487                  * endpoint.
1488                  */
1489                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1490                     cpu_to_le32(EP_STATE_HALTED))
1491                         return 1;
1492
1493         return 0;
1494 }
1495
1496 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1497 {
1498         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1499                 /* Vendor defined "informational" completion code,
1500                  * treat as not-an-error.
1501                  */
1502                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1503                                 trb_comp_code);
1504                 xhci_dbg(xhci, "Treating code as success.\n");
1505                 return 1;
1506         }
1507         return 0;
1508 }
1509
1510 /*
1511  * Finish the td processing, remove the td from td list;
1512  * Return 1 if the urb can be given back.
1513  */
1514 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1515         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1516         struct xhci_virt_ep *ep, int *status, bool skip)
1517 {
1518         struct xhci_virt_device *xdev;
1519         struct xhci_ring *ep_ring;
1520         unsigned int slot_id;
1521         int ep_index;
1522         struct urb *urb = NULL;
1523         struct xhci_ep_ctx *ep_ctx;
1524         int ret = 0;
1525         struct urb_priv *urb_priv;
1526         u32 trb_comp_code;
1527
1528         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1529         xdev = xhci->devs[slot_id];
1530         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1531         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1532         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1533         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1534
1535         if (skip)
1536                 goto td_cleanup;
1537
1538         if (trb_comp_code == COMP_STOP_INVAL ||
1539                         trb_comp_code == COMP_STOP) {
1540                 /* The Endpoint Stop Command completion will take care of any
1541                  * stopped TDs.  A stopped TD may be restarted, so don't update
1542                  * the ring dequeue pointer or take this TD off any lists yet.
1543                  */
1544                 ep->stopped_td = td;
1545                 ep->stopped_trb = event_trb;
1546                 return 0;
1547         } else {
1548                 if (trb_comp_code == COMP_STALL) {
1549                         /* The transfer is completed from the driver's
1550                          * perspective, but we need to issue a set dequeue
1551                          * command for this stalled endpoint to move the dequeue
1552                          * pointer past the TD.  We can't do that here because
1553                          * the halt condition must be cleared first.  Let the
1554                          * USB class driver clear the stall later.
1555                          */
1556                         ep->stopped_td = td;
1557                         ep->stopped_trb = event_trb;
1558                         ep->stopped_stream = ep_ring->stream_id;
1559                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1560                                         ep_ctx, trb_comp_code)) {
1561                         /* Other types of errors halt the endpoint, but the
1562                          * class driver doesn't call usb_reset_endpoint() unless
1563                          * the error is -EPIPE.  Clear the halted status in the
1564                          * xHCI hardware manually.
1565                          */
1566                         xhci_cleanup_halted_endpoint(xhci,
1567                                         slot_id, ep_index, ep_ring->stream_id,
1568                                         td, event_trb);
1569                 } else {
1570                         /* Update ring dequeue pointer */
1571                         while (ep_ring->dequeue != td->last_trb)
1572                                 inc_deq(xhci, ep_ring, false);
1573                         inc_deq(xhci, ep_ring, false);
1574                 }
1575
1576 td_cleanup:
1577                 /* Clean up the endpoint's TD list */
1578                 urb = td->urb;
1579                 urb_priv = urb->hcpriv;
1580
1581                 /* Do one last check of the actual transfer length.
1582                  * If the host controller said we transferred more data than
1583                  * the buffer length, urb->actual_length will be a very big
1584                  * number (since it's unsigned).  Play it safe and say we didn't
1585                  * transfer anything.
1586                  */
1587                 if (urb->actual_length > urb->transfer_buffer_length) {
1588                         xhci_warn(xhci, "URB transfer length is wrong, "
1589                                         "xHC issue? req. len = %u, "
1590                                         "act. len = %u\n",
1591                                         urb->transfer_buffer_length,
1592                                         urb->actual_length);
1593                         urb->actual_length = 0;
1594                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1595                                 *status = -EREMOTEIO;
1596                         else
1597                                 *status = 0;
1598                 }
1599                 list_del_init(&td->td_list);
1600                 /* Was this TD slated to be cancelled but completed anyway? */
1601                 if (!list_empty(&td->cancelled_td_list))
1602                         list_del_init(&td->cancelled_td_list);
1603
1604                 urb_priv->td_cnt++;
1605                 /* Giveback the urb when all the tds are completed */
1606                 if (urb_priv->td_cnt == urb_priv->length) {
1607                         ret = 1;
1608                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1609                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1610                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1611                                         == 0) {
1612                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1613                                                 usb_amd_quirk_pll_enable();
1614                                 }
1615                         }
1616                 }
1617         }
1618
1619         return ret;
1620 }
1621
1622 /*
1623  * Process control tds, update urb status and actual_length.
1624  */
1625 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1626         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1627         struct xhci_virt_ep *ep, int *status)
1628 {
1629         struct xhci_virt_device *xdev;
1630         struct xhci_ring *ep_ring;
1631         unsigned int slot_id;
1632         int ep_index;
1633         struct xhci_ep_ctx *ep_ctx;
1634         u32 trb_comp_code;
1635
1636         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1637         xdev = xhci->devs[slot_id];
1638         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1639         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1640         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1641         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1642
1643         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1644         switch (trb_comp_code) {
1645         case COMP_SUCCESS:
1646                 if (event_trb == ep_ring->dequeue) {
1647                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1648                                         "without IOC set??\n");
1649                         *status = -ESHUTDOWN;
1650                 } else if (event_trb != td->last_trb) {
1651                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1652                                         "without IOC set??\n");
1653                         *status = -ESHUTDOWN;
1654                 } else {
1655                         *status = 0;
1656                 }
1657                 break;
1658         case COMP_SHORT_TX:
1659                 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1660                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1661                         *status = -EREMOTEIO;
1662                 else
1663                         *status = 0;
1664                 break;
1665         case COMP_STOP_INVAL:
1666         case COMP_STOP:
1667                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1668         default:
1669                 if (!xhci_requires_manual_halt_cleanup(xhci,
1670                                         ep_ctx, trb_comp_code))
1671                         break;
1672                 xhci_dbg(xhci, "TRB error code %u, "
1673                                 "halted endpoint index = %u\n",
1674                                 trb_comp_code, ep_index);
1675                 /* else fall through */
1676         case COMP_STALL:
1677                 /* Did we transfer part of the data (middle) phase? */
1678                 if (event_trb != ep_ring->dequeue &&
1679                                 event_trb != td->last_trb)
1680                         td->urb->actual_length =
1681                                 td->urb->transfer_buffer_length
1682                                 - TRB_LEN(le32_to_cpu(event->transfer_len));
1683                 else
1684                         td->urb->actual_length = 0;
1685
1686                 xhci_cleanup_halted_endpoint(xhci,
1687                         slot_id, ep_index, 0, td, event_trb);
1688                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1689         }
1690         /*
1691          * Did we transfer any data, despite the errors that might have
1692          * happened?  I.e. did we get past the setup stage?
1693          */
1694         if (event_trb != ep_ring->dequeue) {
1695                 /* The event was for the status stage */
1696                 if (event_trb == td->last_trb) {
1697                         if (td->urb->actual_length != 0) {
1698                                 /* Don't overwrite a previously set error code
1699                                  */
1700                                 if ((*status == -EINPROGRESS || *status == 0) &&
1701                                                 (td->urb->transfer_flags
1702                                                  & URB_SHORT_NOT_OK))
1703                                         /* Did we already see a short data
1704                                          * stage? */
1705                                         *status = -EREMOTEIO;
1706                         } else {
1707                                 td->urb->actual_length =
1708                                         td->urb->transfer_buffer_length;
1709                         }
1710                 } else {
1711                 /* Maybe the event was for the data stage? */
1712                         td->urb->actual_length =
1713                                 td->urb->transfer_buffer_length -
1714                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1715                         xhci_dbg(xhci, "Waiting for status "
1716                                         "stage event\n");
1717                         return 0;
1718                 }
1719         }
1720
1721         return finish_td(xhci, td, event_trb, event, ep, status, false);
1722 }
1723
1724 /*
1725  * Process isochronous tds, update urb packet status and actual_length.
1726  */
1727 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1728         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1729         struct xhci_virt_ep *ep, int *status)
1730 {
1731         struct xhci_ring *ep_ring;
1732         struct urb_priv *urb_priv;
1733         int idx;
1734         int len = 0;
1735         union xhci_trb *cur_trb;
1736         struct xhci_segment *cur_seg;
1737         struct usb_iso_packet_descriptor *frame;
1738         u32 trb_comp_code;
1739         bool skip_td = false;
1740
1741         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1742         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1743         urb_priv = td->urb->hcpriv;
1744         idx = urb_priv->td_cnt;
1745         frame = &td->urb->iso_frame_desc[idx];
1746
1747         /* handle completion code */
1748         switch (trb_comp_code) {
1749         case COMP_SUCCESS:
1750                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
1751                         frame->status = 0;
1752                         break;
1753                 }
1754                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
1755                         trb_comp_code = COMP_SHORT_TX;
1756         case COMP_SHORT_TX:
1757                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1758                                 -EREMOTEIO : 0;
1759                 break;
1760         case COMP_BW_OVER:
1761                 frame->status = -ECOMM;
1762                 skip_td = true;
1763                 break;
1764         case COMP_BUFF_OVER:
1765         case COMP_BABBLE:
1766                 frame->status = -EOVERFLOW;
1767                 skip_td = true;
1768                 break;
1769         case COMP_DEV_ERR:
1770         case COMP_STALL:
1771         case COMP_TX_ERR:
1772                 frame->status = -EPROTO;
1773                 skip_td = true;
1774                 break;
1775         case COMP_STOP:
1776         case COMP_STOP_INVAL:
1777                 break;
1778         default:
1779                 frame->status = -1;
1780                 break;
1781         }
1782
1783         if (trb_comp_code == COMP_SUCCESS || skip_td) {
1784                 frame->actual_length = frame->length;
1785                 td->urb->actual_length += frame->length;
1786         } else {
1787                 for (cur_trb = ep_ring->dequeue,
1788                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1789                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1790                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1791                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1792                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1793                 }
1794                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1795                         TRB_LEN(le32_to_cpu(event->transfer_len));
1796
1797                 if (trb_comp_code != COMP_STOP_INVAL) {
1798                         frame->actual_length = len;
1799                         td->urb->actual_length += len;
1800                 }
1801         }
1802
1803         return finish_td(xhci, td, event_trb, event, ep, status, false);
1804 }
1805
1806 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1807                         struct xhci_transfer_event *event,
1808                         struct xhci_virt_ep *ep, int *status)
1809 {
1810         struct xhci_ring *ep_ring;
1811         struct urb_priv *urb_priv;
1812         struct usb_iso_packet_descriptor *frame;
1813         int idx;
1814
1815         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1816         urb_priv = td->urb->hcpriv;
1817         idx = urb_priv->td_cnt;
1818         frame = &td->urb->iso_frame_desc[idx];
1819
1820         /* The transfer is partly done. */
1821         frame->status = -EXDEV;
1822
1823         /* calc actual length */
1824         frame->actual_length = 0;
1825
1826         /* Update ring dequeue pointer */
1827         while (ep_ring->dequeue != td->last_trb)
1828                 inc_deq(xhci, ep_ring, false);
1829         inc_deq(xhci, ep_ring, false);
1830
1831         return finish_td(xhci, td, NULL, event, ep, status, true);
1832 }
1833
1834 /*
1835  * Process bulk and interrupt tds, update urb status and actual_length.
1836  */
1837 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1838         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1839         struct xhci_virt_ep *ep, int *status)
1840 {
1841         struct xhci_ring *ep_ring;
1842         union xhci_trb *cur_trb;
1843         struct xhci_segment *cur_seg;
1844         u32 trb_comp_code;
1845
1846         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1847         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1848
1849         switch (trb_comp_code) {
1850         case COMP_SUCCESS:
1851                 /* Double check that the HW transferred everything. */
1852                 if (event_trb != td->last_trb ||
1853                                 TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1854                         xhci_warn(xhci, "WARN Successful completion "
1855                                         "on short TX\n");
1856                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1857                                 *status = -EREMOTEIO;
1858                         else
1859                                 *status = 0;
1860                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
1861                                 trb_comp_code = COMP_SHORT_TX;
1862                 } else {
1863                         *status = 0;
1864                 }
1865                 break;
1866         case COMP_SHORT_TX:
1867                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1868                         *status = -EREMOTEIO;
1869                 else
1870                         *status = 0;
1871                 break;
1872         default:
1873                 /* Others already handled above */
1874                 break;
1875         }
1876         if (trb_comp_code == COMP_SHORT_TX)
1877                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1878                                 "%d bytes untransferred\n",
1879                                 td->urb->ep->desc.bEndpointAddress,
1880                                 td->urb->transfer_buffer_length,
1881                                 TRB_LEN(le32_to_cpu(event->transfer_len)));
1882         /* Fast path - was this the last TRB in the TD for this URB? */
1883         if (event_trb == td->last_trb) {
1884                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1885                         td->urb->actual_length =
1886                                 td->urb->transfer_buffer_length -
1887                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1888                         if (td->urb->transfer_buffer_length <
1889                                         td->urb->actual_length) {
1890                                 xhci_warn(xhci, "HC gave bad length "
1891                                                 "of %d bytes left\n",
1892                                           TRB_LEN(le32_to_cpu(event->transfer_len)));
1893                                 td->urb->actual_length = 0;
1894                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1895                                         *status = -EREMOTEIO;
1896                                 else
1897                                         *status = 0;
1898                         }
1899                         /* Don't overwrite a previously set error code */
1900                         if (*status == -EINPROGRESS) {
1901                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1902                                         *status = -EREMOTEIO;
1903                                 else
1904                                         *status = 0;
1905                         }
1906                 } else {
1907                         td->urb->actual_length =
1908                                 td->urb->transfer_buffer_length;
1909                         /* Ignore a short packet completion if the
1910                          * untransferred length was zero.
1911                          */
1912                         if (*status == -EREMOTEIO)
1913                                 *status = 0;
1914                 }
1915         } else {
1916                 /* Slow path - walk the list, starting from the dequeue
1917                  * pointer, to get the actual length transferred.
1918                  */
1919                 td->urb->actual_length = 0;
1920                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1921                                 cur_trb != event_trb;
1922                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1923                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1924                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1925                                 td->urb->actual_length +=
1926                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1927                 }
1928                 /* If the ring didn't stop on a Link or No-op TRB, add
1929                  * in the actual bytes transferred from the Normal TRB
1930                  */
1931                 if (trb_comp_code != COMP_STOP_INVAL)
1932                         td->urb->actual_length +=
1933                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1934                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1935         }
1936
1937         return finish_td(xhci, td, event_trb, event, ep, status, false);
1938 }
1939
1940 /*
1941  * If this function returns an error condition, it means it got a Transfer
1942  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1943  * At this point, the host controller is probably hosed and should be reset.
1944  */
1945 static int handle_tx_event(struct xhci_hcd *xhci,
1946                 struct xhci_transfer_event *event)
1947 {
1948         struct xhci_virt_device *xdev;
1949         struct xhci_virt_ep *ep;
1950         struct xhci_ring *ep_ring;
1951         unsigned int slot_id;
1952         int ep_index;
1953         struct xhci_td *td = NULL;
1954         dma_addr_t event_dma;
1955         struct xhci_segment *event_seg;
1956         union xhci_trb *event_trb;
1957         struct urb *urb = NULL;
1958         int status = -EINPROGRESS;
1959         struct urb_priv *urb_priv;
1960         struct xhci_ep_ctx *ep_ctx;
1961         struct list_head *tmp;
1962         u32 trb_comp_code;
1963         int ret = 0;
1964         int td_num = 0;
1965
1966         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1967         xdev = xhci->devs[slot_id];
1968         if (!xdev) {
1969                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1970                 return -ENODEV;
1971         }
1972
1973         /* Endpoint ID is 1 based, our index is zero based */
1974         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1975         ep = &xdev->eps[ep_index];
1976         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1977         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1978         if (!ep_ring ||
1979             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
1980             EP_STATE_DISABLED) {
1981                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1982                                 "or incorrect stream ring\n");
1983                 return -ENODEV;
1984         }
1985
1986         /* Count current td numbers if ep->skip is set */
1987         if (ep->skip) {
1988                 list_for_each(tmp, &ep_ring->td_list)
1989                         td_num++;
1990         }
1991
1992         event_dma = le64_to_cpu(event->buffer);
1993         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1994         /* Look for common error cases */
1995         switch (trb_comp_code) {
1996         /* Skip codes that require special handling depending on
1997          * transfer type
1998          */
1999         case COMP_SUCCESS:
2000                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2001                         break;
2002                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2003                         trb_comp_code = COMP_SHORT_TX;
2004                 else
2005                         xhci_warn(xhci, "WARN Successful completion on short TX: "
2006                                         "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2007         case COMP_SHORT_TX:
2008                 break;
2009         case COMP_STOP:
2010                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2011                 break;
2012         case COMP_STOP_INVAL:
2013                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2014                 break;
2015         case COMP_STALL:
2016                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
2017                 ep->ep_state |= EP_HALTED;
2018                 status = -EPIPE;
2019                 break;
2020         case COMP_TRB_ERR:
2021                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2022                 status = -EILSEQ;
2023                 break;
2024         case COMP_SPLIT_ERR:
2025         case COMP_TX_ERR:
2026                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
2027                 status = -EPROTO;
2028                 break;
2029         case COMP_BABBLE:
2030                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
2031                 status = -EOVERFLOW;
2032                 break;
2033         case COMP_DB_ERR:
2034                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2035                 status = -ENOSR;
2036                 break;
2037         case COMP_BW_OVER:
2038                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2039                 break;
2040         case COMP_BUFF_OVER:
2041                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2042                 break;
2043         case COMP_UNDERRUN:
2044                 /*
2045                  * When the Isoch ring is empty, the xHC will generate
2046                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2047                  * Underrun Event for OUT Isoch endpoint.
2048                  */
2049                 xhci_dbg(xhci, "underrun event on endpoint\n");
2050                 if (!list_empty(&ep_ring->td_list))
2051                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2052                                         "still with TDs queued?\n",
2053                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2054                                  ep_index);
2055                 goto cleanup;
2056         case COMP_OVERRUN:
2057                 xhci_dbg(xhci, "overrun event on endpoint\n");
2058                 if (!list_empty(&ep_ring->td_list))
2059                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2060                                         "still with TDs queued?\n",
2061                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2062                                  ep_index);
2063                 goto cleanup;
2064         case COMP_DEV_ERR:
2065                 xhci_warn(xhci, "WARN: detect an incompatible device");
2066                 status = -EPROTO;
2067                 break;
2068         case COMP_MISSED_INT:
2069                 /*
2070                  * When encounter missed service error, one or more isoc tds
2071                  * may be missed by xHC.
2072                  * Set skip flag of the ep_ring; Complete the missed tds as
2073                  * short transfer when process the ep_ring next time.
2074                  */
2075                 ep->skip = true;
2076                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2077                 goto cleanup;
2078         default:
2079                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2080                         status = 0;
2081                         break;
2082                 }
2083                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2084                                 "busted\n");
2085                 goto cleanup;
2086         }
2087
2088         do {
2089                 /* This TRB should be in the TD at the head of this ring's
2090                  * TD list.
2091                  */
2092                 if (list_empty(&ep_ring->td_list)) {
2093                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2094                                         "with no TDs queued?\n",
2095                                   TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2096                                   ep_index);
2097                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2098                                  (le32_to_cpu(event->flags) &
2099                                   TRB_TYPE_BITMASK)>>10);
2100                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2101                         if (ep->skip) {
2102                                 ep->skip = false;
2103                                 xhci_dbg(xhci, "td_list is empty while skip "
2104                                                 "flag set. Clear skip flag.\n");
2105                         }
2106                         ret = 0;
2107                         goto cleanup;
2108                 }
2109
2110                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2111                 if (ep->skip && td_num == 0) {
2112                         ep->skip = false;
2113                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2114                                                 "Clear skip flag.\n");
2115                         ret = 0;
2116                         goto cleanup;
2117                 }
2118
2119                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2120                 if (ep->skip)
2121                         td_num--;
2122
2123                 /* Is this a TRB in the currently executing TD? */
2124                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2125                                 td->last_trb, event_dma);
2126
2127                 /*
2128                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2129                  * is not in the current TD pointed by ep_ring->dequeue because
2130                  * that the hardware dequeue pointer still at the previous TRB
2131                  * of the current TD. The previous TRB maybe a Link TD or the
2132                  * last TRB of the previous TD. The command completion handle
2133                  * will take care the rest.
2134                  */
2135                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2136                         ret = 0;
2137                         goto cleanup;
2138                 }
2139
2140                 if (!event_seg) {
2141                         if (!ep->skip ||
2142                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2143                                 /* Some host controllers give a spurious
2144                                  * successful event after a short transfer.
2145                                  * Ignore it.
2146                                  */
2147                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2148                                                 ep_ring->last_td_was_short) {
2149                                         ep_ring->last_td_was_short = false;
2150                                         ret = 0;
2151                                         goto cleanup;
2152                                 }
2153                                 /* HC is busted, give up! */
2154                                 xhci_err(xhci,
2155                                         "ERROR Transfer event TRB DMA ptr not "
2156                                         "part of current TD\n");
2157                                 return -ESHUTDOWN;
2158                         }
2159
2160                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2161                         goto cleanup;
2162                 }
2163                 if (trb_comp_code == COMP_SHORT_TX)
2164                         ep_ring->last_td_was_short = true;
2165                 else
2166                         ep_ring->last_td_was_short = false;
2167
2168                 if (ep->skip) {
2169                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2170                         ep->skip = false;
2171                 }
2172
2173                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2174                                                 sizeof(*event_trb)];
2175                 /*
2176                  * No-op TRB should not trigger interrupts.
2177                  * If event_trb is a no-op TRB, it means the
2178                  * corresponding TD has been cancelled. Just ignore
2179                  * the TD.
2180                  */
2181                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2182                         xhci_dbg(xhci,
2183                                  "event_trb is a no-op TRB. Skip it\n");
2184                         goto cleanup;
2185                 }
2186
2187                 /* Now update the urb's actual_length and give back to
2188                  * the core
2189                  */
2190                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2191                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2192                                                  &status);
2193                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2194                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2195                                                  &status);
2196                 else
2197                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2198                                                  ep, &status);
2199
2200 cleanup:
2201                 /*
2202                  * Do not update event ring dequeue pointer if ep->skip is set.
2203                  * Will roll back to continue process missed tds.
2204                  */
2205                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2206                         inc_deq(xhci, xhci->event_ring, true);
2207                 }
2208
2209                 if (ret) {
2210                         urb = td->urb;
2211                         urb_priv = urb->hcpriv;
2212                         /* Leave the TD around for the reset endpoint function
2213                          * to use(but only if it's not a control endpoint,
2214                          * since we already queued the Set TR dequeue pointer
2215                          * command for stalled control endpoints).
2216                          */
2217                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2218                                 (trb_comp_code != COMP_STALL &&
2219                                         trb_comp_code != COMP_BABBLE))
2220                                 xhci_urb_free_priv(xhci, urb_priv);
2221
2222                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2223                         if ((urb->actual_length != urb->transfer_buffer_length &&
2224                                                 (urb->transfer_flags &
2225                                                  URB_SHORT_NOT_OK)) ||
2226                                         (status != 0 &&
2227                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2228                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2229                                                 "expected = %x, status = %d\n",
2230                                                 urb, urb->actual_length,
2231                                                 urb->transfer_buffer_length,
2232                                                 status);
2233                         spin_unlock(&xhci->lock);
2234                         /* EHCI, UHCI, and OHCI always unconditionally set the
2235                          * urb->status of an isochronous endpoint to 0.
2236                          */
2237                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2238                                 status = 0;
2239                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2240                         spin_lock(&xhci->lock);
2241                 }
2242
2243         /*
2244          * If ep->skip is set, it means there are missed tds on the
2245          * endpoint ring need to take care of.
2246          * Process them as short transfer until reach the td pointed by
2247          * the event.
2248          */
2249         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2250
2251         return 0;
2252 }
2253
2254 /*
2255  * This function handles all OS-owned events on the event ring.  It may drop
2256  * xhci->lock between event processing (e.g. to pass up port status changes).
2257  * Returns >0 for "possibly more events to process" (caller should call again),
2258  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2259  */
2260 static int xhci_handle_event(struct xhci_hcd *xhci)
2261 {
2262         union xhci_trb *event;
2263         int update_ptrs = 1;
2264         int ret;
2265
2266         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2267                 xhci->error_bitmask |= 1 << 1;
2268                 return 0;
2269         }
2270
2271         event = xhci->event_ring->dequeue;
2272         /* Does the HC or OS own the TRB? */
2273         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2274             xhci->event_ring->cycle_state) {
2275                 xhci->error_bitmask |= 1 << 2;
2276                 return 0;
2277         }
2278
2279         /*
2280          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2281          * speculative reads of the event's flags/data below.
2282          */
2283         rmb();
2284         /* FIXME: Handle more event types. */
2285         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2286         case TRB_TYPE(TRB_COMPLETION):
2287                 handle_cmd_completion(xhci, &event->event_cmd);
2288                 break;
2289         case TRB_TYPE(TRB_PORT_STATUS):
2290                 handle_port_status(xhci, event);
2291                 update_ptrs = 0;
2292                 break;
2293         case TRB_TYPE(TRB_TRANSFER):
2294                 ret = handle_tx_event(xhci, &event->trans_event);
2295                 if (ret < 0)
2296                         xhci->error_bitmask |= 1 << 9;
2297                 else
2298                         update_ptrs = 0;
2299                 break;
2300         default:
2301                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2302                     TRB_TYPE(48))
2303                         handle_vendor_event(xhci, event);
2304                 else
2305                         xhci->error_bitmask |= 1 << 3;
2306         }
2307         /* Any of the above functions may drop and re-acquire the lock, so check
2308          * to make sure a watchdog timer didn't mark the host as non-responsive.
2309          */
2310         if (xhci->xhc_state & XHCI_STATE_DYING) {
2311                 xhci_dbg(xhci, "xHCI host dying, returning from "
2312                                 "event handler.\n");
2313                 return 0;
2314         }
2315
2316         if (update_ptrs)
2317                 /* Update SW event ring dequeue pointer */
2318                 inc_deq(xhci, xhci->event_ring, true);
2319
2320         /* Are there more items on the event ring?  Caller will call us again to
2321          * check.
2322          */
2323         return 1;
2324 }
2325
2326 /*
2327  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2328  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2329  * indicators of an event TRB error, but we check the status *first* to be safe.
2330  */
2331 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2332 {
2333         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2334         u32 status;
2335         union xhci_trb *trb;
2336         u64 temp_64;
2337         union xhci_trb *event_ring_deq;
2338         dma_addr_t deq;
2339
2340         spin_lock(&xhci->lock);
2341         trb = xhci->event_ring->dequeue;
2342         /* Check if the xHC generated the interrupt, or the irq is shared */
2343         status = xhci_readl(xhci, &xhci->op_regs->status);
2344         if (status == 0xffffffff)
2345                 goto hw_died;
2346
2347         if (!(status & STS_EINT)) {
2348                 spin_unlock(&xhci->lock);
2349                 return IRQ_NONE;
2350         }
2351         if (status & STS_FATAL) {
2352                 xhci_warn(xhci, "WARNING: Host System Error\n");
2353                 xhci_halt(xhci);
2354 hw_died:
2355                 spin_unlock(&xhci->lock);
2356                 return -ESHUTDOWN;
2357         }
2358
2359         /*
2360          * Clear the op reg interrupt status first,
2361          * so we can receive interrupts from other MSI-X interrupters.
2362          * Write 1 to clear the interrupt status.
2363          */
2364         status |= STS_EINT;
2365         xhci_writel(xhci, status, &xhci->op_regs->status);
2366         /* FIXME when MSI-X is supported and there are multiple vectors */
2367         /* Clear the MSI-X event interrupt status */
2368
2369         if (hcd->irq != -1) {
2370                 u32 irq_pending;
2371                 /* Acknowledge the PCI interrupt */
2372                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2373                 irq_pending |= IMAN_IP;
2374                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2375         }
2376
2377         if (xhci->xhc_state & XHCI_STATE_DYING) {
2378                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2379                                 "Shouldn't IRQs be disabled?\n");
2380                 /* Clear the event handler busy flag (RW1C);
2381                  * the event ring should be empty.
2382                  */
2383                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2384                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2385                                 &xhci->ir_set->erst_dequeue);
2386                 spin_unlock(&xhci->lock);
2387
2388                 return IRQ_HANDLED;
2389         }
2390
2391         event_ring_deq = xhci->event_ring->dequeue;
2392         /* FIXME this should be a delayed service routine
2393          * that clears the EHB.
2394          */
2395         while (xhci_handle_event(xhci) > 0) {}
2396
2397         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2398         /* If necessary, update the HW's version of the event ring deq ptr. */
2399         if (event_ring_deq != xhci->event_ring->dequeue) {
2400                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2401                                 xhci->event_ring->dequeue);
2402                 if (deq == 0)
2403                         xhci_warn(xhci, "WARN something wrong with SW event "
2404                                         "ring dequeue ptr.\n");
2405                 /* Update HC event ring dequeue pointer */
2406                 temp_64 &= ERST_PTR_MASK;
2407                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2408         }
2409
2410         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2411         temp_64 |= ERST_EHB;
2412         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2413
2414         spin_unlock(&xhci->lock);
2415
2416         return IRQ_HANDLED;
2417 }
2418
2419 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2420 {
2421         irqreturn_t ret;
2422         struct xhci_hcd *xhci;
2423
2424         xhci = hcd_to_xhci(hcd);
2425         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2426         if (xhci->shared_hcd)
2427                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2428
2429         ret = xhci_irq(hcd);
2430
2431         return ret;
2432 }
2433
2434 /****           Endpoint Ring Operations        ****/
2435
2436 /*
2437  * Generic function for queueing a TRB on a ring.
2438  * The caller must have checked to make sure there's room on the ring.
2439  *
2440  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2441  *                      prepare_transfer()?
2442  */
2443 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2444                 bool consumer, bool more_trbs_coming, bool isoc,
2445                 u32 field1, u32 field2, u32 field3, u32 field4)
2446 {
2447         struct xhci_generic_trb *trb;
2448
2449         trb = &ring->enqueue->generic;
2450         trb->field[0] = cpu_to_le32(field1);
2451         trb->field[1] = cpu_to_le32(field2);
2452         trb->field[2] = cpu_to_le32(field3);
2453         trb->field[3] = cpu_to_le32(field4);
2454         inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2455 }
2456
2457 /*
2458  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2459  * FIXME allocate segments if the ring is full.
2460  */
2461 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2462                 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2463 {
2464         /* Make sure the endpoint has been added to xHC schedule */
2465         switch (ep_state) {
2466         case EP_STATE_DISABLED:
2467                 /*
2468                  * USB core changed config/interfaces without notifying us,
2469                  * or hardware is reporting the wrong state.
2470                  */
2471                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2472                 return -ENOENT;
2473         case EP_STATE_ERROR:
2474                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2475                 /* FIXME event handling code for error needs to clear it */
2476                 /* XXX not sure if this should be -ENOENT or not */
2477                 return -EINVAL;
2478         case EP_STATE_HALTED:
2479                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2480         case EP_STATE_STOPPED:
2481         case EP_STATE_RUNNING:
2482                 break;
2483         default:
2484                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2485                 /*
2486                  * FIXME issue Configure Endpoint command to try to get the HC
2487                  * back into a known state.
2488                  */
2489                 return -EINVAL;
2490         }
2491         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2492                 /* FIXME allocate more room */
2493                 xhci_err(xhci, "ERROR no room on ep ring\n");
2494                 return -ENOMEM;
2495         }
2496
2497         if (enqueue_is_link_trb(ep_ring)) {
2498                 struct xhci_ring *ring = ep_ring;
2499                 union xhci_trb *next;
2500
2501                 next = ring->enqueue;
2502
2503                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2504                         /* If we're not dealing with 0.95 hardware or isoc rings
2505                          * on AMD 0.96 host, clear the chain bit.
2506                          */
2507                         if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2508                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2509                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2510                         else
2511                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2512
2513                         wmb();
2514                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2515
2516                         /* Toggle the cycle bit after the last ring segment. */
2517                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2518                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2519                                 if (!in_interrupt()) {
2520                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2521                                                 "state for ring %p = %i\n",
2522                                                 ring, (unsigned int)ring->cycle_state);
2523                                 }
2524                         }
2525                         ring->enq_seg = ring->enq_seg->next;
2526                         ring->enqueue = ring->enq_seg->trbs;
2527                         next = ring->enqueue;
2528                 }
2529         }
2530
2531         return 0;
2532 }
2533
2534 static int prepare_transfer(struct xhci_hcd *xhci,
2535                 struct xhci_virt_device *xdev,
2536                 unsigned int ep_index,
2537                 unsigned int stream_id,
2538                 unsigned int num_trbs,
2539                 struct urb *urb,
2540                 unsigned int td_index,
2541                 bool isoc,
2542                 gfp_t mem_flags)
2543 {
2544         int ret;
2545         struct urb_priv *urb_priv;
2546         struct xhci_td  *td;
2547         struct xhci_ring *ep_ring;
2548         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2549
2550         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2551         if (!ep_ring) {
2552                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2553                                 stream_id);
2554                 return -EINVAL;
2555         }
2556
2557         ret = prepare_ring(xhci, ep_ring,
2558                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2559                            num_trbs, isoc, mem_flags);
2560         if (ret)
2561                 return ret;
2562
2563         urb_priv = urb->hcpriv;
2564         td = urb_priv->td[td_index];
2565
2566         INIT_LIST_HEAD(&td->td_list);
2567         INIT_LIST_HEAD(&td->cancelled_td_list);
2568
2569         if (td_index == 0) {
2570                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2571                 if (unlikely(ret))
2572                         return ret;
2573         }
2574
2575         td->urb = urb;
2576         /* Add this TD to the tail of the endpoint ring's TD list */
2577         list_add_tail(&td->td_list, &ep_ring->td_list);
2578         td->start_seg = ep_ring->enq_seg;
2579         td->first_trb = ep_ring->enqueue;
2580
2581         urb_priv->td[td_index] = td;
2582
2583         return 0;
2584 }
2585
2586 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2587 {
2588         int num_sgs, num_trbs, running_total, temp, i;
2589         struct scatterlist *sg;
2590
2591         sg = NULL;
2592         num_sgs = urb->num_mapped_sgs;
2593         temp = urb->transfer_buffer_length;
2594
2595         xhci_dbg(xhci, "count sg list trbs: \n");
2596         num_trbs = 0;
2597         for_each_sg(urb->sg, sg, num_sgs, i) {
2598                 unsigned int previous_total_trbs = num_trbs;
2599                 unsigned int len = sg_dma_len(sg);
2600
2601                 /* Scatter gather list entries may cross 64KB boundaries */
2602                 running_total = TRB_MAX_BUFF_SIZE -
2603                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2604                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2605                 if (running_total != 0)
2606                         num_trbs++;
2607
2608                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2609                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2610                         num_trbs++;
2611                         running_total += TRB_MAX_BUFF_SIZE;
2612                 }
2613                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2614                                 i, (unsigned long long)sg_dma_address(sg),
2615                                 len, len, num_trbs - previous_total_trbs);
2616
2617                 len = min_t(int, len, temp);
2618                 temp -= len;
2619                 if (temp == 0)
2620                         break;
2621         }
2622         xhci_dbg(xhci, "\n");
2623         if (!in_interrupt())
2624                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2625                                 "num_trbs = %d\n",
2626                                 urb->ep->desc.bEndpointAddress,
2627                                 urb->transfer_buffer_length,
2628                                 num_trbs);
2629         return num_trbs;
2630 }
2631
2632 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2633 {
2634         if (num_trbs != 0)
2635                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2636                                 "TRBs, %d left\n", __func__,
2637                                 urb->ep->desc.bEndpointAddress, num_trbs);
2638         if (running_total != urb->transfer_buffer_length)
2639                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2640                                 "queued %#x (%d), asked for %#x (%d)\n",
2641                                 __func__,
2642                                 urb->ep->desc.bEndpointAddress,
2643                                 running_total, running_total,
2644                                 urb->transfer_buffer_length,
2645                                 urb->transfer_buffer_length);
2646 }
2647
2648 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2649                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2650                 struct xhci_generic_trb *start_trb)
2651 {
2652         /*
2653          * Pass all the TRBs to the hardware at once and make sure this write
2654          * isn't reordered.
2655          */
2656         wmb();
2657         if (start_cycle)
2658                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2659         else
2660                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2661         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2662 }
2663
2664 /*
2665  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2666  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2667  * (comprised of sg list entries) can take several service intervals to
2668  * transmit.
2669  */
2670 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2671                 struct urb *urb, int slot_id, unsigned int ep_index)
2672 {
2673         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2674                         xhci->devs[slot_id]->out_ctx, ep_index);
2675         int xhci_interval;
2676         int ep_interval;
2677
2678         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2679         ep_interval = urb->interval;
2680         /* Convert to microframes */
2681         if (urb->dev->speed == USB_SPEED_LOW ||
2682                         urb->dev->speed == USB_SPEED_FULL)
2683                 ep_interval *= 8;
2684         /* FIXME change this to a warning and a suggestion to use the new API
2685          * to set the polling interval (once the API is added).
2686          */
2687         if (xhci_interval != ep_interval) {
2688                 if (printk_ratelimit())
2689                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2690                                         " (%d microframe%s) than xHCI "
2691                                         "(%d microframe%s)\n",
2692                                         ep_interval,
2693                                         ep_interval == 1 ? "" : "s",
2694                                         xhci_interval,
2695                                         xhci_interval == 1 ? "" : "s");
2696                 urb->interval = xhci_interval;
2697                 /* Convert back to frames for LS/FS devices */
2698                 if (urb->dev->speed == USB_SPEED_LOW ||
2699                                 urb->dev->speed == USB_SPEED_FULL)
2700                         urb->interval /= 8;
2701         }
2702         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2703 }
2704
2705 /*
2706  * The TD size is the number of bytes remaining in the TD (including this TRB),
2707  * right shifted by 10.
2708  * It must fit in bits 21:17, so it can't be bigger than 31.
2709  */
2710 static u32 xhci_td_remainder(unsigned int remainder)
2711 {
2712         u32 max = (1 << (21 - 17 + 1)) - 1;
2713
2714         if ((remainder >> 10) >= max)
2715                 return max << 17;
2716         else
2717                 return (remainder >> 10) << 17;
2718 }
2719
2720 /*
2721  * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2722  * the TD (*not* including this TRB).
2723  *
2724  * Total TD packet count = total_packet_count =
2725  *     roundup(TD size in bytes / wMaxPacketSize)
2726  *
2727  * Packets transferred up to and including this TRB = packets_transferred =
2728  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2729  *
2730  * TD size = total_packet_count - packets_transferred
2731  *
2732  * It must fit in bits 21:17, so it can't be bigger than 31.
2733  */
2734
2735 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2736                 unsigned int total_packet_count, struct urb *urb)
2737 {
2738         int packets_transferred;
2739
2740         /* One TRB with a zero-length data packet. */
2741         if (running_total == 0 && trb_buff_len == 0)
2742                 return 0;
2743
2744         /* All the TRB queueing functions don't count the current TRB in
2745          * running_total.
2746          */
2747         packets_transferred = (running_total + trb_buff_len) /
2748                 usb_endpoint_maxp(&urb->ep->desc);
2749
2750         return xhci_td_remainder(total_packet_count - packets_transferred);
2751 }
2752
2753 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2754                 struct urb *urb, int slot_id, unsigned int ep_index)
2755 {
2756         struct xhci_ring *ep_ring;
2757         unsigned int num_trbs;
2758         struct urb_priv *urb_priv;
2759         struct xhci_td *td;
2760         struct scatterlist *sg;
2761         int num_sgs;
2762         int trb_buff_len, this_sg_len, running_total;
2763         unsigned int total_packet_count;
2764         bool first_trb;
2765         u64 addr;
2766         bool more_trbs_coming;
2767
2768         struct xhci_generic_trb *start_trb;
2769         int start_cycle;
2770
2771         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2772         if (!ep_ring)
2773                 return -EINVAL;
2774
2775         num_trbs = count_sg_trbs_needed(xhci, urb);
2776         num_sgs = urb->num_mapped_sgs;
2777         total_packet_count = roundup(urb->transfer_buffer_length,
2778                         usb_endpoint_maxp(&urb->ep->desc));
2779
2780         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2781                         ep_index, urb->stream_id,
2782                         num_trbs, urb, 0, false, mem_flags);
2783         if (trb_buff_len < 0)
2784                 return trb_buff_len;
2785
2786         urb_priv = urb->hcpriv;
2787         td = urb_priv->td[0];
2788
2789         /*
2790          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2791          * until we've finished creating all the other TRBs.  The ring's cycle
2792          * state may change as we enqueue the other TRBs, so save it too.
2793          */
2794         start_trb = &ep_ring->enqueue->generic;
2795         start_cycle = ep_ring->cycle_state;
2796
2797         running_total = 0;
2798         /*
2799          * How much data is in the first TRB?
2800          *
2801          * There are three forces at work for TRB buffer pointers and lengths:
2802          * 1. We don't want to walk off the end of this sg-list entry buffer.
2803          * 2. The transfer length that the driver requested may be smaller than
2804          *    the amount of memory allocated for this scatter-gather list.
2805          * 3. TRBs buffers can't cross 64KB boundaries.
2806          */
2807         sg = urb->sg;
2808         addr = (u64) sg_dma_address(sg);
2809         this_sg_len = sg_dma_len(sg);
2810         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2811         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2812         if (trb_buff_len > urb->transfer_buffer_length)
2813                 trb_buff_len = urb->transfer_buffer_length;
2814         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2815                         trb_buff_len);
2816
2817         first_trb = true;
2818         /* Queue the first TRB, even if it's zero-length */
2819         do {
2820                 u32 field = 0;
2821                 u32 length_field = 0;
2822                 u32 remainder = 0;
2823
2824                 /* Don't change the cycle bit of the first TRB until later */
2825                 if (first_trb) {
2826                         first_trb = false;
2827                         if (start_cycle == 0)
2828                                 field |= 0x1;
2829                 } else
2830                         field |= ep_ring->cycle_state;
2831
2832                 /* Chain all the TRBs together; clear the chain bit in the last
2833                  * TRB to indicate it's the last TRB in the chain.
2834                  */
2835                 if (num_trbs > 1) {
2836                         field |= TRB_CHAIN;
2837                 } else {
2838                         /* FIXME - add check for ZERO_PACKET flag before this */
2839                         td->last_trb = ep_ring->enqueue;
2840                         field |= TRB_IOC;
2841                 }
2842
2843                 /* Only set interrupt on short packet for IN endpoints */
2844                 if (usb_urb_dir_in(urb))
2845                         field |= TRB_ISP;
2846
2847                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2848                                 "64KB boundary at %#x, end dma = %#x\n",
2849                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
2850                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2851                                 (unsigned int) addr + trb_buff_len);
2852                 if (TRB_MAX_BUFF_SIZE -
2853                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2854                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2855                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2856                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2857                                         (unsigned int) addr + trb_buff_len);
2858                 }
2859
2860                 /* Set the TRB length, TD size, and interrupter fields. */
2861                 if (xhci->hci_version < 0x100) {
2862                         remainder = xhci_td_remainder(
2863                                         urb->transfer_buffer_length -
2864                                         running_total);
2865                 } else {
2866                         remainder = xhci_v1_0_td_remainder(running_total,
2867                                         trb_buff_len, total_packet_count, urb);
2868                 }
2869                 length_field = TRB_LEN(trb_buff_len) |
2870                         remainder |
2871                         TRB_INTR_TARGET(0);
2872
2873                 if (num_trbs > 1)
2874                         more_trbs_coming = true;
2875                 else
2876                         more_trbs_coming = false;
2877                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
2878                                 lower_32_bits(addr),
2879                                 upper_32_bits(addr),
2880                                 length_field,
2881                                 field | TRB_TYPE(TRB_NORMAL));
2882                 --num_trbs;
2883                 running_total += trb_buff_len;
2884
2885                 /* Calculate length for next transfer --
2886                  * Are we done queueing all the TRBs for this sg entry?
2887                  */
2888                 this_sg_len -= trb_buff_len;
2889                 if (this_sg_len == 0) {
2890                         --num_sgs;
2891                         if (num_sgs == 0)
2892                                 break;
2893                         sg = sg_next(sg);
2894                         addr = (u64) sg_dma_address(sg);
2895                         this_sg_len = sg_dma_len(sg);
2896                 } else {
2897                         addr += trb_buff_len;
2898                 }
2899
2900                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2901                         (addr & (TRB_MAX_BUFF_SIZE - 1));
2902                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2903                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2904                         trb_buff_len =
2905                                 urb->transfer_buffer_length - running_total;
2906         } while (running_total < urb->transfer_buffer_length);
2907
2908         check_trb_math(urb, num_trbs, running_total);
2909         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2910                         start_cycle, start_trb);
2911         return 0;
2912 }
2913
2914 /* This is very similar to what ehci-q.c qtd_fill() does */
2915 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2916                 struct urb *urb, int slot_id, unsigned int ep_index)
2917 {
2918         struct xhci_ring *ep_ring;
2919         struct urb_priv *urb_priv;
2920         struct xhci_td *td;
2921         int num_trbs;
2922         struct xhci_generic_trb *start_trb;
2923         bool first_trb;
2924         bool more_trbs_coming;
2925         int start_cycle;
2926         u32 field, length_field;
2927
2928         int running_total, trb_buff_len, ret;
2929         unsigned int total_packet_count;
2930         u64 addr;
2931
2932         if (urb->num_sgs)
2933                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2934
2935         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2936         if (!ep_ring)
2937                 return -EINVAL;
2938
2939         num_trbs = 0;
2940         /* How much data is (potentially) left before the 64KB boundary? */
2941         running_total = TRB_MAX_BUFF_SIZE -
2942                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2943         running_total &= TRB_MAX_BUFF_SIZE - 1;
2944
2945         /* If there's some data on this 64KB chunk, or we have to send a
2946          * zero-length transfer, we need at least one TRB
2947          */
2948         if (running_total != 0 || urb->transfer_buffer_length == 0)
2949                 num_trbs++;
2950         /* How many more 64KB chunks to transfer, how many more TRBs? */
2951         while (running_total < urb->transfer_buffer_length) {
2952                 num_trbs++;
2953                 running_total += TRB_MAX_BUFF_SIZE;
2954         }
2955         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2956
2957         if (!in_interrupt())
2958                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2959                                 "addr = %#llx, num_trbs = %d\n",
2960                                 urb->ep->desc.bEndpointAddress,
2961                                 urb->transfer_buffer_length,
2962                                 urb->transfer_buffer_length,
2963                                 (unsigned long long)urb->transfer_dma,
2964                                 num_trbs);
2965
2966         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2967                         ep_index, urb->stream_id,
2968                         num_trbs, urb, 0, false, mem_flags);
2969         if (ret < 0)
2970                 return ret;
2971
2972         urb_priv = urb->hcpriv;
2973         td = urb_priv->td[0];
2974
2975         /*
2976          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2977          * until we've finished creating all the other TRBs.  The ring's cycle
2978          * state may change as we enqueue the other TRBs, so save it too.
2979          */
2980         start_trb = &ep_ring->enqueue->generic;
2981         start_cycle = ep_ring->cycle_state;
2982
2983         running_total = 0;
2984         total_packet_count = roundup(urb->transfer_buffer_length,
2985                         usb_endpoint_maxp(&urb->ep->desc));
2986         /* How much data is in the first TRB? */
2987         addr = (u64) urb->transfer_dma;
2988         trb_buff_len = TRB_MAX_BUFF_SIZE -
2989                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2990         if (trb_buff_len > urb->transfer_buffer_length)
2991                 trb_buff_len = urb->transfer_buffer_length;
2992
2993         first_trb = true;
2994
2995         /* Queue the first TRB, even if it's zero-length */
2996         do {
2997                 u32 remainder = 0;
2998                 field = 0;
2999
3000                 /* Don't change the cycle bit of the first TRB until later */
3001                 if (first_trb) {
3002                         first_trb = false;
3003                         if (start_cycle == 0)
3004                                 field |= 0x1;
3005                 } else
3006                         field |= ep_ring->cycle_state;
3007
3008                 /* Chain all the TRBs together; clear the chain bit in the last
3009                  * TRB to indicate it's the last TRB in the chain.
3010                  */
3011                 if (num_trbs > 1) {
3012                         field |= TRB_CHAIN;
3013                 } else {
3014                         /* FIXME - add check for ZERO_PACKET flag before this */
3015                         td->last_trb = ep_ring->enqueue;
3016                         field |= TRB_IOC;
3017                 }
3018
3019                 /* Only set interrupt on short packet for IN endpoints */
3020                 if (usb_urb_dir_in(urb))
3021                         field |= TRB_ISP;
3022
3023                 /* Set the TRB length, TD size, and interrupter fields. */
3024                 if (xhci->hci_version < 0x100) {
3025                         remainder = xhci_td_remainder(
3026                                         urb->transfer_buffer_length -
3027                                         running_total);
3028                 } else {
3029                         remainder = xhci_v1_0_td_remainder(running_total,
3030                                         trb_buff_len, total_packet_count, urb);
3031                 }
3032                 length_field = TRB_LEN(trb_buff_len) |
3033                         remainder |
3034                         TRB_INTR_TARGET(0);
3035
3036                 if (num_trbs > 1)
3037                         more_trbs_coming = true;
3038                 else
3039                         more_trbs_coming = false;
3040                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3041                                 lower_32_bits(addr),
3042                                 upper_32_bits(addr),
3043                                 length_field,
3044                                 field | TRB_TYPE(TRB_NORMAL));
3045                 --num_trbs;
3046                 running_total += trb_buff_len;
3047
3048                 /* Calculate length for next transfer */
3049                 addr += trb_buff_len;
3050                 trb_buff_len = urb->transfer_buffer_length - running_total;
3051                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3052                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3053         } while (running_total < urb->transfer_buffer_length);
3054
3055         check_trb_math(urb, num_trbs, running_total);
3056         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3057                         start_cycle, start_trb);
3058         return 0;
3059 }
3060
3061 /* Caller must have locked xhci->lock */
3062 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3063                 struct urb *urb, int slot_id, unsigned int ep_index)
3064 {
3065         struct xhci_ring *ep_ring;
3066         int num_trbs;
3067         int ret;
3068         struct usb_ctrlrequest *setup;
3069         struct xhci_generic_trb *start_trb;
3070         int start_cycle;
3071         u32 field, length_field;
3072         struct urb_priv *urb_priv;
3073         struct xhci_td *td;
3074
3075         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3076         if (!ep_ring)
3077                 return -EINVAL;
3078
3079         /*
3080          * Need to copy setup packet into setup TRB, so we can't use the setup
3081          * DMA address.
3082          */
3083         if (!urb->setup_packet)
3084                 return -EINVAL;
3085
3086         if (!in_interrupt())
3087                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3088                                 slot_id, ep_index);
3089         /* 1 TRB for setup, 1 for status */
3090         num_trbs = 2;
3091         /*
3092          * Don't need to check if we need additional event data and normal TRBs,
3093          * since data in control transfers will never get bigger than 16MB
3094          * XXX: can we get a buffer that crosses 64KB boundaries?
3095          */
3096         if (urb->transfer_buffer_length > 0)
3097                 num_trbs++;
3098         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3099                         ep_index, urb->stream_id,
3100                         num_trbs, urb, 0, false, mem_flags);
3101         if (ret < 0)
3102                 return ret;
3103
3104         urb_priv = urb->hcpriv;
3105         td = urb_priv->td[0];
3106
3107         /*
3108          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3109          * until we've finished creating all the other TRBs.  The ring's cycle
3110          * state may change as we enqueue the other TRBs, so save it too.
3111          */
3112         start_trb = &ep_ring->enqueue->generic;
3113         start_cycle = ep_ring->cycle_state;
3114
3115         /* Queue setup TRB - see section 6.4.1.2.1 */
3116         /* FIXME better way to translate setup_packet into two u32 fields? */
3117         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3118         field = 0;
3119         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3120         if (start_cycle == 0)
3121                 field |= 0x1;
3122
3123         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3124         if (xhci->hci_version == 0x100) {
3125                 if (urb->transfer_buffer_length > 0) {
3126                         if (setup->bRequestType & USB_DIR_IN)
3127                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3128                         else
3129                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3130                 }
3131         }
3132
3133         queue_trb(xhci, ep_ring, false, true, false,
3134                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3135                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3136                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3137                   /* Immediate data in pointer */
3138                   field);
3139
3140         /* If there's data, queue data TRBs */
3141         /* Only set interrupt on short packet for IN endpoints */
3142         if (usb_urb_dir_in(urb))
3143                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3144         else
3145                 field = TRB_TYPE(TRB_DATA);
3146
3147         length_field = TRB_LEN(urb->transfer_buffer_length) |
3148                 xhci_td_remainder(urb->transfer_buffer_length) |
3149                 TRB_INTR_TARGET(0);
3150         if (urb->transfer_buffer_length > 0) {
3151                 if (setup->bRequestType & USB_DIR_IN)
3152                         field |= TRB_DIR_IN;
3153                 queue_trb(xhci, ep_ring, false, true, false,
3154                                 lower_32_bits(urb->transfer_dma),
3155                                 upper_32_bits(urb->transfer_dma),
3156                                 length_field,
3157                                 field | ep_ring->cycle_state);
3158         }
3159
3160         /* Save the DMA address of the last TRB in the TD */
3161         td->last_trb = ep_ring->enqueue;
3162
3163         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3164         /* If the device sent data, the status stage is an OUT transfer */
3165         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3166                 field = 0;
3167         else
3168                 field = TRB_DIR_IN;
3169         queue_trb(xhci, ep_ring, false, false, false,
3170                         0,
3171                         0,
3172                         TRB_INTR_TARGET(0),
3173                         /* Event on completion */
3174                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3175
3176         giveback_first_trb(xhci, slot_id, ep_index, 0,
3177                         start_cycle, start_trb);
3178         return 0;
3179 }
3180
3181 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3182                 struct urb *urb, int i)
3183 {
3184         int num_trbs = 0;
3185         u64 addr, td_len;
3186
3187         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3188         td_len = urb->iso_frame_desc[i].length;
3189
3190         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3191                         TRB_MAX_BUFF_SIZE);
3192         if (num_trbs == 0)
3193                 num_trbs++;
3194
3195         return num_trbs;
3196 }
3197
3198 /*
3199  * The transfer burst count field of the isochronous TRB defines the number of
3200  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3201  * devices can burst up to bMaxBurst number of packets per service interval.
3202  * This field is zero based, meaning a value of zero in the field means one
3203  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3204  * zero.  Only xHCI 1.0 host controllers support this field.
3205  */
3206 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3207                 struct usb_device *udev,
3208                 struct urb *urb, unsigned int total_packet_count)
3209 {
3210         unsigned int max_burst;
3211
3212         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3213                 return 0;
3214
3215         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3216         return roundup(total_packet_count, max_burst + 1) - 1;
3217 }
3218
3219 /*
3220  * Returns the number of packets in the last "burst" of packets.  This field is
3221  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3222  * the last burst packet count is equal to the total number of packets in the
3223  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3224  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3225  * contain 1 to (bMaxBurst + 1) packets.
3226  */
3227 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3228                 struct usb_device *udev,
3229                 struct urb *urb, unsigned int total_packet_count)
3230 {
3231         unsigned int max_burst;
3232         unsigned int residue;
3233
3234         if (xhci->hci_version < 0x100)
3235                 return 0;
3236
3237         switch (udev->speed) {
3238         case USB_SPEED_SUPER:
3239                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3240                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3241                 residue = total_packet_count % (max_burst + 1);
3242                 /* If residue is zero, the last burst contains (max_burst + 1)
3243                  * number of packets, but the TLBPC field is zero-based.
3244                  */
3245                 if (residue == 0)
3246                         return max_burst;
3247                 return residue - 1;
3248         default:
3249                 if (total_packet_count == 0)
3250                         return 0;
3251                 return total_packet_count - 1;
3252         }
3253 }
3254
3255 /* This is for isoc transfer */
3256 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3257                 struct urb *urb, int slot_id, unsigned int ep_index)
3258 {
3259         struct xhci_ring *ep_ring;
3260         struct urb_priv *urb_priv;
3261         struct xhci_td *td;
3262         int num_tds, trbs_per_td;
3263         struct xhci_generic_trb *start_trb;
3264         bool first_trb;
3265         int start_cycle;
3266         u32 field, length_field;
3267         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3268         u64 start_addr, addr;
3269         int i, j;
3270         bool more_trbs_coming;
3271
3272         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3273
3274         num_tds = urb->number_of_packets;
3275         if (num_tds < 1) {
3276                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3277                 return -EINVAL;
3278         }
3279
3280         if (!in_interrupt())
3281                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3282                                 " addr = %#llx, num_tds = %d\n",
3283                                 urb->ep->desc.bEndpointAddress,
3284                                 urb->transfer_buffer_length,
3285                                 urb->transfer_buffer_length,
3286                                 (unsigned long long)urb->transfer_dma,
3287                                 num_tds);
3288
3289         start_addr = (u64) urb->transfer_dma;
3290         start_trb = &ep_ring->enqueue->generic;
3291         start_cycle = ep_ring->cycle_state;
3292
3293         urb_priv = urb->hcpriv;
3294         /* Queue the first TRB, even if it's zero-length */
3295         for (i = 0; i < num_tds; i++) {
3296                 unsigned int total_packet_count;
3297                 unsigned int burst_count;
3298                 unsigned int residue;
3299
3300                 first_trb = true;
3301                 running_total = 0;
3302                 addr = start_addr + urb->iso_frame_desc[i].offset;
3303                 td_len = urb->iso_frame_desc[i].length;
3304                 td_remain_len = td_len;
3305                 total_packet_count = roundup(td_len,
3306                                 usb_endpoint_maxp(&urb->ep->desc));
3307                 /* A zero-length transfer still involves at least one packet. */
3308                 if (total_packet_count == 0)
3309                         total_packet_count++;
3310                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3311                                 total_packet_count);
3312                 residue = xhci_get_last_burst_packet_count(xhci,
3313                                 urb->dev, urb, total_packet_count);
3314
3315                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3316
3317                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3318                                 urb->stream_id, trbs_per_td, urb, i, true,
3319                                 mem_flags);
3320                 if (ret < 0) {
3321                         if (i == 0)
3322                                 return ret;
3323                         goto cleanup;
3324                 }
3325
3326                 td = urb_priv->td[i];
3327                 for (j = 0; j < trbs_per_td; j++) {
3328                         u32 remainder = 0;
3329                         field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3330
3331                         if (first_trb) {
3332                                 /* Queue the isoc TRB */
3333                                 field |= TRB_TYPE(TRB_ISOC);
3334                                 /* Assume URB_ISO_ASAP is set */
3335                                 field |= TRB_SIA;
3336                                 if (i == 0) {
3337                                         if (start_cycle == 0)
3338                                                 field |= 0x1;
3339                                 } else
3340                                         field |= ep_ring->cycle_state;
3341                                 first_trb = false;
3342                         } else {
3343                                 /* Queue other normal TRBs */
3344                                 field |= TRB_TYPE(TRB_NORMAL);
3345                                 field |= ep_ring->cycle_state;
3346                         }
3347
3348                         /* Only set interrupt on short packet for IN EPs */
3349                         if (usb_urb_dir_in(urb))
3350                                 field |= TRB_ISP;
3351
3352                         /* Chain all the TRBs together; clear the chain bit in
3353                          * the last TRB to indicate it's the last TRB in the
3354                          * chain.
3355                          */
3356                         if (j < trbs_per_td - 1) {
3357                                 field |= TRB_CHAIN;
3358                                 more_trbs_coming = true;
3359                         } else {
3360                                 td->last_trb = ep_ring->enqueue;
3361                                 field |= TRB_IOC;
3362                                 if (xhci->hci_version == 0x100) {
3363                                         /* Set BEI bit except for the last td */
3364                                         if (i < num_tds - 1)
3365                                                 field |= TRB_BEI;
3366                                 }
3367                                 more_trbs_coming = false;
3368                         }
3369
3370                         /* Calculate TRB length */
3371                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3372                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3373                         if (trb_buff_len > td_remain_len)
3374                                 trb_buff_len = td_remain_len;
3375
3376                         /* Set the TRB length, TD size, & interrupter fields. */
3377                         if (xhci->hci_version < 0x100) {
3378                                 remainder = xhci_td_remainder(
3379                                                 td_len - running_total);
3380                         } else {
3381                                 remainder = xhci_v1_0_td_remainder(
3382                                                 running_total, trb_buff_len,
3383                                                 total_packet_count, urb);
3384                         }
3385                         length_field = TRB_LEN(trb_buff_len) |
3386                                 remainder |
3387                                 TRB_INTR_TARGET(0);
3388
3389                         queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3390                                 lower_32_bits(addr),
3391                                 upper_32_bits(addr),
3392                                 length_field,
3393                                 field);
3394                         running_total += trb_buff_len;
3395
3396                         addr += trb_buff_len;
3397                         td_remain_len -= trb_buff_len;
3398                 }
3399
3400                 /* Check TD length */
3401                 if (running_total != td_len) {
3402                         xhci_err(xhci, "ISOC TD length unmatch\n");
3403                         ret = -EINVAL;
3404                         goto cleanup;
3405                 }
3406         }
3407
3408         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3409                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3410                         usb_amd_quirk_pll_disable();
3411         }
3412         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3413
3414         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3415                         start_cycle, start_trb);
3416         return 0;
3417 cleanup:
3418         /* Clean up a partially enqueued isoc transfer. */
3419
3420         for (i--; i >= 0; i--)
3421                 list_del_init(&urb_priv->td[i]->td_list);
3422
3423         /* Use the first TD as a temporary variable to turn the TDs we've queued
3424          * into No-ops with a software-owned cycle bit. That way the hardware
3425          * won't accidentally start executing bogus TDs when we partially
3426          * overwrite them.  td->first_trb and td->start_seg are already set.
3427          */
3428         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3429         /* Every TRB except the first & last will have its cycle bit flipped. */
3430         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3431
3432         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3433         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3434         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3435         ep_ring->cycle_state = start_cycle;
3436         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3437         return ret;
3438 }
3439
3440 /*
3441  * Check transfer ring to guarantee there is enough room for the urb.
3442  * Update ISO URB start_frame and interval.
3443  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3444  * update the urb->start_frame by now.
3445  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3446  */
3447 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3448                 struct urb *urb, int slot_id, unsigned int ep_index)
3449 {
3450         struct xhci_virt_device *xdev;
3451         struct xhci_ring *ep_ring;
3452         struct xhci_ep_ctx *ep_ctx;
3453         int start_frame;
3454         int xhci_interval;
3455         int ep_interval;
3456         int num_tds, num_trbs, i;
3457         int ret;
3458
3459         xdev = xhci->devs[slot_id];
3460         ep_ring = xdev->eps[ep_index].ring;
3461         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3462
3463         num_trbs = 0;
3464         num_tds = urb->number_of_packets;
3465         for (i = 0; i < num_tds; i++)
3466                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3467
3468         /* Check the ring to guarantee there is enough room for the whole urb.
3469          * Do not insert any td of the urb to the ring if the check failed.
3470          */
3471         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3472                            num_trbs, true, mem_flags);
3473         if (ret)
3474                 return ret;
3475
3476         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3477         start_frame &= 0x3fff;
3478
3479         urb->start_frame = start_frame;
3480         if (urb->dev->speed == USB_SPEED_LOW ||
3481                         urb->dev->speed == USB_SPEED_FULL)
3482                 urb->start_frame >>= 3;
3483
3484         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3485         ep_interval = urb->interval;
3486         /* Convert to microframes */
3487         if (urb->dev->speed == USB_SPEED_LOW ||
3488                         urb->dev->speed == USB_SPEED_FULL)
3489                 ep_interval *= 8;
3490         /* FIXME change this to a warning and a suggestion to use the new API
3491          * to set the polling interval (once the API is added).
3492          */
3493         if (xhci_interval != ep_interval) {
3494                 if (printk_ratelimit())
3495                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3496                                         " (%d microframe%s) than xHCI "
3497                                         "(%d microframe%s)\n",
3498                                         ep_interval,
3499                                         ep_interval == 1 ? "" : "s",
3500                                         xhci_interval,
3501                                         xhci_interval == 1 ? "" : "s");
3502                 urb->interval = xhci_interval;
3503                 /* Convert back to frames for LS/FS devices */
3504                 if (urb->dev->speed == USB_SPEED_LOW ||
3505                                 urb->dev->speed == USB_SPEED_FULL)
3506                         urb->interval /= 8;
3507         }
3508         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3509 }
3510
3511 /****           Command Ring Operations         ****/
3512
3513 /* Generic function for queueing a command TRB on the command ring.
3514  * Check to make sure there's room on the command ring for one command TRB.
3515  * Also check that there's room reserved for commands that must not fail.
3516  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3517  * then only check for the number of reserved spots.
3518  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3519  * because the command event handler may want to resubmit a failed command.
3520  */
3521 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3522                 u32 field3, u32 field4, bool command_must_succeed)
3523 {
3524         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3525         int ret;
3526
3527         if (!command_must_succeed)
3528                 reserved_trbs++;
3529
3530         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3531                         reserved_trbs, false, GFP_ATOMIC);
3532         if (ret < 0) {
3533                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3534                 if (command_must_succeed)
3535                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3536                                         "unfailable commands failed.\n");
3537                 return ret;
3538         }
3539         queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3540                         field3, field4 | xhci->cmd_ring->cycle_state);
3541         return 0;
3542 }
3543
3544 /* Queue a slot enable or disable request on the command ring */
3545 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3546 {
3547         return queue_command(xhci, 0, 0, 0,
3548                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3549 }
3550
3551 /* Queue an address device command TRB */
3552 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3553                 u32 slot_id)
3554 {
3555         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3556                         upper_32_bits(in_ctx_ptr), 0,
3557                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3558                         false);
3559 }
3560
3561 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3562                 u32 field1, u32 field2, u32 field3, u32 field4)
3563 {
3564         return queue_command(xhci, field1, field2, field3, field4, false);
3565 }
3566
3567 /* Queue a reset device command TRB */
3568 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3569 {
3570         return queue_command(xhci, 0, 0, 0,
3571                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3572                         false);
3573 }
3574
3575 /* Queue a configure endpoint command TRB */
3576 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3577                 u32 slot_id, bool command_must_succeed)
3578 {
3579         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3580                         upper_32_bits(in_ctx_ptr), 0,
3581                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3582                         command_must_succeed);
3583 }
3584
3585 /* Queue an evaluate context command TRB */
3586 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3587                 u32 slot_id)
3588 {
3589         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3590                         upper_32_bits(in_ctx_ptr), 0,
3591                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3592                         false);
3593 }
3594
3595 /*
3596  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3597  * activity on an endpoint that is about to be suspended.
3598  */
3599 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3600                 unsigned int ep_index, int suspend)
3601 {
3602         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3603         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3604         u32 type = TRB_TYPE(TRB_STOP_RING);
3605         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3606
3607         return queue_command(xhci, 0, 0, 0,
3608                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3609 }
3610
3611 /* Set Transfer Ring Dequeue Pointer command.
3612  * This should not be used for endpoints that have streams enabled.
3613  */
3614 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3615                 unsigned int ep_index, unsigned int stream_id,
3616                 struct xhci_segment *deq_seg,
3617                 union xhci_trb *deq_ptr, u32 cycle_state)
3618 {
3619         dma_addr_t addr;
3620         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3621         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3622         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3623         u32 type = TRB_TYPE(TRB_SET_DEQ);
3624         struct xhci_virt_ep *ep;
3625
3626         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3627         if (addr == 0) {
3628                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3629                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3630                                 deq_seg, deq_ptr);
3631                 return 0;
3632         }
3633         ep = &xhci->devs[slot_id]->eps[ep_index];
3634         if ((ep->ep_state & SET_DEQ_PENDING)) {
3635                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3636                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3637                 return 0;
3638         }
3639         ep->queued_deq_seg = deq_seg;
3640         ep->queued_deq_ptr = deq_ptr;
3641         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3642                         upper_32_bits(addr), trb_stream_id,
3643                         trb_slot_id | trb_ep_index | type, false);
3644 }
3645
3646 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3647                 unsigned int ep_index)
3648 {
3649         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3650         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3651         u32 type = TRB_TYPE(TRB_RESET_EP);
3652
3653         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3654                         false);
3655 }