drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 147 {
 148         unsigned long long addr;
 149
 150         ring->deq_updates++;
 151
 152         /*
 153          * If this is not event ring, and the dequeue pointer
 154          * is not on a link TRB, there is one more usable TRB
 155          */
 156         if (ring->type != TYPE_EVENT &&
 157                         !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
 158                 ring->num_trbs_free++;
 159
 160         do {
 161                 /*
 162                  * Update the dequeue pointer further if that was a link TRB or
 163                  * we're at the end of an event ring segment (which doesn't have
 164                  * link TRBS)
 165                  */
 166                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 167                         if (ring->type == TYPE_EVENT &&
 168                                         last_trb_on_last_seg(xhci, ring,
 169                                                 ring->deq_seg, ring->dequeue)) {
 170                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 171                         }
 172                         ring->deq_seg = ring->deq_seg->next;
 173                         ring->dequeue = ring->deq_seg->trbs;
 174                 } else {
 175                         ring->dequeue++;
 176                 }
 177         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 178
 179         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 180 }
 181
 182 /*
 183  * See Cycle bit rules. SW is the consumer for the event ring only.
 184  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 185  *
 186  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 187  * chain bit is set), then set the chain bit in all the following link TRBs.
 188  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 189  * have their chain bit cleared (so that each Link TRB is a separate TD).
 190  *
 191  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 192  * set, but other sections talk about dealing with the chain bit set.  This was
 193  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 194  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 195  *
 196  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 197  *                      prepare_transfer()?
 198  */
 199 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 200                         bool more_trbs_coming)
 201 {
 202         u32 chain;
 203         union xhci_trb *next;
 204         unsigned long long addr;
 205
 206         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 207         /* If this is not event ring, there is one less usable TRB */
 208         if (ring->type != TYPE_EVENT &&
 209                         !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
 210                 ring->num_trbs_free--;
 211         next = ++(ring->enqueue);
 212
 213         ring->enq_updates++;
 214         /* Update the dequeue pointer further if that was a link TRB or we're at
 215          * the end of an event ring segment (which doesn't have link TRBS)
 216          */
 217         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 218                 if (ring->type != TYPE_EVENT) {
 219                         /*
 220                          * If the caller doesn't plan on enqueueing more
 221                          * TDs before ringing the doorbell, then we
 222                          * don't want to give the link TRB to the
 223                          * hardware just yet.  We'll give the link TRB
 224                          * back in prepare_ring() just before we enqueue
 225                          * the TD at the top of the ring.
 226                          */
 227                         if (!chain && !more_trbs_coming)
 228                                 break;
 229
 230                         /* If we're not dealing with 0.95 hardware or
 231                          * isoc rings on AMD 0.96 host,
 232                          * carry over the chain bit of the previous TRB
 233                          * (which may mean the chain bit is cleared).
 234                          */
 235                         if (!(ring->type == TYPE_ISOC &&
 236                                         (xhci->quirks & XHCI_AMD_0x96_HOST))
 237                                                 && !xhci_link_trb_quirk(xhci)) {
 238                                 next->link.control &=
 239                                         cpu_to_le32(~TRB_CHAIN);
 240                                 next->link.control |=
 241                                         cpu_to_le32(chain);
 242                         }
 243                         /* Give this link TRB to the hardware */
 244                         wmb();
 245                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
 246
 247                         /* Toggle the cycle bit after the last ring segment. */
 248                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 249                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 250                         }
 251                 }
 252                 ring->enq_seg = ring->enq_seg->next;
 253                 ring->enqueue = ring->enq_seg->trbs;
 254                 next = ring->enqueue;
 255         }
 256         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 257 }
 258
 259 /*
 260  * Check to see if there's room to enqueue num_trbs on the ring and make sure
 261  * enqueue pointer will not advance into dequeue segment. See rules above.
 262  */
 263 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 264                 unsigned int num_trbs)
 265 {
 266         int num_trbs_in_deq_seg;
 267
 268         if (ring->num_trbs_free < num_trbs)
 269                 return 0;
 270
 271         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 272                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 273                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 274                         return 0;
 275         }
 276
 277         return 1;
 278 }
 279
 280 /* Ring the host controller doorbell after placing a command on the ring */
 281 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 282 {
 283         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 284                 return;
 285
 286         xhci_dbg(xhci, "// Ding dong!\n");
 287         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 288         /* Flush PCI posted writes */
 289         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 290 }
 291
 292 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 293 {
 294         u64 temp_64;
 295         int ret;
 296
 297         xhci_dbg(xhci, "Abort command ring\n");
 298
 299         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 300                 xhci_dbg(xhci, "The command ring isn't running, "
 301                                 "Have the command ring been stopped?\n");
 302                 return 0;
 303         }
 304
 305         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 306         if (!(temp_64 & CMD_RING_RUNNING)) {
 307                 xhci_dbg(xhci, "Command ring had been stopped\n");
 308                 return 0;
 309         }
 310         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 311         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 312                         &xhci->op_regs->cmd_ring);
 313
 314         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 315          * time the completion od all xHCI commands, including
 316          * the Command Abort operation. If software doesn't see
 317          * CRR negated in a timely manner (e.g. longer than 5
 318          * seconds), then it should assume that the there are
 319          * larger problems with the xHC and assert HCRST.
 320          */
 321         ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
 322                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 323         if (ret < 0) {
 324                 xhci_err(xhci, "Stopped the command ring failed, "
 325                                 "maybe the host is dead\n");
 326                 xhci->xhc_state |= XHCI_STATE_DYING;
 327                 xhci_quiesce(xhci);
 328                 xhci_halt(xhci);
 329                 return -ESHUTDOWN;
 330         }
 331
 332         return 0;
 333 }
 334
 335 static int xhci_queue_cd(struct xhci_hcd *xhci,
 336                 struct xhci_command *command,
 337                 union xhci_trb *cmd_trb)
 338 {
 339         struct xhci_cd *cd;
 340         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 341         if (!cd)
 342                 return -ENOMEM;
 343         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 344
 345         cd->command = command;
 346         cd->cmd_trb = cmd_trb;
 347         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 348
 349         return 0;
 350 }
 351
 352 /*
 353  * Cancel the command which has issue.
 354  *
 355  * Some commands may hang due to waiting for acknowledgement from
 356  * usb device. It is outside of the xHC's ability to control and
 357  * will cause the command ring is blocked. When it occurs software
 358  * should intervene to recover the command ring.
 359  * See Section 4.6.1.1 and 4.6.1.2
 360  */
 361 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 362                 union xhci_trb *cmd_trb)
 363 {
 364         int retval = 0;
 365         unsigned long flags;
 366
 367         spin_lock_irqsave(&xhci->lock, flags);
 368
 369         if (xhci->xhc_state & XHCI_STATE_DYING) {
 370                 xhci_warn(xhci, "Abort the command ring,"
 371                                 " but the xHCI is dead.\n");
 372                 retval = -ESHUTDOWN;
 373                 goto fail;
 374         }
 375
 376         /* queue the cmd desriptor to cancel_cmd_list */
 377         retval = xhci_queue_cd(xhci, command, cmd_trb);
 378         if (retval) {
 379                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 380                 goto fail;
 381         }
 382
 383         /* abort command ring */
 384         retval = xhci_abort_cmd_ring(xhci);
 385         if (retval) {
 386                 xhci_err(xhci, "Abort command ring failed\n");
 387                 if (unlikely(retval == -ESHUTDOWN)) {
 388                         spin_unlock_irqrestore(&xhci->lock, flags);
 389                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 390                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 391                         return retval;
 392                 }
 393         }
 394
 395 fail:
 396         spin_unlock_irqrestore(&xhci->lock, flags);
 397         return retval;
 398 }
 399
 400 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 401                 unsigned int slot_id,
 402                 unsigned int ep_index,
 403                 unsigned int stream_id)
 404 {
 405         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 406         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 407         unsigned int ep_state = ep->ep_state;
 408
 409         /* Don't ring the doorbell for this endpoint if there are pending
 410          * cancellations because we don't want to interrupt processing.
 411          * We don't want to restart any stream rings if there's a set dequeue
 412          * pointer command pending because the device can choose to start any
 413          * stream once the endpoint is on the HW schedule.
 414          * FIXME - check all the stream rings for pending cancellations.
 415          */
 416         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 417             (ep_state & EP_HALTED))
 418                 return;
 419         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 420         /* The CPU has better things to do at this point than wait for a
 421          * write-posting flush.  It'll get there soon enough.
 422          */
 423 }
 424
 425 /* Ring the doorbell for any rings with pending URBs */
 426 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 427                 unsigned int slot_id,
 428                 unsigned int ep_index)
 429 {
 430         unsigned int stream_id;
 431         struct xhci_virt_ep *ep;
 432
 433         ep = &xhci->devs[slot_id]->eps[ep_index];
 434
 435         /* A ring has pending URBs if its TD list is not empty */
 436         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 437                 if (!(list_empty(&ep->ring->td_list)))
 438                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 439                 return;
 440         }
 441
 442         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 443                         stream_id++) {
 444                 struct xhci_stream_info *stream_info = ep->stream_info;
 445                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 446                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 447                                                 stream_id);
 448         }
 449 }
 450
 451 /*
 452  * Find the segment that trb is in.  Start searching in start_seg.
 453  * If we must move past a segment that has a link TRB with a toggle cycle state
 454  * bit set, then we will toggle the value pointed at by cycle_state.
 455  */
 456 static struct xhci_segment *find_trb_seg(
 457                 struct xhci_segment *start_seg,
 458                 union xhci_trb  *trb, int *cycle_state)
 459 {
 460         struct xhci_segment *cur_seg = start_seg;
 461         struct xhci_generic_trb *generic_trb;
 462
 463         while (cur_seg->trbs > trb ||
 464                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 465                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 466                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 467                         *cycle_state ^= 0x1;
 468                 cur_seg = cur_seg->next;
 469                 if (cur_seg == start_seg)
 470                         /* Looped over the entire list.  Oops! */
 471                         return NULL;
 472         }
 473         return cur_seg;
 474 }
 475
 476
 477 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 478                 unsigned int slot_id, unsigned int ep_index,
 479                 unsigned int stream_id)
 480 {
 481         struct xhci_virt_ep *ep;
 482
 483         ep = &xhci->devs[slot_id]->eps[ep_index];
 484         /* Common case: no streams */
 485         if (!(ep->ep_state & EP_HAS_STREAMS))
 486                 return ep->ring;
 487
 488         if (stream_id == 0) {
 489                 xhci_warn(xhci,
 490                                 "WARN: Slot ID %u, ep index %u has streams, "
 491                                 "but URB has no stream ID.\n",
 492                                 slot_id, ep_index);
 493                 return NULL;
 494         }
 495
 496         if (stream_id < ep->stream_info->num_streams)
 497                 return ep->stream_info->stream_rings[stream_id];
 498
 499         xhci_warn(xhci,
 500                         "WARN: Slot ID %u, ep index %u has "
 501                         "stream IDs 1 to %u allocated, "
 502                         "but stream ID %u is requested.\n",
 503                         slot_id, ep_index,
 504                         ep->stream_info->num_streams - 1,
 505                         stream_id);
 506         return NULL;
 507 }
 508
 509 /* Get the right ring for the given URB.
 510  * If the endpoint supports streams, boundary check the URB's stream ID.
 511  * If the endpoint doesn't support streams, return the singular endpoint ring.
 512  */
 513 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 514                 struct urb *urb)
 515 {
 516         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 517                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 518 }
 519
 520 /*
 521  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 522  * Record the new state of the xHC's endpoint ring dequeue segment,
 523  * dequeue pointer, and new consumer cycle state in state.
 524  * Update our internal representation of the ring's dequeue pointer.
 525  *
 526  * We do this in three jumps:
 527  *  - First we update our new ring state to be the same as when the xHC stopped.
 528  *  - Then we traverse the ring to find the segment that contains
 529  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 530  *    any link TRBs with the toggle cycle bit set.
 531  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 532  *    if we've moved it past a link TRB with the toggle cycle bit set.
 533  *
 534  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 535  * with correct __le32 accesses they should work fine.  Only users of this are
 536  * in here.
 537  */
 538 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 539                 unsigned int slot_id, unsigned int ep_index,
 540                 unsigned int stream_id, struct xhci_td *cur_td,
 541                 struct xhci_dequeue_state *state)
 542 {
 543         struct xhci_virt_device *dev = xhci->devs[slot_id];
 544         struct xhci_ring *ep_ring;
 545         struct xhci_generic_trb *trb;
 546         struct xhci_ep_ctx *ep_ctx;
 547         dma_addr_t addr;
 548
 549         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 550                         ep_index, stream_id);
 551         if (!ep_ring) {
 552                 xhci_warn(xhci, "WARN can't find new dequeue state "
 553                                 "for invalid stream ID %u.\n",
 554                                 stream_id);
 555                 return;
 556         }
 557         state->new_cycle_state = 0;
 558         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 559         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 560                         dev->eps[ep_index].stopped_trb,
 561                         &state->new_cycle_state);
 562         if (!state->new_deq_seg) {
 563                 WARN_ON(1);
 564                 return;
 565         }
 566
 567         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 568         xhci_dbg(xhci, "Finding endpoint context\n");
 569         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 570         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 571
 572         state->new_deq_ptr = cur_td->last_trb;
 573         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 574         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 575                         state->new_deq_ptr,
 576                         &state->new_cycle_state);
 577         if (!state->new_deq_seg) {
 578                 WARN_ON(1);
 579                 return;
 580         }
 581
 582         trb = &state->new_deq_ptr->generic;
 583         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 584             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 585                 state->new_cycle_state ^= 0x1;
 586         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 587
 588         /*
 589          * If there is only one segment in a ring, find_trb_seg()'s while loop
 590          * will not run, and it will return before it has a chance to see if it
 591          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 592          * ended just before the link TRB on a one-segment ring, or if the TD
 593          * wrapped around the top of the ring, because it doesn't have the TD in
 594          * question.  Look for the one-segment case where stalled TRB's address
 595          * is greater than the new dequeue pointer address.
 596          */
 597         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 598                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 599                 state->new_cycle_state ^= 0x1;
 600         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 601
 602         /* Don't update the ring cycle state for the producer (us). */
 603         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 604                         state->new_deq_seg);
 605         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 606         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 607                         (unsigned long long) addr);
 608 }
 609
 610 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 611  * (The last TRB actually points to the ring enqueue pointer, which is not part
 612  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 613  */
 614 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 615                 struct xhci_td *cur_td, bool flip_cycle)
 616 {
 617         struct xhci_segment *cur_seg;
 618         union xhci_trb *cur_trb;
 619
 620         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 621                         true;
 622                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 623                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 624                         /* Unchain any chained Link TRBs, but
 625                          * leave the pointers intact.
 626                          */
 627                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 628                         /* Flip the cycle bit (link TRBs can't be the first
 629                          * or last TRB).
 630                          */
 631                         if (flip_cycle)
 632                                 cur_trb->generic.field[3] ^=
 633                                         cpu_to_le32(TRB_CYCLE);
 634                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 635                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 636                                         "in seg %p (0x%llx dma)\n",
 637                                         cur_trb,
 638                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 639                                         cur_seg,
 640                                         (unsigned long long)cur_seg->dma);
 641                 } else {
 642                         cur_trb->generic.field[0] = 0;
 643                         cur_trb->generic.field[1] = 0;
 644                         cur_trb->generic.field[2] = 0;
 645                         /* Preserve only the cycle bit of this TRB */
 646                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 647                         /* Flip the cycle bit except on the first or last TRB */
 648                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 649                                         cur_trb != cur_td->last_trb)
 650                                 cur_trb->generic.field[3] ^=
 651                                         cpu_to_le32(TRB_CYCLE);
 652                         cur_trb->generic.field[3] |= cpu_to_le32(
 653                                 TRB_TYPE(TRB_TR_NOOP));
 654                         xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n",
 655                                         (unsigned long long)
 656                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 657                 }
 658                 if (cur_trb == cur_td->last_trb)
 659                         break;
 660         }
 661 }
 662
 663 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 664                 unsigned int ep_index, unsigned int stream_id,
 665                 struct xhci_segment *deq_seg,
 666                 union xhci_trb *deq_ptr, u32 cycle_state);
 667
 668 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 669                 unsigned int slot_id, unsigned int ep_index,
 670                 unsigned int stream_id,
 671                 struct xhci_dequeue_state *deq_state)
 672 {
 673         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 674
 675         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 676                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 677                         deq_state->new_deq_seg,
 678                         (unsigned long long)deq_state->new_deq_seg->dma,
 679                         deq_state->new_deq_ptr,
 680                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 681                         deq_state->new_cycle_state);
 682         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 683                         deq_state->new_deq_seg,
 684                         deq_state->new_deq_ptr,
 685                         (u32) deq_state->new_cycle_state);
 686         /* Stop the TD queueing code from ringing the doorbell until
 687          * this command completes.  The HC won't set the dequeue pointer
 688          * if the ring is running, and ringing the doorbell starts the
 689          * ring running.
 690          */
 691         ep->ep_state |= SET_DEQ_PENDING;
 692 }
 693
 694 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 695                 struct xhci_virt_ep *ep)
 696 {
 697         ep->ep_state &= ~EP_HALT_PENDING;
 698         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 699          * timer is running on another CPU, we don't decrement stop_cmds_pending
 700          * (since we didn't successfully stop the watchdog timer).
 701          */
 702         if (del_timer(&ep->stop_cmd_timer))
 703                 ep->stop_cmds_pending--;
 704 }
 705
 706 /* Must be called with xhci->lock held in interrupt context */
 707 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 708                 struct xhci_td *cur_td, int status, char *adjective)
 709 {
 710         struct usb_hcd *hcd;
 711         struct urb      *urb;
 712         struct urb_priv *urb_priv;
 713
 714         urb = cur_td->urb;
 715         urb_priv = urb->hcpriv;
 716         urb_priv->td_cnt++;
 717         hcd = bus_to_hcd(urb->dev->bus);
 718
 719         /* Only giveback urb when this is the last td in urb */
 720         if (urb_priv->td_cnt == urb_priv->length) {
 721                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 722                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 723                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 724                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 725                                         usb_amd_quirk_pll_enable();
 726                         }
 727                 }
 728                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 729
 730                 spin_unlock(&xhci->lock);
 731                 usb_hcd_giveback_urb(hcd, urb, status);
 732                 xhci_urb_free_priv(xhci, urb_priv);
 733                 spin_lock(&xhci->lock);
 734         }
 735 }
 736
 737 /*
 738  * When we get a command completion for a Stop Endpoint Command, we need to
 739  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 740  *
 741  *  1. If the HW was in the middle of processing the TD that needs to be
 742  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 743  *     in the TD with a Set Dequeue Pointer Command.
 744  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 745  *     bit cleared) so that the HW will skip over them.
 746  */
 747 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 748                 union xhci_trb *trb, struct xhci_event_cmd *event)
 749 {
 750         unsigned int slot_id;
 751         unsigned int ep_index;
 752         struct xhci_virt_device *virt_dev;
 753         struct xhci_ring *ep_ring;
 754         struct xhci_virt_ep *ep;
 755         struct list_head *entry;
 756         struct xhci_td *cur_td = NULL;
 757         struct xhci_td *last_unlinked_td;
 758
 759         struct xhci_dequeue_state deq_state;
 760
 761         if (unlikely(TRB_TO_SUSPEND_PORT(
 762                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 763                 slot_id = TRB_TO_SLOT_ID(
 764                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 765                 virt_dev = xhci->devs[slot_id];
 766                 if (virt_dev)
 767                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 768                                 event);
 769                 else
 770                         xhci_warn(xhci, "Stop endpoint command "
 771                                 "completion for disabled slot %u\n",
 772                                 slot_id);
 773                 return;
 774         }
 775
 776         memset(&deq_state, 0, sizeof(deq_state));
 777         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 778         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 779         ep = &xhci->devs[slot_id]->eps[ep_index];
 780
 781         if (list_empty(&ep->cancelled_td_list)) {
 782                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 783                 ep->stopped_td = NULL;
 784                 ep->stopped_trb = NULL;
 785                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 786                 return;
 787         }
 788
 789         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 790          * We have the xHCI lock, so nothing can modify this list until we drop
 791          * it.  We're also in the event handler, so we can't get re-interrupted
 792          * if another Stop Endpoint command completes
 793          */
 794         list_for_each(entry, &ep->cancelled_td_list) {
 795                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 796                 xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n",
 797                                 (unsigned long long)xhci_trb_virt_to_dma(
 798                                         cur_td->start_seg, cur_td->first_trb));
 799                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 800                 if (!ep_ring) {
 801                         /* This shouldn't happen unless a driver is mucking
 802                          * with the stream ID after submission.  This will
 803                          * leave the TD on the hardware ring, and the hardware
 804                          * will try to execute it, and may access a buffer
 805                          * that has already been freed.  In the best case, the
 806                          * hardware will execute it, and the event handler will
 807                          * ignore the completion event for that TD, since it was
 808                          * removed from the td_list for that endpoint.  In
 809                          * short, don't muck with the stream ID after
 810                          * submission.
 811                          */
 812                         xhci_warn(xhci, "WARN Cancelled URB %p "
 813                                         "has invalid stream ID %u.\n",
 814                                         cur_td->urb,
 815                                         cur_td->urb->stream_id);
 816                         goto remove_finished_td;
 817                 }
 818                 /*
 819                  * If we stopped on the TD we need to cancel, then we have to
 820                  * move the xHC endpoint ring dequeue pointer past this TD.
 821                  */
 822                 if (cur_td == ep->stopped_td)
 823                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 824                                         cur_td->urb->stream_id,
 825                                         cur_td, &deq_state);
 826                 else
 827                         td_to_noop(xhci, ep_ring, cur_td, false);
 828 remove_finished_td:
 829                 /*
 830                  * The event handler won't see a completion for this TD anymore,
 831                  * so remove it from the endpoint ring's TD list.  Keep it in
 832                  * the cancelled TD list for URB completion later.
 833                  */
 834                 list_del_init(&cur_td->td_list);
 835         }
 836         last_unlinked_td = cur_td;
 837         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 838
 839         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 840         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 841                 xhci_queue_new_dequeue_state(xhci,
 842                                 slot_id, ep_index,
 843                                 ep->stopped_td->urb->stream_id,
 844                                 &deq_state);
 845                 xhci_ring_cmd_db(xhci);
 846         } else {
 847                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 848                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 849         }
 850         ep->stopped_td = NULL;
 851         ep->stopped_trb = NULL;
 852
 853         /*
 854          * Drop the lock and complete the URBs in the cancelled TD list.
 855          * New TDs to be cancelled might be added to the end of the list before
 856          * we can complete all the URBs for the TDs we already unlinked.
 857          * So stop when we've completed the URB for the last TD we unlinked.
 858          */
 859         do {
 860                 cur_td = list_entry(ep->cancelled_td_list.next,
 861                                 struct xhci_td, cancelled_td_list);
 862                 list_del_init(&cur_td->cancelled_td_list);
 863
 864                 /* Clean up the cancelled URB */
 865                 /* Doesn't matter what we pass for status, since the core will
 866                  * just overwrite it (because the URB has been unlinked).
 867                  */
 868                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 869
 870                 /* Stop processing the cancelled list if the watchdog timer is
 871                  * running.
 872                  */
 873                 if (xhci->xhc_state & XHCI_STATE_DYING)
 874                         return;
 875         } while (cur_td != last_unlinked_td);
 876
 877         /* Return to the event handler with xhci->lock re-acquired */
 878 }
 879
 880 /* Watchdog timer function for when a stop endpoint command fails to complete.
 881  * In this case, we assume the host controller is broken or dying or dead.  The
 882  * host may still be completing some other events, so we have to be careful to
 883  * let the event ring handler and the URB dequeueing/enqueueing functions know
 884  * through xhci->state.
 885  *
 886  * The timer may also fire if the host takes a very long time to respond to the
 887  * command, and the stop endpoint command completion handler cannot delete the
 888  * timer before the timer function is called.  Another endpoint cancellation may
 889  * sneak in before the timer function can grab the lock, and that may queue
 890  * another stop endpoint command and add the timer back.  So we cannot use a
 891  * simple flag to say whether there is a pending stop endpoint command for a
 892  * particular endpoint.
 893  *
 894  * Instead we use a combination of that flag and a counter for the number of
 895  * pending stop endpoint commands.  If the timer is the tail end of the last
 896  * stop endpoint command, and the endpoint's command is still pending, we assume
 897  * the host is dying.
 898  */
 899 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 900 {
 901         struct xhci_hcd *xhci;
 902         struct xhci_virt_ep *ep;
 903         struct xhci_virt_ep *temp_ep;
 904         struct xhci_ring *ring;
 905         struct xhci_td *cur_td;
 906         int ret, i, j;
 907         unsigned long flags;
 908
 909         ep = (struct xhci_virt_ep *) arg;
 910         xhci = ep->xhci;
 911
 912         spin_lock_irqsave(&xhci->lock, flags);
 913
 914         ep->stop_cmds_pending--;
 915         if (xhci->xhc_state & XHCI_STATE_DYING) {
 916                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 917                                 "xHCI as DYING, exiting.\n");
 918                 spin_unlock_irqrestore(&xhci->lock, flags);
 919                 return;
 920         }
 921         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 922                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 923                                 "exiting.\n");
 924                 spin_unlock_irqrestore(&xhci->lock, flags);
 925                 return;
 926         }
 927
 928         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 929         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 930         /* Oops, HC is dead or dying or at least not responding to the stop
 931          * endpoint command.
 932          */
 933         xhci->xhc_state |= XHCI_STATE_DYING;
 934         /* Disable interrupts from the host controller and start halting it */
 935         xhci_quiesce(xhci);
 936         spin_unlock_irqrestore(&xhci->lock, flags);
 937
 938         ret = xhci_halt(xhci);
 939
 940         spin_lock_irqsave(&xhci->lock, flags);
 941         if (ret < 0) {
 942                 /* This is bad; the host is not responding to commands and it's
 943                  * not allowing itself to be halted.  At least interrupts are
 944                  * disabled. If we call usb_hc_died(), it will attempt to
 945                  * disconnect all device drivers under this host.  Those
 946                  * disconnect() methods will wait for all URBs to be unlinked,
 947                  * so we must complete them.
 948                  */
 949                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 950                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 951                 /* We could turn all TDs on the rings to no-ops.  This won't
 952                  * help if the host has cached part of the ring, and is slow if
 953                  * we want to preserve the cycle bit.  Skip it and hope the host
 954                  * doesn't touch the memory.
 955                  */
 956         }
 957         for (i = 0; i < MAX_HC_SLOTS; i++) {
 958                 if (!xhci->devs[i])
 959                         continue;
 960                 for (j = 0; j < 31; j++) {
 961                         temp_ep = &xhci->devs[i]->eps[j];
 962                         ring = temp_ep->ring;
 963                         if (!ring)
 964                                 continue;
 965                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 966                                         "ep index %u\n", i, j);
 967                         while (!list_empty(&ring->td_list)) {
 968                                 cur_td = list_first_entry(&ring->td_list,
 969                                                 struct xhci_td,
 970                                                 td_list);
 971                                 list_del_init(&cur_td->td_list);
 972                                 if (!list_empty(&cur_td->cancelled_td_list))
 973                                         list_del_init(&cur_td->cancelled_td_list);
 974                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 975                                                 -ESHUTDOWN, "killed");
 976                         }
 977                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 978                                 cur_td = list_first_entry(
 979                                                 &temp_ep->cancelled_td_list,
 980                                                 struct xhci_td,
 981                                                 cancelled_td_list);
 982                                 list_del_init(&cur_td->cancelled_td_list);
 983                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 984                                                 -ESHUTDOWN, "killed");
 985                         }
 986                 }
 987         }
 988         spin_unlock_irqrestore(&xhci->lock, flags);
 989         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 990         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 991         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 992 }
 993
 994
 995 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
 996                 struct xhci_virt_device *dev,
 997                 struct xhci_ring *ep_ring,
 998                 unsigned int ep_index)
 999 {
1000         union xhci_trb *dequeue_temp;
1001         int num_trbs_free_temp;
1002         bool revert = false;
1003
1004         num_trbs_free_temp = ep_ring->num_trbs_free;
1005         dequeue_temp = ep_ring->dequeue;
1006
1007         /* If we get two back-to-back stalls, and the first stalled transfer
1008          * ends just before a link TRB, the dequeue pointer will be left on
1009          * the link TRB by the code in the while loop.  So we have to update
1010          * the dequeue pointer one segment further, or we'll jump off
1011          * the segment into la-la-land.
1012          */
1013         if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1014                 ep_ring->deq_seg = ep_ring->deq_seg->next;
1015                 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1016         }
1017
1018         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1019                 /* We have more usable TRBs */
1020                 ep_ring->num_trbs_free++;
1021                 ep_ring->dequeue++;
1022                 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1023                                 ep_ring->dequeue)) {
1024                         if (ep_ring->dequeue ==
1025                                         dev->eps[ep_index].queued_deq_ptr)
1026                                 break;
1027                         ep_ring->deq_seg = ep_ring->deq_seg->next;
1028                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
1029                 }
1030                 if (ep_ring->dequeue == dequeue_temp) {
1031                         revert = true;
1032                         break;
1033                 }
1034         }
1035
1036         if (revert) {
1037                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1038                 ep_ring->num_trbs_free = num_trbs_free_temp;
1039         }
1040 }
1041
1042 /*
1043  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1044  * we need to clear the set deq pending flag in the endpoint ring state, so that
1045  * the TD queueing code can ring the doorbell again.  We also need to ring the
1046  * endpoint doorbell to restart the ring, but only if there aren't more
1047  * cancellations pending.
1048  */
1049 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1050                 struct xhci_event_cmd *event,
1051                 union xhci_trb *trb)
1052 {
1053         unsigned int slot_id;
1054         unsigned int ep_index;
1055         unsigned int stream_id;
1056         struct xhci_ring *ep_ring;
1057         struct xhci_virt_device *dev;
1058         struct xhci_ep_ctx *ep_ctx;
1059         struct xhci_slot_ctx *slot_ctx;
1060
1061         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1062         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1063         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1064         dev = xhci->devs[slot_id];
1065
1066         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1067         if (!ep_ring) {
1068                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1069                                 "freed stream ID %u\n",
1070                                 stream_id);
1071                 /* XXX: Harmless??? */
1072                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1073                 return;
1074         }
1075
1076         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1077         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1078
1079         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1080                 unsigned int ep_state;
1081                 unsigned int slot_state;
1082
1083                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1084                 case COMP_TRB_ERR:
1085                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1086                                         "of stream ID configuration\n");
1087                         break;
1088                 case COMP_CTX_STATE:
1089                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1090                                         "to incorrect slot or ep state.\n");
1091                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1092                         ep_state &= EP_STATE_MASK;
1093                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1094                         slot_state = GET_SLOT_STATE(slot_state);
1095                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1096                                         slot_state, ep_state);
1097                         break;
1098                 case COMP_EBADSLT:
1099                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1100                                         "slot %u was not enabled.\n", slot_id);
1101                         break;
1102                 default:
1103                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1104                                         "completion code of %u.\n",
1105                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1106                         break;
1107                 }
1108                 /* OK what do we do now?  The endpoint state is hosed, and we
1109                  * should never get to this point if the synchronization between
1110                  * queueing, and endpoint state are correct.  This might happen
1111                  * if the device gets disconnected after we've finished
1112                  * cancelling URBs, which might not be an error...
1113                  */
1114         } else {
1115                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1116                          le64_to_cpu(ep_ctx->deq));
1117                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1118                                          dev->eps[ep_index].queued_deq_ptr) ==
1119                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1120                         /* Update the ring's dequeue segment and dequeue pointer
1121                          * to reflect the new position.
1122                          */
1123                         update_ring_for_set_deq_completion(xhci, dev,
1124                                 ep_ring, ep_index);
1125                 } else {
1126                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1127                                         "Ptr command & xHCI internal state.\n");
1128                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1129                                         dev->eps[ep_index].queued_deq_seg,
1130                                         dev->eps[ep_index].queued_deq_ptr);
1131                 }
1132         }
1133
1134         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1135         dev->eps[ep_index].queued_deq_seg = NULL;
1136         dev->eps[ep_index].queued_deq_ptr = NULL;
1137         /* Restart any rings with pending URBs */
1138         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1139 }
1140
1141 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1142                 struct xhci_event_cmd *event,
1143                 union xhci_trb *trb)
1144 {
1145         int slot_id;
1146         unsigned int ep_index;
1147
1148         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1149         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1150         /* This command will only fail if the endpoint wasn't halted,
1151          * but we don't care.
1152          */
1153         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1154                  GET_COMP_CODE(le32_to_cpu(event->status)));
1155
1156         /* HW with the reset endpoint quirk needs to have a configure endpoint
1157          * command complete before the endpoint can be used.  Queue that here
1158          * because the HW can't handle two commands being queued in a row.
1159          */
1160         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1161                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1162                 xhci_queue_configure_endpoint(xhci,
1163                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1164                                 false);
1165                 xhci_ring_cmd_db(xhci);
1166         } else {
1167                 /* Clear our internal halted state and restart the ring(s) */
1168                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1169                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1170         }
1171 }
1172
1173 /* Complete the command and detele it from the devcie's command queue.
1174  */
1175 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1176                 struct xhci_command *command, u32 status)
1177 {
1178         command->status = status;
1179         list_del(&command->cmd_list);
1180         if (command->completion)
1181                 complete(command->completion);
1182         else
1183                 xhci_free_command(xhci, command);
1184 }
1185
1186
1187 /* Check to see if a command in the device's command queue matches this one.
1188  * Signal the completion or free the command, and return 1.  Return 0 if the
1189  * completed command isn't at the head of the command list.
1190  */
1191 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1192                 struct xhci_virt_device *virt_dev,
1193                 struct xhci_event_cmd *event)
1194 {
1195         struct xhci_command *command;
1196
1197         if (list_empty(&virt_dev->cmd_list))
1198                 return 0;
1199
1200         command = list_entry(virt_dev->cmd_list.next,
1201                         struct xhci_command, cmd_list);
1202         if (xhci->cmd_ring->dequeue != command->command_trb)
1203                 return 0;
1204
1205         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1206                         GET_COMP_CODE(le32_to_cpu(event->status)));
1207         return 1;
1208 }
1209
1210 /*
1211  * Finding the command trb need to be cancelled and modifying it to
1212  * NO OP command. And if the command is in device's command wait
1213  * list, finishing and freeing it.
1214  *
1215  * If we can't find the command trb, we think it had already been
1216  * executed.
1217  */
1218 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1219 {
1220         struct xhci_segment *cur_seg;
1221         union xhci_trb *cmd_trb;
1222         u32 cycle_state;
1223
1224         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1225                 return;
1226
1227         /* find the current segment of command ring */
1228         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1229                         xhci->cmd_ring->dequeue, &cycle_state);
1230
1231         if (!cur_seg) {
1232                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1233                                 xhci->cmd_ring->dequeue,
1234                                 (unsigned long long)
1235                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1236                                         xhci->cmd_ring->dequeue));
1237                 xhci_debug_ring(xhci, xhci->cmd_ring);
1238                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1239                 return;
1240         }
1241
1242         /* find the command trb matched by cd from command ring */
1243         for (cmd_trb = xhci->cmd_ring->dequeue;
1244                         cmd_trb != xhci->cmd_ring->enqueue;
1245                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1246                 /* If the trb is link trb, continue */
1247                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1248                         continue;
1249
1250                 if (cur_cd->cmd_trb == cmd_trb) {
1251
1252                         /* If the command in device's command list, we should
1253                          * finish it and free the command structure.
1254                          */
1255                         if (cur_cd->command)
1256                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1257                                         cur_cd->command, COMP_CMD_STOP);
1258
1259                         /* get cycle state from the origin command trb */
1260                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1261                                 & TRB_CYCLE;
1262
1263                         /* modify the command trb to NO OP command */
1264                         cmd_trb->generic.field[0] = 0;
1265                         cmd_trb->generic.field[1] = 0;
1266                         cmd_trb->generic.field[2] = 0;
1267                         cmd_trb->generic.field[3] = cpu_to_le32(
1268                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1269                         break;
1270                 }
1271         }
1272 }
1273
1274 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1275 {
1276         struct xhci_cd *cur_cd, *next_cd;
1277
1278         if (list_empty(&xhci->cancel_cmd_list))
1279                 return;
1280
1281         list_for_each_entry_safe(cur_cd, next_cd,
1282                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1283                 xhci_cmd_to_noop(xhci, cur_cd);
1284                 list_del(&cur_cd->cancel_cmd_list);
1285                 kfree(cur_cd);
1286         }
1287 }
1288
1289 /*
1290  * traversing the cancel_cmd_list. If the command descriptor according
1291  * to cmd_trb is found, the function free it and return 1, otherwise
1292  * return 0.
1293  */
1294 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1295                 union xhci_trb *cmd_trb)
1296 {
1297         struct xhci_cd *cur_cd, *next_cd;
1298
1299         if (list_empty(&xhci->cancel_cmd_list))
1300                 return 0;
1301
1302         list_for_each_entry_safe(cur_cd, next_cd,
1303                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1304                 if (cur_cd->cmd_trb == cmd_trb) {
1305                         if (cur_cd->command)
1306                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1307                                         cur_cd->command, COMP_CMD_STOP);
1308                         list_del(&cur_cd->cancel_cmd_list);
1309                         kfree(cur_cd);
1310                         return 1;
1311                 }
1312         }
1313
1314         return 0;
1315 }
1316
1317 /*
1318  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1319  * trb pointed by the command ring dequeue pointer is the trb we want to
1320  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1321  * traverse the cancel_cmd_list to trun the all of the commands according
1322  * to command descriptor to NO-OP trb.
1323  */
1324 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1325                 int cmd_trb_comp_code)
1326 {
1327         int cur_trb_is_good = 0;
1328
1329         /* Searching the cmd trb pointed by the command ring dequeue
1330          * pointer in command descriptor list. If it is found, free it.
1331          */
1332         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1333                         xhci->cmd_ring->dequeue);
1334
1335         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1336                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1337         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1338                 /* traversing the cancel_cmd_list and canceling
1339                  * the command according to command descriptor
1340                  */
1341                 xhci_cancel_cmd_in_cd_list(xhci);
1342
1343                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1344                 /*
1345                  * ring command ring doorbell again to restart the
1346                  * command ring
1347                  */
1348                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1349                         xhci_ring_cmd_db(xhci);
1350         }
1351         return cur_trb_is_good;
1352 }
1353
1354 static void handle_cmd_completion(struct xhci_hcd *xhci,
1355                 struct xhci_event_cmd *event)
1356 {
1357         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1358         u64 cmd_dma;
1359         dma_addr_t cmd_dequeue_dma;
1360         struct xhci_input_control_ctx *ctrl_ctx;
1361         struct xhci_virt_device *virt_dev;
1362         unsigned int ep_index;
1363         struct xhci_ring *ep_ring;
1364         unsigned int ep_state;
1365
1366         cmd_dma = le64_to_cpu(event->cmd_trb);
1367         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1368                         xhci->cmd_ring->dequeue);
1369         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1370         if (cmd_dequeue_dma == 0) {
1371                 xhci->error_bitmask |= 1 << 4;
1372                 return;
1373         }
1374         /* Does the DMA address match our internal dequeue pointer address? */
1375         if (cmd_dma != (u64) cmd_dequeue_dma) {
1376                 xhci->error_bitmask |= 1 << 5;
1377                 return;
1378         }
1379
1380         if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1381                 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1382                 /* If the return value is 0, we think the trb pointed by
1383                  * command ring dequeue pointer is a good trb. The good
1384                  * trb means we don't want to cancel the trb, but it have
1385                  * been stopped by host. So we should handle it normally.
1386                  * Otherwise, driver should invoke inc_deq() and return.
1387                  */
1388                 if (handle_stopped_cmd_ring(xhci,
1389                                 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1390                         inc_deq(xhci, xhci->cmd_ring);
1391                         return;
1392                 }
1393         }
1394
1395         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1396                 & TRB_TYPE_BITMASK) {
1397         case TRB_TYPE(TRB_ENABLE_SLOT):
1398                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1399                         xhci->slot_id = slot_id;
1400                 else
1401                         xhci->slot_id = 0;
1402                 complete(&xhci->addr_dev);
1403                 break;
1404         case TRB_TYPE(TRB_DISABLE_SLOT):
1405                 if (xhci->devs[slot_id]) {
1406                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1407                                 /* Delete default control endpoint resources */
1408                                 xhci_free_device_endpoint_resources(xhci,
1409                                                 xhci->devs[slot_id], true);
1410                         xhci_free_virt_device(xhci, slot_id);
1411                 }
1412                 break;
1413         case TRB_TYPE(TRB_CONFIG_EP):
1414                 virt_dev = xhci->devs[slot_id];
1415                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1416                         break;
1417                 /*
1418                  * Configure endpoint commands can come from the USB core
1419                  * configuration or alt setting changes, or because the HW
1420                  * needed an extra configure endpoint command after a reset
1421                  * endpoint command or streams were being configured.
1422                  * If the command was for a halted endpoint, the xHCI driver
1423                  * is not waiting on the configure endpoint command.
1424                  */
1425                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1426                                 virt_dev->in_ctx);
1427                 /* Input ctx add_flags are the endpoint index plus one */
1428                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1429                 /* A usb_set_interface() call directly after clearing a halted
1430                  * condition may race on this quirky hardware.  Not worth
1431                  * worrying about, since this is prototype hardware.  Not sure
1432                  * if this will work for streams, but streams support was
1433                  * untested on this prototype.
1434                  */
1435                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1436                                 ep_index != (unsigned int) -1 &&
1437                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1438                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1439                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1440                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1441                         if (!(ep_state & EP_HALTED))
1442                                 goto bandwidth_change;
1443                         xhci_dbg(xhci, "Completed config ep cmd - "
1444                                         "last ep index = %d, state = %d\n",
1445                                         ep_index, ep_state);
1446                         /* Clear internal halted state and restart ring(s) */
1447                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1448                                 ~EP_HALTED;
1449                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1450                         break;
1451                 }
1452 bandwidth_change:
1453                 xhci_dbg(xhci, "Completed config ep cmd\n");
1454                 xhci->devs[slot_id]->cmd_status =
1455                         GET_COMP_CODE(le32_to_cpu(event->status));
1456                 complete(&xhci->devs[slot_id]->cmd_completion);
1457                 break;
1458         case TRB_TYPE(TRB_EVAL_CONTEXT):
1459                 virt_dev = xhci->devs[slot_id];
1460                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1461                         break;
1462                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1463                 complete(&xhci->devs[slot_id]->cmd_completion);
1464                 break;
1465         case TRB_TYPE(TRB_ADDR_DEV):
1466                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1467                 complete(&xhci->addr_dev);
1468                 break;
1469         case TRB_TYPE(TRB_STOP_RING):
1470                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1471                 break;
1472         case TRB_TYPE(TRB_SET_DEQ):
1473                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1474                 break;
1475         case TRB_TYPE(TRB_CMD_NOOP):
1476                 break;
1477         case TRB_TYPE(TRB_RESET_EP):
1478                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1479                 break;
1480         case TRB_TYPE(TRB_RESET_DEV):
1481                 xhci_dbg(xhci, "Completed reset device command.\n");
1482                 slot_id = TRB_TO_SLOT_ID(
1483                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1484                 virt_dev = xhci->devs[slot_id];
1485                 if (virt_dev)
1486                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1487                 else
1488                         xhci_warn(xhci, "Reset device command completion "
1489                                         "for disabled slot %u\n", slot_id);
1490                 break;
1491         case TRB_TYPE(TRB_NEC_GET_FW):
1492                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1493                         xhci->error_bitmask |= 1 << 6;
1494                         break;
1495                 }
1496                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1497                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1498                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1499                 break;
1500         default:
1501                 /* Skip over unknown commands on the event ring */
1502                 xhci->error_bitmask |= 1 << 6;
1503                 break;
1504         }
1505         inc_deq(xhci, xhci->cmd_ring);
1506 }
1507
1508 static void handle_vendor_event(struct xhci_hcd *xhci,
1509                 union xhci_trb *event)
1510 {
1511         u32 trb_type;
1512
1513         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1514         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1515         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1516                 handle_cmd_completion(xhci, &event->event_cmd);
1517 }
1518
1519 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1520  * port registers -- USB 3.0 and USB 2.0).
1521  *
1522  * Returns a zero-based port number, which is suitable for indexing into each of
1523  * the split roothubs' port arrays and bus state arrays.
1524  * Add one to it in order to call xhci_find_slot_id_by_port.
1525  */
1526 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1527                 struct xhci_hcd *xhci, u32 port_id)
1528 {
1529         unsigned int i;
1530         unsigned int num_similar_speed_ports = 0;
1531
1532         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1533          * and usb2_ports are 0-based indexes.  Count the number of similar
1534          * speed ports, up to 1 port before this port.
1535          */
1536         for (i = 0; i < (port_id - 1); i++) {
1537                 u8 port_speed = xhci->port_array[i];
1538
1539                 /*
1540                  * Skip ports that don't have known speeds, or have duplicate
1541                  * Extended Capabilities port speed entries.
1542                  */
1543                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1544                         continue;
1545
1546                 /*
1547                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1548                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1549                  * matches the device speed, it's a similar speed port.
1550                  */
1551                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1552                         num_similar_speed_ports++;
1553         }
1554         return num_similar_speed_ports;
1555 }
1556
1557 static void handle_device_notification(struct xhci_hcd *xhci,
1558                 union xhci_trb *event)
1559 {
1560         u32 slot_id;
1561         struct usb_device *udev;
1562
1563         slot_id = TRB_TO_SLOT_ID(event->generic.field[3]);
1564         if (!xhci->devs[slot_id]) {
1565                 xhci_warn(xhci, "Device Notification event for "
1566                                 "unused slot %u\n", slot_id);
1567                 return;
1568         }
1569
1570         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1571                         slot_id);
1572         udev = xhci->devs[slot_id]->udev;
1573         if (udev && udev->parent)
1574                 usb_wakeup_notification(udev->parent, udev->portnum);
1575 }
1576
1577 static void handle_port_status(struct xhci_hcd *xhci,
1578                 union xhci_trb *event)
1579 {
1580         struct usb_hcd *hcd;
1581         u32 port_id;
1582         u32 temp, temp1;
1583         int max_ports;
1584         int slot_id;
1585         unsigned int faked_port_index;
1586         u8 major_revision;
1587         struct xhci_bus_state *bus_state;
1588         __le32 __iomem **port_array;
1589         bool bogus_port_status = false;
1590
1591         /* Port status change events always have a successful completion code */
1592         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1593                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1594                 xhci->error_bitmask |= 1 << 8;
1595         }
1596         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1597         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1598
1599         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1600         if ((port_id <= 0) || (port_id > max_ports)) {
1601                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1602                 bogus_port_status = true;
1603                 goto cleanup;
1604         }
1605
1606         /* Figure out which usb_hcd this port is attached to:
1607          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1608          */
1609         major_revision = xhci->port_array[port_id - 1];
1610         if (major_revision == 0) {
1611                 xhci_warn(xhci, "Event for port %u not in "
1612                                 "Extended Capabilities, ignoring.\n",
1613                                 port_id);
1614                 bogus_port_status = true;
1615                 goto cleanup;
1616         }
1617         if (major_revision == DUPLICATE_ENTRY) {
1618                 xhci_warn(xhci, "Event for port %u duplicated in"
1619                                 "Extended Capabilities, ignoring.\n",
1620                                 port_id);
1621                 bogus_port_status = true;
1622                 goto cleanup;
1623         }
1624
1625         /*
1626          * Hardware port IDs reported by a Port Status Change Event include USB
1627          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1628          * resume event, but we first need to translate the hardware port ID
1629          * into the index into the ports on the correct split roothub, and the
1630          * correct bus_state structure.
1631          */
1632         /* Find the right roothub. */
1633         hcd = xhci_to_hcd(xhci);
1634         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1635                 hcd = xhci->shared_hcd;
1636         bus_state = &xhci->bus_state[hcd_index(hcd)];
1637         if (hcd->speed == HCD_USB3)
1638                 port_array = xhci->usb3_ports;
1639         else
1640                 port_array = xhci->usb2_ports;
1641         /* Find the faked port hub number */
1642         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1643                         port_id);
1644
1645         temp = xhci_readl(xhci, port_array[faked_port_index]);
1646         if (hcd->state == HC_STATE_SUSPENDED) {
1647                 xhci_dbg(xhci, "resume root hub\n");
1648                 usb_hcd_resume_root_hub(hcd);
1649         }
1650
1651         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1652                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1653
1654                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1655                 if (!(temp1 & CMD_RUN)) {
1656                         xhci_warn(xhci, "xHC is not running.\n");
1657                         goto cleanup;
1658                 }
1659
1660                 if (DEV_SUPERSPEED(temp)) {
1661                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1662                         /* Set a flag to say the port signaled remote wakeup,
1663                          * so we can tell the difference between the end of
1664                          * device and host initiated resume.
1665                          */
1666                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1667                         xhci_test_and_clear_bit(xhci, port_array,
1668                                         faked_port_index, PORT_PLC);
1669                         xhci_set_link_state(xhci, port_array, faked_port_index,
1670                                                 XDEV_U0);
1671                         /* Need to wait until the next link state change
1672                          * indicates the device is actually in U0.
1673                          */
1674                         bogus_port_status = true;
1675                         goto cleanup;
1676                 } else {
1677                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1678                         bus_state->resume_done[faked_port_index] = jiffies +
1679                                 msecs_to_jiffies(20);
1680                         set_bit(faked_port_index, &bus_state->resuming_ports);
1681                         mod_timer(&hcd->rh_timer,
1682                                   bus_state->resume_done[faked_port_index]);
1683                         /* Do the rest in GetPortStatus */
1684                 }
1685         }
1686
1687         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1688                         DEV_SUPERSPEED(temp)) {
1689                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1690                 /* We've just brought the device into U0 through either the
1691                  * Resume state after a device remote wakeup, or through the
1692                  * U3Exit state after a host-initiated resume.  If it's a device
1693                  * initiated remote wake, don't pass up the link state change,
1694                  * so the roothub behavior is consistent with external
1695                  * USB 3.0 hub behavior.
1696                  */
1697                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1698                                 faked_port_index + 1);
1699                 if (slot_id && xhci->devs[slot_id])
1700                         xhci_ring_device(xhci, slot_id);
1701                 if (bus_state->port_remote_wakeup && (1 << faked_port_index)) {
1702                         bus_state->port_remote_wakeup &=
1703                                 ~(1 << faked_port_index);
1704                         xhci_test_and_clear_bit(xhci, port_array,
1705                                         faked_port_index, PORT_PLC);
1706                         usb_wakeup_notification(hcd->self.root_hub,
1707                                         faked_port_index + 1);
1708                         bogus_port_status = true;
1709                         goto cleanup;
1710                 }
1711         }
1712
1713         if (hcd->speed != HCD_USB3)
1714                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1715                                         PORT_PLC);
1716
1717 cleanup:
1718         /* Update event ring dequeue pointer before dropping the lock */
1719         inc_deq(xhci, xhci->event_ring);
1720
1721         /* Don't make the USB core poll the roothub if we got a bad port status
1722          * change event.  Besides, at that point we can't tell which roothub
1723          * (USB 2.0 or USB 3.0) to kick.
1724          */
1725         if (bogus_port_status)
1726                 return;
1727
1728         /*
1729          * xHCI port-status-change events occur when the "or" of all the
1730          * status-change bits in the portsc register changes from 0 to 1.
1731          * New status changes won't cause an event if any other change
1732          * bits are still set.  When an event occurs, switch over to
1733          * polling to avoid losing status changes.
1734          */
1735         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1736         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1737         spin_unlock(&xhci->lock);
1738         /* Pass this up to the core */
1739         usb_hcd_poll_rh_status(hcd);
1740         spin_lock(&xhci->lock);
1741 }
1742
1743 /*
1744  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1745  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1746  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1747  * returns 0.
1748  */
1749 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1750                 union xhci_trb  *start_trb,
1751                 union xhci_trb  *end_trb,
1752                 dma_addr_t      suspect_dma)
1753 {
1754         dma_addr_t start_dma;
1755         dma_addr_t end_seg_dma;
1756         dma_addr_t end_trb_dma;
1757         struct xhci_segment *cur_seg;
1758
1759         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1760         cur_seg = start_seg;
1761
1762         do {
1763                 if (start_dma == 0)
1764                         return NULL;
1765                 /* We may get an event for a Link TRB in the middle of a TD */
1766                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1767                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1768                 /* If the end TRB isn't in this segment, this is set to 0 */
1769                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1770
1771                 if (end_trb_dma > 0) {
1772                         /* The end TRB is in this segment, so suspect should be here */
1773                         if (start_dma <= end_trb_dma) {
1774                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1775                                         return cur_seg;
1776                         } else {
1777                                 /* Case for one segment with
1778                                  * a TD wrapped around to the top
1779                                  */
1780                                 if ((suspect_dma >= start_dma &&
1781                                                         suspect_dma <= end_seg_dma) ||
1782                                                 (suspect_dma >= cur_seg->dma &&
1783                                                  suspect_dma <= end_trb_dma))
1784                                         return cur_seg;
1785                         }
1786                         return NULL;
1787                 } else {
1788                         /* Might still be somewhere in this segment */
1789                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1790                                 return cur_seg;
1791                 }
1792                 cur_seg = cur_seg->next;
1793                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1794         } while (cur_seg != start_seg);
1795
1796         return NULL;
1797 }
1798
1799 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1800                 unsigned int slot_id, unsigned int ep_index,
1801                 unsigned int stream_id,
1802                 struct xhci_td *td, union xhci_trb *event_trb)
1803 {
1804         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1805         ep->ep_state |= EP_HALTED;
1806         ep->stopped_td = td;
1807         ep->stopped_trb = event_trb;
1808         ep->stopped_stream = stream_id;
1809
1810         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1811         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1812
1813         ep->stopped_td = NULL;
1814         ep->stopped_trb = NULL;
1815         ep->stopped_stream = 0;
1816
1817         xhci_ring_cmd_db(xhci);
1818 }
1819
1820 /* Check if an error has halted the endpoint ring.  The class driver will
1821  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1822  * However, a babble and other errors also halt the endpoint ring, and the class
1823  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1824  * Ring Dequeue Pointer command manually.
1825  */
1826 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1827                 struct xhci_ep_ctx *ep_ctx,
1828                 unsigned int trb_comp_code)
1829 {
1830         /* TRB completion codes that may require a manual halt cleanup */
1831         if (trb_comp_code == COMP_TX_ERR ||
1832                         trb_comp_code == COMP_BABBLE ||
1833                         trb_comp_code == COMP_SPLIT_ERR)
1834                 /* The 0.96 spec says a babbling control endpoint
1835                  * is not halted. The 0.96 spec says it is.  Some HW
1836                  * claims to be 0.95 compliant, but it halts the control
1837                  * endpoint anyway.  Check if a babble halted the
1838                  * endpoint.
1839                  */
1840                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1841                     cpu_to_le32(EP_STATE_HALTED))
1842                         return 1;
1843
1844         return 0;
1845 }
1846
1847 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1848 {
1849         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1850                 /* Vendor defined "informational" completion code,
1851                  * treat as not-an-error.
1852                  */
1853                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1854                                 trb_comp_code);
1855                 xhci_dbg(xhci, "Treating code as success.\n");
1856                 return 1;
1857         }
1858         return 0;
1859 }
1860
1861 /*
1862  * Finish the td processing, remove the td from td list;
1863  * Return 1 if the urb can be given back.
1864  */
1865 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1866         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1867         struct xhci_virt_ep *ep, int *status, bool skip)
1868 {
1869         struct xhci_virt_device *xdev;
1870         struct xhci_ring *ep_ring;
1871         unsigned int slot_id;
1872         int ep_index;
1873         struct urb *urb = NULL;
1874         struct xhci_ep_ctx *ep_ctx;
1875         int ret = 0;
1876         struct urb_priv *urb_priv;
1877         u32 trb_comp_code;
1878
1879         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1880         xdev = xhci->devs[slot_id];
1881         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1882         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1883         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1884         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1885
1886         if (skip)
1887                 goto td_cleanup;
1888
1889         if (trb_comp_code == COMP_STOP_INVAL ||
1890                         trb_comp_code == COMP_STOP) {
1891                 /* The Endpoint Stop Command completion will take care of any
1892                  * stopped TDs.  A stopped TD may be restarted, so don't update
1893                  * the ring dequeue pointer or take this TD off any lists yet.
1894                  */
1895                 ep->stopped_td = td;
1896                 ep->stopped_trb = event_trb;
1897                 return 0;
1898         } else {
1899                 if (trb_comp_code == COMP_STALL) {
1900                         /* The transfer is completed from the driver's
1901                          * perspective, but we need to issue a set dequeue
1902                          * command for this stalled endpoint to move the dequeue
1903                          * pointer past the TD.  We can't do that here because
1904                          * the halt condition must be cleared first.  Let the
1905                          * USB class driver clear the stall later.
1906                          */
1907                         ep->stopped_td = td;
1908                         ep->stopped_trb = event_trb;
1909                         ep->stopped_stream = ep_ring->stream_id;
1910                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1911                                         ep_ctx, trb_comp_code)) {
1912                         /* Other types of errors halt the endpoint, but the
1913                          * class driver doesn't call usb_reset_endpoint() unless
1914                          * the error is -EPIPE.  Clear the halted status in the
1915                          * xHCI hardware manually.
1916                          */
1917                         xhci_cleanup_halted_endpoint(xhci,
1918                                         slot_id, ep_index, ep_ring->stream_id,
1919                                         td, event_trb);
1920                 } else {
1921                         /* Update ring dequeue pointer */
1922                         while (ep_ring->dequeue != td->last_trb)
1923                                 inc_deq(xhci, ep_ring);
1924                         inc_deq(xhci, ep_ring);
1925                 }
1926
1927 td_cleanup:
1928                 /* Clean up the endpoint's TD list */
1929                 urb = td->urb;
1930                 urb_priv = urb->hcpriv;
1931
1932                 /* Do one last check of the actual transfer length.
1933                  * If the host controller said we transferred more data than
1934                  * the buffer length, urb->actual_length will be a very big
1935                  * number (since it's unsigned).  Play it safe and say we didn't
1936                  * transfer anything.
1937                  */
1938                 if (urb->actual_length > urb->transfer_buffer_length) {
1939                         xhci_warn(xhci, "URB transfer length is wrong, "
1940                                         "xHC issue? req. len = %u, "
1941                                         "act. len = %u\n",
1942                                         urb->transfer_buffer_length,
1943                                         urb->actual_length);
1944                         urb->actual_length = 0;
1945                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1946                                 *status = -EREMOTEIO;
1947                         else
1948                                 *status = 0;
1949                 }
1950                 list_del_init(&td->td_list);
1951                 /* Was this TD slated to be cancelled but completed anyway? */
1952                 if (!list_empty(&td->cancelled_td_list))
1953                         list_del_init(&td->cancelled_td_list);
1954
1955                 urb_priv->td_cnt++;
1956                 /* Giveback the urb when all the tds are completed */
1957                 if (urb_priv->td_cnt == urb_priv->length) {
1958                         ret = 1;
1959                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1960                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1961                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1962                                         == 0) {
1963                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1964                                                 usb_amd_quirk_pll_enable();
1965                                 }
1966                         }
1967                 }
1968         }
1969
1970         return ret;
1971 }
1972
1973 /*
1974  * Process control tds, update urb status and actual_length.
1975  */
1976 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1977         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1978         struct xhci_virt_ep *ep, int *status)
1979 {
1980         struct xhci_virt_device *xdev;
1981         struct xhci_ring *ep_ring;
1982         unsigned int slot_id;
1983         int ep_index;
1984         struct xhci_ep_ctx *ep_ctx;
1985         u32 trb_comp_code;
1986
1987         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1988         xdev = xhci->devs[slot_id];
1989         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1990         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1991         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1992         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1993
1994         switch (trb_comp_code) {
1995         case COMP_SUCCESS:
1996                 if (event_trb == ep_ring->dequeue) {
1997                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1998                                         "without IOC set??\n");
1999                         *status = -ESHUTDOWN;
2000                 } else if (event_trb != td->last_trb) {
2001                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2002                                         "without IOC set??\n");
2003                         *status = -ESHUTDOWN;
2004                 } else {
2005                         *status = 0;
2006                 }
2007                 break;
2008         case COMP_SHORT_TX:
2009                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2010                         *status = -EREMOTEIO;
2011                 else
2012                         *status = 0;
2013                 break;
2014         case COMP_STOP_INVAL:
2015         case COMP_STOP:
2016                 return finish_td(xhci, td, event_trb, event, ep, status, false);
2017         default:
2018                 if (!xhci_requires_manual_halt_cleanup(xhci,
2019                                         ep_ctx, trb_comp_code))
2020                         break;
2021                 xhci_dbg(xhci, "TRB error code %u, "
2022                                 "halted endpoint index = %u\n",
2023                                 trb_comp_code, ep_index);
2024                 /* else fall through */
2025         case COMP_STALL:
2026                 /* Did we transfer part of the data (middle) phase? */
2027                 if (event_trb != ep_ring->dequeue &&
2028                                 event_trb != td->last_trb)
2029                         td->urb->actual_length =
2030                                 td->urb->transfer_buffer_length
2031                                 - TRB_LEN(le32_to_cpu(event->transfer_len));
2032                 else
2033                         td->urb->actual_length = 0;
2034
2035                 xhci_cleanup_halted_endpoint(xhci,
2036                         slot_id, ep_index, 0, td, event_trb);
2037                 return finish_td(xhci, td, event_trb, event, ep, status, true);
2038         }
2039         /*
2040          * Did we transfer any data, despite the errors that might have
2041          * happened?  I.e. did we get past the setup stage?
2042          */
2043         if (event_trb != ep_ring->dequeue) {
2044                 /* The event was for the status stage */
2045                 if (event_trb == td->last_trb) {
2046                         if (td->urb->actual_length != 0) {
2047                                 /* Don't overwrite a previously set error code
2048                                  */
2049                                 if ((*status == -EINPROGRESS || *status == 0) &&
2050                                                 (td->urb->transfer_flags
2051                                                  & URB_SHORT_NOT_OK))
2052                                         /* Did we already see a short data
2053                                          * stage? */
2054                                         *status = -EREMOTEIO;
2055                         } else {
2056                                 td->urb->actual_length =
2057                                         td->urb->transfer_buffer_length;
2058                         }
2059                 } else {
2060                 /* Maybe the event was for the data stage? */
2061                         td->urb->actual_length =
2062                                 td->urb->transfer_buffer_length -
2063                                 TRB_LEN(le32_to_cpu(event->transfer_len));
2064                         xhci_dbg(xhci, "Waiting for status "
2065                                         "stage event\n");
2066                         return 0;
2067                 }
2068         }
2069
2070         return finish_td(xhci, td, event_trb, event, ep, status, false);
2071 }
2072
2073 /*
2074  * Process isochronous tds, update urb packet status and actual_length.
2075  */
2076 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2077         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2078         struct xhci_virt_ep *ep, int *status)
2079 {
2080         struct xhci_ring *ep_ring;
2081         struct urb_priv *urb_priv;
2082         int idx;
2083         int len = 0;
2084         union xhci_trb *cur_trb;
2085         struct xhci_segment *cur_seg;
2086         struct usb_iso_packet_descriptor *frame;
2087         u32 trb_comp_code;
2088         bool skip_td = false;
2089
2090         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2091         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2092         urb_priv = td->urb->hcpriv;
2093         idx = urb_priv->td_cnt;
2094         frame = &td->urb->iso_frame_desc[idx];
2095
2096         /* handle completion code */
2097         switch (trb_comp_code) {
2098         case COMP_SUCCESS:
2099                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2100                         frame->status = 0;
2101                         break;
2102                 }
2103                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2104                         trb_comp_code = COMP_SHORT_TX;
2105         case COMP_SHORT_TX:
2106                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2107                                 -EREMOTEIO : 0;
2108                 break;
2109         case COMP_BW_OVER:
2110                 frame->status = -ECOMM;
2111                 skip_td = true;
2112                 break;
2113         case COMP_BUFF_OVER:
2114         case COMP_BABBLE:
2115                 frame->status = -EOVERFLOW;
2116                 skip_td = true;
2117                 break;
2118         case COMP_DEV_ERR:
2119         case COMP_STALL:
2120         case COMP_TX_ERR:
2121                 frame->status = -EPROTO;
2122                 skip_td = true;
2123                 break;
2124         case COMP_STOP:
2125         case COMP_STOP_INVAL:
2126                 break;
2127         default:
2128                 frame->status = -1;
2129                 break;
2130         }
2131
2132         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2133                 frame->actual_length = frame->length;
2134                 td->urb->actual_length += frame->length;
2135         } else {
2136                 for (cur_trb = ep_ring->dequeue,
2137                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2138                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2139                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2140                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2141                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2142                 }
2143                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2144                         TRB_LEN(le32_to_cpu(event->transfer_len));
2145
2146                 if (trb_comp_code != COMP_STOP_INVAL) {
2147                         frame->actual_length = len;
2148                         td->urb->actual_length += len;
2149                 }
2150         }
2151
2152         return finish_td(xhci, td, event_trb, event, ep, status, false);
2153 }
2154
2155 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2156                         struct xhci_transfer_event *event,
2157                         struct xhci_virt_ep *ep, int *status)
2158 {
2159         struct xhci_ring *ep_ring;
2160         struct urb_priv *urb_priv;
2161         struct usb_iso_packet_descriptor *frame;
2162         int idx;
2163
2164         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2165         urb_priv = td->urb->hcpriv;
2166         idx = urb_priv->td_cnt;
2167         frame = &td->urb->iso_frame_desc[idx];
2168
2169         /* The transfer is partly done. */
2170         frame->status = -EXDEV;
2171
2172         /* calc actual length */
2173         frame->actual_length = 0;
2174
2175         /* Update ring dequeue pointer */
2176         while (ep_ring->dequeue != td->last_trb)
2177                 inc_deq(xhci, ep_ring);
2178         inc_deq(xhci, ep_ring);
2179
2180         return finish_td(xhci, td, NULL, event, ep, status, true);
2181 }
2182
2183 /*
2184  * Process bulk and interrupt tds, update urb status and actual_length.
2185  */
2186 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2187         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2188         struct xhci_virt_ep *ep, int *status)
2189 {
2190         struct xhci_ring *ep_ring;
2191         union xhci_trb *cur_trb;
2192         struct xhci_segment *cur_seg;
2193         u32 trb_comp_code;
2194
2195         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2196         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2197
2198         switch (trb_comp_code) {
2199         case COMP_SUCCESS:
2200                 /* Double check that the HW transferred everything. */
2201                 if (event_trb != td->last_trb ||
2202                                 TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2203                         xhci_warn(xhci, "WARN Successful completion "
2204                                         "on short TX\n");
2205                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2206                                 *status = -EREMOTEIO;
2207                         else
2208                                 *status = 0;
2209                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2210                                 trb_comp_code = COMP_SHORT_TX;
2211                 } else {
2212                         *status = 0;
2213                 }
2214                 break;
2215         case COMP_SHORT_TX:
2216                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2217                         *status = -EREMOTEIO;
2218                 else
2219                         *status = 0;
2220                 break;
2221         default:
2222                 /* Others already handled above */
2223                 break;
2224         }
2225         if (trb_comp_code == COMP_SHORT_TX)
2226                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2227                                 "%d bytes untransferred\n",
2228                                 td->urb->ep->desc.bEndpointAddress,
2229                                 td->urb->transfer_buffer_length,
2230                                 TRB_LEN(le32_to_cpu(event->transfer_len)));
2231         /* Fast path - was this the last TRB in the TD for this URB? */
2232         if (event_trb == td->last_trb) {
2233                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2234                         td->urb->actual_length =
2235                                 td->urb->transfer_buffer_length -
2236                                 TRB_LEN(le32_to_cpu(event->transfer_len));
2237                         if (td->urb->transfer_buffer_length <
2238                                         td->urb->actual_length) {
2239                                 xhci_warn(xhci, "HC gave bad length "
2240                                                 "of %d bytes left\n",
2241                                           TRB_LEN(le32_to_cpu(event->transfer_len)));
2242                                 td->urb->actual_length = 0;
2243                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2244                                         *status = -EREMOTEIO;
2245                                 else
2246                                         *status = 0;
2247                         }
2248                         /* Don't overwrite a previously set error code */
2249                         if (*status == -EINPROGRESS) {
2250                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2251                                         *status = -EREMOTEIO;
2252                                 else
2253                                         *status = 0;
2254                         }
2255                 } else {
2256                         td->urb->actual_length =
2257                                 td->urb->transfer_buffer_length;
2258                         /* Ignore a short packet completion if the
2259                          * untransferred length was zero.
2260                          */
2261                         if (*status == -EREMOTEIO)
2262                                 *status = 0;
2263                 }
2264         } else {
2265                 /* Slow path - walk the list, starting from the dequeue
2266                  * pointer, to get the actual length transferred.
2267                  */
2268                 td->urb->actual_length = 0;
2269                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2270                                 cur_trb != event_trb;
2271                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2272                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2273                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2274                                 td->urb->actual_length +=
2275                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2276                 }
2277                 /* If the ring didn't stop on a Link or No-op TRB, add
2278                  * in the actual bytes transferred from the Normal TRB
2279                  */
2280                 if (trb_comp_code != COMP_STOP_INVAL)
2281                         td->urb->actual_length +=
2282                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2283                                 TRB_LEN(le32_to_cpu(event->transfer_len));
2284         }
2285
2286         return finish_td(xhci, td, event_trb, event, ep, status, false);
2287 }
2288
2289 /*
2290  * If this function returns an error condition, it means it got a Transfer
2291  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2292  * At this point, the host controller is probably hosed and should be reset.
2293  */
2294 static int handle_tx_event(struct xhci_hcd *xhci,
2295                 struct xhci_transfer_event *event)
2296         __releases(&xhci->lock)
2297         __acquires(&xhci->lock)
2298 {
2299         struct xhci_virt_device *xdev;
2300         struct xhci_virt_ep *ep;
2301         struct xhci_ring *ep_ring;
2302         unsigned int slot_id;
2303         int ep_index;
2304         struct xhci_td *td = NULL;
2305         dma_addr_t event_dma;
2306         struct xhci_segment *event_seg;
2307         union xhci_trb *event_trb;
2308         struct urb *urb = NULL;
2309         int status = -EINPROGRESS;
2310         struct urb_priv *urb_priv;
2311         struct xhci_ep_ctx *ep_ctx;
2312         struct list_head *tmp;
2313         u32 trb_comp_code;
2314         int ret = 0;
2315         int td_num = 0;
2316
2317         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2318         xdev = xhci->devs[slot_id];
2319         if (!xdev) {
2320                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2321                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2322                          (unsigned long long) xhci_trb_virt_to_dma(
2323                                  xhci->event_ring->deq_seg,
2324                                  xhci->event_ring->dequeue),
2325                          lower_32_bits(le64_to_cpu(event->buffer)),
2326                          upper_32_bits(le64_to_cpu(event->buffer)),
2327                          le32_to_cpu(event->transfer_len),
2328                          le32_to_cpu(event->flags));
2329                 xhci_dbg(xhci, "Event ring:\n");
2330                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2331                 return -ENODEV;
2332         }
2333
2334         /* Endpoint ID is 1 based, our index is zero based */
2335         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2336         ep = &xdev->eps[ep_index];
2337         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2338         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2339         if (!ep_ring ||
2340             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2341             EP_STATE_DISABLED) {
2342                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2343                                 "or incorrect stream ring\n");
2344                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2345                          (unsigned long long) xhci_trb_virt_to_dma(
2346                                  xhci->event_ring->deq_seg,
2347                                  xhci->event_ring->dequeue),
2348                          lower_32_bits(le64_to_cpu(event->buffer)),
2349                          upper_32_bits(le64_to_cpu(event->buffer)),
2350                          le32_to_cpu(event->transfer_len),
2351                          le32_to_cpu(event->flags));
2352                 xhci_dbg(xhci, "Event ring:\n");
2353                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2354                 return -ENODEV;
2355         }
2356
2357         /* Count current td numbers if ep->skip is set */
2358         if (ep->skip) {
2359                 list_for_each(tmp, &ep_ring->td_list)
2360                         td_num++;
2361         }
2362
2363         event_dma = le64_to_cpu(event->buffer);
2364         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2365         /* Look for common error cases */
2366         switch (trb_comp_code) {
2367         /* Skip codes that require special handling depending on
2368          * transfer type
2369          */
2370         case COMP_SUCCESS:
2371                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2372                         break;
2373                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2374                         trb_comp_code = COMP_SHORT_TX;
2375                 else
2376                         xhci_warn_ratelimited(xhci,
2377                                         "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2378         case COMP_SHORT_TX:
2379                 break;
2380         case COMP_STOP:
2381                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2382                 break;
2383         case COMP_STOP_INVAL:
2384                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2385                 break;
2386         case COMP_STALL:
2387                 xhci_dbg(xhci, "Stalled endpoint\n");
2388                 ep->ep_state |= EP_HALTED;
2389                 status = -EPIPE;
2390                 break;
2391         case COMP_TRB_ERR:
2392                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2393                 status = -EILSEQ;
2394                 break;
2395         case COMP_SPLIT_ERR:
2396         case COMP_TX_ERR:
2397                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2398                 status = -EPROTO;
2399                 break;
2400         case COMP_BABBLE:
2401                 xhci_dbg(xhci, "Babble error on endpoint\n");
2402                 status = -EOVERFLOW;
2403                 break;
2404         case COMP_DB_ERR:
2405                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2406                 status = -ENOSR;
2407                 break;
2408         case COMP_BW_OVER:
2409                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2410                 break;
2411         case COMP_BUFF_OVER:
2412                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2413                 break;
2414         case COMP_UNDERRUN:
2415                 /*
2416                  * When the Isoch ring is empty, the xHC will generate
2417                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2418                  * Underrun Event for OUT Isoch endpoint.
2419                  */
2420                 xhci_dbg(xhci, "underrun event on endpoint\n");
2421                 if (!list_empty(&ep_ring->td_list))
2422                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2423                                         "still with TDs queued?\n",
2424                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2425                                  ep_index);
2426                 goto cleanup;
2427         case COMP_OVERRUN:
2428                 xhci_dbg(xhci, "overrun event on endpoint\n");
2429                 if (!list_empty(&ep_ring->td_list))
2430                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2431                                         "still with TDs queued?\n",
2432                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2433                                  ep_index);
2434                 goto cleanup;
2435         case COMP_DEV_ERR:
2436                 xhci_warn(xhci, "WARN: detect an incompatible device");
2437                 status = -EPROTO;
2438                 break;
2439         case COMP_MISSED_INT:
2440                 /*
2441                  * When encounter missed service error, one or more isoc tds
2442                  * may be missed by xHC.
2443                  * Set skip flag of the ep_ring; Complete the missed tds as
2444                  * short transfer when process the ep_ring next time.
2445                  */
2446                 ep->skip = true;
2447                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2448                 goto cleanup;
2449         default:
2450                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2451                         status = 0;
2452                         break;
2453                 }
2454                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2455                                 "busted\n");
2456                 goto cleanup;
2457         }
2458
2459         do {
2460                 /* This TRB should be in the TD at the head of this ring's
2461                  * TD list.
2462                  */
2463                 if (list_empty(&ep_ring->td_list)) {
2464                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2465                                         "with no TDs queued?\n",
2466                                   TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2467                                   ep_index);
2468                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2469                                  (le32_to_cpu(event->flags) &
2470                                   TRB_TYPE_BITMASK)>>10);
2471                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2472                         if (ep->skip) {
2473                                 ep->skip = false;
2474                                 xhci_dbg(xhci, "td_list is empty while skip "
2475                                                 "flag set. Clear skip flag.\n");
2476                         }
2477                         ret = 0;
2478                         goto cleanup;
2479                 }
2480
2481                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2482                 if (ep->skip && td_num == 0) {
2483                         ep->skip = false;
2484                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2485                                                 "Clear skip flag.\n");
2486                         ret = 0;
2487                         goto cleanup;
2488                 }
2489
2490                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2491                 if (ep->skip)
2492                         td_num--;
2493
2494                 /* Is this a TRB in the currently executing TD? */
2495                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2496                                 td->last_trb, event_dma);
2497
2498                 /*
2499                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2500                  * is not in the current TD pointed by ep_ring->dequeue because
2501                  * that the hardware dequeue pointer still at the previous TRB
2502                  * of the current TD. The previous TRB maybe a Link TD or the
2503                  * last TRB of the previous TD. The command completion handle
2504                  * will take care the rest.
2505                  */
2506                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2507                         ret = 0;
2508                         goto cleanup;
2509                 }
2510
2511                 if (!event_seg) {
2512                         if (!ep->skip ||
2513                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2514                                 /* Some host controllers give a spurious
2515                                  * successful event after a short transfer.
2516                                  * Ignore it.
2517                                  */
2518                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2519                                                 ep_ring->last_td_was_short) {
2520                                         ep_ring->last_td_was_short = false;
2521                                         ret = 0;
2522                                         goto cleanup;
2523                                 }
2524                                 /* HC is busted, give up! */
2525                                 xhci_err(xhci,
2526                                         "ERROR Transfer event TRB DMA ptr not "
2527                                         "part of current TD\n");
2528                                 return -ESHUTDOWN;
2529                         }
2530
2531                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2532                         goto cleanup;
2533                 }
2534                 if (trb_comp_code == COMP_SHORT_TX)
2535                         ep_ring->last_td_was_short = true;
2536                 else
2537                         ep_ring->last_td_was_short = false;
2538
2539                 if (ep->skip) {
2540                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2541                         ep->skip = false;
2542                 }
2543
2544                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2545                                                 sizeof(*event_trb)];
2546                 /*
2547                  * No-op TRB should not trigger interrupts.
2548                  * If event_trb is a no-op TRB, it means the
2549                  * corresponding TD has been cancelled. Just ignore
2550                  * the TD.
2551                  */
2552                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2553                         xhci_dbg(xhci,
2554                                  "event_trb is a no-op TRB. Skip it\n");
2555                         goto cleanup;
2556                 }
2557
2558                 /* Now update the urb's actual_length and give back to
2559                  * the core
2560                  */
2561                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2562                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2563                                                  &status);
2564                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2565                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2566                                                  &status);
2567                 else
2568                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2569                                                  ep, &status);
2570
2571 cleanup:
2572                 /*
2573                  * Do not update event ring dequeue pointer if ep->skip is set.
2574                  * Will roll back to continue process missed tds.
2575                  */
2576                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2577                         inc_deq(xhci, xhci->event_ring);
2578                 }
2579
2580                 if (ret) {
2581                         urb = td->urb;
2582                         urb_priv = urb->hcpriv;
2583                         /* Leave the TD around for the reset endpoint function
2584                          * to use(but only if it's not a control endpoint,
2585                          * since we already queued the Set TR dequeue pointer
2586                          * command for stalled control endpoints).
2587                          */
2588                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2589                                 (trb_comp_code != COMP_STALL &&
2590                                         trb_comp_code != COMP_BABBLE))
2591                                 xhci_urb_free_priv(xhci, urb_priv);
2592
2593                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2594                         if ((urb->actual_length != urb->transfer_buffer_length &&
2595                                                 (urb->transfer_flags &
2596                                                  URB_SHORT_NOT_OK)) ||
2597                                         (status != 0 &&
2598                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2599                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2600                                                 "expected = %d, status = %d\n",
2601                                                 urb, urb->actual_length,
2602                                                 urb->transfer_buffer_length,
2603                                                 status);
2604                         spin_unlock(&xhci->lock);
2605                         /* EHCI, UHCI, and OHCI always unconditionally set the
2606                          * urb->status of an isochronous endpoint to 0.
2607                          */
2608                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2609                                 status = 0;
2610                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2611                         spin_lock(&xhci->lock);
2612                 }
2613
2614         /*
2615          * If ep->skip is set, it means there are missed tds on the
2616          * endpoint ring need to take care of.
2617          * Process them as short transfer until reach the td pointed by
2618          * the event.
2619          */
2620         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2621
2622         return 0;
2623 }
2624
2625 /*
2626  * This function handles all OS-owned events on the event ring.  It may drop
2627  * xhci->lock between event processing (e.g. to pass up port status changes).
2628  * Returns >0 for "possibly more events to process" (caller should call again),
2629  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2630  */
2631 static int xhci_handle_event(struct xhci_hcd *xhci)
2632 {
2633         union xhci_trb *event;
2634         int update_ptrs = 1;
2635         int ret;
2636
2637         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2638                 xhci->error_bitmask |= 1 << 1;
2639                 return 0;
2640         }
2641
2642         event = xhci->event_ring->dequeue;
2643         /* Does the HC or OS own the TRB? */
2644         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2645             xhci->event_ring->cycle_state) {
2646                 xhci->error_bitmask |= 1 << 2;
2647                 return 0;
2648         }
2649
2650         /*
2651          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2652          * speculative reads of the event's flags/data below.
2653          */
2654         rmb();
2655         /* FIXME: Handle more event types. */
2656         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2657         case TRB_TYPE(TRB_COMPLETION):
2658                 handle_cmd_completion(xhci, &event->event_cmd);
2659                 break;
2660         case TRB_TYPE(TRB_PORT_STATUS):
2661                 handle_port_status(xhci, event);
2662                 update_ptrs = 0;
2663                 break;
2664         case TRB_TYPE(TRB_TRANSFER):
2665                 ret = handle_tx_event(xhci, &event->trans_event);
2666                 if (ret < 0)
2667                         xhci->error_bitmask |= 1 << 9;
2668                 else
2669                         update_ptrs = 0;
2670                 break;
2671         case TRB_TYPE(TRB_DEV_NOTE):
2672                 handle_device_notification(xhci, event);
2673                 break;
2674         default:
2675                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2676                     TRB_TYPE(48))
2677                         handle_vendor_event(xhci, event);
2678                 else
2679                         xhci->error_bitmask |= 1 << 3;
2680         }
2681         /* Any of the above functions may drop and re-acquire the lock, so check
2682          * to make sure a watchdog timer didn't mark the host as non-responsive.
2683          */
2684         if (xhci->xhc_state & XHCI_STATE_DYING) {
2685                 xhci_dbg(xhci, "xHCI host dying, returning from "
2686                                 "event handler.\n");
2687                 return 0;
2688         }
2689
2690         if (update_ptrs)
2691                 /* Update SW event ring dequeue pointer */
2692                 inc_deq(xhci, xhci->event_ring);
2693
2694         /* Are there more items on the event ring?  Caller will call us again to
2695          * check.
2696          */
2697         return 1;
2698 }
2699
2700 /*
2701  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2702  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2703  * indicators of an event TRB error, but we check the status *first* to be safe.
2704  */
2705 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2706 {
2707         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2708         u32 status;
2709         union xhci_trb *trb;
2710         u64 temp_64;
2711         union xhci_trb *event_ring_deq;
2712         dma_addr_t deq;
2713
2714         spin_lock(&xhci->lock);
2715         trb = xhci->event_ring->dequeue;
2716         /* Check if the xHC generated the interrupt, or the irq is shared */
2717         status = xhci_readl(xhci, &xhci->op_regs->status);
2718         if (status == 0xffffffff)
2719                 goto hw_died;
2720
2721         if (!(status & STS_EINT)) {
2722                 spin_unlock(&xhci->lock);
2723                 return IRQ_NONE;
2724         }
2725         if (status & STS_FATAL) {
2726                 xhci_warn(xhci, "WARNING: Host System Error\n");
2727                 xhci_halt(xhci);
2728 hw_died:
2729                 spin_unlock(&xhci->lock);
2730                 return -ESHUTDOWN;
2731         }
2732
2733         /*
2734          * Clear the op reg interrupt status first,
2735          * so we can receive interrupts from other MSI-X interrupters.
2736          * Write 1 to clear the interrupt status.
2737          */
2738         status |= STS_EINT;
2739         xhci_writel(xhci, status, &xhci->op_regs->status);
2740         /* FIXME when MSI-X is supported and there are multiple vectors */
2741         /* Clear the MSI-X event interrupt status */
2742
2743         if (hcd->irq) {
2744                 u32 irq_pending;
2745                 /* Acknowledge the PCI interrupt */
2746                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2747                 irq_pending |= IMAN_IP;
2748                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2749         }
2750
2751         if (xhci->xhc_state & XHCI_STATE_DYING) {
2752                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2753                                 "Shouldn't IRQs be disabled?\n");
2754                 /* Clear the event handler busy flag (RW1C);
2755                  * the event ring should be empty.
2756                  */
2757                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2758                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2759                                 &xhci->ir_set->erst_dequeue);
2760                 spin_unlock(&xhci->lock);
2761
2762                 return IRQ_HANDLED;
2763         }
2764
2765         event_ring_deq = xhci->event_ring->dequeue;
2766         /* FIXME this should be a delayed service routine
2767          * that clears the EHB.
2768          */
2769         while (xhci_handle_event(xhci) > 0) {}
2770
2771         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2772         /* If necessary, update the HW's version of the event ring deq ptr. */
2773         if (event_ring_deq != xhci->event_ring->dequeue) {
2774                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2775                                 xhci->event_ring->dequeue);
2776                 if (deq == 0)
2777                         xhci_warn(xhci, "WARN something wrong with SW event "
2778                                         "ring dequeue ptr.\n");
2779                 /* Update HC event ring dequeue pointer */
2780                 temp_64 &= ERST_PTR_MASK;
2781                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2782         }
2783
2784         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2785         temp_64 |= ERST_EHB;
2786         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2787
2788         spin_unlock(&xhci->lock);
2789
2790         return IRQ_HANDLED;
2791 }
2792
2793 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2794 {
2795         return xhci_irq(hcd);
2796 }
2797
2798 /****           Endpoint Ring Operations        ****/
2799
2800 /*
2801  * Generic function for queueing a TRB on a ring.
2802  * The caller must have checked to make sure there's room on the ring.
2803  *
2804  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2805  *                      prepare_transfer()?
2806  */
2807 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2808                 bool more_trbs_coming,
2809                 u32 field1, u32 field2, u32 field3, u32 field4)
2810 {
2811         struct xhci_generic_trb *trb;
2812
2813         trb = &ring->enqueue->generic;
2814         trb->field[0] = cpu_to_le32(field1);
2815         trb->field[1] = cpu_to_le32(field2);
2816         trb->field[2] = cpu_to_le32(field3);
2817         trb->field[3] = cpu_to_le32(field4);
2818         inc_enq(xhci, ring, more_trbs_coming);
2819 }
2820
2821 /*
2822  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2823  * FIXME allocate segments if the ring is full.
2824  */
2825 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2826                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2827 {
2828         unsigned int num_trbs_needed;
2829
2830         /* Make sure the endpoint has been added to xHC schedule */
2831         switch (ep_state) {
2832         case EP_STATE_DISABLED:
2833                 /*
2834                  * USB core changed config/interfaces without notifying us,
2835                  * or hardware is reporting the wrong state.
2836                  */
2837                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2838                 return -ENOENT;
2839         case EP_STATE_ERROR:
2840                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2841                 /* FIXME event handling code for error needs to clear it */
2842                 /* XXX not sure if this should be -ENOENT or not */
2843                 return -EINVAL;
2844         case EP_STATE_HALTED:
2845                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2846         case EP_STATE_STOPPED:
2847         case EP_STATE_RUNNING:
2848                 break;
2849         default:
2850                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2851                 /*
2852                  * FIXME issue Configure Endpoint command to try to get the HC
2853                  * back into a known state.
2854                  */
2855                 return -EINVAL;
2856         }
2857
2858         while (1) {
2859                 if (room_on_ring(xhci, ep_ring, num_trbs))
2860                         break;
2861
2862                 if (ep_ring == xhci->cmd_ring) {
2863                         xhci_err(xhci, "Do not support expand command ring\n");
2864                         return -ENOMEM;
2865                 }
2866
2867                 xhci_dbg(xhci, "ERROR no room on ep ring, "
2868                                         "try ring expansion\n");
2869                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2870                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2871                                         mem_flags)) {
2872                         xhci_err(xhci, "Ring expansion failed\n");
2873                         return -ENOMEM;
2874                 }
2875         }
2876
2877         if (enqueue_is_link_trb(ep_ring)) {
2878                 struct xhci_ring *ring = ep_ring;
2879                 union xhci_trb *next;
2880
2881                 next = ring->enqueue;
2882
2883                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2884                         /* If we're not dealing with 0.95 hardware or isoc rings
2885                          * on AMD 0.96 host, clear the chain bit.
2886                          */
2887                         if (!xhci_link_trb_quirk(xhci) &&
2888                                         !(ring->type == TYPE_ISOC &&
2889                                          (xhci->quirks & XHCI_AMD_0x96_HOST)))
2890                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2891                         else
2892                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2893
2894                         wmb();
2895                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2896
2897                         /* Toggle the cycle bit after the last ring segment. */
2898                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2899                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2900                         }
2901                         ring->enq_seg = ring->enq_seg->next;
2902                         ring->enqueue = ring->enq_seg->trbs;
2903                         next = ring->enqueue;
2904                 }
2905         }
2906
2907         return 0;
2908 }
2909
2910 static int prepare_transfer(struct xhci_hcd *xhci,
2911                 struct xhci_virt_device *xdev,
2912                 unsigned int ep_index,
2913                 unsigned int stream_id,
2914                 unsigned int num_trbs,
2915                 struct urb *urb,
2916                 unsigned int td_index,
2917                 gfp_t mem_flags)
2918 {
2919         int ret;
2920         struct urb_priv *urb_priv;
2921         struct xhci_td  *td;
2922         struct xhci_ring *ep_ring;
2923         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2924
2925         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2926         if (!ep_ring) {
2927                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2928                                 stream_id);
2929                 return -EINVAL;
2930         }
2931
2932         ret = prepare_ring(xhci, ep_ring,
2933                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2934                            num_trbs, mem_flags);
2935         if (ret)
2936                 return ret;
2937
2938         urb_priv = urb->hcpriv;
2939         td = urb_priv->td[td_index];
2940
2941         INIT_LIST_HEAD(&td->td_list);
2942         INIT_LIST_HEAD(&td->cancelled_td_list);
2943
2944         if (td_index == 0) {
2945                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2946                 if (unlikely(ret))
2947                         return ret;
2948         }
2949
2950         td->urb = urb;
2951         /* Add this TD to the tail of the endpoint ring's TD list */
2952         list_add_tail(&td->td_list, &ep_ring->td_list);
2953         td->start_seg = ep_ring->enq_seg;
2954         td->first_trb = ep_ring->enqueue;
2955
2956         urb_priv->td[td_index] = td;
2957
2958         return 0;
2959 }
2960
2961 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2962 {
2963         int num_sgs, num_trbs, running_total, temp, i;
2964         struct scatterlist *sg;
2965
2966         sg = NULL;
2967         num_sgs = urb->num_mapped_sgs;
2968         temp = urb->transfer_buffer_length;
2969
2970         num_trbs = 0;
2971         for_each_sg(urb->sg, sg, num_sgs, i) {
2972                 unsigned int len = sg_dma_len(sg);
2973
2974                 /* Scatter gather list entries may cross 64KB boundaries */
2975                 running_total = TRB_MAX_BUFF_SIZE -
2976                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2977                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2978                 if (running_total != 0)
2979                         num_trbs++;
2980
2981                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2982                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2983                         num_trbs++;
2984                         running_total += TRB_MAX_BUFF_SIZE;
2985                 }
2986                 len = min_t(int, len, temp);
2987                 temp -= len;
2988                 if (temp == 0)
2989                         break;
2990         }
2991         return num_trbs;
2992 }
2993
2994 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2995 {
2996         if (num_trbs != 0)
2997                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2998                                 "TRBs, %d left\n", __func__,
2999                                 urb->ep->desc.bEndpointAddress, num_trbs);
3000         if (running_total != urb->transfer_buffer_length)
3001                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3002                                 "queued %#x (%d), asked for %#x (%d)\n",
3003                                 __func__,
3004                                 urb->ep->desc.bEndpointAddress,
3005                                 running_total, running_total,
3006                                 urb->transfer_buffer_length,
3007                                 urb->transfer_buffer_length);
3008 }
3009
3010 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3011                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3012                 struct xhci_generic_trb *start_trb)
3013 {
3014         /*
3015          * Pass all the TRBs to the hardware at once and make sure this write
3016          * isn't reordered.
3017          */
3018         wmb();
3019         if (start_cycle)
3020                 start_trb->field[3] |= cpu_to_le32(start_cycle);
3021         else
3022                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3023         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3024 }
3025
3026 /*
3027  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3028  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3029  * (comprised of sg list entries) can take several service intervals to
3030  * transmit.
3031  */
3032 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3033                 struct urb *urb, int slot_id, unsigned int ep_index)
3034 {
3035         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3036                         xhci->devs[slot_id]->out_ctx, ep_index);
3037         int xhci_interval;
3038         int ep_interval;
3039
3040         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3041         ep_interval = urb->interval;
3042         /* Convert to microframes */
3043         if (urb->dev->speed == USB_SPEED_LOW ||
3044                         urb->dev->speed == USB_SPEED_FULL)
3045                 ep_interval *= 8;
3046         /* FIXME change this to a warning and a suggestion to use the new API
3047          * to set the polling interval (once the API is added).
3048          */
3049         if (xhci_interval != ep_interval) {
3050                 if (printk_ratelimit())
3051                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3052                                         " (%d microframe%s) than xHCI "
3053                                         "(%d microframe%s)\n",
3054                                         ep_interval,
3055                                         ep_interval == 1 ? "" : "s",
3056                                         xhci_interval,
3057                                         xhci_interval == 1 ? "" : "s");
3058                 urb->interval = xhci_interval;
3059                 /* Convert back to frames for LS/FS devices */
3060                 if (urb->dev->speed == USB_SPEED_LOW ||
3061                                 urb->dev->speed == USB_SPEED_FULL)
3062                         urb->interval /= 8;
3063         }
3064         return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3065 }
3066
3067 /*
3068  * The TD size is the number of bytes remaining in the TD (including this TRB),
3069  * right shifted by 10.
3070  * It must fit in bits 21:17, so it can't be bigger than 31.
3071  */
3072 static u32 xhci_td_remainder(unsigned int remainder)
3073 {
3074         u32 max = (1 << (21 - 17 + 1)) - 1;
3075
3076         if ((remainder >> 10) >= max)
3077                 return max << 17;
3078         else
3079                 return (remainder >> 10) << 17;
3080 }
3081
3082 /*
3083  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3084  * packets remaining in the TD (*not* including this TRB).
3085  *
3086  * Total TD packet count = total_packet_count =
3087  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3088  *
3089  * Packets transferred up to and including this TRB = packets_transferred =
3090  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3091  *
3092  * TD size = total_packet_count - packets_transferred
3093  *
3094  * It must fit in bits 21:17, so it can't be bigger than 31.
3095  * The last TRB in a TD must have the TD size set to zero.
3096  */
3097 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3098                 unsigned int total_packet_count, struct urb *urb,
3099                 unsigned int num_trbs_left)
3100 {
3101         int packets_transferred;
3102
3103         /* One TRB with a zero-length data packet. */
3104         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3105                 return 0;
3106
3107         /* All the TRB queueing functions don't count the current TRB in
3108          * running_total.
3109          */
3110         packets_transferred = (running_total + trb_buff_len) /
3111                 usb_endpoint_maxp(&urb->ep->desc);
3112
3113         if ((total_packet_count - packets_transferred) > 31)
3114                 return 31 << 17;
3115         return (total_packet_count - packets_transferred) << 17;
3116 }
3117
3118 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3119                 struct urb *urb, int slot_id, unsigned int ep_index)
3120 {
3121         struct xhci_ring *ep_ring;
3122         unsigned int num_trbs;
3123         struct urb_priv *urb_priv;
3124         struct xhci_td *td;
3125         struct scatterlist *sg;
3126         int num_sgs;
3127         int trb_buff_len, this_sg_len, running_total;
3128         unsigned int total_packet_count;
3129         bool first_trb;
3130         u64 addr;
3131         bool more_trbs_coming;
3132
3133         struct xhci_generic_trb *start_trb;
3134         int start_cycle;
3135
3136         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3137         if (!ep_ring)
3138                 return -EINVAL;
3139
3140         num_trbs = count_sg_trbs_needed(xhci, urb);
3141         num_sgs = urb->num_mapped_sgs;
3142         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3143                         usb_endpoint_maxp(&urb->ep->desc));
3144
3145         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3146                         ep_index, urb->stream_id,
3147                         num_trbs, urb, 0, mem_flags);
3148         if (trb_buff_len < 0)
3149                 return trb_buff_len;
3150
3151         urb_priv = urb->hcpriv;
3152         td = urb_priv->td[0];
3153
3154         /*
3155          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3156          * until we've finished creating all the other TRBs.  The ring's cycle
3157          * state may change as we enqueue the other TRBs, so save it too.
3158          */
3159         start_trb = &ep_ring->enqueue->generic;
3160         start_cycle = ep_ring->cycle_state;
3161
3162         running_total = 0;
3163         /*
3164          * How much data is in the first TRB?
3165          *
3166          * There are three forces at work for TRB buffer pointers and lengths:
3167          * 1. We don't want to walk off the end of this sg-list entry buffer.
3168          * 2. The transfer length that the driver requested may be smaller than
3169          *    the amount of memory allocated for this scatter-gather list.
3170          * 3. TRBs buffers can't cross 64KB boundaries.
3171          */
3172         sg = urb->sg;
3173         addr = (u64) sg_dma_address(sg);
3174         this_sg_len = sg_dma_len(sg);
3175         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3176         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3177         if (trb_buff_len > urb->transfer_buffer_length)
3178                 trb_buff_len = urb->transfer_buffer_length;
3179
3180         first_trb = true;
3181         /* Queue the first TRB, even if it's zero-length */
3182         do {
3183                 u32 field = 0;
3184                 u32 length_field = 0;
3185                 u32 remainder = 0;
3186
3187                 /* Don't change the cycle bit of the first TRB until later */
3188                 if (first_trb) {
3189                         first_trb = false;
3190                         if (start_cycle == 0)
3191                                 field |= 0x1;
3192                 } else
3193                         field |= ep_ring->cycle_state;
3194
3195                 /* Chain all the TRBs together; clear the chain bit in the last
3196                  * TRB to indicate it's the last TRB in the chain.
3197                  */
3198                 if (num_trbs > 1) {
3199                         field |= TRB_CHAIN;
3200                 } else {
3201                         /* FIXME - add check for ZERO_PACKET flag before this */
3202                         td->last_trb = ep_ring->enqueue;
3203                         field |= TRB_IOC;
3204                 }
3205
3206                 /* Only set interrupt on short packet for IN endpoints */
3207                 if (usb_urb_dir_in(urb))
3208                         field |= TRB_ISP;
3209
3210                 if (TRB_MAX_BUFF_SIZE -
3211                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3212                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3213                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3214                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3215                                         (unsigned int) addr + trb_buff_len);
3216                 }
3217
3218                 /* Set the TRB length, TD size, and interrupter fields. */
3219                 if (xhci->hci_version < 0x100) {
3220                         remainder = xhci_td_remainder(
3221                                         urb->transfer_buffer_length -
3222                                         running_total);
3223                 } else {
3224                         remainder = xhci_v1_0_td_remainder(running_total,
3225                                         trb_buff_len, total_packet_count, urb,
3226                                         num_trbs - 1);
3227                 }
3228                 length_field = TRB_LEN(trb_buff_len) |
3229                         remainder |
3230                         TRB_INTR_TARGET(0);
3231
3232                 if (num_trbs > 1)
3233                         more_trbs_coming = true;
3234                 else
3235                         more_trbs_coming = false;
3236                 queue_trb(xhci, ep_ring, more_trbs_coming,
3237                                 lower_32_bits(addr),
3238                                 upper_32_bits(addr),
3239                                 length_field,
3240                                 field | TRB_TYPE(TRB_NORMAL));
3241                 --num_trbs;
3242                 running_total += trb_buff_len;
3243
3244                 /* Calculate length for next transfer --
3245                  * Are we done queueing all the TRBs for this sg entry?
3246                  */
3247                 this_sg_len -= trb_buff_len;
3248                 if (this_sg_len == 0) {
3249                         --num_sgs;
3250                         if (num_sgs == 0)
3251                                 break;
3252                         sg = sg_next(sg);
3253                         addr = (u64) sg_dma_address(sg);
3254                         this_sg_len = sg_dma_len(sg);
3255                 } else {
3256                         addr += trb_buff_len;
3257                 }
3258
3259                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3260                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3261                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3262                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3263                         trb_buff_len =
3264                                 urb->transfer_buffer_length - running_total;
3265         } while (running_total < urb->transfer_buffer_length);
3266
3267         check_trb_math(urb, num_trbs, running_total);
3268         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3269                         start_cycle, start_trb);
3270         return 0;
3271 }
3272
3273 /* This is very similar to what ehci-q.c qtd_fill() does */
3274 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3275                 struct urb *urb, int slot_id, unsigned int ep_index)
3276 {
3277         struct xhci_ring *ep_ring;
3278         struct urb_priv *urb_priv;
3279         struct xhci_td *td;
3280         int num_trbs;
3281         struct xhci_generic_trb *start_trb;
3282         bool first_trb;
3283         bool more_trbs_coming;
3284         int start_cycle;
3285         u32 field, length_field;
3286
3287         int running_total, trb_buff_len, ret;
3288         unsigned int total_packet_count;
3289         u64 addr;
3290
3291         if (urb->num_sgs)
3292                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3293
3294         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3295         if (!ep_ring)
3296                 return -EINVAL;
3297
3298         num_trbs = 0;
3299         /* How much data is (potentially) left before the 64KB boundary? */
3300         running_total = TRB_MAX_BUFF_SIZE -
3301                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3302         running_total &= TRB_MAX_BUFF_SIZE - 1;
3303
3304         /* If there's some data on this 64KB chunk, or we have to send a
3305          * zero-length transfer, we need at least one TRB
3306          */
3307         if (running_total != 0 || urb->transfer_buffer_length == 0)
3308                 num_trbs++;
3309         /* How many more 64KB chunks to transfer, how many more TRBs? */
3310         while (running_total < urb->transfer_buffer_length) {
3311                 num_trbs++;
3312                 running_total += TRB_MAX_BUFF_SIZE;
3313         }
3314         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3315
3316         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3317                         ep_index, urb->stream_id,
3318                         num_trbs, urb, 0, mem_flags);
3319         if (ret < 0)
3320                 return ret;
3321
3322         urb_priv = urb->hcpriv;
3323         td = urb_priv->td[0];
3324
3325         /*
3326          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3327          * until we've finished creating all the other TRBs.  The ring's cycle
3328          * state may change as we enqueue the other TRBs, so save it too.
3329          */
3330         start_trb = &ep_ring->enqueue->generic;
3331         start_cycle = ep_ring->cycle_state;
3332
3333         running_total = 0;
3334         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3335                         usb_endpoint_maxp(&urb->ep->desc));
3336         /* How much data is in the first TRB? */
3337         addr = (u64) urb->transfer_dma;
3338         trb_buff_len = TRB_MAX_BUFF_SIZE -
3339                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3340         if (trb_buff_len > urb->transfer_buffer_length)
3341                 trb_buff_len = urb->transfer_buffer_length;
3342
3343         first_trb = true;
3344
3345         /* Queue the first TRB, even if it's zero-length */
3346         do {
3347                 u32 remainder = 0;
3348                 field = 0;
3349
3350                 /* Don't change the cycle bit of the first TRB until later */
3351                 if (first_trb) {
3352                         first_trb = false;
3353                         if (start_cycle == 0)
3354                                 field |= 0x1;
3355                 } else
3356                         field |= ep_ring->cycle_state;
3357
3358                 /* Chain all the TRBs together; clear the chain bit in the last
3359                  * TRB to indicate it's the last TRB in the chain.
3360                  */
3361                 if (num_trbs > 1) {
3362                         field |= TRB_CHAIN;
3363                 } else {
3364                         /* FIXME - add check for ZERO_PACKET flag before this */
3365                         td->last_trb = ep_ring->enqueue;
3366                         field |= TRB_IOC;
3367                 }
3368
3369                 /* Only set interrupt on short packet for IN endpoints */
3370                 if (usb_urb_dir_in(urb))
3371                         field |= TRB_ISP;
3372
3373                 /* Set the TRB length, TD size, and interrupter fields. */
3374                 if (xhci->hci_version < 0x100) {
3375                         remainder = xhci_td_remainder(
3376                                         urb->transfer_buffer_length -
3377                                         running_total);
3378                 } else {
3379                         remainder = xhci_v1_0_td_remainder(running_total,
3380                                         trb_buff_len, total_packet_count, urb,
3381                                         num_trbs - 1);
3382                 }
3383                 length_field = TRB_LEN(trb_buff_len) |
3384                         remainder |
3385                         TRB_INTR_TARGET(0);
3386
3387                 if (num_trbs > 1)
3388                         more_trbs_coming = true;
3389                 else
3390                         more_trbs_coming = false;
3391                 queue_trb(xhci, ep_ring, more_trbs_coming,
3392                                 lower_32_bits(addr),
3393                                 upper_32_bits(addr),
3394                                 length_field,
3395                                 field | TRB_TYPE(TRB_NORMAL));
3396                 --num_trbs;
3397                 running_total += trb_buff_len;
3398
3399                 /* Calculate length for next transfer */
3400                 addr += trb_buff_len;
3401                 trb_buff_len = urb->transfer_buffer_length - running_total;
3402                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3403                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3404         } while (running_total < urb->transfer_buffer_length);
3405
3406         check_trb_math(urb, num_trbs, running_total);
3407         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3408                         start_cycle, start_trb);
3409         return 0;
3410 }
3411
3412 /* Caller must have locked xhci->lock */
3413 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3414                 struct urb *urb, int slot_id, unsigned int ep_index)
3415 {
3416         struct xhci_ring *ep_ring;
3417         int num_trbs;
3418         int ret;
3419         struct usb_ctrlrequest *setup;
3420         struct xhci_generic_trb *start_trb;
3421         int start_cycle;
3422         u32 field, length_field;
3423         struct urb_priv *urb_priv;
3424         struct xhci_td *td;
3425
3426         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3427         if (!ep_ring)
3428                 return -EINVAL;
3429
3430         /*
3431          * Need to copy setup packet into setup TRB, so we can't use the setup
3432          * DMA address.
3433          */
3434         if (!urb->setup_packet)
3435                 return -EINVAL;
3436
3437         /* 1 TRB for setup, 1 for status */
3438         num_trbs = 2;
3439         /*
3440          * Don't need to check if we need additional event data and normal TRBs,
3441          * since data in control transfers will never get bigger than 16MB
3442          * XXX: can we get a buffer that crosses 64KB boundaries?
3443          */
3444         if (urb->transfer_buffer_length > 0)
3445                 num_trbs++;
3446         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3447                         ep_index, urb->stream_id,
3448                         num_trbs, urb, 0, mem_flags);
3449         if (ret < 0)
3450                 return ret;
3451
3452         urb_priv = urb->hcpriv;
3453         td = urb_priv->td[0];
3454
3455         /*
3456          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3457          * until we've finished creating all the other TRBs.  The ring's cycle
3458          * state may change as we enqueue the other TRBs, so save it too.
3459          */
3460         start_trb = &ep_ring->enqueue->generic;
3461         start_cycle = ep_ring->cycle_state;
3462
3463         /* Queue setup TRB - see section 6.4.1.2.1 */
3464         /* FIXME better way to translate setup_packet into two u32 fields? */
3465         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3466         field = 0;
3467         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3468         if (start_cycle == 0)
3469                 field |= 0x1;
3470
3471         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3472         if (xhci->hci_version == 0x100) {
3473                 if (urb->transfer_buffer_length > 0) {
3474                         if (setup->bRequestType & USB_DIR_IN)
3475                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3476                         else
3477                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3478                 }
3479         }
3480
3481         queue_trb(xhci, ep_ring, true,
3482                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3483                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3484                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3485                   /* Immediate data in pointer */
3486                   field);
3487
3488         /* If there's data, queue data TRBs */
3489         /* Only set interrupt on short packet for IN endpoints */
3490         if (usb_urb_dir_in(urb))
3491                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3492         else
3493                 field = TRB_TYPE(TRB_DATA);
3494
3495         length_field = TRB_LEN(urb->transfer_buffer_length) |
3496                 xhci_td_remainder(urb->transfer_buffer_length) |
3497                 TRB_INTR_TARGET(0);
3498         if (urb->transfer_buffer_length > 0) {
3499                 if (setup->bRequestType & USB_DIR_IN)
3500                         field |= TRB_DIR_IN;
3501                 queue_trb(xhci, ep_ring, true,
3502                                 lower_32_bits(urb->transfer_dma),
3503                                 upper_32_bits(urb->transfer_dma),
3504                                 length_field,
3505                                 field | ep_ring->cycle_state);
3506         }
3507
3508         /* Save the DMA address of the last TRB in the TD */
3509         td->last_trb = ep_ring->enqueue;
3510
3511         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3512         /* If the device sent data, the status stage is an OUT transfer */
3513         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3514                 field = 0;
3515         else
3516                 field = TRB_DIR_IN;
3517         queue_trb(xhci, ep_ring, false,
3518                         0,
3519                         0,
3520                         TRB_INTR_TARGET(0),
3521                         /* Event on completion */
3522                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3523
3524         giveback_first_trb(xhci, slot_id, ep_index, 0,
3525                         start_cycle, start_trb);
3526         return 0;
3527 }
3528
3529 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3530                 struct urb *urb, int i)
3531 {
3532         int num_trbs = 0;
3533         u64 addr, td_len;
3534
3535         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3536         td_len = urb->iso_frame_desc[i].length;
3537
3538         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3539                         TRB_MAX_BUFF_SIZE);
3540         if (num_trbs == 0)
3541                 num_trbs++;
3542
3543         return num_trbs;
3544 }
3545
3546 /*
3547  * The transfer burst count field of the isochronous TRB defines the number of
3548  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3549  * devices can burst up to bMaxBurst number of packets per service interval.
3550  * This field is zero based, meaning a value of zero in the field means one
3551  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3552  * zero.  Only xHCI 1.0 host controllers support this field.
3553  */
3554 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3555                 struct usb_device *udev,
3556                 struct urb *urb, unsigned int total_packet_count)
3557 {
3558         unsigned int max_burst;
3559
3560         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3561                 return 0;
3562
3563         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3564         return roundup(total_packet_count, max_burst + 1) - 1;
3565 }
3566
3567 /*
3568  * Returns the number of packets in the last "burst" of packets.  This field is
3569  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3570  * the last burst packet count is equal to the total number of packets in the
3571  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3572  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3573  * contain 1 to (bMaxBurst + 1) packets.
3574  */
3575 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3576                 struct usb_device *udev,
3577                 struct urb *urb, unsigned int total_packet_count)
3578 {
3579         unsigned int max_burst;
3580         unsigned int residue;
3581
3582         if (xhci->hci_version < 0x100)
3583                 return 0;
3584
3585         switch (udev->speed) {
3586         case USB_SPEED_SUPER:
3587                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3588                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3589                 residue = total_packet_count % (max_burst + 1);
3590                 /* If residue is zero, the last burst contains (max_burst + 1)
3591                  * number of packets, but the TLBPC field is zero-based.
3592                  */
3593                 if (residue == 0)
3594                         return max_burst;
3595                 return residue - 1;
3596         default:
3597                 if (total_packet_count == 0)
3598                         return 0;
3599                 return total_packet_count - 1;
3600         }
3601 }
3602
3603 /* This is for isoc transfer */
3604 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3605                 struct urb *urb, int slot_id, unsigned int ep_index)
3606 {
3607         struct xhci_ring *ep_ring;
3608         struct urb_priv *urb_priv;
3609         struct xhci_td *td;
3610         int num_tds, trbs_per_td;
3611         struct xhci_generic_trb *start_trb;
3612         bool first_trb;
3613         int start_cycle;
3614         u32 field, length_field;
3615         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3616         u64 start_addr, addr;
3617         int i, j;
3618         bool more_trbs_coming;
3619
3620         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3621
3622         num_tds = urb->number_of_packets;
3623         if (num_tds < 1) {
3624                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3625                 return -EINVAL;
3626         }
3627
3628         start_addr = (u64) urb->transfer_dma;
3629         start_trb = &ep_ring->enqueue->generic;
3630         start_cycle = ep_ring->cycle_state;
3631
3632         urb_priv = urb->hcpriv;
3633         /* Queue the first TRB, even if it's zero-length */
3634         for (i = 0; i < num_tds; i++) {
3635                 unsigned int total_packet_count;
3636                 unsigned int burst_count;
3637                 unsigned int residue;
3638
3639                 first_trb = true;
3640                 running_total = 0;
3641                 addr = start_addr + urb->iso_frame_desc[i].offset;
3642                 td_len = urb->iso_frame_desc[i].length;
3643                 td_remain_len = td_len;
3644                 total_packet_count = DIV_ROUND_UP(td_len,
3645                                 usb_endpoint_maxp(&urb->ep->desc));
3646                 /* A zero-length transfer still involves at least one packet. */
3647                 if (total_packet_count == 0)
3648                         total_packet_count++;
3649                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3650                                 total_packet_count);
3651                 residue = xhci_get_last_burst_packet_count(xhci,
3652                                 urb->dev, urb, total_packet_count);
3653
3654                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3655
3656                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3657                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3658                 if (ret < 0) {
3659                         if (i == 0)
3660                                 return ret;
3661                         goto cleanup;
3662                 }
3663
3664                 td = urb_priv->td[i];
3665                 for (j = 0; j < trbs_per_td; j++) {
3666                         u32 remainder = 0;
3667                         field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3668
3669                         if (first_trb) {
3670                                 /* Queue the isoc TRB */
3671                                 field |= TRB_TYPE(TRB_ISOC);
3672                                 /* Assume URB_ISO_ASAP is set */
3673                                 field |= TRB_SIA;
3674                                 if (i == 0) {
3675                                         if (start_cycle == 0)
3676                                                 field |= 0x1;
3677                                 } else
3678                                         field |= ep_ring->cycle_state;
3679                                 first_trb = false;
3680                         } else {
3681                                 /* Queue other normal TRBs */
3682                                 field |= TRB_TYPE(TRB_NORMAL);
3683                                 field |= ep_ring->cycle_state;
3684                         }
3685
3686                         /* Only set interrupt on short packet for IN EPs */
3687                         if (usb_urb_dir_in(urb))
3688                                 field |= TRB_ISP;
3689
3690                         /* Chain all the TRBs together; clear the chain bit in
3691                          * the last TRB to indicate it's the last TRB in the
3692                          * chain.
3693                          */
3694                         if (j < trbs_per_td - 1) {
3695                                 field |= TRB_CHAIN;
3696                                 more_trbs_coming = true;
3697                         } else {
3698                                 td->last_trb = ep_ring->enqueue;
3699                                 field |= TRB_IOC;
3700                                 if (xhci->hci_version == 0x100 &&
3701                                                 !(xhci->quirks &
3702                                                         XHCI_AVOID_BEI)) {
3703                                         /* Set BEI bit except for the last td */
3704                                         if (i < num_tds - 1)
3705                                                 field |= TRB_BEI;
3706                                 }
3707                                 more_trbs_coming = false;
3708                         }
3709
3710                         /* Calculate TRB length */
3711                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3712                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3713                         if (trb_buff_len > td_remain_len)
3714                                 trb_buff_len = td_remain_len;
3715
3716                         /* Set the TRB length, TD size, & interrupter fields. */
3717                         if (xhci->hci_version < 0x100) {
3718                                 remainder = xhci_td_remainder(
3719                                                 td_len - running_total);
3720                         } else {
3721                                 remainder = xhci_v1_0_td_remainder(
3722                                                 running_total, trb_buff_len,
3723                                                 total_packet_count, urb,
3724                                                 (trbs_per_td - j - 1));
3725                         }
3726                         length_field = TRB_LEN(trb_buff_len) |
3727                                 remainder |
3728                                 TRB_INTR_TARGET(0);
3729
3730                         queue_trb(xhci, ep_ring, more_trbs_coming,
3731                                 lower_32_bits(addr),
3732                                 upper_32_bits(addr),
3733                                 length_field,
3734                                 field);
3735                         running_total += trb_buff_len;
3736
3737                         addr += trb_buff_len;
3738                         td_remain_len -= trb_buff_len;
3739                 }
3740
3741                 /* Check TD length */
3742                 if (running_total != td_len) {
3743                         xhci_err(xhci, "ISOC TD length unmatch\n");
3744                         ret = -EINVAL;
3745                         goto cleanup;
3746                 }
3747         }
3748
3749         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3750                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3751                         usb_amd_quirk_pll_disable();
3752         }
3753         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3754
3755         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3756                         start_cycle, start_trb);
3757         return 0;
3758 cleanup:
3759         /* Clean up a partially enqueued isoc transfer. */
3760
3761         for (i--; i >= 0; i--)
3762                 list_del_init(&urb_priv->td[i]->td_list);
3763
3764         /* Use the first TD as a temporary variable to turn the TDs we've queued
3765          * into No-ops with a software-owned cycle bit. That way the hardware
3766          * won't accidentally start executing bogus TDs when we partially
3767          * overwrite them.  td->first_trb and td->start_seg are already set.
3768          */
3769         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3770         /* Every TRB except the first & last will have its cycle bit flipped. */
3771         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3772
3773         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3774         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3775         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3776         ep_ring->cycle_state = start_cycle;
3777         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3778         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3779         return ret;
3780 }
3781
3782 /*
3783  * Check transfer ring to guarantee there is enough room for the urb.
3784  * Update ISO URB start_frame and interval.
3785  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3786  * update the urb->start_frame by now.
3787  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3788  */
3789 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3790                 struct urb *urb, int slot_id, unsigned int ep_index)
3791 {
3792         struct xhci_virt_device *xdev;
3793         struct xhci_ring *ep_ring;
3794         struct xhci_ep_ctx *ep_ctx;
3795         int start_frame;
3796         int xhci_interval;
3797         int ep_interval;
3798         int num_tds, num_trbs, i;
3799         int ret;
3800
3801         xdev = xhci->devs[slot_id];
3802         ep_ring = xdev->eps[ep_index].ring;
3803         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3804
3805         num_trbs = 0;
3806         num_tds = urb->number_of_packets;
3807         for (i = 0; i < num_tds; i++)
3808                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3809
3810         /* Check the ring to guarantee there is enough room for the whole urb.
3811          * Do not insert any td of the urb to the ring if the check failed.
3812          */
3813         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3814                            num_trbs, mem_flags);
3815         if (ret)
3816                 return ret;
3817
3818         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3819         start_frame &= 0x3fff;
3820
3821         urb->start_frame = start_frame;
3822         if (urb->dev->speed == USB_SPEED_LOW ||
3823                         urb->dev->speed == USB_SPEED_FULL)
3824                 urb->start_frame >>= 3;
3825
3826         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3827         ep_interval = urb->interval;
3828         /* Convert to microframes */
3829         if (urb->dev->speed == USB_SPEED_LOW ||
3830                         urb->dev->speed == USB_SPEED_FULL)
3831                 ep_interval *= 8;
3832         /* FIXME change this to a warning and a suggestion to use the new API
3833          * to set the polling interval (once the API is added).
3834          */
3835         if (xhci_interval != ep_interval) {
3836                 if (printk_ratelimit())
3837                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3838                                         " (%d microframe%s) than xHCI "
3839                                         "(%d microframe%s)\n",
3840                                         ep_interval,
3841                                         ep_interval == 1 ? "" : "s",
3842                                         xhci_interval,
3843                                         xhci_interval == 1 ? "" : "s");
3844                 urb->interval = xhci_interval;
3845                 /* Convert back to frames for LS/FS devices */
3846                 if (urb->dev->speed == USB_SPEED_LOW ||
3847                                 urb->dev->speed == USB_SPEED_FULL)
3848                         urb->interval /= 8;
3849         }
3850         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3851
3852         return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3853 }
3854
3855 /****           Command Ring Operations         ****/
3856
3857 /* Generic function for queueing a command TRB on the command ring.
3858  * Check to make sure there's room on the command ring for one command TRB.
3859  * Also check that there's room reserved for commands that must not fail.
3860  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3861  * then only check for the number of reserved spots.
3862  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3863  * because the command event handler may want to resubmit a failed command.
3864  */
3865 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3866                 u32 field3, u32 field4, bool command_must_succeed)
3867 {
3868         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3869         int ret;
3870
3871         if (!command_must_succeed)
3872                 reserved_trbs++;
3873
3874         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3875                         reserved_trbs, GFP_ATOMIC);
3876         if (ret < 0) {
3877                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3878                 if (command_must_succeed)
3879                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3880                                         "unfailable commands failed.\n");
3881                 return ret;
3882         }
3883         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3884                         field4 | xhci->cmd_ring->cycle_state);
3885         return 0;
3886 }
3887
3888 /* Queue a slot enable or disable request on the command ring */
3889 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3890 {
3891         return queue_command(xhci, 0, 0, 0,
3892                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3893 }
3894
3895 /* Queue an address device command TRB */
3896 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3897                 u32 slot_id)
3898 {
3899         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3900                         upper_32_bits(in_ctx_ptr), 0,
3901                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3902                         false);
3903 }
3904
3905 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3906                 u32 field1, u32 field2, u32 field3, u32 field4)
3907 {
3908         return queue_command(xhci, field1, field2, field3, field4, false);
3909 }
3910
3911 /* Queue a reset device command TRB */
3912 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3913 {
3914         return queue_command(xhci, 0, 0, 0,
3915                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3916                         false);
3917 }
3918
3919 /* Queue a configure endpoint command TRB */
3920 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3921                 u32 slot_id, bool command_must_succeed)
3922 {
3923         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3924                         upper_32_bits(in_ctx_ptr), 0,
3925                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3926                         command_must_succeed);
3927 }
3928
3929 /* Queue an evaluate context command TRB */
3930 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3931                 u32 slot_id, bool command_must_succeed)
3932 {
3933         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3934                         upper_32_bits(in_ctx_ptr), 0,
3935                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3936                         command_must_succeed);
3937 }
3938
3939 /*
3940  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3941  * activity on an endpoint that is about to be suspended.
3942  */
3943 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3944                 unsigned int ep_index, int suspend)
3945 {
3946         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3947         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3948         u32 type = TRB_TYPE(TRB_STOP_RING);
3949         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3950
3951         return queue_command(xhci, 0, 0, 0,
3952                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3953 }
3954
3955 /* Set Transfer Ring Dequeue Pointer command.
3956  * This should not be used for endpoints that have streams enabled.
3957  */
3958 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3959                 unsigned int ep_index, unsigned int stream_id,
3960                 struct xhci_segment *deq_seg,
3961                 union xhci_trb *deq_ptr, u32 cycle_state)
3962 {
3963         dma_addr_t addr;
3964         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3965         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3966         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3967         u32 type = TRB_TYPE(TRB_SET_DEQ);
3968         struct xhci_virt_ep *ep;
3969
3970         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3971         if (addr == 0) {
3972                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3973                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3974                                 deq_seg, deq_ptr);
3975                 return 0;
3976         }
3977         ep = &xhci->devs[slot_id]->eps[ep_index];
3978         if ((ep->ep_state & SET_DEQ_PENDING)) {
3979                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3980                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3981                 return 0;
3982         }
3983         ep->queued_deq_seg = deq_seg;
3984         ep->queued_deq_ptr = deq_ptr;
3985         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3986                         upper_32_bits(addr), trb_stream_id,
3987                         trb_slot_id | trb_ep_index | type, false);
3988 }
3989
3990 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3991                 unsigned int ep_index)
3992 {
3993         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3994         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3995         u32 type = TRB_TYPE(TRB_RESET_EP);
3996
3997         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3998                         false);
3999 }