drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         unsigned long long addr;
 149
 150         ring->deq_updates++;
 151
 152         do {
 153                 /*
 154                  * Update the dequeue pointer further if that was a link TRB or
 155                  * we're at the end of an event ring segment (which doesn't have
 156                  * link TRBS)
 157                  */
 158                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 159                         if (consumer && last_trb_on_last_seg(xhci, ring,
 160                                                 ring->deq_seg, ring->dequeue)) {
 161                                 if (!in_interrupt())
 162                                         xhci_dbg(xhci, "Toggle cycle state "
 163                                                         "for ring %p = %i\n",
 164                                                         ring,
 165                                                         (unsigned int)
 166                                                         ring->cycle_state);
 167                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 168                         }
 169                         ring->deq_seg = ring->deq_seg->next;
 170                         ring->dequeue = ring->deq_seg->trbs;
 171                 } else {
 172                         ring->dequeue++;
 173                 }
 174         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 175
 176         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 177 }
 178
 179 /*
 180  * See Cycle bit rules. SW is the consumer for the event ring only.
 181  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 182  *
 183  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 184  * chain bit is set), then set the chain bit in all the following link TRBs.
 185  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 186  * have their chain bit cleared (so that each Link TRB is a separate TD).
 187  *
 188  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 189  * set, but other sections talk about dealing with the chain bit set.  This was
 190  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 191  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 192  *
 193  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 194  *                      prepare_transfer()?
 195  */
 196 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 197                 bool consumer, bool more_trbs_coming, bool isoc)
 198 {
 199         u32 chain;
 200         union xhci_trb *next;
 201         unsigned long long addr;
 202
 203         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 204         next = ++(ring->enqueue);
 205
 206         ring->enq_updates++;
 207         /* Update the dequeue pointer further if that was a link TRB or we're at
 208          * the end of an event ring segment (which doesn't have link TRBS)
 209          */
 210         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 211                 if (!consumer) {
 212                         if (ring != xhci->event_ring) {
 213                                 /*
 214                                  * If the caller doesn't plan on enqueueing more
 215                                  * TDs before ringing the doorbell, then we
 216                                  * don't want to give the link TRB to the
 217                                  * hardware just yet.  We'll give the link TRB
 218                                  * back in prepare_ring() just before we enqueue
 219                                  * the TD at the top of the ring.
 220                                  */
 221                                 if (!chain && !more_trbs_coming)
 222                                         break;
 223
 224                                 /* If we're not dealing with 0.95 hardware or
 225                                  * isoc rings on AMD 0.96 host,
 226                                  * carry over the chain bit of the previous TRB
 227                                  * (which may mean the chain bit is cleared).
 228                                  */
 229                                 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
 230                                                 && !xhci_link_trb_quirk(xhci)) {
 231                                         next->link.control &=
 232                                                 cpu_to_le32(~TRB_CHAIN);
 233                                         next->link.control |=
 234                                                 cpu_to_le32(chain);
 235                                 }
 236                                 /* Give this link TRB to the hardware */
 237                                 wmb();
 238                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 239                         }
 240                         /* Toggle the cycle bit after the last ring segment. */
 241                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 242                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 243                                 if (!in_interrupt())
 244                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 245                                                         ring,
 246                                                         (unsigned int) ring->cycle_state);
 247                         }
 248                 }
 249                 ring->enq_seg = ring->enq_seg->next;
 250                 ring->enqueue = ring->enq_seg->trbs;
 251                 next = ring->enqueue;
 252         }
 253         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 254 }
 255
 256 /*
 257  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 258  * above.
 259  * FIXME: this would be simpler and faster if we just kept track of the number
 260  * of free TRBs in a ring.
 261  */
 262 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 263                 unsigned int num_trbs)
 264 {
 265         int i;
 266         union xhci_trb *enq = ring->enqueue;
 267         struct xhci_segment *enq_seg = ring->enq_seg;
 268         struct xhci_segment *cur_seg;
 269         unsigned int left_on_ring;
 270
 271         /* If we are currently pointing to a link TRB, advance the
 272          * enqueue pointer before checking for space */
 273         while (last_trb(xhci, ring, enq_seg, enq)) {
 274                 enq_seg = enq_seg->next;
 275                 enq = enq_seg->trbs;
 276         }
 277
 278         /* Check if ring is empty */
 279         if (enq == ring->dequeue) {
 280                 /* Can't use link trbs */
 281                 left_on_ring = TRBS_PER_SEGMENT - 1;
 282                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 283                                 cur_seg = cur_seg->next)
 284                         left_on_ring += TRBS_PER_SEGMENT - 1;
 285
 286                 /* Always need one TRB free in the ring. */
 287                 left_on_ring -= 1;
 288                 if (num_trbs > left_on_ring) {
 289                         xhci_warn(xhci, "Not enough room on ring; "
 290                                         "need %u TRBs, %u TRBs left\n",
 291                                         num_trbs, left_on_ring);
 292                         return 0;
 293                 }
 294                 return 1;
 295         }
 296         /* Make sure there's an extra empty TRB available */
 297         for (i = 0; i <= num_trbs; ++i) {
 298                 if (enq == ring->dequeue)
 299                         return 0;
 300                 enq++;
 301                 while (last_trb(xhci, ring, enq_seg, enq)) {
 302                         enq_seg = enq_seg->next;
 303                         enq = enq_seg->trbs;
 304                 }
 305         }
 306         return 1;
 307 }
 308
 309 /* Ring the host controller doorbell after placing a command on the ring */
 310 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 311 {
 312         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 313                 return;
 314
 315         xhci_dbg(xhci, "// Ding dong!\n");
 316         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 317         /* Flush PCI posted writes */
 318         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 319 }
 320
 321 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 322 {
 323         u64 temp_64;
 324         int ret;
 325
 326         xhci_dbg(xhci, "Abort command ring\n");
 327
 328         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 329                 xhci_dbg(xhci, "The command ring isn't running, "
 330                                 "Have the command ring been stopped?\n");
 331                 return 0;
 332         }
 333
 334         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 335         if (!(temp_64 & CMD_RING_RUNNING)) {
 336                 xhci_dbg(xhci, "Command ring had been stopped\n");
 337                 return 0;
 338         }
 339         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 340         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 341                         &xhci->op_regs->cmd_ring);
 342
 343         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 344          * time the completion od all xHCI commands, including
 345          * the Command Abort operation. If software doesn't see
 346          * CRR negated in a timely manner (e.g. longer than 5
 347          * seconds), then it should assume that the there are
 348          * larger problems with the xHC and assert HCRST.
 349          */
 350         ret = handshake(xhci, &xhci->op_regs->cmd_ring,
 351                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 352         if (ret < 0) {
 353                 xhci_err(xhci, "Stopped the command ring failed, "
 354                                 "maybe the host is dead\n");
 355                 xhci->xhc_state |= XHCI_STATE_DYING;
 356                 xhci_quiesce(xhci);
 357                 xhci_halt(xhci);
 358                 return -ESHUTDOWN;
 359         }
 360
 361         return 0;
 362 }
 363
 364 static int xhci_queue_cd(struct xhci_hcd *xhci,
 365                 struct xhci_command *command,
 366                 union xhci_trb *cmd_trb)
 367 {
 368         struct xhci_cd *cd;
 369         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 370         if (!cd)
 371                 return -ENOMEM;
 372         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 373
 374         cd->command = command;
 375         cd->cmd_trb = cmd_trb;
 376         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 377
 378         return 0;
 379 }
 380
 381 /*
 382  * Cancel the command which has issue.
 383  *
 384  * Some commands may hang due to waiting for acknowledgement from
 385  * usb device. It is outside of the xHC's ability to control and
 386  * will cause the command ring is blocked. When it occurs software
 387  * should intervene to recover the command ring.
 388  * See Section 4.6.1.1 and 4.6.1.2
 389  */
 390 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 391                 union xhci_trb *cmd_trb)
 392 {
 393         int retval = 0;
 394         unsigned long flags;
 395
 396         spin_lock_irqsave(&xhci->lock, flags);
 397
 398         if (xhci->xhc_state & XHCI_STATE_DYING) {
 399                 xhci_warn(xhci, "Abort the command ring,"
 400                                 " but the xHCI is dead.\n");
 401                 retval = -ESHUTDOWN;
 402                 goto fail;
 403         }
 404
 405         /* queue the cmd desriptor to cancel_cmd_list */
 406         retval = xhci_queue_cd(xhci, command, cmd_trb);
 407         if (retval) {
 408                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 409                 goto fail;
 410         }
 411
 412         /* abort command ring */
 413         retval = xhci_abort_cmd_ring(xhci);
 414         if (retval) {
 415                 xhci_err(xhci, "Abort command ring failed\n");
 416                 if (unlikely(retval == -ESHUTDOWN)) {
 417                         spin_unlock_irqrestore(&xhci->lock, flags);
 418                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 419                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 420                         return retval;
 421                 }
 422         }
 423
 424 fail:
 425         spin_unlock_irqrestore(&xhci->lock, flags);
 426         return retval;
 427 }
 428
 429 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 430                 unsigned int slot_id,
 431                 unsigned int ep_index,
 432                 unsigned int stream_id)
 433 {
 434         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 435         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 436         unsigned int ep_state = ep->ep_state;
 437
 438         /* Don't ring the doorbell for this endpoint if there are pending
 439          * cancellations because we don't want to interrupt processing.
 440          * We don't want to restart any stream rings if there's a set dequeue
 441          * pointer command pending because the device can choose to start any
 442          * stream once the endpoint is on the HW schedule.
 443          * FIXME - check all the stream rings for pending cancellations.
 444          */
 445         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 446             (ep_state & EP_HALTED))
 447                 return;
 448         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 449         /* The CPU has better things to do at this point than wait for a
 450          * write-posting flush.  It'll get there soon enough.
 451          */
 452 }
 453
 454 /* Ring the doorbell for any rings with pending URBs */
 455 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 456                 unsigned int slot_id,
 457                 unsigned int ep_index)
 458 {
 459         unsigned int stream_id;
 460         struct xhci_virt_ep *ep;
 461
 462         ep = &xhci->devs[slot_id]->eps[ep_index];
 463
 464         /* A ring has pending URBs if its TD list is not empty */
 465         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 466                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 467                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 468                 return;
 469         }
 470
 471         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 472                         stream_id++) {
 473                 struct xhci_stream_info *stream_info = ep->stream_info;
 474                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 475                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 476                                                 stream_id);
 477         }
 478 }
 479
 480 /*
 481  * Find the segment that trb is in.  Start searching in start_seg.
 482  * If we must move past a segment that has a link TRB with a toggle cycle state
 483  * bit set, then we will toggle the value pointed at by cycle_state.
 484  */
 485 static struct xhci_segment *find_trb_seg(
 486                 struct xhci_segment *start_seg,
 487                 union xhci_trb  *trb, int *cycle_state)
 488 {
 489         struct xhci_segment *cur_seg = start_seg;
 490         struct xhci_generic_trb *generic_trb;
 491
 492         while (cur_seg->trbs > trb ||
 493                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 494                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 495                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 496                         *cycle_state ^= 0x1;
 497                 cur_seg = cur_seg->next;
 498                 if (cur_seg == start_seg)
 499                         /* Looped over the entire list.  Oops! */
 500                         return NULL;
 501         }
 502         return cur_seg;
 503 }
 504
 505
 506 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 507                 unsigned int slot_id, unsigned int ep_index,
 508                 unsigned int stream_id)
 509 {
 510         struct xhci_virt_ep *ep;
 511
 512         ep = &xhci->devs[slot_id]->eps[ep_index];
 513         /* Common case: no streams */
 514         if (!(ep->ep_state & EP_HAS_STREAMS))
 515                 return ep->ring;
 516
 517         if (stream_id == 0) {
 518                 xhci_warn(xhci,
 519                                 "WARN: Slot ID %u, ep index %u has streams, "
 520                                 "but URB has no stream ID.\n",
 521                                 slot_id, ep_index);
 522                 return NULL;
 523         }
 524
 525         if (stream_id < ep->stream_info->num_streams)
 526                 return ep->stream_info->stream_rings[stream_id];
 527
 528         xhci_warn(xhci,
 529                         "WARN: Slot ID %u, ep index %u has "
 530                         "stream IDs 1 to %u allocated, "
 531                         "but stream ID %u is requested.\n",
 532                         slot_id, ep_index,
 533                         ep->stream_info->num_streams - 1,
 534                         stream_id);
 535         return NULL;
 536 }
 537
 538 /* Get the right ring for the given URB.
 539  * If the endpoint supports streams, boundary check the URB's stream ID.
 540  * If the endpoint doesn't support streams, return the singular endpoint ring.
 541  */
 542 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 543                 struct urb *urb)
 544 {
 545         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 546                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 547 }
 548
 549 /*
 550  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 551  * Record the new state of the xHC's endpoint ring dequeue segment,
 552  * dequeue pointer, and new consumer cycle state in state.
 553  * Update our internal representation of the ring's dequeue pointer.
 554  *
 555  * We do this in three jumps:
 556  *  - First we update our new ring state to be the same as when the xHC stopped.
 557  *  - Then we traverse the ring to find the segment that contains
 558  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 559  *    any link TRBs with the toggle cycle bit set.
 560  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 561  *    if we've moved it past a link TRB with the toggle cycle bit set.
 562  *
 563  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 564  * with correct __le32 accesses they should work fine.  Only users of this are
 565  * in here.
 566  */
 567 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 568                 unsigned int slot_id, unsigned int ep_index,
 569                 unsigned int stream_id, struct xhci_td *cur_td,
 570                 struct xhci_dequeue_state *state)
 571 {
 572         struct xhci_virt_device *dev = xhci->devs[slot_id];
 573         struct xhci_ring *ep_ring;
 574         struct xhci_generic_trb *trb;
 575         struct xhci_ep_ctx *ep_ctx;
 576         dma_addr_t addr;
 577
 578         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 579                         ep_index, stream_id);
 580         if (!ep_ring) {
 581                 xhci_warn(xhci, "WARN can't find new dequeue state "
 582                                 "for invalid stream ID %u.\n",
 583                                 stream_id);
 584                 return;
 585         }
 586         state->new_cycle_state = 0;
 587         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 588         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 589                         dev->eps[ep_index].stopped_trb,
 590                         &state->new_cycle_state);
 591         if (!state->new_deq_seg) {
 592                 WARN_ON(1);
 593                 return;
 594         }
 595
 596         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 597         xhci_dbg(xhci, "Finding endpoint context\n");
 598         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 599         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 600
 601         state->new_deq_ptr = cur_td->last_trb;
 602         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 603         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 604                         state->new_deq_ptr,
 605                         &state->new_cycle_state);
 606         if (!state->new_deq_seg) {
 607                 WARN_ON(1);
 608                 return;
 609         }
 610
 611         trb = &state->new_deq_ptr->generic;
 612         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 613             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 614                 state->new_cycle_state ^= 0x1;
 615         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 616
 617         /*
 618          * If there is only one segment in a ring, find_trb_seg()'s while loop
 619          * will not run, and it will return before it has a chance to see if it
 620          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 621          * ended just before the link TRB on a one-segment ring, or if the TD
 622          * wrapped around the top of the ring, because it doesn't have the TD in
 623          * question.  Look for the one-segment case where stalled TRB's address
 624          * is greater than the new dequeue pointer address.
 625          */
 626         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 627                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 628                 state->new_cycle_state ^= 0x1;
 629         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 630
 631         /* Don't update the ring cycle state for the producer (us). */
 632         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 633                         state->new_deq_seg);
 634         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 635         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 636                         (unsigned long long) addr);
 637 }
 638
 639 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 640  * (The last TRB actually points to the ring enqueue pointer, which is not part
 641  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 642  */
 643 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 644                 struct xhci_td *cur_td, bool flip_cycle)
 645 {
 646         struct xhci_segment *cur_seg;
 647         union xhci_trb *cur_trb;
 648
 649         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 650                         true;
 651                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 652                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 653                         /* Unchain any chained Link TRBs, but
 654                          * leave the pointers intact.
 655                          */
 656                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 657                         /* Flip the cycle bit (link TRBs can't be the first
 658                          * or last TRB).
 659                          */
 660                         if (flip_cycle)
 661                                 cur_trb->generic.field[3] ^=
 662                                         cpu_to_le32(TRB_CYCLE);
 663                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 664                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 665                                         "in seg %p (0x%llx dma)\n",
 666                                         cur_trb,
 667                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 668                                         cur_seg,
 669                                         (unsigned long long)cur_seg->dma);
 670                 } else {
 671                         cur_trb->generic.field[0] = 0;
 672                         cur_trb->generic.field[1] = 0;
 673                         cur_trb->generic.field[2] = 0;
 674                         /* Preserve only the cycle bit of this TRB */
 675                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 676                         /* Flip the cycle bit except on the first or last TRB */
 677                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 678                                         cur_trb != cur_td->last_trb)
 679                                 cur_trb->generic.field[3] ^=
 680                                         cpu_to_le32(TRB_CYCLE);
 681                         cur_trb->generic.field[3] |= cpu_to_le32(
 682                                 TRB_TYPE(TRB_TR_NOOP));
 683                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 684                                         "in seg %p (0x%llx dma)\n",
 685                                         cur_trb,
 686                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 687                                         cur_seg,
 688                                         (unsigned long long)cur_seg->dma);
 689                 }
 690                 if (cur_trb == cur_td->last_trb)
 691                         break;
 692         }
 693 }
 694
 695 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 696                 unsigned int ep_index, unsigned int stream_id,
 697                 struct xhci_segment *deq_seg,
 698                 union xhci_trb *deq_ptr, u32 cycle_state);
 699
 700 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 701                 unsigned int slot_id, unsigned int ep_index,
 702                 unsigned int stream_id,
 703                 struct xhci_dequeue_state *deq_state)
 704 {
 705         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 706
 707         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 708                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 709                         deq_state->new_deq_seg,
 710                         (unsigned long long)deq_state->new_deq_seg->dma,
 711                         deq_state->new_deq_ptr,
 712                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 713                         deq_state->new_cycle_state);
 714         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 715                         deq_state->new_deq_seg,
 716                         deq_state->new_deq_ptr,
 717                         (u32) deq_state->new_cycle_state);
 718         /* Stop the TD queueing code from ringing the doorbell until
 719          * this command completes.  The HC won't set the dequeue pointer
 720          * if the ring is running, and ringing the doorbell starts the
 721          * ring running.
 722          */
 723         ep->ep_state |= SET_DEQ_PENDING;
 724 }
 725
 726 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 727                 struct xhci_virt_ep *ep)
 728 {
 729         ep->ep_state &= ~EP_HALT_PENDING;
 730         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 731          * timer is running on another CPU, we don't decrement stop_cmds_pending
 732          * (since we didn't successfully stop the watchdog timer).
 733          */
 734         if (del_timer(&ep->stop_cmd_timer))
 735                 ep->stop_cmds_pending--;
 736 }
 737
 738 /* Must be called with xhci->lock held in interrupt context */
 739 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 740                 struct xhci_td *cur_td, int status, char *adjective)
 741 {
 742         struct usb_hcd *hcd;
 743         struct urb      *urb;
 744         struct urb_priv *urb_priv;
 745
 746         urb = cur_td->urb;
 747         urb_priv = urb->hcpriv;
 748         urb_priv->td_cnt++;
 749         hcd = bus_to_hcd(urb->dev->bus);
 750
 751         /* Only giveback urb when this is the last td in urb */
 752         if (urb_priv->td_cnt == urb_priv->length) {
 753                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 754                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 755                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 756                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 757                                         usb_amd_quirk_pll_enable();
 758                         }
 759                 }
 760                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 761
 762                 spin_unlock(&xhci->lock);
 763                 usb_hcd_giveback_urb(hcd, urb, status);
 764                 xhci_urb_free_priv(xhci, urb_priv);
 765                 spin_lock(&xhci->lock);
 766         }
 767 }
 768
 769 /*
 770  * When we get a command completion for a Stop Endpoint Command, we need to
 771  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 772  *
 773  *  1. If the HW was in the middle of processing the TD that needs to be
 774  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 775  *     in the TD with a Set Dequeue Pointer Command.
 776  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 777  *     bit cleared) so that the HW will skip over them.
 778  */
 779 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 780                 union xhci_trb *trb, struct xhci_event_cmd *event)
 781 {
 782         unsigned int slot_id;
 783         unsigned int ep_index;
 784         struct xhci_virt_device *virt_dev;
 785         struct xhci_ring *ep_ring;
 786         struct xhci_virt_ep *ep;
 787         struct list_head *entry;
 788         struct xhci_td *cur_td = NULL;
 789         struct xhci_td *last_unlinked_td;
 790
 791         struct xhci_dequeue_state deq_state;
 792
 793         if (unlikely(TRB_TO_SUSPEND_PORT(
 794                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 795                 slot_id = TRB_TO_SLOT_ID(
 796                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 797                 virt_dev = xhci->devs[slot_id];
 798                 if (virt_dev)
 799                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 800                                 event);
 801                 else
 802                         xhci_warn(xhci, "Stop endpoint command "
 803                                 "completion for disabled slot %u\n",
 804                                 slot_id);
 805                 return;
 806         }
 807
 808         memset(&deq_state, 0, sizeof(deq_state));
 809         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 810         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 811         ep = &xhci->devs[slot_id]->eps[ep_index];
 812
 813         if (list_empty(&ep->cancelled_td_list)) {
 814                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 815                 ep->stopped_td = NULL;
 816                 ep->stopped_trb = NULL;
 817                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 818                 return;
 819         }
 820
 821         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 822          * We have the xHCI lock, so nothing can modify this list until we drop
 823          * it.  We're also in the event handler, so we can't get re-interrupted
 824          * if another Stop Endpoint command completes
 825          */
 826         list_for_each(entry, &ep->cancelled_td_list) {
 827                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 828                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 829                                 cur_td->first_trb,
 830                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 831                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 832                 if (!ep_ring) {
 833                         /* This shouldn't happen unless a driver is mucking
 834                          * with the stream ID after submission.  This will
 835                          * leave the TD on the hardware ring, and the hardware
 836                          * will try to execute it, and may access a buffer
 837                          * that has already been freed.  In the best case, the
 838                          * hardware will execute it, and the event handler will
 839                          * ignore the completion event for that TD, since it was
 840                          * removed from the td_list for that endpoint.  In
 841                          * short, don't muck with the stream ID after
 842                          * submission.
 843                          */
 844                         xhci_warn(xhci, "WARN Cancelled URB %p "
 845                                         "has invalid stream ID %u.\n",
 846                                         cur_td->urb,
 847                                         cur_td->urb->stream_id);
 848                         goto remove_finished_td;
 849                 }
 850                 /*
 851                  * If we stopped on the TD we need to cancel, then we have to
 852                  * move the xHC endpoint ring dequeue pointer past this TD.
 853                  */
 854                 if (cur_td == ep->stopped_td)
 855                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 856                                         cur_td->urb->stream_id,
 857                                         cur_td, &deq_state);
 858                 else
 859                         td_to_noop(xhci, ep_ring, cur_td, false);
 860 remove_finished_td:
 861                 /*
 862                  * The event handler won't see a completion for this TD anymore,
 863                  * so remove it from the endpoint ring's TD list.  Keep it in
 864                  * the cancelled TD list for URB completion later.
 865                  */
 866                 list_del_init(&cur_td->td_list);
 867         }
 868         last_unlinked_td = cur_td;
 869         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 870
 871         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 872         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 873                 xhci_queue_new_dequeue_state(xhci,
 874                                 slot_id, ep_index,
 875                                 ep->stopped_td->urb->stream_id,
 876                                 &deq_state);
 877                 xhci_ring_cmd_db(xhci);
 878         } else {
 879                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 880                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 881         }
 882
 883         /* Clear stopped_td and stopped_trb if endpoint is not halted */
 884         if (!(ep->ep_state & EP_HALTED)) {
 885                 ep->stopped_td = NULL;
 886                 ep->stopped_trb = NULL;
 887         }
 888
 889         /*
 890          * Drop the lock and complete the URBs in the cancelled TD list.
 891          * New TDs to be cancelled might be added to the end of the list before
 892          * we can complete all the URBs for the TDs we already unlinked.
 893          * So stop when we've completed the URB for the last TD we unlinked.
 894          */
 895         do {
 896                 cur_td = list_entry(ep->cancelled_td_list.next,
 897                                 struct xhci_td, cancelled_td_list);
 898                 list_del_init(&cur_td->cancelled_td_list);
 899
 900                 /* Clean up the cancelled URB */
 901                 /* Doesn't matter what we pass for status, since the core will
 902                  * just overwrite it (because the URB has been unlinked).
 903                  */
 904                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 905
 906                 /* Stop processing the cancelled list if the watchdog timer is
 907                  * running.
 908                  */
 909                 if (xhci->xhc_state & XHCI_STATE_DYING)
 910                         return;
 911         } while (cur_td != last_unlinked_td);
 912
 913         /* Return to the event handler with xhci->lock re-acquired */
 914 }
 915
 916 /* Watchdog timer function for when a stop endpoint command fails to complete.
 917  * In this case, we assume the host controller is broken or dying or dead.  The
 918  * host may still be completing some other events, so we have to be careful to
 919  * let the event ring handler and the URB dequeueing/enqueueing functions know
 920  * through xhci->state.
 921  *
 922  * The timer may also fire if the host takes a very long time to respond to the
 923  * command, and the stop endpoint command completion handler cannot delete the
 924  * timer before the timer function is called.  Another endpoint cancellation may
 925  * sneak in before the timer function can grab the lock, and that may queue
 926  * another stop endpoint command and add the timer back.  So we cannot use a
 927  * simple flag to say whether there is a pending stop endpoint command for a
 928  * particular endpoint.
 929  *
 930  * Instead we use a combination of that flag and a counter for the number of
 931  * pending stop endpoint commands.  If the timer is the tail end of the last
 932  * stop endpoint command, and the endpoint's command is still pending, we assume
 933  * the host is dying.
 934  */
 935 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 936 {
 937         struct xhci_hcd *xhci;
 938         struct xhci_virt_ep *ep;
 939         struct xhci_virt_ep *temp_ep;
 940         struct xhci_ring *ring;
 941         struct xhci_td *cur_td;
 942         int ret, i, j;
 943         unsigned long flags;
 944
 945         ep = (struct xhci_virt_ep *) arg;
 946         xhci = ep->xhci;
 947
 948         spin_lock_irqsave(&xhci->lock, flags);
 949
 950         ep->stop_cmds_pending--;
 951         if (xhci->xhc_state & XHCI_STATE_DYING) {
 952                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 953                                 "xHCI as DYING, exiting.\n");
 954                 spin_unlock_irqrestore(&xhci->lock, flags);
 955                 return;
 956         }
 957         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 958                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 959                                 "exiting.\n");
 960                 spin_unlock_irqrestore(&xhci->lock, flags);
 961                 return;
 962         }
 963
 964         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 965         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 966         /* Oops, HC is dead or dying or at least not responding to the stop
 967          * endpoint command.
 968          */
 969         xhci->xhc_state |= XHCI_STATE_DYING;
 970         /* Disable interrupts from the host controller and start halting it */
 971         xhci_quiesce(xhci);
 972         spin_unlock_irqrestore(&xhci->lock, flags);
 973
 974         ret = xhci_halt(xhci);
 975
 976         spin_lock_irqsave(&xhci->lock, flags);
 977         if (ret < 0) {
 978                 /* This is bad; the host is not responding to commands and it's
 979                  * not allowing itself to be halted.  At least interrupts are
 980                  * disabled. If we call usb_hc_died(), it will attempt to
 981                  * disconnect all device drivers under this host.  Those
 982                  * disconnect() methods will wait for all URBs to be unlinked,
 983                  * so we must complete them.
 984                  */
 985                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 986                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 987                 /* We could turn all TDs on the rings to no-ops.  This won't
 988                  * help if the host has cached part of the ring, and is slow if
 989                  * we want to preserve the cycle bit.  Skip it and hope the host
 990                  * doesn't touch the memory.
 991                  */
 992         }
 993         for (i = 0; i < MAX_HC_SLOTS; i++) {
 994                 if (!xhci->devs[i])
 995                         continue;
 996                 for (j = 0; j < 31; j++) {
 997                         temp_ep = &xhci->devs[i]->eps[j];
 998                         ring = temp_ep->ring;
 999                         if (!ring)
1000                                 continue;
1001                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
1002                                         "ep index %u\n", i, j);
1003                         while (!list_empty(&ring->td_list)) {
1004                                 cur_td = list_first_entry(&ring->td_list,
1005                                                 struct xhci_td,
1006                                                 td_list);
1007                                 list_del_init(&cur_td->td_list);
1008                                 if (!list_empty(&cur_td->cancelled_td_list))
1009                                         list_del_init(&cur_td->cancelled_td_list);
1010                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1011                                                 -ESHUTDOWN, "killed");
1012                         }
1013                         while (!list_empty(&temp_ep->cancelled_td_list)) {
1014                                 cur_td = list_first_entry(
1015                                                 &temp_ep->cancelled_td_list,
1016                                                 struct xhci_td,
1017                                                 cancelled_td_list);
1018                                 list_del_init(&cur_td->cancelled_td_list);
1019                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1020                                                 -ESHUTDOWN, "killed");
1021                         }
1022                 }
1023         }
1024         spin_unlock_irqrestore(&xhci->lock, flags);
1025         xhci_dbg(xhci, "Calling usb_hc_died()\n");
1026         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1027         xhci_dbg(xhci, "xHCI host controller is dead.\n");
1028 }
1029
1030 /*
1031  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1032  * we need to clear the set deq pending flag in the endpoint ring state, so that
1033  * the TD queueing code can ring the doorbell again.  We also need to ring the
1034  * endpoint doorbell to restart the ring, but only if there aren't more
1035  * cancellations pending.
1036  */
1037 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1038                 struct xhci_event_cmd *event,
1039                 union xhci_trb *trb)
1040 {
1041         unsigned int slot_id;
1042         unsigned int ep_index;
1043         unsigned int stream_id;
1044         struct xhci_ring *ep_ring;
1045         struct xhci_virt_device *dev;
1046         struct xhci_ep_ctx *ep_ctx;
1047         struct xhci_slot_ctx *slot_ctx;
1048
1049         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1050         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1051         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1052         dev = xhci->devs[slot_id];
1053
1054         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1055         if (!ep_ring) {
1056                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1057                                 "freed stream ID %u\n",
1058                                 stream_id);
1059                 /* XXX: Harmless??? */
1060                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1061                 return;
1062         }
1063
1064         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1065         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1066
1067         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1068                 unsigned int ep_state;
1069                 unsigned int slot_state;
1070
1071                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1072                 case COMP_TRB_ERR:
1073                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1074                                         "of stream ID configuration\n");
1075                         break;
1076                 case COMP_CTX_STATE:
1077                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1078                                         "to incorrect slot or ep state.\n");
1079                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1080                         ep_state &= EP_STATE_MASK;
1081                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1082                         slot_state = GET_SLOT_STATE(slot_state);
1083                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1084                                         slot_state, ep_state);
1085                         break;
1086                 case COMP_EBADSLT:
1087                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1088                                         "slot %u was not enabled.\n", slot_id);
1089                         break;
1090                 default:
1091                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1092                                         "completion code of %u.\n",
1093                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1094                         break;
1095                 }
1096                 /* OK what do we do now?  The endpoint state is hosed, and we
1097                  * should never get to this point if the synchronization between
1098                  * queueing, and endpoint state are correct.  This might happen
1099                  * if the device gets disconnected after we've finished
1100                  * cancelling URBs, which might not be an error...
1101                  */
1102         } else {
1103                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1104                          le64_to_cpu(ep_ctx->deq));
1105                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1106                                          dev->eps[ep_index].queued_deq_ptr) ==
1107                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1108                         /* Update the ring's dequeue segment and dequeue pointer
1109                          * to reflect the new position.
1110                          */
1111                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
1112                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
1113                 } else {
1114                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1115                                         "Ptr command & xHCI internal state.\n");
1116                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1117                                         dev->eps[ep_index].queued_deq_seg,
1118                                         dev->eps[ep_index].queued_deq_ptr);
1119                 }
1120         }
1121
1122         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1123         dev->eps[ep_index].queued_deq_seg = NULL;
1124         dev->eps[ep_index].queued_deq_ptr = NULL;
1125         /* Restart any rings with pending URBs */
1126         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1127 }
1128
1129 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1130                 struct xhci_event_cmd *event,
1131                 union xhci_trb *trb)
1132 {
1133         int slot_id;
1134         unsigned int ep_index;
1135
1136         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1137         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1138         /* This command will only fail if the endpoint wasn't halted,
1139          * but we don't care.
1140          */
1141         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1142                  GET_COMP_CODE(le32_to_cpu(event->status)));
1143
1144         /* HW with the reset endpoint quirk needs to have a configure endpoint
1145          * command complete before the endpoint can be used.  Queue that here
1146          * because the HW can't handle two commands being queued in a row.
1147          */
1148         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1149                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1150                 xhci_queue_configure_endpoint(xhci,
1151                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1152                                 false);
1153                 xhci_ring_cmd_db(xhci);
1154         } else {
1155                 /* Clear our internal halted state and restart the ring(s) */
1156                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1157                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1158         }
1159 }
1160
1161 /* Complete the command and detele it from the devcie's command queue.
1162  */
1163 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1164                 struct xhci_command *command, u32 status)
1165 {
1166         command->status = status;
1167         list_del(&command->cmd_list);
1168         if (command->completion)
1169                 complete(command->completion);
1170         else
1171                 xhci_free_command(xhci, command);
1172 }
1173
1174
1175 /* Check to see if a command in the device's command queue matches this one.
1176  * Signal the completion or free the command, and return 1.  Return 0 if the
1177  * completed command isn't at the head of the command list.
1178  */
1179 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1180                 struct xhci_virt_device *virt_dev,
1181                 struct xhci_event_cmd *event)
1182 {
1183         struct xhci_command *command;
1184
1185         if (list_empty(&virt_dev->cmd_list))
1186                 return 0;
1187
1188         command = list_entry(virt_dev->cmd_list.next,
1189                         struct xhci_command, cmd_list);
1190         if (xhci->cmd_ring->dequeue != command->command_trb)
1191                 return 0;
1192
1193         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1194                         GET_COMP_CODE(le32_to_cpu(event->status)));
1195         return 1;
1196 }
1197
1198 /*
1199  * Finding the command trb need to be cancelled and modifying it to
1200  * NO OP command. And if the command is in device's command wait
1201  * list, finishing and freeing it.
1202  *
1203  * If we can't find the command trb, we think it had already been
1204  * executed.
1205  */
1206 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1207 {
1208         struct xhci_segment *cur_seg;
1209         union xhci_trb *cmd_trb;
1210         u32 cycle_state;
1211
1212         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1213                 return;
1214
1215         /* find the current segment of command ring */
1216         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1217                         xhci->cmd_ring->dequeue, &cycle_state);
1218
1219         if (!cur_seg) {
1220                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1221                                 xhci->cmd_ring->dequeue,
1222                                 (unsigned long long)
1223                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1224                                         xhci->cmd_ring->dequeue));
1225                 xhci_debug_ring(xhci, xhci->cmd_ring);
1226                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1227                 return;
1228         }
1229
1230         /* find the command trb matched by cd from command ring */
1231         for (cmd_trb = xhci->cmd_ring->dequeue;
1232                         cmd_trb != xhci->cmd_ring->enqueue;
1233                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1234                 /* If the trb is link trb, continue */
1235                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1236                         continue;
1237
1238                 if (cur_cd->cmd_trb == cmd_trb) {
1239
1240                         /* If the command in device's command list, we should
1241                          * finish it and free the command structure.
1242                          */
1243                         if (cur_cd->command)
1244                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1245                                         cur_cd->command, COMP_CMD_STOP);
1246
1247                         /* get cycle state from the origin command trb */
1248                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1249                                 & TRB_CYCLE;
1250
1251                         /* modify the command trb to NO OP command */
1252                         cmd_trb->generic.field[0] = 0;
1253                         cmd_trb->generic.field[1] = 0;
1254                         cmd_trb->generic.field[2] = 0;
1255                         cmd_trb->generic.field[3] = cpu_to_le32(
1256                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1257                         break;
1258                 }
1259         }
1260 }
1261
1262 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1263 {
1264         struct xhci_cd *cur_cd, *next_cd;
1265
1266         if (list_empty(&xhci->cancel_cmd_list))
1267                 return;
1268
1269         list_for_each_entry_safe(cur_cd, next_cd,
1270                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1271                 xhci_cmd_to_noop(xhci, cur_cd);
1272                 list_del(&cur_cd->cancel_cmd_list);
1273                 kfree(cur_cd);
1274         }
1275 }
1276
1277 /*
1278  * traversing the cancel_cmd_list. If the command descriptor according
1279  * to cmd_trb is found, the function free it and return 1, otherwise
1280  * return 0.
1281  */
1282 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1283                 union xhci_trb *cmd_trb)
1284 {
1285         struct xhci_cd *cur_cd, *next_cd;
1286
1287         if (list_empty(&xhci->cancel_cmd_list))
1288                 return 0;
1289
1290         list_for_each_entry_safe(cur_cd, next_cd,
1291                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1292                 if (cur_cd->cmd_trb == cmd_trb) {
1293                         if (cur_cd->command)
1294                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1295                                         cur_cd->command, COMP_CMD_STOP);
1296                         list_del(&cur_cd->cancel_cmd_list);
1297                         kfree(cur_cd);
1298                         return 1;
1299                 }
1300         }
1301
1302         return 0;
1303 }
1304
1305 /*
1306  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1307  * trb pointed by the command ring dequeue pointer is the trb we want to
1308  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1309  * traverse the cancel_cmd_list to trun the all of the commands according
1310  * to command descriptor to NO-OP trb.
1311  */
1312 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1313                 int cmd_trb_comp_code)
1314 {
1315         int cur_trb_is_good = 0;
1316
1317         /* Searching the cmd trb pointed by the command ring dequeue
1318          * pointer in command descriptor list. If it is found, free it.
1319          */
1320         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1321                         xhci->cmd_ring->dequeue);
1322
1323         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1324                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1325         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1326                 /* traversing the cancel_cmd_list and canceling
1327                  * the command according to command descriptor
1328                  */
1329                 xhci_cancel_cmd_in_cd_list(xhci);
1330
1331                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1332                 /*
1333                  * ring command ring doorbell again to restart the
1334                  * command ring
1335                  */
1336                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1337                         xhci_ring_cmd_db(xhci);
1338         }
1339         return cur_trb_is_good;
1340 }
1341
1342 static void handle_cmd_completion(struct xhci_hcd *xhci,
1343                 struct xhci_event_cmd *event)
1344 {
1345         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1346         u64 cmd_dma;
1347         dma_addr_t cmd_dequeue_dma;
1348         struct xhci_input_control_ctx *ctrl_ctx;
1349         struct xhci_virt_device *virt_dev;
1350         unsigned int ep_index;
1351         struct xhci_ring *ep_ring;
1352         unsigned int ep_state;
1353
1354         cmd_dma = le64_to_cpu(event->cmd_trb);
1355         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1356                         xhci->cmd_ring->dequeue);
1357         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1358         if (cmd_dequeue_dma == 0) {
1359                 xhci->error_bitmask |= 1 << 4;
1360                 return;
1361         }
1362         /* Does the DMA address match our internal dequeue pointer address? */
1363         if (cmd_dma != (u64) cmd_dequeue_dma) {
1364                 xhci->error_bitmask |= 1 << 5;
1365                 return;
1366         }
1367
1368         if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1369                 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1370                 /* If the return value is 0, we think the trb pointed by
1371                  * command ring dequeue pointer is a good trb. The good
1372                  * trb means we don't want to cancel the trb, but it have
1373                  * been stopped by host. So we should handle it normally.
1374                  * Otherwise, driver should invoke inc_deq() and return.
1375                  */
1376                 if (handle_stopped_cmd_ring(xhci,
1377                                 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1378                         inc_deq(xhci, xhci->cmd_ring, false);
1379                         return;
1380                 }
1381         }
1382
1383         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1384                 & TRB_TYPE_BITMASK) {
1385         case TRB_TYPE(TRB_ENABLE_SLOT):
1386                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1387                         xhci->slot_id = slot_id;
1388                 else
1389                         xhci->slot_id = 0;
1390                 complete(&xhci->addr_dev);
1391                 break;
1392         case TRB_TYPE(TRB_DISABLE_SLOT):
1393                 if (xhci->devs[slot_id]) {
1394                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1395                                 /* Delete default control endpoint resources */
1396                                 xhci_free_device_endpoint_resources(xhci,
1397                                                 xhci->devs[slot_id], true);
1398                         xhci_free_virt_device(xhci, slot_id);
1399                 }
1400                 break;
1401         case TRB_TYPE(TRB_CONFIG_EP):
1402                 virt_dev = xhci->devs[slot_id];
1403                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1404                         break;
1405                 /*
1406                  * Configure endpoint commands can come from the USB core
1407                  * configuration or alt setting changes, or because the HW
1408                  * needed an extra configure endpoint command after a reset
1409                  * endpoint command or streams were being configured.
1410                  * If the command was for a halted endpoint, the xHCI driver
1411                  * is not waiting on the configure endpoint command.
1412                  */
1413                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1414                                 virt_dev->in_ctx);
1415                 /* Input ctx add_flags are the endpoint index plus one */
1416                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1417                 /* A usb_set_interface() call directly after clearing a halted
1418                  * condition may race on this quirky hardware.  Not worth
1419                  * worrying about, since this is prototype hardware.  Not sure
1420                  * if this will work for streams, but streams support was
1421                  * untested on this prototype.
1422                  */
1423                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1424                                 ep_index != (unsigned int) -1 &&
1425                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1426                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1427                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1428                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1429                         if (!(ep_state & EP_HALTED))
1430                                 goto bandwidth_change;
1431                         xhci_dbg(xhci, "Completed config ep cmd - "
1432                                         "last ep index = %d, state = %d\n",
1433                                         ep_index, ep_state);
1434                         /* Clear internal halted state and restart ring(s) */
1435                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1436                                 ~EP_HALTED;
1437                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1438                         break;
1439                 }
1440 bandwidth_change:
1441                 xhci_dbg(xhci, "Completed config ep cmd\n");
1442                 xhci->devs[slot_id]->cmd_status =
1443                         GET_COMP_CODE(le32_to_cpu(event->status));
1444                 complete(&xhci->devs[slot_id]->cmd_completion);
1445                 break;
1446         case TRB_TYPE(TRB_EVAL_CONTEXT):
1447                 virt_dev = xhci->devs[slot_id];
1448                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1449                         break;
1450                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1451                 complete(&xhci->devs[slot_id]->cmd_completion);
1452                 break;
1453         case TRB_TYPE(TRB_ADDR_DEV):
1454                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1455                 complete(&xhci->addr_dev);
1456                 break;
1457         case TRB_TYPE(TRB_STOP_RING):
1458                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1459                 break;
1460         case TRB_TYPE(TRB_SET_DEQ):
1461                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1462                 break;
1463         case TRB_TYPE(TRB_CMD_NOOP):
1464                 break;
1465         case TRB_TYPE(TRB_RESET_EP):
1466                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1467                 break;
1468         case TRB_TYPE(TRB_RESET_DEV):
1469                 xhci_dbg(xhci, "Completed reset device command.\n");
1470                 slot_id = TRB_TO_SLOT_ID(
1471                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1472                 virt_dev = xhci->devs[slot_id];
1473                 if (virt_dev)
1474                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1475                 else
1476                         xhci_warn(xhci, "Reset device command completion "
1477                                         "for disabled slot %u\n", slot_id);
1478                 break;
1479         case TRB_TYPE(TRB_NEC_GET_FW):
1480                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1481                         xhci->error_bitmask |= 1 << 6;
1482                         break;
1483                 }
1484                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1485                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1486                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1487                 break;
1488         default:
1489                 /* Skip over unknown commands on the event ring */
1490                 xhci->error_bitmask |= 1 << 6;
1491                 break;
1492         }
1493         inc_deq(xhci, xhci->cmd_ring, false);
1494 }
1495
1496 static void handle_vendor_event(struct xhci_hcd *xhci,
1497                 union xhci_trb *event)
1498 {
1499         u32 trb_type;
1500
1501         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1502         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1503         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1504                 handle_cmd_completion(xhci, &event->event_cmd);
1505 }
1506
1507 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1508  * port registers -- USB 3.0 and USB 2.0).
1509  *
1510  * Returns a zero-based port number, which is suitable for indexing into each of
1511  * the split roothubs' port arrays and bus state arrays.
1512  * Add one to it in order to call xhci_find_slot_id_by_port.
1513  */
1514 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1515                 struct xhci_hcd *xhci, u32 port_id)
1516 {
1517         unsigned int i;
1518         unsigned int num_similar_speed_ports = 0;
1519
1520         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1521          * and usb2_ports are 0-based indexes.  Count the number of similar
1522          * speed ports, up to 1 port before this port.
1523          */
1524         for (i = 0; i < (port_id - 1); i++) {
1525                 u8 port_speed = xhci->port_array[i];
1526
1527                 /*
1528                  * Skip ports that don't have known speeds, or have duplicate
1529                  * Extended Capabilities port speed entries.
1530                  */
1531                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1532                         continue;
1533
1534                 /*
1535                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1536                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1537                  * matches the device speed, it's a similar speed port.
1538                  */
1539                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1540                         num_similar_speed_ports++;
1541         }
1542         return num_similar_speed_ports;
1543 }
1544
1545 static void handle_port_status(struct xhci_hcd *xhci,
1546                 union xhci_trb *event)
1547 {
1548         struct usb_hcd *hcd;
1549         u32 port_id;
1550         u32 temp, temp1;
1551         int max_ports;
1552         int slot_id;
1553         unsigned int faked_port_index;
1554         u8 major_revision;
1555         struct xhci_bus_state *bus_state;
1556         __le32 __iomem **port_array;
1557         bool bogus_port_status = false;
1558
1559         /* Port status change events always have a successful completion code */
1560         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1561                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1562                 xhci->error_bitmask |= 1 << 8;
1563         }
1564         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1565         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1566
1567         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1568         if ((port_id <= 0) || (port_id > max_ports)) {
1569                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1570                 bogus_port_status = true;
1571                 goto cleanup;
1572         }
1573
1574         /* Figure out which usb_hcd this port is attached to:
1575          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1576          */
1577         major_revision = xhci->port_array[port_id - 1];
1578         if (major_revision == 0) {
1579                 xhci_warn(xhci, "Event for port %u not in "
1580                                 "Extended Capabilities, ignoring.\n",
1581                                 port_id);
1582                 bogus_port_status = true;
1583                 goto cleanup;
1584         }
1585         if (major_revision == DUPLICATE_ENTRY) {
1586                 xhci_warn(xhci, "Event for port %u duplicated in"
1587                                 "Extended Capabilities, ignoring.\n",
1588                                 port_id);
1589                 bogus_port_status = true;
1590                 goto cleanup;
1591         }
1592
1593         /*
1594          * Hardware port IDs reported by a Port Status Change Event include USB
1595          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1596          * resume event, but we first need to translate the hardware port ID
1597          * into the index into the ports on the correct split roothub, and the
1598          * correct bus_state structure.
1599          */
1600         /* Find the right roothub. */
1601         hcd = xhci_to_hcd(xhci);
1602         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1603                 hcd = xhci->shared_hcd;
1604         bus_state = &xhci->bus_state[hcd_index(hcd)];
1605         if (hcd->speed == HCD_USB3)
1606                 port_array = xhci->usb3_ports;
1607         else
1608                 port_array = xhci->usb2_ports;
1609         /* Find the faked port hub number */
1610         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1611                         port_id);
1612
1613         temp = xhci_readl(xhci, port_array[faked_port_index]);
1614         if (hcd->state == HC_STATE_SUSPENDED) {
1615                 xhci_dbg(xhci, "resume root hub\n");
1616                 usb_hcd_resume_root_hub(hcd);
1617         }
1618
1619         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1620                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1621
1622                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1623                 if (!(temp1 & CMD_RUN)) {
1624                         xhci_warn(xhci, "xHC is not running.\n");
1625                         goto cleanup;
1626                 }
1627
1628                 if (DEV_SUPERSPEED(temp)) {
1629                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1630                         xhci_set_link_state(xhci, port_array, faked_port_index,
1631                                                 XDEV_U0);
1632                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1633                                         faked_port_index + 1);
1634                         if (!slot_id) {
1635                                 xhci_dbg(xhci, "slot_id is zero\n");
1636                                 goto cleanup;
1637                         }
1638                         xhci_ring_device(xhci, slot_id);
1639                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1640                         /* Clear PORT_PLC */
1641                         xhci_test_and_clear_bit(xhci, port_array,
1642                                                 faked_port_index, PORT_PLC);
1643                 } else {
1644                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1645                         bus_state->resume_done[faked_port_index] = jiffies +
1646                                 msecs_to_jiffies(20);
1647                         mod_timer(&hcd->rh_timer,
1648                                   bus_state->resume_done[faked_port_index]);
1649                         /* Do the rest in GetPortStatus */
1650                 }
1651         }
1652
1653         if (hcd->speed != HCD_USB3)
1654                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1655                                         PORT_PLC);
1656
1657 cleanup:
1658         /* Update event ring dequeue pointer before dropping the lock */
1659         inc_deq(xhci, xhci->event_ring, true);
1660
1661         /* Don't make the USB core poll the roothub if we got a bad port status
1662          * change event.  Besides, at that point we can't tell which roothub
1663          * (USB 2.0 or USB 3.0) to kick.
1664          */
1665         if (bogus_port_status)
1666                 return;
1667
1668         /*
1669          * xHCI port-status-change events occur when the "or" of all the
1670          * status-change bits in the portsc register changes from 0 to 1.
1671          * New status changes won't cause an event if any other change
1672          * bits are still set.  When an event occurs, switch over to
1673          * polling to avoid losing status changes.
1674          */
1675         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1676         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1677         spin_unlock(&xhci->lock);
1678         /* Pass this up to the core */
1679         usb_hcd_poll_rh_status(hcd);
1680         spin_lock(&xhci->lock);
1681 }
1682
1683 /*
1684  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1685  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1686  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1687  * returns 0.
1688  */
1689 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1690                 union xhci_trb  *start_trb,
1691                 union xhci_trb  *end_trb,
1692                 dma_addr_t      suspect_dma)
1693 {
1694         dma_addr_t start_dma;
1695         dma_addr_t end_seg_dma;
1696         dma_addr_t end_trb_dma;
1697         struct xhci_segment *cur_seg;
1698
1699         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1700         cur_seg = start_seg;
1701
1702         do {
1703                 if (start_dma == 0)
1704                         return NULL;
1705                 /* We may get an event for a Link TRB in the middle of a TD */
1706                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1707                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1708                 /* If the end TRB isn't in this segment, this is set to 0 */
1709                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1710
1711                 if (end_trb_dma > 0) {
1712                         /* The end TRB is in this segment, so suspect should be here */
1713                         if (start_dma <= end_trb_dma) {
1714                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1715                                         return cur_seg;
1716                         } else {
1717                                 /* Case for one segment with
1718                                  * a TD wrapped around to the top
1719                                  */
1720                                 if ((suspect_dma >= start_dma &&
1721                                                         suspect_dma <= end_seg_dma) ||
1722                                                 (suspect_dma >= cur_seg->dma &&
1723                                                  suspect_dma <= end_trb_dma))
1724                                         return cur_seg;
1725                         }
1726                         return NULL;
1727                 } else {
1728                         /* Might still be somewhere in this segment */
1729                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1730                                 return cur_seg;
1731                 }
1732                 cur_seg = cur_seg->next;
1733                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1734         } while (cur_seg != start_seg);
1735
1736         return NULL;
1737 }
1738
1739 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1740                 unsigned int slot_id, unsigned int ep_index,
1741                 unsigned int stream_id,
1742                 struct xhci_td *td, union xhci_trb *event_trb)
1743 {
1744         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1745         ep->ep_state |= EP_HALTED;
1746         ep->stopped_td = td;
1747         ep->stopped_trb = event_trb;
1748         ep->stopped_stream = stream_id;
1749
1750         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1751         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1752
1753         ep->stopped_td = NULL;
1754         ep->stopped_trb = NULL;
1755         ep->stopped_stream = 0;
1756
1757         xhci_ring_cmd_db(xhci);
1758 }
1759
1760 /* Check if an error has halted the endpoint ring.  The class driver will
1761  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1762  * However, a babble and other errors also halt the endpoint ring, and the class
1763  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1764  * Ring Dequeue Pointer command manually.
1765  */
1766 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1767                 struct xhci_ep_ctx *ep_ctx,
1768                 unsigned int trb_comp_code)
1769 {
1770         /* TRB completion codes that may require a manual halt cleanup */
1771         if (trb_comp_code == COMP_TX_ERR ||
1772                         trb_comp_code == COMP_BABBLE ||
1773                         trb_comp_code == COMP_SPLIT_ERR)
1774                 /* The 0.96 spec says a babbling control endpoint
1775                  * is not halted. The 0.96 spec says it is.  Some HW
1776                  * claims to be 0.95 compliant, but it halts the control
1777                  * endpoint anyway.  Check if a babble halted the
1778                  * endpoint.
1779                  */
1780                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1781                     cpu_to_le32(EP_STATE_HALTED))
1782                         return 1;
1783
1784         return 0;
1785 }
1786
1787 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1788 {
1789         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1790                 /* Vendor defined "informational" completion code,
1791                  * treat as not-an-error.
1792                  */
1793                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1794                                 trb_comp_code);
1795                 xhci_dbg(xhci, "Treating code as success.\n");
1796                 return 1;
1797         }
1798         return 0;
1799 }
1800
1801 /*
1802  * Finish the td processing, remove the td from td list;
1803  * Return 1 if the urb can be given back.
1804  */
1805 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1806         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1807         struct xhci_virt_ep *ep, int *status, bool skip)
1808 {
1809         struct xhci_virt_device *xdev;
1810         struct xhci_ring *ep_ring;
1811         unsigned int slot_id;
1812         int ep_index;
1813         struct urb *urb = NULL;
1814         struct xhci_ep_ctx *ep_ctx;
1815         int ret = 0;
1816         struct urb_priv *urb_priv;
1817         u32 trb_comp_code;
1818
1819         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1820         xdev = xhci->devs[slot_id];
1821         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1822         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1823         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1824         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1825
1826         if (skip)
1827                 goto td_cleanup;
1828
1829         if (trb_comp_code == COMP_STOP_INVAL ||
1830                         trb_comp_code == COMP_STOP) {
1831                 /* The Endpoint Stop Command completion will take care of any
1832                  * stopped TDs.  A stopped TD may be restarted, so don't update
1833                  * the ring dequeue pointer or take this TD off any lists yet.
1834                  */
1835                 ep->stopped_td = td;
1836                 ep->stopped_trb = event_trb;
1837                 return 0;
1838         } else {
1839                 if (trb_comp_code == COMP_STALL) {
1840                         /* The transfer is completed from the driver's
1841                          * perspective, but we need to issue a set dequeue
1842                          * command for this stalled endpoint to move the dequeue
1843                          * pointer past the TD.  We can't do that here because
1844                          * the halt condition must be cleared first.  Let the
1845                          * USB class driver clear the stall later.
1846                          */
1847                         ep->stopped_td = td;
1848                         ep->stopped_trb = event_trb;
1849                         ep->stopped_stream = ep_ring->stream_id;
1850                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1851                                         ep_ctx, trb_comp_code)) {
1852                         /* Other types of errors halt the endpoint, but the
1853                          * class driver doesn't call usb_reset_endpoint() unless
1854                          * the error is -EPIPE.  Clear the halted status in the
1855                          * xHCI hardware manually.
1856                          */
1857                         xhci_cleanup_halted_endpoint(xhci,
1858                                         slot_id, ep_index, ep_ring->stream_id,
1859                                         td, event_trb);
1860                 } else {
1861                         /* Update ring dequeue pointer */
1862                         while (ep_ring->dequeue != td->last_trb)
1863                                 inc_deq(xhci, ep_ring, false);
1864                         inc_deq(xhci, ep_ring, false);
1865                 }
1866
1867 td_cleanup:
1868                 /* Clean up the endpoint's TD list */
1869                 urb = td->urb;
1870                 urb_priv = urb->hcpriv;
1871
1872                 /* Do one last check of the actual transfer length.
1873                  * If the host controller said we transferred more data than
1874                  * the buffer length, urb->actual_length will be a very big
1875                  * number (since it's unsigned).  Play it safe and say we didn't
1876                  * transfer anything.
1877                  */
1878                 if (urb->actual_length > urb->transfer_buffer_length) {
1879                         xhci_warn(xhci, "URB transfer length is wrong, "
1880                                         "xHC issue? req. len = %u, "
1881                                         "act. len = %u\n",
1882                                         urb->transfer_buffer_length,
1883                                         urb->actual_length);
1884                         urb->actual_length = 0;
1885                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1886                                 *status = -EREMOTEIO;
1887                         else
1888                                 *status = 0;
1889                 }
1890                 list_del_init(&td->td_list);
1891                 /* Was this TD slated to be cancelled but completed anyway? */
1892                 if (!list_empty(&td->cancelled_td_list))
1893                         list_del_init(&td->cancelled_td_list);
1894
1895                 urb_priv->td_cnt++;
1896                 /* Giveback the urb when all the tds are completed */
1897                 if (urb_priv->td_cnt == urb_priv->length) {
1898                         ret = 1;
1899                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1900                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1901                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1902                                         == 0) {
1903                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1904                                                 usb_amd_quirk_pll_enable();
1905                                 }
1906                         }
1907                 }
1908         }
1909
1910         return ret;
1911 }
1912
1913 /*
1914  * Process control tds, update urb status and actual_length.
1915  */
1916 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1917         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1918         struct xhci_virt_ep *ep, int *status)
1919 {
1920         struct xhci_virt_device *xdev;
1921         struct xhci_ring *ep_ring;
1922         unsigned int slot_id;
1923         int ep_index;
1924         struct xhci_ep_ctx *ep_ctx;
1925         u32 trb_comp_code;
1926
1927         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1928         xdev = xhci->devs[slot_id];
1929         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1930         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1931         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1932         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1933
1934         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1935         switch (trb_comp_code) {
1936         case COMP_SUCCESS:
1937                 if (event_trb == ep_ring->dequeue) {
1938                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1939                                         "without IOC set??\n");
1940                         *status = -ESHUTDOWN;
1941                 } else if (event_trb != td->last_trb) {
1942                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1943                                         "without IOC set??\n");
1944                         *status = -ESHUTDOWN;
1945                 } else {
1946                         *status = 0;
1947                 }
1948                 break;
1949         case COMP_SHORT_TX:
1950                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1951                         *status = -EREMOTEIO;
1952                 else
1953                         *status = 0;
1954                 break;
1955         case COMP_STOP_INVAL:
1956         case COMP_STOP:
1957                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1958         default:
1959                 if (!xhci_requires_manual_halt_cleanup(xhci,
1960                                         ep_ctx, trb_comp_code))
1961                         break;
1962                 xhci_dbg(xhci, "TRB error code %u, "
1963                                 "halted endpoint index = %u\n",
1964                                 trb_comp_code, ep_index);
1965                 /* else fall through */
1966         case COMP_STALL:
1967                 /* Did we transfer part of the data (middle) phase? */
1968                 if (event_trb != ep_ring->dequeue &&
1969                                 event_trb != td->last_trb)
1970                         td->urb->actual_length =
1971                                 td->urb->transfer_buffer_length -
1972                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1973                 else
1974                         td->urb->actual_length = 0;
1975
1976                 xhci_cleanup_halted_endpoint(xhci,
1977                         slot_id, ep_index, 0, td, event_trb);
1978                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1979         }
1980         /*
1981          * Did we transfer any data, despite the errors that might have
1982          * happened?  I.e. did we get past the setup stage?
1983          */
1984         if (event_trb != ep_ring->dequeue) {
1985                 /* The event was for the status stage */
1986                 if (event_trb == td->last_trb) {
1987                         if (td->urb->actual_length != 0) {
1988                                 /* Don't overwrite a previously set error code
1989                                  */
1990                                 if ((*status == -EINPROGRESS || *status == 0) &&
1991                                                 (td->urb->transfer_flags
1992                                                  & URB_SHORT_NOT_OK))
1993                                         /* Did we already see a short data
1994                                          * stage? */
1995                                         *status = -EREMOTEIO;
1996                         } else {
1997                                 td->urb->actual_length =
1998                                         td->urb->transfer_buffer_length;
1999                         }
2000                 } else {
2001                 /* Maybe the event was for the data stage? */
2002                         td->urb->actual_length =
2003                                 td->urb->transfer_buffer_length -
2004                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2005                         xhci_dbg(xhci, "Waiting for status "
2006                                         "stage event\n");
2007                         return 0;
2008                 }
2009         }
2010
2011         return finish_td(xhci, td, event_trb, event, ep, status, false);
2012 }
2013
2014 /*
2015  * Process isochronous tds, update urb packet status and actual_length.
2016  */
2017 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2018         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2019         struct xhci_virt_ep *ep, int *status)
2020 {
2021         struct xhci_ring *ep_ring;
2022         struct urb_priv *urb_priv;
2023         int idx;
2024         int len = 0;
2025         union xhci_trb *cur_trb;
2026         struct xhci_segment *cur_seg;
2027         struct usb_iso_packet_descriptor *frame;
2028         u32 trb_comp_code;
2029         bool skip_td = false;
2030
2031         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2032         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2033         urb_priv = td->urb->hcpriv;
2034         idx = urb_priv->td_cnt;
2035         frame = &td->urb->iso_frame_desc[idx];
2036
2037         /* handle completion code */
2038         switch (trb_comp_code) {
2039         case COMP_SUCCESS:
2040                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2041                         frame->status = 0;
2042                         break;
2043                 }
2044                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2045                         trb_comp_code = COMP_SHORT_TX;
2046         case COMP_SHORT_TX:
2047                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2048                                 -EREMOTEIO : 0;
2049                 break;
2050         case COMP_BW_OVER:
2051                 frame->status = -ECOMM;
2052                 skip_td = true;
2053                 break;
2054         case COMP_BUFF_OVER:
2055         case COMP_BABBLE:
2056                 frame->status = -EOVERFLOW;
2057                 skip_td = true;
2058                 break;
2059         case COMP_DEV_ERR:
2060         case COMP_STALL:
2061         case COMP_TX_ERR:
2062                 frame->status = -EPROTO;
2063                 skip_td = true;
2064                 break;
2065         case COMP_STOP:
2066         case COMP_STOP_INVAL:
2067                 break;
2068         default:
2069                 frame->status = -1;
2070                 break;
2071         }
2072
2073         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2074                 frame->actual_length = frame->length;
2075                 td->urb->actual_length += frame->length;
2076         } else {
2077                 for (cur_trb = ep_ring->dequeue,
2078                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2079                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2080                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2081                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2082                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2083                 }
2084                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2085                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2086
2087                 if (trb_comp_code != COMP_STOP_INVAL) {
2088                         frame->actual_length = len;
2089                         td->urb->actual_length += len;
2090                 }
2091         }
2092
2093         return finish_td(xhci, td, event_trb, event, ep, status, false);
2094 }
2095
2096 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2097                         struct xhci_transfer_event *event,
2098                         struct xhci_virt_ep *ep, int *status)
2099 {
2100         struct xhci_ring *ep_ring;
2101         struct urb_priv *urb_priv;
2102         struct usb_iso_packet_descriptor *frame;
2103         int idx;
2104
2105         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2106         urb_priv = td->urb->hcpriv;
2107         idx = urb_priv->td_cnt;
2108         frame = &td->urb->iso_frame_desc[idx];
2109
2110         /* The transfer is partly done. */
2111         frame->status = -EXDEV;
2112
2113         /* calc actual length */
2114         frame->actual_length = 0;
2115
2116         /* Update ring dequeue pointer */
2117         while (ep_ring->dequeue != td->last_trb)
2118                 inc_deq(xhci, ep_ring, false);
2119         inc_deq(xhci, ep_ring, false);
2120
2121         return finish_td(xhci, td, NULL, event, ep, status, true);
2122 }
2123
2124 /*
2125  * Process bulk and interrupt tds, update urb status and actual_length.
2126  */
2127 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2128         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2129         struct xhci_virt_ep *ep, int *status)
2130 {
2131         struct xhci_ring *ep_ring;
2132         union xhci_trb *cur_trb;
2133         struct xhci_segment *cur_seg;
2134         u32 trb_comp_code;
2135
2136         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2137         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2138
2139         switch (trb_comp_code) {
2140         case COMP_SUCCESS:
2141                 /* Double check that the HW transferred everything. */
2142                 if (event_trb != td->last_trb ||
2143                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2144                         xhci_warn(xhci, "WARN Successful completion "
2145                                         "on short TX\n");
2146                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2147                                 *status = -EREMOTEIO;
2148                         else
2149                                 *status = 0;
2150                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2151                                 trb_comp_code = COMP_SHORT_TX;
2152                 } else {
2153                         *status = 0;
2154                 }
2155                 break;
2156         case COMP_SHORT_TX:
2157                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2158                         *status = -EREMOTEIO;
2159                 else
2160                         *status = 0;
2161                 break;
2162         default:
2163                 /* Others already handled above */
2164                 break;
2165         }
2166         if (trb_comp_code == COMP_SHORT_TX)
2167                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2168                                 "%d bytes untransferred\n",
2169                                 td->urb->ep->desc.bEndpointAddress,
2170                                 td->urb->transfer_buffer_length,
2171                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2172         /* Fast path - was this the last TRB in the TD for this URB? */
2173         if (event_trb == td->last_trb) {
2174                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2175                         td->urb->actual_length =
2176                                 td->urb->transfer_buffer_length -
2177                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2178                         if (td->urb->transfer_buffer_length <
2179                                         td->urb->actual_length) {
2180                                 xhci_warn(xhci, "HC gave bad length "
2181                                                 "of %d bytes left\n",
2182                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2183                                 td->urb->actual_length = 0;
2184                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2185                                         *status = -EREMOTEIO;
2186                                 else
2187                                         *status = 0;
2188                         }
2189                         /* Don't overwrite a previously set error code */
2190                         if (*status == -EINPROGRESS) {
2191                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2192                                         *status = -EREMOTEIO;
2193                                 else
2194                                         *status = 0;
2195                         }
2196                 } else {
2197                         td->urb->actual_length =
2198                                 td->urb->transfer_buffer_length;
2199                         /* Ignore a short packet completion if the
2200                          * untransferred length was zero.
2201                          */
2202                         if (*status == -EREMOTEIO)
2203                                 *status = 0;
2204                 }
2205         } else {
2206                 /* Slow path - walk the list, starting from the dequeue
2207                  * pointer, to get the actual length transferred.
2208                  */
2209                 td->urb->actual_length = 0;
2210                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2211                                 cur_trb != event_trb;
2212                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2213                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2214                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2215                                 td->urb->actual_length +=
2216                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2217                 }
2218                 /* If the ring didn't stop on a Link or No-op TRB, add
2219                  * in the actual bytes transferred from the Normal TRB
2220                  */
2221                 if (trb_comp_code != COMP_STOP_INVAL)
2222                         td->urb->actual_length +=
2223                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2224                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2225         }
2226
2227         return finish_td(xhci, td, event_trb, event, ep, status, false);
2228 }
2229
2230 /*
2231  * If this function returns an error condition, it means it got a Transfer
2232  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2233  * At this point, the host controller is probably hosed and should be reset.
2234  */
2235 static int handle_tx_event(struct xhci_hcd *xhci,
2236                 struct xhci_transfer_event *event)
2237 {
2238         struct xhci_virt_device *xdev;
2239         struct xhci_virt_ep *ep;
2240         struct xhci_ring *ep_ring;
2241         unsigned int slot_id;
2242         int ep_index;
2243         struct xhci_td *td = NULL;
2244         dma_addr_t event_dma;
2245         struct xhci_segment *event_seg;
2246         union xhci_trb *event_trb;
2247         struct urb *urb = NULL;
2248         int status = -EINPROGRESS;
2249         struct urb_priv *urb_priv;
2250         struct xhci_ep_ctx *ep_ctx;
2251         struct list_head *tmp;
2252         u32 trb_comp_code;
2253         int ret = 0;
2254         int td_num = 0;
2255
2256         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2257         xdev = xhci->devs[slot_id];
2258         if (!xdev) {
2259                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2260                 return -ENODEV;
2261         }
2262
2263         /* Endpoint ID is 1 based, our index is zero based */
2264         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2265         ep = &xdev->eps[ep_index];
2266         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2267         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2268         if (!ep_ring ||
2269             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2270             EP_STATE_DISABLED) {
2271                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2272                                 "or incorrect stream ring\n");
2273                 return -ENODEV;
2274         }
2275
2276         /* Count current td numbers if ep->skip is set */
2277         if (ep->skip) {
2278                 list_for_each(tmp, &ep_ring->td_list)
2279                         td_num++;
2280         }
2281
2282         event_dma = le64_to_cpu(event->buffer);
2283         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2284         /* Look for common error cases */
2285         switch (trb_comp_code) {
2286         /* Skip codes that require special handling depending on
2287          * transfer type
2288          */
2289         case COMP_SUCCESS:
2290                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2291                         break;
2292                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2293                         trb_comp_code = COMP_SHORT_TX;
2294                 else
2295                         xhci_warn(xhci, "WARN Successful completion on short TX: "
2296                                         "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2297         case COMP_SHORT_TX:
2298                 break;
2299         case COMP_STOP:
2300                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2301                 break;
2302         case COMP_STOP_INVAL:
2303                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2304                 break;
2305         case COMP_STALL:
2306                 xhci_dbg(xhci, "Stalled endpoint\n");
2307                 ep->ep_state |= EP_HALTED;
2308                 status = -EPIPE;
2309                 break;
2310         case COMP_TRB_ERR:
2311                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2312                 status = -EILSEQ;
2313                 break;
2314         case COMP_SPLIT_ERR:
2315         case COMP_TX_ERR:
2316                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2317                 status = -EPROTO;
2318                 break;
2319         case COMP_BABBLE:
2320                 xhci_dbg(xhci, "Babble error on endpoint\n");
2321                 status = -EOVERFLOW;
2322                 break;
2323         case COMP_DB_ERR:
2324                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2325                 status = -ENOSR;
2326                 break;
2327         case COMP_BW_OVER:
2328                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2329                 break;
2330         case COMP_BUFF_OVER:
2331                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2332                 break;
2333         case COMP_UNDERRUN:
2334                 /*
2335                  * When the Isoch ring is empty, the xHC will generate
2336                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2337                  * Underrun Event for OUT Isoch endpoint.
2338                  */
2339                 xhci_dbg(xhci, "underrun event on endpoint\n");
2340                 if (!list_empty(&ep_ring->td_list))
2341                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2342                                         "still with TDs queued?\n",
2343                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2344                                  ep_index);
2345                 goto cleanup;
2346         case COMP_OVERRUN:
2347                 xhci_dbg(xhci, "overrun event on endpoint\n");
2348                 if (!list_empty(&ep_ring->td_list))
2349                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2350                                         "still with TDs queued?\n",
2351                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2352                                  ep_index);
2353                 goto cleanup;
2354         case COMP_DEV_ERR:
2355                 xhci_warn(xhci, "WARN: detect an incompatible device");
2356                 status = -EPROTO;
2357                 break;
2358         case COMP_MISSED_INT:
2359                 /*
2360                  * When encounter missed service error, one or more isoc tds
2361                  * may be missed by xHC.
2362                  * Set skip flag of the ep_ring; Complete the missed tds as
2363                  * short transfer when process the ep_ring next time.
2364                  */
2365                 ep->skip = true;
2366                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2367                 goto cleanup;
2368         default:
2369                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2370                         status = 0;
2371                         break;
2372                 }
2373                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2374                                 "busted\n");
2375                 goto cleanup;
2376         }
2377
2378         do {
2379                 /* This TRB should be in the TD at the head of this ring's
2380                  * TD list.
2381                  */
2382                 if (list_empty(&ep_ring->td_list)) {
2383                         /*
2384                          * A stopped endpoint may generate an extra completion
2385                          * event if the device was suspended.  Don't print
2386                          * warnings.
2387                          */
2388                         if (!(trb_comp_code == COMP_STOP ||
2389                                                 trb_comp_code == COMP_STOP_INVAL)) {
2390                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2391                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2392                                                 ep_index);
2393                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2394                                                 (le32_to_cpu(event->flags) &
2395                                                  TRB_TYPE_BITMASK)>>10);
2396                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2397                         }
2398                         if (ep->skip) {
2399                                 ep->skip = false;
2400                                 xhci_dbg(xhci, "td_list is empty while skip "
2401                                                 "flag set. Clear skip flag.\n");
2402                         }
2403                         ret = 0;
2404                         goto cleanup;
2405                 }
2406
2407                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2408                 if (ep->skip && td_num == 0) {
2409                         ep->skip = false;
2410                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2411                                                 "Clear skip flag.\n");
2412                         ret = 0;
2413                         goto cleanup;
2414                 }
2415
2416                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2417                 if (ep->skip)
2418                         td_num--;
2419
2420                 /* Is this a TRB in the currently executing TD? */
2421                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2422                                 td->last_trb, event_dma);
2423
2424                 /*
2425                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2426                  * is not in the current TD pointed by ep_ring->dequeue because
2427                  * that the hardware dequeue pointer still at the previous TRB
2428                  * of the current TD. The previous TRB maybe a Link TD or the
2429                  * last TRB of the previous TD. The command completion handle
2430                  * will take care the rest.
2431                  */
2432                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2433                         ret = 0;
2434                         goto cleanup;
2435                 }
2436
2437                 if (!event_seg) {
2438                         if (!ep->skip ||
2439                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2440                                 /* Some host controllers give a spurious
2441                                  * successful event after a short transfer.
2442                                  * Ignore it.
2443                                  */
2444                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2445                                                 ep_ring->last_td_was_short) {
2446                                         ep_ring->last_td_was_short = false;
2447                                         ret = 0;
2448                                         goto cleanup;
2449                                 }
2450                                 /* HC is busted, give up! */
2451                                 xhci_err(xhci,
2452                                         "ERROR Transfer event TRB DMA ptr not "
2453                                         "part of current TD\n");
2454                                 return -ESHUTDOWN;
2455                         }
2456
2457                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2458                         goto cleanup;
2459                 }
2460                 if (trb_comp_code == COMP_SHORT_TX)
2461                         ep_ring->last_td_was_short = true;
2462                 else
2463                         ep_ring->last_td_was_short = false;
2464
2465                 if (ep->skip) {
2466                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2467                         ep->skip = false;
2468                 }
2469
2470                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2471                                                 sizeof(*event_trb)];
2472                 /*
2473                  * No-op TRB should not trigger interrupts.
2474                  * If event_trb is a no-op TRB, it means the
2475                  * corresponding TD has been cancelled. Just ignore
2476                  * the TD.
2477                  */
2478                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2479                         xhci_dbg(xhci,
2480                                  "event_trb is a no-op TRB. Skip it\n");
2481                         goto cleanup;
2482                 }
2483
2484                 /* Now update the urb's actual_length and give back to
2485                  * the core
2486                  */
2487                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2488                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2489                                                  &status);
2490                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2491                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2492                                                  &status);
2493                 else
2494                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2495                                                  ep, &status);
2496
2497 cleanup:
2498                 /*
2499                  * Do not update event ring dequeue pointer if ep->skip is set.
2500                  * Will roll back to continue process missed tds.
2501                  */
2502                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2503                         inc_deq(xhci, xhci->event_ring, true);
2504                 }
2505
2506                 if (ret) {
2507                         urb = td->urb;
2508                         urb_priv = urb->hcpriv;
2509                         /* Leave the TD around for the reset endpoint function
2510                          * to use(but only if it's not a control endpoint,
2511                          * since we already queued the Set TR dequeue pointer
2512                          * command for stalled control endpoints).
2513                          */
2514                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2515                                 (trb_comp_code != COMP_STALL &&
2516                                         trb_comp_code != COMP_BABBLE))
2517                                 xhci_urb_free_priv(xhci, urb_priv);
2518                         else
2519                                 kfree(urb_priv);
2520
2521                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2522                         if ((urb->actual_length != urb->transfer_buffer_length &&
2523                                                 (urb->transfer_flags &
2524                                                  URB_SHORT_NOT_OK)) ||
2525                                         (status != 0 &&
2526                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2527                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2528                                                 "expected = %x, status = %d\n",
2529                                                 urb, urb->actual_length,
2530                                                 urb->transfer_buffer_length,
2531                                                 status);
2532                         spin_unlock(&xhci->lock);
2533                         /* EHCI, UHCI, and OHCI always unconditionally set the
2534                          * urb->status of an isochronous endpoint to 0.
2535                          */
2536                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2537                                 status = 0;
2538                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2539                         spin_lock(&xhci->lock);
2540                 }
2541
2542         /*
2543          * If ep->skip is set, it means there are missed tds on the
2544          * endpoint ring need to take care of.
2545          * Process them as short transfer until reach the td pointed by
2546          * the event.
2547          */
2548         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2549
2550         return 0;
2551 }
2552
2553 /*
2554  * This function handles all OS-owned events on the event ring.  It may drop
2555  * xhci->lock between event processing (e.g. to pass up port status changes).
2556  * Returns >0 for "possibly more events to process" (caller should call again),
2557  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2558  */
2559 static int xhci_handle_event(struct xhci_hcd *xhci)
2560 {
2561         union xhci_trb *event;
2562         int update_ptrs = 1;
2563         int ret;
2564
2565         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2566                 xhci->error_bitmask |= 1 << 1;
2567                 return 0;
2568         }
2569
2570         event = xhci->event_ring->dequeue;
2571         /* Does the HC or OS own the TRB? */
2572         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2573             xhci->event_ring->cycle_state) {
2574                 xhci->error_bitmask |= 1 << 2;
2575                 return 0;
2576         }
2577
2578         /*
2579          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2580          * speculative reads of the event's flags/data below.
2581          */
2582         rmb();
2583         /* FIXME: Handle more event types. */
2584         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2585         case TRB_TYPE(TRB_COMPLETION):
2586                 handle_cmd_completion(xhci, &event->event_cmd);
2587                 break;
2588         case TRB_TYPE(TRB_PORT_STATUS):
2589                 handle_port_status(xhci, event);
2590                 update_ptrs = 0;
2591                 break;
2592         case TRB_TYPE(TRB_TRANSFER):
2593                 ret = handle_tx_event(xhci, &event->trans_event);
2594                 if (ret < 0)
2595                         xhci->error_bitmask |= 1 << 9;
2596                 else
2597                         update_ptrs = 0;
2598                 break;
2599         default:
2600                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2601                     TRB_TYPE(48))
2602                         handle_vendor_event(xhci, event);
2603                 else
2604                         xhci->error_bitmask |= 1 << 3;
2605         }
2606         /* Any of the above functions may drop and re-acquire the lock, so check
2607          * to make sure a watchdog timer didn't mark the host as non-responsive.
2608          */
2609         if (xhci->xhc_state & XHCI_STATE_DYING) {
2610                 xhci_dbg(xhci, "xHCI host dying, returning from "
2611                                 "event handler.\n");
2612                 return 0;
2613         }
2614
2615         if (update_ptrs)
2616                 /* Update SW event ring dequeue pointer */
2617                 inc_deq(xhci, xhci->event_ring, true);
2618
2619         /* Are there more items on the event ring?  Caller will call us again to
2620          * check.
2621          */
2622         return 1;
2623 }
2624
2625 /*
2626  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2627  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2628  * indicators of an event TRB error, but we check the status *first* to be safe.
2629  */
2630 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2631 {
2632         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2633         u32 status;
2634         union xhci_trb *trb;
2635         u64 temp_64;
2636         union xhci_trb *event_ring_deq;
2637         dma_addr_t deq;
2638
2639         spin_lock(&xhci->lock);
2640         trb = xhci->event_ring->dequeue;
2641         /* Check if the xHC generated the interrupt, or the irq is shared */
2642         status = xhci_readl(xhci, &xhci->op_regs->status);
2643         if (status == 0xffffffff)
2644                 goto hw_died;
2645
2646         if (!(status & STS_EINT)) {
2647                 spin_unlock(&xhci->lock);
2648                 return IRQ_NONE;
2649         }
2650         if (status & STS_FATAL) {
2651                 xhci_warn(xhci, "WARNING: Host System Error\n");
2652                 xhci_halt(xhci);
2653 hw_died:
2654                 spin_unlock(&xhci->lock);
2655                 return -ESHUTDOWN;
2656         }
2657
2658         /*
2659          * Clear the op reg interrupt status first,
2660          * so we can receive interrupts from other MSI-X interrupters.
2661          * Write 1 to clear the interrupt status.
2662          */
2663         status |= STS_EINT;
2664         xhci_writel(xhci, status, &xhci->op_regs->status);
2665         /* FIXME when MSI-X is supported and there are multiple vectors */
2666         /* Clear the MSI-X event interrupt status */
2667
2668         if (hcd->irq != -1) {
2669                 u32 irq_pending;
2670                 /* Acknowledge the PCI interrupt */
2671                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2672                 irq_pending |= IMAN_IP;
2673                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2674         }
2675
2676         if (xhci->xhc_state & XHCI_STATE_DYING) {
2677                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2678                                 "Shouldn't IRQs be disabled?\n");
2679                 /* Clear the event handler busy flag (RW1C);
2680                  * the event ring should be empty.
2681                  */
2682                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2683                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2684                                 &xhci->ir_set->erst_dequeue);
2685                 spin_unlock(&xhci->lock);
2686
2687                 return IRQ_HANDLED;
2688         }
2689
2690         event_ring_deq = xhci->event_ring->dequeue;
2691         /* FIXME this should be a delayed service routine
2692          * that clears the EHB.
2693          */
2694         while (xhci_handle_event(xhci) > 0) {}
2695
2696         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2697         /* If necessary, update the HW's version of the event ring deq ptr. */
2698         if (event_ring_deq != xhci->event_ring->dequeue) {
2699                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2700                                 xhci->event_ring->dequeue);
2701                 if (deq == 0)
2702                         xhci_warn(xhci, "WARN something wrong with SW event "
2703                                         "ring dequeue ptr.\n");
2704                 /* Update HC event ring dequeue pointer */
2705                 temp_64 &= ERST_PTR_MASK;
2706                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2707         }
2708
2709         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2710         temp_64 |= ERST_EHB;
2711         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2712
2713         spin_unlock(&xhci->lock);
2714
2715         return IRQ_HANDLED;
2716 }
2717
2718 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2719 {
2720         irqreturn_t ret;
2721         struct xhci_hcd *xhci;
2722
2723         xhci = hcd_to_xhci(hcd);
2724         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2725         if (xhci->shared_hcd)
2726                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2727
2728         ret = xhci_irq(hcd);
2729
2730         return ret;
2731 }
2732
2733 /****           Endpoint Ring Operations        ****/
2734
2735 /*
2736  * Generic function for queueing a TRB on a ring.
2737  * The caller must have checked to make sure there's room on the ring.
2738  *
2739  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2740  *                      prepare_transfer()?
2741  */
2742 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2743                 bool consumer, bool more_trbs_coming, bool isoc,
2744                 u32 field1, u32 field2, u32 field3, u32 field4)
2745 {
2746         struct xhci_generic_trb *trb;
2747
2748         trb = &ring->enqueue->generic;
2749         trb->field[0] = cpu_to_le32(field1);
2750         trb->field[1] = cpu_to_le32(field2);
2751         trb->field[2] = cpu_to_le32(field3);
2752         trb->field[3] = cpu_to_le32(field4);
2753         inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2754 }
2755
2756 /*
2757  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2758  * FIXME allocate segments if the ring is full.
2759  */
2760 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2761                 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2762 {
2763         /* Make sure the endpoint has been added to xHC schedule */
2764         switch (ep_state) {
2765         case EP_STATE_DISABLED:
2766                 /*
2767                  * USB core changed config/interfaces without notifying us,
2768                  * or hardware is reporting the wrong state.
2769                  */
2770                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2771                 return -ENOENT;
2772         case EP_STATE_ERROR:
2773                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2774                 /* FIXME event handling code for error needs to clear it */
2775                 /* XXX not sure if this should be -ENOENT or not */
2776                 return -EINVAL;
2777         case EP_STATE_HALTED:
2778                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2779         case EP_STATE_STOPPED:
2780         case EP_STATE_RUNNING:
2781                 break;
2782         default:
2783                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2784                 /*
2785                  * FIXME issue Configure Endpoint command to try to get the HC
2786                  * back into a known state.
2787                  */
2788                 return -EINVAL;
2789         }
2790         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2791                 /* FIXME allocate more room */
2792                 xhci_err(xhci, "ERROR no room on ep ring\n");
2793                 return -ENOMEM;
2794         }
2795
2796         if (enqueue_is_link_trb(ep_ring)) {
2797                 struct xhci_ring *ring = ep_ring;
2798                 union xhci_trb *next;
2799
2800                 next = ring->enqueue;
2801
2802                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2803                         /* If we're not dealing with 0.95 hardware or isoc rings
2804                          * on AMD 0.96 host, clear the chain bit.
2805                          */
2806                         if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2807                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2808                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2809                         else
2810                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2811
2812                         wmb();
2813                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2814
2815                         /* Toggle the cycle bit after the last ring segment. */
2816                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2817                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2818                                 if (!in_interrupt()) {
2819                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2820                                                 "state for ring %p = %i\n",
2821                                                 ring, (unsigned int)ring->cycle_state);
2822                                 }
2823                         }
2824                         ring->enq_seg = ring->enq_seg->next;
2825                         ring->enqueue = ring->enq_seg->trbs;
2826                         next = ring->enqueue;
2827                 }
2828         }
2829
2830         return 0;
2831 }
2832
2833 static int prepare_transfer(struct xhci_hcd *xhci,
2834                 struct xhci_virt_device *xdev,
2835                 unsigned int ep_index,
2836                 unsigned int stream_id,
2837                 unsigned int num_trbs,
2838                 struct urb *urb,
2839                 unsigned int td_index,
2840                 bool isoc,
2841                 gfp_t mem_flags)
2842 {
2843         int ret;
2844         struct urb_priv *urb_priv;
2845         struct xhci_td  *td;
2846         struct xhci_ring *ep_ring;
2847         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2848
2849         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2850         if (!ep_ring) {
2851                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2852                                 stream_id);
2853                 return -EINVAL;
2854         }
2855
2856         ret = prepare_ring(xhci, ep_ring,
2857                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2858                            num_trbs, isoc, mem_flags);
2859         if (ret)
2860                 return ret;
2861
2862         urb_priv = urb->hcpriv;
2863         td = urb_priv->td[td_index];
2864
2865         INIT_LIST_HEAD(&td->td_list);
2866         INIT_LIST_HEAD(&td->cancelled_td_list);
2867
2868         if (td_index == 0) {
2869                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2870                 if (unlikely(ret))
2871                         return ret;
2872         }
2873
2874         td->urb = urb;
2875         /* Add this TD to the tail of the endpoint ring's TD list */
2876         list_add_tail(&td->td_list, &ep_ring->td_list);
2877         td->start_seg = ep_ring->enq_seg;
2878         td->first_trb = ep_ring->enqueue;
2879
2880         urb_priv->td[td_index] = td;
2881
2882         return 0;
2883 }
2884
2885 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2886 {
2887         int num_sgs, num_trbs, running_total, temp, i;
2888         struct scatterlist *sg;
2889
2890         sg = NULL;
2891         num_sgs = urb->num_mapped_sgs;
2892         temp = urb->transfer_buffer_length;
2893
2894         xhci_dbg(xhci, "count sg list trbs: \n");
2895         num_trbs = 0;
2896         for_each_sg(urb->sg, sg, num_sgs, i) {
2897                 unsigned int previous_total_trbs = num_trbs;
2898                 unsigned int len = sg_dma_len(sg);
2899
2900                 /* Scatter gather list entries may cross 64KB boundaries */
2901                 running_total = TRB_MAX_BUFF_SIZE -
2902                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2903                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2904                 if (running_total != 0)
2905                         num_trbs++;
2906
2907                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2908                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2909                         num_trbs++;
2910                         running_total += TRB_MAX_BUFF_SIZE;
2911                 }
2912                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2913                                 i, (unsigned long long)sg_dma_address(sg),
2914                                 len, len, num_trbs - previous_total_trbs);
2915
2916                 len = min_t(int, len, temp);
2917                 temp -= len;
2918                 if (temp == 0)
2919                         break;
2920         }
2921         xhci_dbg(xhci, "\n");
2922         if (!in_interrupt())
2923                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2924                                 "num_trbs = %d\n",
2925                                 urb->ep->desc.bEndpointAddress,
2926                                 urb->transfer_buffer_length,
2927                                 num_trbs);
2928         return num_trbs;
2929 }
2930
2931 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2932 {
2933         if (num_trbs != 0)
2934                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2935                                 "TRBs, %d left\n", __func__,
2936                                 urb->ep->desc.bEndpointAddress, num_trbs);
2937         if (running_total != urb->transfer_buffer_length)
2938                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2939                                 "queued %#x (%d), asked for %#x (%d)\n",
2940                                 __func__,
2941                                 urb->ep->desc.bEndpointAddress,
2942                                 running_total, running_total,
2943                                 urb->transfer_buffer_length,
2944                                 urb->transfer_buffer_length);
2945 }
2946
2947 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2948                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2949                 struct xhci_generic_trb *start_trb)
2950 {
2951         /*
2952          * Pass all the TRBs to the hardware at once and make sure this write
2953          * isn't reordered.
2954          */
2955         wmb();
2956         if (start_cycle)
2957                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2958         else
2959                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2960         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2961 }
2962
2963 /*
2964  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2965  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2966  * (comprised of sg list entries) can take several service intervals to
2967  * transmit.
2968  */
2969 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2970                 struct urb *urb, int slot_id, unsigned int ep_index)
2971 {
2972         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2973                         xhci->devs[slot_id]->out_ctx, ep_index);
2974         int xhci_interval;
2975         int ep_interval;
2976
2977         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2978         ep_interval = urb->interval;
2979         /* Convert to microframes */
2980         if (urb->dev->speed == USB_SPEED_LOW ||
2981                         urb->dev->speed == USB_SPEED_FULL)
2982                 ep_interval *= 8;
2983         /* FIXME change this to a warning and a suggestion to use the new API
2984          * to set the polling interval (once the API is added).
2985          */
2986         if (xhci_interval != ep_interval) {
2987                 if (printk_ratelimit())
2988                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2989                                         " (%d microframe%s) than xHCI "
2990                                         "(%d microframe%s)\n",
2991                                         ep_interval,
2992                                         ep_interval == 1 ? "" : "s",
2993                                         xhci_interval,
2994                                         xhci_interval == 1 ? "" : "s");
2995                 urb->interval = xhci_interval;
2996                 /* Convert back to frames for LS/FS devices */
2997                 if (urb->dev->speed == USB_SPEED_LOW ||
2998                                 urb->dev->speed == USB_SPEED_FULL)
2999                         urb->interval /= 8;
3000         }
3001         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3002 }
3003
3004 /*
3005  * The TD size is the number of bytes remaining in the TD (including this TRB),
3006  * right shifted by 10.
3007  * It must fit in bits 21:17, so it can't be bigger than 31.
3008  */
3009 static u32 xhci_td_remainder(unsigned int remainder)
3010 {
3011         u32 max = (1 << (21 - 17 + 1)) - 1;
3012
3013         if ((remainder >> 10) >= max)
3014                 return max << 17;
3015         else
3016                 return (remainder >> 10) << 17;
3017 }
3018
3019 /*
3020  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3021  * packets remaining in the TD (*not* including this TRB).
3022  *
3023  * Total TD packet count = total_packet_count =
3024  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3025  *
3026  * Packets transferred up to and including this TRB = packets_transferred =
3027  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3028  *
3029  * TD size = total_packet_count - packets_transferred
3030  *
3031  * It must fit in bits 21:17, so it can't be bigger than 31.
3032  * The last TRB in a TD must have the TD size set to zero.
3033  */
3034 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3035                 unsigned int total_packet_count, struct urb *urb,
3036                 unsigned int num_trbs_left)
3037 {
3038         int packets_transferred;
3039
3040         /* One TRB with a zero-length data packet. */
3041         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3042                 return 0;
3043
3044         /* All the TRB queueing functions don't count the current TRB in
3045          * running_total.
3046          */
3047         packets_transferred = (running_total + trb_buff_len) /
3048                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3049
3050         if ((total_packet_count - packets_transferred) > 31)
3051                 return 31 << 17;
3052         return (total_packet_count - packets_transferred) << 17;
3053 }
3054
3055 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3056                 struct urb *urb, int slot_id, unsigned int ep_index)
3057 {
3058         struct xhci_ring *ep_ring;
3059         unsigned int num_trbs;
3060         struct urb_priv *urb_priv;
3061         struct xhci_td *td;
3062         struct scatterlist *sg;
3063         int num_sgs;
3064         int trb_buff_len, this_sg_len, running_total;
3065         unsigned int total_packet_count;
3066         bool first_trb;
3067         u64 addr;
3068         bool more_trbs_coming;
3069
3070         struct xhci_generic_trb *start_trb;
3071         int start_cycle;
3072
3073         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3074         if (!ep_ring)
3075                 return -EINVAL;
3076
3077         num_trbs = count_sg_trbs_needed(xhci, urb);
3078         num_sgs = urb->num_mapped_sgs;
3079         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3080                         usb_endpoint_maxp(&urb->ep->desc));
3081
3082         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3083                         ep_index, urb->stream_id,
3084                         num_trbs, urb, 0, false, mem_flags);
3085         if (trb_buff_len < 0)
3086                 return trb_buff_len;
3087
3088         urb_priv = urb->hcpriv;
3089         td = urb_priv->td[0];
3090
3091         /*
3092          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3093          * until we've finished creating all the other TRBs.  The ring's cycle
3094          * state may change as we enqueue the other TRBs, so save it too.
3095          */
3096         start_trb = &ep_ring->enqueue->generic;
3097         start_cycle = ep_ring->cycle_state;
3098
3099         running_total = 0;
3100         /*
3101          * How much data is in the first TRB?
3102          *
3103          * There are three forces at work for TRB buffer pointers and lengths:
3104          * 1. We don't want to walk off the end of this sg-list entry buffer.
3105          * 2. The transfer length that the driver requested may be smaller than
3106          *    the amount of memory allocated for this scatter-gather list.
3107          * 3. TRBs buffers can't cross 64KB boundaries.
3108          */
3109         sg = urb->sg;
3110         addr = (u64) sg_dma_address(sg);
3111         this_sg_len = sg_dma_len(sg);
3112         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3113         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3114         if (trb_buff_len > urb->transfer_buffer_length)
3115                 trb_buff_len = urb->transfer_buffer_length;
3116         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
3117                         trb_buff_len);
3118
3119         first_trb = true;
3120         /* Queue the first TRB, even if it's zero-length */
3121         do {
3122                 u32 field = 0;
3123                 u32 length_field = 0;
3124                 u32 remainder = 0;
3125
3126                 /* Don't change the cycle bit of the first TRB until later */
3127                 if (first_trb) {
3128                         first_trb = false;
3129                         if (start_cycle == 0)
3130                                 field |= 0x1;
3131                 } else
3132                         field |= ep_ring->cycle_state;
3133
3134                 /* Chain all the TRBs together; clear the chain bit in the last
3135                  * TRB to indicate it's the last TRB in the chain.
3136                  */
3137                 if (num_trbs > 1) {
3138                         field |= TRB_CHAIN;
3139                 } else {
3140                         /* FIXME - add check for ZERO_PACKET flag before this */
3141                         td->last_trb = ep_ring->enqueue;
3142                         field |= TRB_IOC;
3143                 }
3144
3145                 /* Only set interrupt on short packet for IN endpoints */
3146                 if (usb_urb_dir_in(urb))
3147                         field |= TRB_ISP;
3148
3149                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
3150                                 "64KB boundary at %#x, end dma = %#x\n",
3151                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
3152                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3153                                 (unsigned int) addr + trb_buff_len);
3154                 if (TRB_MAX_BUFF_SIZE -
3155                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3156                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3157                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3158                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3159                                         (unsigned int) addr + trb_buff_len);
3160                 }
3161
3162                 /* Set the TRB length, TD size, and interrupter fields. */
3163                 if (xhci->hci_version < 0x100) {
3164                         remainder = xhci_td_remainder(
3165                                         urb->transfer_buffer_length -
3166                                         running_total);
3167                 } else {
3168                         remainder = xhci_v1_0_td_remainder(running_total,
3169                                         trb_buff_len, total_packet_count, urb,
3170                                         num_trbs - 1);
3171                 }
3172                 length_field = TRB_LEN(trb_buff_len) |
3173                         remainder |
3174                         TRB_INTR_TARGET(0);
3175
3176                 if (num_trbs > 1)
3177                         more_trbs_coming = true;
3178                 else
3179                         more_trbs_coming = false;
3180                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3181                                 lower_32_bits(addr),
3182                                 upper_32_bits(addr),
3183                                 length_field,
3184                                 field | TRB_TYPE(TRB_NORMAL));
3185                 --num_trbs;
3186                 running_total += trb_buff_len;
3187
3188                 /* Calculate length for next transfer --
3189                  * Are we done queueing all the TRBs for this sg entry?
3190                  */
3191                 this_sg_len -= trb_buff_len;
3192                 if (this_sg_len == 0) {
3193                         --num_sgs;
3194                         if (num_sgs == 0)
3195                                 break;
3196                         sg = sg_next(sg);
3197                         addr = (u64) sg_dma_address(sg);
3198                         this_sg_len = sg_dma_len(sg);
3199                 } else {
3200                         addr += trb_buff_len;
3201                 }
3202
3203                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3204                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3205                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3206                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3207                         trb_buff_len =
3208                                 urb->transfer_buffer_length - running_total;
3209         } while (running_total < urb->transfer_buffer_length);
3210
3211         check_trb_math(urb, num_trbs, running_total);
3212         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3213                         start_cycle, start_trb);
3214         return 0;
3215 }
3216
3217 /* This is very similar to what ehci-q.c qtd_fill() does */
3218 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3219                 struct urb *urb, int slot_id, unsigned int ep_index)
3220 {
3221         struct xhci_ring *ep_ring;
3222         struct urb_priv *urb_priv;
3223         struct xhci_td *td;
3224         int num_trbs;
3225         struct xhci_generic_trb *start_trb;
3226         bool first_trb;
3227         bool more_trbs_coming;
3228         int start_cycle;
3229         u32 field, length_field;
3230
3231         int running_total, trb_buff_len, ret;
3232         unsigned int total_packet_count;
3233         u64 addr;
3234
3235         if (urb->num_sgs)
3236                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3237
3238         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3239         if (!ep_ring)
3240                 return -EINVAL;
3241
3242         num_trbs = 0;
3243         /* How much data is (potentially) left before the 64KB boundary? */
3244         running_total = TRB_MAX_BUFF_SIZE -
3245                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3246         running_total &= TRB_MAX_BUFF_SIZE - 1;
3247
3248         /* If there's some data on this 64KB chunk, or we have to send a
3249          * zero-length transfer, we need at least one TRB
3250          */
3251         if (running_total != 0 || urb->transfer_buffer_length == 0)
3252                 num_trbs++;
3253         /* How many more 64KB chunks to transfer, how many more TRBs? */
3254         while (running_total < urb->transfer_buffer_length) {
3255                 num_trbs++;
3256                 running_total += TRB_MAX_BUFF_SIZE;
3257         }
3258         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3259
3260         if (!in_interrupt())
3261                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
3262                                 "addr = %#llx, num_trbs = %d\n",
3263                                 urb->ep->desc.bEndpointAddress,
3264                                 urb->transfer_buffer_length,
3265                                 urb->transfer_buffer_length,
3266                                 (unsigned long long)urb->transfer_dma,
3267                                 num_trbs);
3268
3269         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3270                         ep_index, urb->stream_id,
3271                         num_trbs, urb, 0, false, mem_flags);
3272         if (ret < 0)
3273                 return ret;
3274
3275         urb_priv = urb->hcpriv;
3276         td = urb_priv->td[0];
3277
3278         /*
3279          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3280          * until we've finished creating all the other TRBs.  The ring's cycle
3281          * state may change as we enqueue the other TRBs, so save it too.
3282          */
3283         start_trb = &ep_ring->enqueue->generic;
3284         start_cycle = ep_ring->cycle_state;
3285
3286         running_total = 0;
3287         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3288                         usb_endpoint_maxp(&urb->ep->desc));
3289         /* How much data is in the first TRB? */
3290         addr = (u64) urb->transfer_dma;
3291         trb_buff_len = TRB_MAX_BUFF_SIZE -
3292                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3293         if (trb_buff_len > urb->transfer_buffer_length)
3294                 trb_buff_len = urb->transfer_buffer_length;
3295
3296         first_trb = true;
3297
3298         /* Queue the first TRB, even if it's zero-length */
3299         do {
3300                 u32 remainder = 0;
3301                 field = 0;
3302
3303                 /* Don't change the cycle bit of the first TRB until later */
3304                 if (first_trb) {
3305                         first_trb = false;
3306                         if (start_cycle == 0)
3307                                 field |= 0x1;
3308                 } else
3309                         field |= ep_ring->cycle_state;
3310
3311                 /* Chain all the TRBs together; clear the chain bit in the last
3312                  * TRB to indicate it's the last TRB in the chain.
3313                  */
3314                 if (num_trbs > 1) {
3315                         field |= TRB_CHAIN;
3316                 } else {
3317                         /* FIXME - add check for ZERO_PACKET flag before this */
3318                         td->last_trb = ep_ring->enqueue;
3319                         field |= TRB_IOC;
3320                 }
3321
3322                 /* Only set interrupt on short packet for IN endpoints */
3323                 if (usb_urb_dir_in(urb))
3324                         field |= TRB_ISP;
3325
3326                 /* Set the TRB length, TD size, and interrupter fields. */
3327                 if (xhci->hci_version < 0x100) {
3328                         remainder = xhci_td_remainder(
3329                                         urb->transfer_buffer_length -
3330                                         running_total);
3331                 } else {
3332                         remainder = xhci_v1_0_td_remainder(running_total,
3333                                         trb_buff_len, total_packet_count, urb,
3334                                         num_trbs - 1);
3335                 }
3336                 length_field = TRB_LEN(trb_buff_len) |
3337                         remainder |
3338                         TRB_INTR_TARGET(0);
3339
3340                 if (num_trbs > 1)
3341                         more_trbs_coming = true;
3342                 else
3343                         more_trbs_coming = false;
3344                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3345                                 lower_32_bits(addr),
3346                                 upper_32_bits(addr),
3347                                 length_field,
3348                                 field | TRB_TYPE(TRB_NORMAL));
3349                 --num_trbs;
3350                 running_total += trb_buff_len;
3351
3352                 /* Calculate length for next transfer */
3353                 addr += trb_buff_len;
3354                 trb_buff_len = urb->transfer_buffer_length - running_total;
3355                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3356                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3357         } while (running_total < urb->transfer_buffer_length);
3358
3359         check_trb_math(urb, num_trbs, running_total);
3360         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3361                         start_cycle, start_trb);
3362         return 0;
3363 }
3364
3365 /* Caller must have locked xhci->lock */
3366 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3367                 struct urb *urb, int slot_id, unsigned int ep_index)
3368 {
3369         struct xhci_ring *ep_ring;
3370         int num_trbs;
3371         int ret;
3372         struct usb_ctrlrequest *setup;
3373         struct xhci_generic_trb *start_trb;
3374         int start_cycle;
3375         u32 field, length_field;
3376         struct urb_priv *urb_priv;
3377         struct xhci_td *td;
3378
3379         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3380         if (!ep_ring)
3381                 return -EINVAL;
3382
3383         /*
3384          * Need to copy setup packet into setup TRB, so we can't use the setup
3385          * DMA address.
3386          */
3387         if (!urb->setup_packet)
3388                 return -EINVAL;
3389
3390         if (!in_interrupt())
3391                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3392                                 slot_id, ep_index);
3393         /* 1 TRB for setup, 1 for status */
3394         num_trbs = 2;
3395         /*
3396          * Don't need to check if we need additional event data and normal TRBs,
3397          * since data in control transfers will never get bigger than 16MB
3398          * XXX: can we get a buffer that crosses 64KB boundaries?
3399          */
3400         if (urb->transfer_buffer_length > 0)
3401                 num_trbs++;
3402         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3403                         ep_index, urb->stream_id,
3404                         num_trbs, urb, 0, false, mem_flags);
3405         if (ret < 0)
3406                 return ret;
3407
3408         urb_priv = urb->hcpriv;
3409         td = urb_priv->td[0];
3410
3411         /*
3412          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3413          * until we've finished creating all the other TRBs.  The ring's cycle
3414          * state may change as we enqueue the other TRBs, so save it too.
3415          */
3416         start_trb = &ep_ring->enqueue->generic;
3417         start_cycle = ep_ring->cycle_state;
3418
3419         /* Queue setup TRB - see section 6.4.1.2.1 */
3420         /* FIXME better way to translate setup_packet into two u32 fields? */
3421         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3422         field = 0;
3423         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3424         if (start_cycle == 0)
3425                 field |= 0x1;
3426
3427         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3428         if (xhci->hci_version == 0x100) {
3429                 if (urb->transfer_buffer_length > 0) {
3430                         if (setup->bRequestType & USB_DIR_IN)
3431                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3432                         else
3433                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3434                 }
3435         }
3436
3437         queue_trb(xhci, ep_ring, false, true, false,
3438                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3439                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3440                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3441                   /* Immediate data in pointer */
3442                   field);
3443
3444         /* If there's data, queue data TRBs */
3445         /* Only set interrupt on short packet for IN endpoints */
3446         if (usb_urb_dir_in(urb))
3447                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3448         else
3449                 field = TRB_TYPE(TRB_DATA);
3450
3451         length_field = TRB_LEN(urb->transfer_buffer_length) |
3452                 xhci_td_remainder(urb->transfer_buffer_length) |
3453                 TRB_INTR_TARGET(0);
3454         if (urb->transfer_buffer_length > 0) {
3455                 if (setup->bRequestType & USB_DIR_IN)
3456                         field |= TRB_DIR_IN;
3457                 queue_trb(xhci, ep_ring, false, true, false,
3458                                 lower_32_bits(urb->transfer_dma),
3459                                 upper_32_bits(urb->transfer_dma),
3460                                 length_field,
3461                                 field | ep_ring->cycle_state);
3462         }
3463
3464         /* Save the DMA address of the last TRB in the TD */
3465         td->last_trb = ep_ring->enqueue;
3466
3467         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3468         /* If the device sent data, the status stage is an OUT transfer */
3469         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3470                 field = 0;
3471         else
3472                 field = TRB_DIR_IN;
3473         queue_trb(xhci, ep_ring, false, false, false,
3474                         0,
3475                         0,
3476                         TRB_INTR_TARGET(0),
3477                         /* Event on completion */
3478                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3479
3480         giveback_first_trb(xhci, slot_id, ep_index, 0,
3481                         start_cycle, start_trb);
3482         return 0;
3483 }
3484
3485 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3486                 struct urb *urb, int i)
3487 {
3488         int num_trbs = 0;
3489         u64 addr, td_len;
3490
3491         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3492         td_len = urb->iso_frame_desc[i].length;
3493
3494         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3495                         TRB_MAX_BUFF_SIZE);
3496         if (num_trbs == 0)
3497                 num_trbs++;
3498
3499         return num_trbs;
3500 }
3501
3502 /*
3503  * The transfer burst count field of the isochronous TRB defines the number of
3504  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3505  * devices can burst up to bMaxBurst number of packets per service interval.
3506  * This field is zero based, meaning a value of zero in the field means one
3507  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3508  * zero.  Only xHCI 1.0 host controllers support this field.
3509  */
3510 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3511                 struct usb_device *udev,
3512                 struct urb *urb, unsigned int total_packet_count)
3513 {
3514         unsigned int max_burst;
3515
3516         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3517                 return 0;
3518
3519         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3520         return roundup(total_packet_count, max_burst + 1) - 1;
3521 }
3522
3523 /*
3524  * Returns the number of packets in the last "burst" of packets.  This field is
3525  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3526  * the last burst packet count is equal to the total number of packets in the
3527  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3528  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3529  * contain 1 to (bMaxBurst + 1) packets.
3530  */
3531 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3532                 struct usb_device *udev,
3533                 struct urb *urb, unsigned int total_packet_count)
3534 {
3535         unsigned int max_burst;
3536         unsigned int residue;
3537
3538         if (xhci->hci_version < 0x100)
3539                 return 0;
3540
3541         switch (udev->speed) {
3542         case USB_SPEED_SUPER:
3543                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3544                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3545                 residue = total_packet_count % (max_burst + 1);
3546                 /* If residue is zero, the last burst contains (max_burst + 1)
3547                  * number of packets, but the TLBPC field is zero-based.
3548                  */
3549                 if (residue == 0)
3550                         return max_burst;
3551                 return residue - 1;
3552         default:
3553                 if (total_packet_count == 0)
3554                         return 0;
3555                 return total_packet_count - 1;
3556         }
3557 }
3558
3559 /* This is for isoc transfer */
3560 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3561                 struct urb *urb, int slot_id, unsigned int ep_index)
3562 {
3563         struct xhci_ring *ep_ring;
3564         struct urb_priv *urb_priv;
3565         struct xhci_td *td;
3566         int num_tds, trbs_per_td;
3567         struct xhci_generic_trb *start_trb;
3568         bool first_trb;
3569         int start_cycle;
3570         u32 field, length_field;
3571         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3572         u64 start_addr, addr;
3573         int i, j;
3574         bool more_trbs_coming;
3575
3576         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3577
3578         num_tds = urb->number_of_packets;
3579         if (num_tds < 1) {
3580                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3581                 return -EINVAL;
3582         }
3583
3584         if (!in_interrupt())
3585                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3586                                 " addr = %#llx, num_tds = %d\n",
3587                                 urb->ep->desc.bEndpointAddress,
3588                                 urb->transfer_buffer_length,
3589                                 urb->transfer_buffer_length,
3590                                 (unsigned long long)urb->transfer_dma,
3591                                 num_tds);
3592
3593         start_addr = (u64) urb->transfer_dma;
3594         start_trb = &ep_ring->enqueue->generic;
3595         start_cycle = ep_ring->cycle_state;
3596
3597         urb_priv = urb->hcpriv;
3598         /* Queue the first TRB, even if it's zero-length */
3599         for (i = 0; i < num_tds; i++) {
3600                 unsigned int total_packet_count;
3601                 unsigned int burst_count;
3602                 unsigned int residue;
3603
3604                 first_trb = true;
3605                 running_total = 0;
3606                 addr = start_addr + urb->iso_frame_desc[i].offset;
3607                 td_len = urb->iso_frame_desc[i].length;
3608                 td_remain_len = td_len;
3609                 total_packet_count = DIV_ROUND_UP(td_len,
3610                                 GET_MAX_PACKET(
3611                                         usb_endpoint_maxp(&urb->ep->desc)));
3612                 /* A zero-length transfer still involves at least one packet. */
3613                 if (total_packet_count == 0)
3614                         total_packet_count++;
3615                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3616                                 total_packet_count);
3617                 residue = xhci_get_last_burst_packet_count(xhci,
3618                                 urb->dev, urb, total_packet_count);
3619
3620                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3621
3622                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3623                                 urb->stream_id, trbs_per_td, urb, i, true,
3624                                 mem_flags);
3625                 if (ret < 0) {
3626                         if (i == 0)
3627                                 return ret;
3628                         goto cleanup;
3629                 }
3630
3631                 td = urb_priv->td[i];
3632                 for (j = 0; j < trbs_per_td; j++) {
3633                         u32 remainder = 0;
3634                         field = 0;
3635
3636                         if (first_trb) {
3637                                 field = TRB_TBC(burst_count) |
3638                                         TRB_TLBPC(residue);
3639                                 /* Queue the isoc TRB */
3640                                 field |= TRB_TYPE(TRB_ISOC);
3641                                 /* Assume URB_ISO_ASAP is set */
3642                                 field |= TRB_SIA;
3643                                 if (i == 0) {
3644                                         if (start_cycle == 0)
3645                                                 field |= 0x1;
3646                                 } else
3647                                         field |= ep_ring->cycle_state;
3648                                 first_trb = false;
3649                         } else {
3650                                 /* Queue other normal TRBs */
3651                                 field |= TRB_TYPE(TRB_NORMAL);
3652                                 field |= ep_ring->cycle_state;
3653                         }
3654
3655                         /* Only set interrupt on short packet for IN EPs */
3656                         if (usb_urb_dir_in(urb))
3657                                 field |= TRB_ISP;
3658
3659                         /* Chain all the TRBs together; clear the chain bit in
3660                          * the last TRB to indicate it's the last TRB in the
3661                          * chain.
3662                          */
3663                         if (j < trbs_per_td - 1) {
3664                                 field |= TRB_CHAIN;
3665                                 more_trbs_coming = true;
3666                         } else {
3667                                 td->last_trb = ep_ring->enqueue;
3668                                 field |= TRB_IOC;
3669                                 if (xhci->hci_version == 0x100 &&
3670                                                 !(xhci->quirks &
3671                                                         XHCI_AVOID_BEI)) {
3672                                         /* Set BEI bit except for the last td */
3673                                         if (i < num_tds - 1)
3674                                                 field |= TRB_BEI;
3675                                 }
3676                                 more_trbs_coming = false;
3677                         }
3678
3679                         /* Calculate TRB length */
3680                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3681                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3682                         if (trb_buff_len > td_remain_len)
3683                                 trb_buff_len = td_remain_len;
3684
3685                         /* Set the TRB length, TD size, & interrupter fields. */
3686                         if (xhci->hci_version < 0x100) {
3687                                 remainder = xhci_td_remainder(
3688                                                 td_len - running_total);
3689                         } else {
3690                                 remainder = xhci_v1_0_td_remainder(
3691                                                 running_total, trb_buff_len,
3692                                                 total_packet_count, urb,
3693                                                 (trbs_per_td - j - 1));
3694                         }
3695                         length_field = TRB_LEN(trb_buff_len) |
3696                                 remainder |
3697                                 TRB_INTR_TARGET(0);
3698
3699                         queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3700                                 lower_32_bits(addr),
3701                                 upper_32_bits(addr),
3702                                 length_field,
3703                                 field);
3704                         running_total += trb_buff_len;
3705
3706                         addr += trb_buff_len;
3707                         td_remain_len -= trb_buff_len;
3708                 }
3709
3710                 /* Check TD length */
3711                 if (running_total != td_len) {
3712                         xhci_err(xhci, "ISOC TD length unmatch\n");
3713                         ret = -EINVAL;
3714                         goto cleanup;
3715                 }
3716         }
3717
3718         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3719                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3720                         usb_amd_quirk_pll_disable();
3721         }
3722         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3723
3724         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3725                         start_cycle, start_trb);
3726         return 0;
3727 cleanup:
3728         /* Clean up a partially enqueued isoc transfer. */
3729
3730         for (i--; i >= 0; i--)
3731                 list_del_init(&urb_priv->td[i]->td_list);
3732
3733         /* Use the first TD as a temporary variable to turn the TDs we've queued
3734          * into No-ops with a software-owned cycle bit. That way the hardware
3735          * won't accidentally start executing bogus TDs when we partially
3736          * overwrite them.  td->first_trb and td->start_seg are already set.
3737          */
3738         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3739         /* Every TRB except the first & last will have its cycle bit flipped. */
3740         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3741
3742         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3743         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3744         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3745         ep_ring->cycle_state = start_cycle;
3746         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3747         return ret;
3748 }
3749
3750 /*
3751  * Check transfer ring to guarantee there is enough room for the urb.
3752  * Update ISO URB start_frame and interval.
3753  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3754  * update the urb->start_frame by now.
3755  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3756  */
3757 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3758                 struct urb *urb, int slot_id, unsigned int ep_index)
3759 {
3760         struct xhci_virt_device *xdev;
3761         struct xhci_ring *ep_ring;
3762         struct xhci_ep_ctx *ep_ctx;
3763         int start_frame;
3764         int xhci_interval;
3765         int ep_interval;
3766         int num_tds, num_trbs, i;
3767         int ret;
3768
3769         xdev = xhci->devs[slot_id];
3770         ep_ring = xdev->eps[ep_index].ring;
3771         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3772
3773         num_trbs = 0;
3774         num_tds = urb->number_of_packets;
3775         for (i = 0; i < num_tds; i++)
3776                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3777
3778         /* Check the ring to guarantee there is enough room for the whole urb.
3779          * Do not insert any td of the urb to the ring if the check failed.
3780          */
3781         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3782                            num_trbs, true, mem_flags);
3783         if (ret)
3784                 return ret;
3785
3786         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3787         start_frame &= 0x3fff;
3788
3789         urb->start_frame = start_frame;
3790         if (urb->dev->speed == USB_SPEED_LOW ||
3791                         urb->dev->speed == USB_SPEED_FULL)
3792                 urb->start_frame >>= 3;
3793
3794         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3795         ep_interval = urb->interval;
3796         /* Convert to microframes */
3797         if (urb->dev->speed == USB_SPEED_LOW ||
3798                         urb->dev->speed == USB_SPEED_FULL)
3799                 ep_interval *= 8;
3800         /* FIXME change this to a warning and a suggestion to use the new API
3801          * to set the polling interval (once the API is added).
3802          */
3803         if (xhci_interval != ep_interval) {
3804                 if (printk_ratelimit())
3805                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3806                                         " (%d microframe%s) than xHCI "
3807                                         "(%d microframe%s)\n",
3808                                         ep_interval,
3809                                         ep_interval == 1 ? "" : "s",
3810                                         xhci_interval,
3811                                         xhci_interval == 1 ? "" : "s");
3812                 urb->interval = xhci_interval;
3813                 /* Convert back to frames for LS/FS devices */
3814                 if (urb->dev->speed == USB_SPEED_LOW ||
3815                                 urb->dev->speed == USB_SPEED_FULL)
3816                         urb->interval /= 8;
3817         }
3818         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3819 }
3820
3821 /****           Command Ring Operations         ****/
3822
3823 /* Generic function for queueing a command TRB on the command ring.
3824  * Check to make sure there's room on the command ring for one command TRB.
3825  * Also check that there's room reserved for commands that must not fail.
3826  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3827  * then only check for the number of reserved spots.
3828  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3829  * because the command event handler may want to resubmit a failed command.
3830  */
3831 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3832                 u32 field3, u32 field4, bool command_must_succeed)
3833 {
3834         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3835         int ret;
3836
3837         if (!command_must_succeed)
3838                 reserved_trbs++;
3839
3840         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3841                         reserved_trbs, false, GFP_ATOMIC);
3842         if (ret < 0) {
3843                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3844                 if (command_must_succeed)
3845                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3846                                         "unfailable commands failed.\n");
3847                 return ret;
3848         }
3849         queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3850                         field3, field4 | xhci->cmd_ring->cycle_state);
3851         return 0;
3852 }
3853
3854 /* Queue a slot enable or disable request on the command ring */
3855 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3856 {
3857         return queue_command(xhci, 0, 0, 0,
3858                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3859 }
3860
3861 /* Queue an address device command TRB */
3862 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3863                 u32 slot_id)
3864 {
3865         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3866                         upper_32_bits(in_ctx_ptr), 0,
3867                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3868                         false);
3869 }
3870
3871 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3872                 u32 field1, u32 field2, u32 field3, u32 field4)
3873 {
3874         return queue_command(xhci, field1, field2, field3, field4, false);
3875 }
3876
3877 /* Queue a reset device command TRB */
3878 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3879 {
3880         return queue_command(xhci, 0, 0, 0,
3881                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3882                         false);
3883 }
3884
3885 /* Queue a configure endpoint command TRB */
3886 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3887                 u32 slot_id, bool command_must_succeed)
3888 {
3889         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3890                         upper_32_bits(in_ctx_ptr), 0,
3891                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3892                         command_must_succeed);
3893 }
3894
3895 /* Queue an evaluate context command TRB */
3896 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3897                 u32 slot_id)
3898 {
3899         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3900                         upper_32_bits(in_ctx_ptr), 0,
3901                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3902                         false);
3903 }
3904
3905 /*
3906  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3907  * activity on an endpoint that is about to be suspended.
3908  */
3909 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3910                 unsigned int ep_index, int suspend)
3911 {
3912         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3913         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3914         u32 type = TRB_TYPE(TRB_STOP_RING);
3915         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3916
3917         return queue_command(xhci, 0, 0, 0,
3918                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3919 }
3920
3921 /* Set Transfer Ring Dequeue Pointer command.
3922  * This should not be used for endpoints that have streams enabled.
3923  */
3924 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3925                 unsigned int ep_index, unsigned int stream_id,
3926                 struct xhci_segment *deq_seg,
3927                 union xhci_trb *deq_ptr, u32 cycle_state)
3928 {
3929         dma_addr_t addr;
3930         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3931         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3932         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3933         u32 type = TRB_TYPE(TRB_SET_DEQ);
3934         struct xhci_virt_ep *ep;
3935
3936         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3937         if (addr == 0) {
3938                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3939                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3940                                 deq_seg, deq_ptr);
3941                 return 0;
3942         }
3943         ep = &xhci->devs[slot_id]->eps[ep_index];
3944         if ((ep->ep_state & SET_DEQ_PENDING)) {
3945                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3946                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3947                 return 0;
3948         }
3949         ep->queued_deq_seg = deq_seg;
3950         ep->queued_deq_ptr = deq_ptr;
3951         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3952                         upper_32_bits(addr), trb_stream_id,
3953                         trb_slot_id | trb_ep_index | type, false);
3954 }
3955
3956 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3957                 unsigned int ep_index)
3958 {
3959         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3960         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3961         u32 type = TRB_TYPE(TRB_RESET_EP);
3962
3963         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3964                         false);
3965 }