drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include "xhci.h"
  69
  70 /*
  71  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  72  * address of the TRB.
  73  */
  74 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  75                 union xhci_trb *trb)
  76 {
  77         unsigned long segment_offset;
  78
  79         if (!seg || !trb || trb < seg->trbs)
  80                 return 0;
  81         /* offset in TRBs */
  82         segment_offset = trb - seg->trbs;
  83         if (segment_offset > TRBS_PER_SEGMENT)
  84                 return 0;
  85         return seg->dma + (segment_offset * sizeof(*trb));
  86 }
  87
  88 /* Does this link TRB point to the first segment in a ring,
  89  * or was the previous TRB the last TRB on the last segment in the ERST?
  90  */
  91 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  92                 struct xhci_segment *seg, union xhci_trb *trb)
  93 {
  94         if (ring == xhci->event_ring)
  95                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
  96                         (seg->next == xhci->event_ring->first_seg);
  97         else
  98                 return trb->link.control & LINK_TOGGLE;
  99 }
 100
 101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 102  * segment?  I.e. would the updated event TRB pointer step off the end of the
 103  * event seg?
 104  */
 105 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 106                 struct xhci_segment *seg, union xhci_trb *trb)
 107 {
 108         if (ring == xhci->event_ring)
 109                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 110         else
 111                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 112 }
 113
 114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 115  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 116  * effect the ring dequeue or enqueue pointers.
 117  */
 118 static void next_trb(struct xhci_hcd *xhci,
 119                 struct xhci_ring *ring,
 120                 struct xhci_segment **seg,
 121                 union xhci_trb **trb)
 122 {
 123         if (last_trb(xhci, ring, *seg, *trb)) {
 124                 *seg = (*seg)->next;
 125                 *trb = ((*seg)->trbs);
 126         } else {
 127                 *trb = (*trb)++;
 128         }
 129 }
 130
 131 /*
 132  * See Cycle bit rules. SW is the consumer for the event ring only.
 133  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 134  */
 135 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 136 {
 137         union xhci_trb *next = ++(ring->dequeue);
 138         unsigned long long addr;
 139
 140         ring->deq_updates++;
 141         /* Update the dequeue pointer further if that was a link TRB or we're at
 142          * the end of an event ring segment (which doesn't have link TRBS)
 143          */
 144         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 145                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 146                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 147                         if (!in_interrupt())
 148                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 149                                                 ring,
 150                                                 (unsigned int) ring->cycle_state);
 151                 }
 152                 ring->deq_seg = ring->deq_seg->next;
 153                 ring->dequeue = ring->deq_seg->trbs;
 154                 next = ring->dequeue;
 155         }
 156         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 157         if (ring == xhci->event_ring)
 158                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 159         else if (ring == xhci->cmd_ring)
 160                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 161         else
 162                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 163 }
 164
 165 /*
 166  * See Cycle bit rules. SW is the consumer for the event ring only.
 167  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 168  *
 169  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 170  * chain bit is set), then set the chain bit in all the following link TRBs.
 171  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 172  * have their chain bit cleared (so that each Link TRB is a separate TD).
 173  *
 174  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 175  * set, but other sections talk about dealing with the chain bit set.
 176  * Assume section 6.4.4.1 is wrong, and the chain bit can be set in a Link TRB.
 177  */
 178 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 179 {
 180         u32 chain;
 181         union xhci_trb *next;
 182         unsigned long long addr;
 183
 184         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 185         next = ++(ring->enqueue);
 186
 187         ring->enq_updates++;
 188         /* Update the dequeue pointer further if that was a link TRB or we're at
 189          * the end of an event ring segment (which doesn't have link TRBS)
 190          */
 191         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 192                 if (!consumer) {
 193                         if (ring != xhci->event_ring) {
 194                                 next->link.control &= ~TRB_CHAIN;
 195                                 next->link.control |= chain;
 196                                 /* Give this link TRB to the hardware */
 197                                 wmb();
 198                                 if (next->link.control & TRB_CYCLE)
 199                                         next->link.control &= (u32) ~TRB_CYCLE;
 200                                 else
 201                                         next->link.control |= (u32) TRB_CYCLE;
 202                         }
 203                         /* Toggle the cycle bit after the last ring segment. */
 204                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 205                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 206                                 if (!in_interrupt())
 207                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 208                                                         ring,
 209                                                         (unsigned int) ring->cycle_state);
 210                         }
 211                 }
 212                 ring->enq_seg = ring->enq_seg->next;
 213                 ring->enqueue = ring->enq_seg->trbs;
 214                 next = ring->enqueue;
 215         }
 216         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 217         if (ring == xhci->event_ring)
 218                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 219         else if (ring == xhci->cmd_ring)
 220                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 221         else
 222                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 223 }
 224
 225 /*
 226  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 227  * above.
 228  * FIXME: this would be simpler and faster if we just kept track of the number
 229  * of free TRBs in a ring.
 230  */
 231 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 232                 unsigned int num_trbs)
 233 {
 234         int i;
 235         union xhci_trb *enq = ring->enqueue;
 236         struct xhci_segment *enq_seg = ring->enq_seg;
 237
 238         /* Check if ring is empty */
 239         if (enq == ring->dequeue)
 240                 return 1;
 241         /* Make sure there's an extra empty TRB available */
 242         for (i = 0; i <= num_trbs; ++i) {
 243                 if (enq == ring->dequeue)
 244                         return 0;
 245                 enq++;
 246                 while (last_trb(xhci, ring, enq_seg, enq)) {
 247                         enq_seg = enq_seg->next;
 248                         enq = enq_seg->trbs;
 249                 }
 250         }
 251         return 1;
 252 }
 253
 254 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
 255 {
 256         u64 temp;
 257         dma_addr_t deq;
 258
 259         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
 260                         xhci->event_ring->dequeue);
 261         if (deq == 0 && !in_interrupt())
 262                 xhci_warn(xhci, "WARN something wrong with SW event ring "
 263                                 "dequeue ptr.\n");
 264         /* Update HC event ring dequeue pointer */
 265         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
 266         temp &= ERST_PTR_MASK;
 267         /* Don't clear the EHB bit (which is RW1C) because
 268          * there might be more events to service.
 269          */
 270         temp &= ~ERST_EHB;
 271         xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
 272         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
 273                         &xhci->ir_set->erst_dequeue);
 274 }
 275
 276 /* Ring the host controller doorbell after placing a command on the ring */
 277 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 278 {
 279         u32 temp;
 280
 281         xhci_dbg(xhci, "// Ding dong!\n");
 282         temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
 283         xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
 284         /* Flush PCI posted writes */
 285         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 286 }
 287
 288 static void ring_ep_doorbell(struct xhci_hcd *xhci,
 289                 unsigned int slot_id,
 290                 unsigned int ep_index)
 291 {
 292         struct xhci_ring *ep_ring;
 293         u32 field;
 294         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 295
 296         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
 297         /* Don't ring the doorbell for this endpoint if there are pending
 298          * cancellations because the we don't want to interrupt processing.
 299          */
 300         if (!ep_ring->cancels_pending && !(ep_ring->state & SET_DEQ_PENDING)
 301                         && !(ep_ring->state & EP_HALTED)) {
 302                 field = xhci_readl(xhci, db_addr) & DB_MASK;
 303                 xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr);
 304                 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
 305                  * isn't time-critical and we shouldn't make the CPU wait for
 306                  * the flush.
 307                  */
 308                 xhci_readl(xhci, db_addr);
 309         }
 310 }
 311
 312 /*
 313  * Find the segment that trb is in.  Start searching in start_seg.
 314  * If we must move past a segment that has a link TRB with a toggle cycle state
 315  * bit set, then we will toggle the value pointed at by cycle_state.
 316  */
 317 static struct xhci_segment *find_trb_seg(
 318                 struct xhci_segment *start_seg,
 319                 union xhci_trb  *trb, int *cycle_state)
 320 {
 321         struct xhci_segment *cur_seg = start_seg;
 322         struct xhci_generic_trb *generic_trb;
 323
 324         while (cur_seg->trbs > trb ||
 325                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 326                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 327                 if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK &&
 328                                 (generic_trb->field[3] & LINK_TOGGLE))
 329                         *cycle_state = ~(*cycle_state) & 0x1;
 330                 cur_seg = cur_seg->next;
 331                 if (cur_seg == start_seg)
 332                         /* Looped over the entire list.  Oops! */
 333                         return 0;
 334         }
 335         return cur_seg;
 336 }
 337
 338 struct dequeue_state {
 339         struct xhci_segment *new_deq_seg;
 340         union xhci_trb *new_deq_ptr;
 341         int new_cycle_state;
 342 };
 343
 344 /*
 345  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 346  * Record the new state of the xHC's endpoint ring dequeue segment,
 347  * dequeue pointer, and new consumer cycle state in state.
 348  * Update our internal representation of the ring's dequeue pointer.
 349  *
 350  * We do this in three jumps:
 351  *  - First we update our new ring state to be the same as when the xHC stopped.
 352  *  - Then we traverse the ring to find the segment that contains
 353  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 354  *    any link TRBs with the toggle cycle bit set.
 355  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 356  *    if we've moved it past a link TRB with the toggle cycle bit set.
 357  */
 358 static void find_new_dequeue_state(struct xhci_hcd *xhci,
 359                 unsigned int slot_id, unsigned int ep_index,
 360                 struct xhci_td *cur_td, struct dequeue_state *state)
 361 {
 362         struct xhci_virt_device *dev = xhci->devs[slot_id];
 363         struct xhci_ring *ep_ring = dev->ep_rings[ep_index];
 364         struct xhci_generic_trb *trb;
 365
 366         state->new_cycle_state = 0;
 367         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 368                         ep_ring->stopped_trb,
 369                         &state->new_cycle_state);
 370         if (!state->new_deq_seg)
 371                 BUG();
 372         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 373         state->new_cycle_state = 0x1 & dev->out_ctx->ep[ep_index].deq;
 374
 375         state->new_deq_ptr = cur_td->last_trb;
 376         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 377                         state->new_deq_ptr,
 378                         &state->new_cycle_state);
 379         if (!state->new_deq_seg)
 380                 BUG();
 381
 382         trb = &state->new_deq_ptr->generic;
 383         if (TRB_TYPE(trb->field[3]) == TRB_LINK &&
 384                                 (trb->field[3] & LINK_TOGGLE))
 385                 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
 386         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 387
 388         /* Don't update the ring cycle state for the producer (us). */
 389         ep_ring->dequeue = state->new_deq_ptr;
 390         ep_ring->deq_seg = state->new_deq_seg;
 391 }
 392
 393 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 394                 struct xhci_td *cur_td)
 395 {
 396         struct xhci_segment *cur_seg;
 397         union xhci_trb *cur_trb;
 398
 399         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 400                         true;
 401                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 402                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 403                                 TRB_TYPE(TRB_LINK)) {
 404                         /* Unchain any chained Link TRBs, but
 405                          * leave the pointers intact.
 406                          */
 407                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 408                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 409                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 410                                         "in seg %p (0x%llx dma)\n",
 411                                         cur_trb,
 412                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 413                                         cur_seg,
 414                                         (unsigned long long)cur_seg->dma);
 415                 } else {
 416                         cur_trb->generic.field[0] = 0;
 417                         cur_trb->generic.field[1] = 0;
 418                         cur_trb->generic.field[2] = 0;
 419                         /* Preserve only the cycle bit of this TRB */
 420                         cur_trb->generic.field[3] &= TRB_CYCLE;
 421                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 422                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 423                                         "in seg %p (0x%llx dma)\n",
 424                                         cur_trb,
 425                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 426                                         cur_seg,
 427                                         (unsigned long long)cur_seg->dma);
 428                 }
 429                 if (cur_trb == cur_td->last_trb)
 430                         break;
 431         }
 432 }
 433
 434 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 435                 unsigned int ep_index, struct xhci_segment *deq_seg,
 436                 union xhci_trb *deq_ptr, u32 cycle_state);
 437
 438 /*
 439  * When we get a command completion for a Stop Endpoint Command, we need to
 440  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 441  *
 442  *  1. If the HW was in the middle of processing the TD that needs to be
 443  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 444  *     in the TD with a Set Dequeue Pointer Command.
 445  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 446  *     bit cleared) so that the HW will skip over them.
 447  */
 448 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 449                 union xhci_trb *trb)
 450 {
 451         unsigned int slot_id;
 452         unsigned int ep_index;
 453         struct xhci_ring *ep_ring;
 454         struct list_head *entry;
 455         struct xhci_td *cur_td = 0;
 456         struct xhci_td *last_unlinked_td;
 457
 458         struct dequeue_state deq_state;
 459 #ifdef CONFIG_USB_HCD_STAT
 460         ktime_t stop_time = ktime_get();
 461 #endif
 462
 463         memset(&deq_state, 0, sizeof(deq_state));
 464         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 465         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 466         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
 467
 468         if (list_empty(&ep_ring->cancelled_td_list))
 469                 return;
 470
 471         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 472          * We have the xHCI lock, so nothing can modify this list until we drop
 473          * it.  We're also in the event handler, so we can't get re-interrupted
 474          * if another Stop Endpoint command completes
 475          */
 476         list_for_each(entry, &ep_ring->cancelled_td_list) {
 477                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 478                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 479                                 cur_td->first_trb,
 480                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 481                 /*
 482                  * If we stopped on the TD we need to cancel, then we have to
 483                  * move the xHC endpoint ring dequeue pointer past this TD.
 484                  */
 485                 if (cur_td == ep_ring->stopped_td)
 486                         find_new_dequeue_state(xhci, slot_id, ep_index, cur_td,
 487                                         &deq_state);
 488                 else
 489                         td_to_noop(xhci, ep_ring, cur_td);
 490                 /*
 491                  * The event handler won't see a completion for this TD anymore,
 492                  * so remove it from the endpoint ring's TD list.  Keep it in
 493                  * the cancelled TD list for URB completion later.
 494                  */
 495                 list_del(&cur_td->td_list);
 496                 ep_ring->cancels_pending--;
 497         }
 498         last_unlinked_td = cur_td;
 499
 500         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 501         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 502                 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 503                                 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 504                                 deq_state.new_deq_seg,
 505                                 (unsigned long long)deq_state.new_deq_seg->dma,
 506                                 deq_state.new_deq_ptr,
 507                                 (unsigned long long)xhci_trb_virt_to_dma(deq_state.new_deq_seg, deq_state.new_deq_ptr),
 508                                 deq_state.new_cycle_state);
 509                 queue_set_tr_deq(xhci, slot_id, ep_index,
 510                                 deq_state.new_deq_seg,
 511                                 deq_state.new_deq_ptr,
 512                                 (u32) deq_state.new_cycle_state);
 513                 /* Stop the TD queueing code from ringing the doorbell until
 514                  * this command completes.  The HC won't set the dequeue pointer
 515                  * if the ring is running, and ringing the doorbell starts the
 516                  * ring running.
 517                  */
 518                 ep_ring->state |= SET_DEQ_PENDING;
 519                 xhci_ring_cmd_db(xhci);
 520         } else {
 521                 /* Otherwise just ring the doorbell to restart the ring */
 522                 ring_ep_doorbell(xhci, slot_id, ep_index);
 523         }
 524
 525         /*
 526          * Drop the lock and complete the URBs in the cancelled TD list.
 527          * New TDs to be cancelled might be added to the end of the list before
 528          * we can complete all the URBs for the TDs we already unlinked.
 529          * So stop when we've completed the URB for the last TD we unlinked.
 530          */
 531         do {
 532                 cur_td = list_entry(ep_ring->cancelled_td_list.next,
 533                                 struct xhci_td, cancelled_td_list);
 534                 list_del(&cur_td->cancelled_td_list);
 535
 536                 /* Clean up the cancelled URB */
 537 #ifdef CONFIG_USB_HCD_STAT
 538                 hcd_stat_update(xhci->tp_stat, cur_td->urb->actual_length,
 539                                 ktime_sub(stop_time, cur_td->start_time));
 540 #endif
 541                 cur_td->urb->hcpriv = NULL;
 542                 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), cur_td->urb);
 543
 544                 xhci_dbg(xhci, "Giveback cancelled URB %p\n", cur_td->urb);
 545                 spin_unlock(&xhci->lock);
 546                 /* Doesn't matter what we pass for status, since the core will
 547                  * just overwrite it (because the URB has been unlinked).
 548                  */
 549                 usb_hcd_giveback_urb(xhci_to_hcd(xhci), cur_td->urb, 0);
 550                 kfree(cur_td);
 551
 552                 spin_lock(&xhci->lock);
 553         } while (cur_td != last_unlinked_td);
 554
 555         /* Return to the event handler with xhci->lock re-acquired */
 556 }
 557
 558 /*
 559  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 560  * we need to clear the set deq pending flag in the endpoint ring state, so that
 561  * the TD queueing code can ring the doorbell again.  We also need to ring the
 562  * endpoint doorbell to restart the ring, but only if there aren't more
 563  * cancellations pending.
 564  */
 565 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 566                 struct xhci_event_cmd *event,
 567                 union xhci_trb *trb)
 568 {
 569         unsigned int slot_id;
 570         unsigned int ep_index;
 571         struct xhci_ring *ep_ring;
 572         struct xhci_virt_device *dev;
 573
 574         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 575         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 576         dev = xhci->devs[slot_id];
 577         ep_ring = dev->ep_rings[ep_index];
 578
 579         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 580                 unsigned int ep_state;
 581                 unsigned int slot_state;
 582
 583                 switch (GET_COMP_CODE(event->status)) {
 584                 case COMP_TRB_ERR:
 585                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 586                                         "of stream ID configuration\n");
 587                         break;
 588                 case COMP_CTX_STATE:
 589                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 590                                         "to incorrect slot or ep state.\n");
 591                         ep_state = dev->out_ctx->ep[ep_index].ep_info;
 592                         ep_state &= EP_STATE_MASK;
 593                         slot_state = dev->out_ctx->slot.dev_state;
 594                         slot_state = GET_SLOT_STATE(slot_state);
 595                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 596                                         slot_state, ep_state);
 597                         break;
 598                 case COMP_EBADSLT:
 599                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 600                                         "slot %u was not enabled.\n", slot_id);
 601                         break;
 602                 default:
 603                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 604                                         "completion code of %u.\n",
 605                                         GET_COMP_CODE(event->status));
 606                         break;
 607                 }
 608                 /* OK what do we do now?  The endpoint state is hosed, and we
 609                  * should never get to this point if the synchronization between
 610                  * queueing, and endpoint state are correct.  This might happen
 611                  * if the device gets disconnected after we've finished
 612                  * cancelling URBs, which might not be an error...
 613                  */
 614         } else {
 615                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 616                                 dev->out_ctx->ep[ep_index].deq);
 617         }
 618
 619         ep_ring->state &= ~SET_DEQ_PENDING;
 620         ring_ep_doorbell(xhci, slot_id, ep_index);
 621 }
 622
 623 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 624                 struct xhci_event_cmd *event,
 625                 union xhci_trb *trb)
 626 {
 627         int slot_id;
 628         unsigned int ep_index;
 629
 630         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 631         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 632         /* This command will only fail if the endpoint wasn't halted,
 633          * but we don't care.
 634          */
 635         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 636                         (unsigned int) GET_COMP_CODE(event->status));
 637
 638         /* Clear our internal halted state and restart the ring */
 639         xhci->devs[slot_id]->ep_rings[ep_index]->state &= ~EP_HALTED;
 640         ring_ep_doorbell(xhci, slot_id, ep_index);
 641 }
 642
 643 static void handle_cmd_completion(struct xhci_hcd *xhci,
 644                 struct xhci_event_cmd *event)
 645 {
 646         int slot_id = TRB_TO_SLOT_ID(event->flags);
 647         u64 cmd_dma;
 648         dma_addr_t cmd_dequeue_dma;
 649
 650         cmd_dma = event->cmd_trb;
 651         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
 652                         xhci->cmd_ring->dequeue);
 653         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
 654         if (cmd_dequeue_dma == 0) {
 655                 xhci->error_bitmask |= 1 << 4;
 656                 return;
 657         }
 658         /* Does the DMA address match our internal dequeue pointer address? */
 659         if (cmd_dma != (u64) cmd_dequeue_dma) {
 660                 xhci->error_bitmask |= 1 << 5;
 661                 return;
 662         }
 663         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
 664         case TRB_TYPE(TRB_ENABLE_SLOT):
 665                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
 666                         xhci->slot_id = slot_id;
 667                 else
 668                         xhci->slot_id = 0;
 669                 complete(&xhci->addr_dev);
 670                 break;
 671         case TRB_TYPE(TRB_DISABLE_SLOT):
 672                 if (xhci->devs[slot_id])
 673                         xhci_free_virt_device(xhci, slot_id);
 674                 break;
 675         case TRB_TYPE(TRB_CONFIG_EP):
 676                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 677                 complete(&xhci->devs[slot_id]->cmd_completion);
 678                 break;
 679         case TRB_TYPE(TRB_ADDR_DEV):
 680                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 681                 complete(&xhci->addr_dev);
 682                 break;
 683         case TRB_TYPE(TRB_STOP_RING):
 684                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
 685                 break;
 686         case TRB_TYPE(TRB_SET_DEQ):
 687                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
 688                 break;
 689         case TRB_TYPE(TRB_CMD_NOOP):
 690                 ++xhci->noops_handled;
 691                 break;
 692         case TRB_TYPE(TRB_RESET_EP):
 693                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
 694                 break;
 695         default:
 696                 /* Skip over unknown commands on the event ring */
 697                 xhci->error_bitmask |= 1 << 6;
 698                 break;
 699         }
 700         inc_deq(xhci, xhci->cmd_ring, false);
 701 }
 702
 703 static void handle_port_status(struct xhci_hcd *xhci,
 704                 union xhci_trb *event)
 705 {
 706         u32 port_id;
 707
 708         /* Port status change events always have a successful completion code */
 709         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
 710                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
 711                 xhci->error_bitmask |= 1 << 8;
 712         }
 713         /* FIXME: core doesn't care about all port link state changes yet */
 714         port_id = GET_PORT_ID(event->generic.field[0]);
 715         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
 716
 717         /* Update event ring dequeue pointer before dropping the lock */
 718         inc_deq(xhci, xhci->event_ring, true);
 719         xhci_set_hc_event_deq(xhci);
 720
 721         spin_unlock(&xhci->lock);
 722         /* Pass this up to the core */
 723         usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
 724         spin_lock(&xhci->lock);
 725 }
 726
 727 /*
 728  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
 729  * at end_trb, which may be in another segment.  If the suspect DMA address is a
 730  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
 731  * returns 0.
 732  */
 733 static struct xhci_segment *trb_in_td(
 734                 struct xhci_segment *start_seg,
 735                 union xhci_trb  *start_trb,
 736                 union xhci_trb  *end_trb,
 737                 dma_addr_t      suspect_dma)
 738 {
 739         dma_addr_t start_dma;
 740         dma_addr_t end_seg_dma;
 741         dma_addr_t end_trb_dma;
 742         struct xhci_segment *cur_seg;
 743
 744         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
 745         cur_seg = start_seg;
 746
 747         do {
 748                 /* We may get an event for a Link TRB in the middle of a TD */
 749                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
 750                                 &start_seg->trbs[TRBS_PER_SEGMENT - 1]);
 751                 /* If the end TRB isn't in this segment, this is set to 0 */
 752                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
 753
 754                 if (end_trb_dma > 0) {
 755                         /* The end TRB is in this segment, so suspect should be here */
 756                         if (start_dma <= end_trb_dma) {
 757                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
 758                                         return cur_seg;
 759                         } else {
 760                                 /* Case for one segment with
 761                                  * a TD wrapped around to the top
 762                                  */
 763                                 if ((suspect_dma >= start_dma &&
 764                                                         suspect_dma <= end_seg_dma) ||
 765                                                 (suspect_dma >= cur_seg->dma &&
 766                                                  suspect_dma <= end_trb_dma))
 767                                         return cur_seg;
 768                         }
 769                         return 0;
 770                 } else {
 771                         /* Might still be somewhere in this segment */
 772                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
 773                                 return cur_seg;
 774                 }
 775                 cur_seg = cur_seg->next;
 776                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
 777         } while (1);
 778
 779 }
 780
 781 /*
 782  * If this function returns an error condition, it means it got a Transfer
 783  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
 784  * At this point, the host controller is probably hosed and should be reset.
 785  */
 786 static int handle_tx_event(struct xhci_hcd *xhci,
 787                 struct xhci_transfer_event *event)
 788 {
 789         struct xhci_virt_device *xdev;
 790         struct xhci_ring *ep_ring;
 791         int ep_index;
 792         struct xhci_td *td = 0;
 793         dma_addr_t event_dma;
 794         struct xhci_segment *event_seg;
 795         union xhci_trb *event_trb;
 796         struct urb *urb = 0;
 797         int status = -EINPROGRESS;
 798
 799         xhci_dbg(xhci, "In %s\n", __func__);
 800         xdev = xhci->devs[TRB_TO_SLOT_ID(event->flags)];
 801         if (!xdev) {
 802                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
 803                 return -ENODEV;
 804         }
 805
 806         /* Endpoint ID is 1 based, our index is zero based */
 807         ep_index = TRB_TO_EP_ID(event->flags) - 1;
 808         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
 809         ep_ring = xdev->ep_rings[ep_index];
 810         if (!ep_ring || (xdev->out_ctx->ep[ep_index].ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
 811                 xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n");
 812                 return -ENODEV;
 813         }
 814
 815         event_dma = event->buffer;
 816         /* This TRB should be in the TD at the head of this ring's TD list */
 817         xhci_dbg(xhci, "%s - checking for list empty\n", __func__);
 818         if (list_empty(&ep_ring->td_list)) {
 819                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
 820                                 TRB_TO_SLOT_ID(event->flags), ep_index);
 821                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
 822                                 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
 823                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
 824                 urb = NULL;
 825                 goto cleanup;
 826         }
 827         xhci_dbg(xhci, "%s - getting list entry\n", __func__);
 828         td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
 829
 830         /* Is this a TRB in the currently executing TD? */
 831         xhci_dbg(xhci, "%s - looking for TD\n", __func__);
 832         event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
 833                         td->last_trb, event_dma);
 834         xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg);
 835         if (!event_seg) {
 836                 /* HC is busted, give up! */
 837                 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
 838                 return -ESHUTDOWN;
 839         }
 840         event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
 841         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
 842                         (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
 843         xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n",
 844                         lower_32_bits(event->buffer));
 845         xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n",
 846                         upper_32_bits(event->buffer));
 847         xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
 848                         (unsigned int) event->transfer_len);
 849         xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
 850                         (unsigned int) event->flags);
 851
 852         /* Look for common error cases */
 853         switch (GET_COMP_CODE(event->transfer_len)) {
 854         /* Skip codes that require special handling depending on
 855          * transfer type
 856          */
 857         case COMP_SUCCESS:
 858         case COMP_SHORT_TX:
 859                 break;
 860         case COMP_STOP:
 861                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
 862                 break;
 863         case COMP_STOP_INVAL:
 864                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
 865                 break;
 866         case COMP_STALL:
 867                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
 868                 ep_ring->state |= EP_HALTED;
 869                 status = -EPIPE;
 870                 break;
 871         case COMP_TRB_ERR:
 872                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
 873                 status = -EILSEQ;
 874                 break;
 875         case COMP_TX_ERR:
 876                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
 877                 status = -EPROTO;
 878                 break;
 879         case COMP_BABBLE:
 880                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
 881                 status = -EOVERFLOW;
 882                 break;
 883         case COMP_DB_ERR:
 884                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
 885                 status = -ENOSR;
 886                 break;
 887         default:
 888                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
 889                 urb = NULL;
 890                 goto cleanup;
 891         }
 892         /* Now update the urb's actual_length and give back to the core */
 893         /* Was this a control transfer? */
 894         if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
 895                 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
 896                 switch (GET_COMP_CODE(event->transfer_len)) {
 897                 case COMP_SUCCESS:
 898                         if (event_trb == ep_ring->dequeue) {
 899                                 xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
 900                                 status = -ESHUTDOWN;
 901                         } else if (event_trb != td->last_trb) {
 902                                 xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
 903                                 status = -ESHUTDOWN;
 904                         } else {
 905                                 xhci_dbg(xhci, "Successful control transfer!\n");
 906                                 status = 0;
 907                         }
 908                         break;
 909                 case COMP_SHORT_TX:
 910                         xhci_warn(xhci, "WARN: short transfer on control ep\n");
 911                         status = -EREMOTEIO;
 912                         break;
 913                 default:
 914                         /* Others already handled above */
 915                         break;
 916                 }
 917                 /*
 918                  * Did we transfer any data, despite the errors that might have
 919                  * happened?  I.e. did we get past the setup stage?
 920                  */
 921                 if (event_trb != ep_ring->dequeue) {
 922                         /* The event was for the status stage */
 923                         if (event_trb == td->last_trb) {
 924                                 /* Did we already see a short data stage? */
 925                                 if (td->urb->actual_length != 0)
 926                                         status = -EREMOTEIO;
 927                                 else
 928                                         td->urb->actual_length =
 929                                                 td->urb->transfer_buffer_length;
 930                         } else {
 931                         /* Maybe the event was for the data stage? */
 932                                 if (GET_COMP_CODE(event->transfer_len) != COMP_STOP_INVAL) {
 933                                         /* We didn't stop on a link TRB in the middle */
 934                                         td->urb->actual_length =
 935                                                 td->urb->transfer_buffer_length -
 936                                                 TRB_LEN(event->transfer_len);
 937                                         xhci_dbg(xhci, "Waiting for status stage event\n");
 938                                         urb = NULL;
 939                                         goto cleanup;
 940                                 }
 941                         }
 942                 }
 943         } else {
 944                 switch (GET_COMP_CODE(event->transfer_len)) {
 945                 case COMP_SUCCESS:
 946                         /* Double check that the HW transferred everything. */
 947                         if (event_trb != td->last_trb) {
 948                                 xhci_warn(xhci, "WARN Successful completion "
 949                                                 "on short TX\n");
 950                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
 951                                         status = -EREMOTEIO;
 952                                 else
 953                                         status = 0;
 954                         } else {
 955                                 xhci_dbg(xhci, "Successful bulk transfer!\n");
 956                                 status = 0;
 957                         }
 958                         break;
 959                 case COMP_SHORT_TX:
 960                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
 961                                 status = -EREMOTEIO;
 962                         else
 963                                 status = 0;
 964                         break;
 965                 default:
 966                         /* Others already handled above */
 967                         break;
 968                 }
 969                 dev_dbg(&td->urb->dev->dev,
 970                                 "ep %#x - asked for %d bytes, "
 971                                 "%d bytes untransferred\n",
 972                                 td->urb->ep->desc.bEndpointAddress,
 973                                 td->urb->transfer_buffer_length,
 974                                 TRB_LEN(event->transfer_len));
 975                 /* Fast path - was this the last TRB in the TD for this URB? */
 976                 if (event_trb == td->last_trb) {
 977                         if (TRB_LEN(event->transfer_len) != 0) {
 978                                 td->urb->actual_length =
 979                                         td->urb->transfer_buffer_length -
 980                                         TRB_LEN(event->transfer_len);
 981                                 if (td->urb->actual_length < 0) {
 982                                         xhci_warn(xhci, "HC gave bad length "
 983                                                         "of %d bytes left\n",
 984                                                         TRB_LEN(event->transfer_len));
 985                                         td->urb->actual_length = 0;
 986                                 }
 987                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
 988                                         status = -EREMOTEIO;
 989                                 else
 990                                         status = 0;
 991                         } else {
 992                                 td->urb->actual_length = td->urb->transfer_buffer_length;
 993                                 /* Ignore a short packet completion if the
 994                                  * untransferred length was zero.
 995                                  */
 996                                 status = 0;
 997                         }
 998                 } else {
 999                         /* Slow path - walk the list, starting from the dequeue
1000                          * pointer, to get the actual length transferred.
1001                          */
1002                         union xhci_trb *cur_trb;
1003                         struct xhci_segment *cur_seg;
1004
1005                         td->urb->actual_length = 0;
1006                         for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1007                                         cur_trb != event_trb;
1008                                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1009                                 if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP &&
1010                                                 TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK)
1011                                         td->urb->actual_length +=
1012                                                 TRB_LEN(cur_trb->generic.field[2]);
1013                         }
1014                         /* If the ring didn't stop on a Link or No-op TRB, add
1015                          * in the actual bytes transferred from the Normal TRB
1016                          */
1017                         if (GET_COMP_CODE(event->transfer_len) != COMP_STOP_INVAL)
1018                                 td->urb->actual_length +=
1019                                         TRB_LEN(cur_trb->generic.field[2]) -
1020                                         TRB_LEN(event->transfer_len);
1021                 }
1022         }
1023         /* The Endpoint Stop Command completion will take care of
1024          * any stopped TDs.  A stopped TD may be restarted, so don't update the
1025          * ring dequeue pointer or take this TD off any lists yet.
1026          */
1027         if (GET_COMP_CODE(event->transfer_len) == COMP_STOP_INVAL ||
1028                         GET_COMP_CODE(event->transfer_len) == COMP_STOP) {
1029                 ep_ring->stopped_td = td;
1030                 ep_ring->stopped_trb = event_trb;
1031         } else {
1032                 /* Update ring dequeue pointer */
1033                 while (ep_ring->dequeue != td->last_trb)
1034                         inc_deq(xhci, ep_ring, false);
1035                 inc_deq(xhci, ep_ring, false);
1036
1037                 /* Clean up the endpoint's TD list */
1038                 urb = td->urb;
1039                 list_del(&td->td_list);
1040                 /* Was this TD slated to be cancelled but completed anyway? */
1041                 if (!list_empty(&td->cancelled_td_list)) {
1042                         list_del(&td->cancelled_td_list);
1043                         ep_ring->cancels_pending--;
1044                 }
1045                 kfree(td);
1046                 urb->hcpriv = NULL;
1047         }
1048 cleanup:
1049         inc_deq(xhci, xhci->event_ring, true);
1050         xhci_set_hc_event_deq(xhci);
1051
1052         /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1053         if (urb) {
1054                 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1055                 xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
1056                                 urb, td->urb->actual_length, status);
1057                 spin_unlock(&xhci->lock);
1058                 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1059                 spin_lock(&xhci->lock);
1060         }
1061         return 0;
1062 }
1063
1064 /*
1065  * This function handles all OS-owned events on the event ring.  It may drop
1066  * xhci->lock between event processing (e.g. to pass up port status changes).
1067  */
1068 void xhci_handle_event(struct xhci_hcd *xhci)
1069 {
1070         union xhci_trb *event;
1071         int update_ptrs = 1;
1072         int ret;
1073
1074         xhci_dbg(xhci, "In %s\n", __func__);
1075         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1076                 xhci->error_bitmask |= 1 << 1;
1077                 return;
1078         }
1079
1080         event = xhci->event_ring->dequeue;
1081         /* Does the HC or OS own the TRB? */
1082         if ((event->event_cmd.flags & TRB_CYCLE) !=
1083                         xhci->event_ring->cycle_state) {
1084                 xhci->error_bitmask |= 1 << 2;
1085                 return;
1086         }
1087         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1088
1089         /* FIXME: Handle more event types. */
1090         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1091         case TRB_TYPE(TRB_COMPLETION):
1092                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1093                 handle_cmd_completion(xhci, &event->event_cmd);
1094                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1095                 break;
1096         case TRB_TYPE(TRB_PORT_STATUS):
1097                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1098                 handle_port_status(xhci, event);
1099                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1100                 update_ptrs = 0;
1101                 break;
1102         case TRB_TYPE(TRB_TRANSFER):
1103                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1104                 ret = handle_tx_event(xhci, &event->trans_event);
1105                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1106                 if (ret < 0)
1107                         xhci->error_bitmask |= 1 << 9;
1108                 else
1109                         update_ptrs = 0;
1110                 break;
1111         default:
1112                 xhci->error_bitmask |= 1 << 3;
1113         }
1114
1115         if (update_ptrs) {
1116                 /* Update SW and HC event ring dequeue pointer */
1117                 inc_deq(xhci, xhci->event_ring, true);
1118                 xhci_set_hc_event_deq(xhci);
1119         }
1120         /* Are there more items on the event ring? */
1121         xhci_handle_event(xhci);
1122 }
1123
1124 /****           Endpoint Ring Operations        ****/
1125
1126 /*
1127  * Generic function for queueing a TRB on a ring.
1128  * The caller must have checked to make sure there's room on the ring.
1129  */
1130 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1131                 bool consumer,
1132                 u32 field1, u32 field2, u32 field3, u32 field4)
1133 {
1134         struct xhci_generic_trb *trb;
1135
1136         trb = &ring->enqueue->generic;
1137         trb->field[0] = field1;
1138         trb->field[1] = field2;
1139         trb->field[2] = field3;
1140         trb->field[3] = field4;
1141         inc_enq(xhci, ring, consumer);
1142 }
1143
1144 /*
1145  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1146  * FIXME allocate segments if the ring is full.
1147  */
1148 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1149                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1150 {
1151         /* Make sure the endpoint has been added to xHC schedule */
1152         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1153         switch (ep_state) {
1154         case EP_STATE_DISABLED:
1155                 /*
1156                  * USB core changed config/interfaces without notifying us,
1157                  * or hardware is reporting the wrong state.
1158                  */
1159                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1160                 return -ENOENT;
1161         case EP_STATE_HALTED:
1162         case EP_STATE_ERROR:
1163                 xhci_warn(xhci, "WARN waiting for halt or error on ep "
1164                                 "to be cleared\n");
1165                 /* FIXME event handling code for error needs to clear it */
1166                 /* XXX not sure if this should be -ENOENT or not */
1167                 return -EINVAL;
1168         case EP_STATE_STOPPED:
1169         case EP_STATE_RUNNING:
1170                 break;
1171         default:
1172                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1173                 /*
1174                  * FIXME issue Configure Endpoint command to try to get the HC
1175                  * back into a known state.
1176                  */
1177                 return -EINVAL;
1178         }
1179         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1180                 /* FIXME allocate more room */
1181                 xhci_err(xhci, "ERROR no room on ep ring\n");
1182                 return -ENOMEM;
1183         }
1184         return 0;
1185 }
1186
1187 static int prepare_transfer(struct xhci_hcd *xhci,
1188                 struct xhci_virt_device *xdev,
1189                 unsigned int ep_index,
1190                 unsigned int num_trbs,
1191                 struct urb *urb,
1192                 struct xhci_td **td,
1193                 gfp_t mem_flags)
1194 {
1195         int ret;
1196
1197         ret = prepare_ring(xhci, xdev->ep_rings[ep_index],
1198                         xdev->out_ctx->ep[ep_index].ep_info & EP_STATE_MASK,
1199                         num_trbs, mem_flags);
1200         if (ret)
1201                 return ret;
1202         *td = kzalloc(sizeof(struct xhci_td), mem_flags);
1203         if (!*td)
1204                 return -ENOMEM;
1205         INIT_LIST_HEAD(&(*td)->td_list);
1206         INIT_LIST_HEAD(&(*td)->cancelled_td_list);
1207
1208         ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
1209         if (unlikely(ret)) {
1210                 kfree(*td);
1211                 return ret;
1212         }
1213
1214         (*td)->urb = urb;
1215         urb->hcpriv = (void *) (*td);
1216         /* Add this TD to the tail of the endpoint ring's TD list */
1217         list_add_tail(&(*td)->td_list, &xdev->ep_rings[ep_index]->td_list);
1218         (*td)->start_seg = xdev->ep_rings[ep_index]->enq_seg;
1219         (*td)->first_trb = xdev->ep_rings[ep_index]->enqueue;
1220
1221         return 0;
1222 }
1223
1224 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
1225 {
1226         int num_sgs, num_trbs, running_total, temp, i;
1227         struct scatterlist *sg;
1228
1229         sg = NULL;
1230         num_sgs = urb->num_sgs;
1231         temp = urb->transfer_buffer_length;
1232
1233         xhci_dbg(xhci, "count sg list trbs: \n");
1234         num_trbs = 0;
1235         for_each_sg(urb->sg->sg, sg, num_sgs, i) {
1236                 unsigned int previous_total_trbs = num_trbs;
1237                 unsigned int len = sg_dma_len(sg);
1238
1239                 /* Scatter gather list entries may cross 64KB boundaries */
1240                 running_total = TRB_MAX_BUFF_SIZE -
1241                         (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1242                 if (running_total != 0)
1243                         num_trbs++;
1244
1245                 /* How many more 64KB chunks to transfer, how many more TRBs? */
1246                 while (running_total < sg_dma_len(sg)) {
1247                         num_trbs++;
1248                         running_total += TRB_MAX_BUFF_SIZE;
1249                 }
1250                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1251                                 i, (unsigned long long)sg_dma_address(sg),
1252                                 len, len, num_trbs - previous_total_trbs);
1253
1254                 len = min_t(int, len, temp);
1255                 temp -= len;
1256                 if (temp == 0)
1257                         break;
1258         }
1259         xhci_dbg(xhci, "\n");
1260         if (!in_interrupt())
1261                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1262                                 urb->ep->desc.bEndpointAddress,
1263                                 urb->transfer_buffer_length,
1264                                 num_trbs);
1265         return num_trbs;
1266 }
1267
1268 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
1269 {
1270         if (num_trbs != 0)
1271                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
1272                                 "TRBs, %d left\n", __func__,
1273                                 urb->ep->desc.bEndpointAddress, num_trbs);
1274         if (running_total != urb->transfer_buffer_length)
1275                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
1276                                 "queued %#x (%d), asked for %#x (%d)\n",
1277                                 __func__,
1278                                 urb->ep->desc.bEndpointAddress,
1279                                 running_total, running_total,
1280                                 urb->transfer_buffer_length,
1281                                 urb->transfer_buffer_length);
1282 }
1283
1284 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
1285                 unsigned int ep_index, int start_cycle,
1286                 struct xhci_generic_trb *start_trb, struct xhci_td *td)
1287 {
1288         /*
1289          * Pass all the TRBs to the hardware at once and make sure this write
1290          * isn't reordered.
1291          */
1292         wmb();
1293         start_trb->field[3] |= start_cycle;
1294         ring_ep_doorbell(xhci, slot_id, ep_index);
1295 }
1296
1297 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1298                 struct urb *urb, int slot_id, unsigned int ep_index)
1299 {
1300         struct xhci_ring *ep_ring;
1301         unsigned int num_trbs;
1302         struct xhci_td *td;
1303         struct scatterlist *sg;
1304         int num_sgs;
1305         int trb_buff_len, this_sg_len, running_total;
1306         bool first_trb;
1307         u64 addr;
1308
1309         struct xhci_generic_trb *start_trb;
1310         int start_cycle;
1311
1312         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1313         num_trbs = count_sg_trbs_needed(xhci, urb);
1314         num_sgs = urb->num_sgs;
1315
1316         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
1317                         ep_index, num_trbs, urb, &td, mem_flags);
1318         if (trb_buff_len < 0)
1319                 return trb_buff_len;
1320         /*
1321          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1322          * until we've finished creating all the other TRBs.  The ring's cycle
1323          * state may change as we enqueue the other TRBs, so save it too.
1324          */
1325         start_trb = &ep_ring->enqueue->generic;
1326         start_cycle = ep_ring->cycle_state;
1327
1328         running_total = 0;
1329         /*
1330          * How much data is in the first TRB?
1331          *
1332          * There are three forces at work for TRB buffer pointers and lengths:
1333          * 1. We don't want to walk off the end of this sg-list entry buffer.
1334          * 2. The transfer length that the driver requested may be smaller than
1335          *    the amount of memory allocated for this scatter-gather list.
1336          * 3. TRBs buffers can't cross 64KB boundaries.
1337          */
1338         sg = urb->sg->sg;
1339         addr = (u64) sg_dma_address(sg);
1340         this_sg_len = sg_dma_len(sg);
1341         trb_buff_len = TRB_MAX_BUFF_SIZE -
1342                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1343         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1344         if (trb_buff_len > urb->transfer_buffer_length)
1345                 trb_buff_len = urb->transfer_buffer_length;
1346         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
1347                         trb_buff_len);
1348
1349         first_trb = true;
1350         /* Queue the first TRB, even if it's zero-length */
1351         do {
1352                 u32 field = 0;
1353                 u32 length_field = 0;
1354
1355                 /* Don't change the cycle bit of the first TRB until later */
1356                 if (first_trb)
1357                         first_trb = false;
1358                 else
1359                         field |= ep_ring->cycle_state;
1360
1361                 /* Chain all the TRBs together; clear the chain bit in the last
1362                  * TRB to indicate it's the last TRB in the chain.
1363                  */
1364                 if (num_trbs > 1) {
1365                         field |= TRB_CHAIN;
1366                 } else {
1367                         /* FIXME - add check for ZERO_PACKET flag before this */
1368                         td->last_trb = ep_ring->enqueue;
1369                         field |= TRB_IOC;
1370                 }
1371                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
1372                                 "64KB boundary at %#x, end dma = %#x\n",
1373                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
1374                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1375                                 (unsigned int) addr + trb_buff_len);
1376                 if (TRB_MAX_BUFF_SIZE -
1377                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
1378                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1379                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
1380                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1381                                         (unsigned int) addr + trb_buff_len);
1382                 }
1383                 length_field = TRB_LEN(trb_buff_len) |
1384                         TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1385                         TRB_INTR_TARGET(0);
1386                 queue_trb(xhci, ep_ring, false,
1387                                 lower_32_bits(addr),
1388                                 upper_32_bits(addr),
1389                                 length_field,
1390                                 /* We always want to know if the TRB was short,
1391                                  * or we won't get an event when it completes.
1392                                  * (Unless we use event data TRBs, which are a
1393                                  * waste of space and HC resources.)
1394                                  */
1395                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1396                 --num_trbs;
1397                 running_total += trb_buff_len;
1398
1399                 /* Calculate length for next transfer --
1400                  * Are we done queueing all the TRBs for this sg entry?
1401                  */
1402                 this_sg_len -= trb_buff_len;
1403                 if (this_sg_len == 0) {
1404                         --num_sgs;
1405                         if (num_sgs == 0)
1406                                 break;
1407                         sg = sg_next(sg);
1408                         addr = (u64) sg_dma_address(sg);
1409                         this_sg_len = sg_dma_len(sg);
1410                 } else {
1411                         addr += trb_buff_len;
1412                 }
1413
1414                 trb_buff_len = TRB_MAX_BUFF_SIZE -
1415                         (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1416                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1417                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
1418                         trb_buff_len =
1419                                 urb->transfer_buffer_length - running_total;
1420         } while (running_total < urb->transfer_buffer_length);
1421
1422         check_trb_math(urb, num_trbs, running_total);
1423         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1424         return 0;
1425 }
1426
1427 /* This is very similar to what ehci-q.c qtd_fill() does */
1428 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1429                 struct urb *urb, int slot_id, unsigned int ep_index)
1430 {
1431         struct xhci_ring *ep_ring;
1432         struct xhci_td *td;
1433         int num_trbs;
1434         struct xhci_generic_trb *start_trb;
1435         bool first_trb;
1436         int start_cycle;
1437         u32 field, length_field;
1438
1439         int running_total, trb_buff_len, ret;
1440         u64 addr;
1441
1442         if (urb->sg)
1443                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
1444
1445         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1446
1447         num_trbs = 0;
1448         /* How much data is (potentially) left before the 64KB boundary? */
1449         running_total = TRB_MAX_BUFF_SIZE -
1450                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1451
1452         /* If there's some data on this 64KB chunk, or we have to send a
1453          * zero-length transfer, we need at least one TRB
1454          */
1455         if (running_total != 0 || urb->transfer_buffer_length == 0)
1456                 num_trbs++;
1457         /* How many more 64KB chunks to transfer, how many more TRBs? */
1458         while (running_total < urb->transfer_buffer_length) {
1459                 num_trbs++;
1460                 running_total += TRB_MAX_BUFF_SIZE;
1461         }
1462         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1463
1464         if (!in_interrupt())
1465                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1466                                 urb->ep->desc.bEndpointAddress,
1467                                 urb->transfer_buffer_length,
1468                                 urb->transfer_buffer_length,
1469                                 (unsigned long long)urb->transfer_dma,
1470                                 num_trbs);
1471
1472         ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
1473                         num_trbs, urb, &td, mem_flags);
1474         if (ret < 0)
1475                 return ret;
1476
1477         /*
1478          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1479          * until we've finished creating all the other TRBs.  The ring's cycle
1480          * state may change as we enqueue the other TRBs, so save it too.
1481          */
1482         start_trb = &ep_ring->enqueue->generic;
1483         start_cycle = ep_ring->cycle_state;
1484
1485         running_total = 0;
1486         /* How much data is in the first TRB? */
1487         addr = (u64) urb->transfer_dma;
1488         trb_buff_len = TRB_MAX_BUFF_SIZE -
1489                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1490         if (urb->transfer_buffer_length < trb_buff_len)
1491                 trb_buff_len = urb->transfer_buffer_length;
1492
1493         first_trb = true;
1494
1495         /* Queue the first TRB, even if it's zero-length */
1496         do {
1497                 field = 0;
1498
1499                 /* Don't change the cycle bit of the first TRB until later */
1500                 if (first_trb)
1501                         first_trb = false;
1502                 else
1503                         field |= ep_ring->cycle_state;
1504
1505                 /* Chain all the TRBs together; clear the chain bit in the last
1506                  * TRB to indicate it's the last TRB in the chain.
1507                  */
1508                 if (num_trbs > 1) {
1509                         field |= TRB_CHAIN;
1510                 } else {
1511                         /* FIXME - add check for ZERO_PACKET flag before this */
1512                         td->last_trb = ep_ring->enqueue;
1513                         field |= TRB_IOC;
1514                 }
1515                 length_field = TRB_LEN(trb_buff_len) |
1516                         TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1517                         TRB_INTR_TARGET(0);
1518                 queue_trb(xhci, ep_ring, false,
1519                                 lower_32_bits(addr),
1520                                 upper_32_bits(addr),
1521                                 length_field,
1522                                 /* We always want to know if the TRB was short,
1523                                  * or we won't get an event when it completes.
1524                                  * (Unless we use event data TRBs, which are a
1525                                  * waste of space and HC resources.)
1526                                  */
1527                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1528                 --num_trbs;
1529                 running_total += trb_buff_len;
1530
1531                 /* Calculate length for next transfer */
1532                 addr += trb_buff_len;
1533                 trb_buff_len = urb->transfer_buffer_length - running_total;
1534                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
1535                         trb_buff_len = TRB_MAX_BUFF_SIZE;
1536         } while (running_total < urb->transfer_buffer_length);
1537
1538         check_trb_math(urb, num_trbs, running_total);
1539         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1540         return 0;
1541 }
1542
1543 /* Caller must have locked xhci->lock */
1544 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1545                 struct urb *urb, int slot_id, unsigned int ep_index)
1546 {
1547         struct xhci_ring *ep_ring;
1548         int num_trbs;
1549         int ret;
1550         struct usb_ctrlrequest *setup;
1551         struct xhci_generic_trb *start_trb;
1552         int start_cycle;
1553         u32 field, length_field;
1554         struct xhci_td *td;
1555
1556         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1557
1558         /*
1559          * Need to copy setup packet into setup TRB, so we can't use the setup
1560          * DMA address.
1561          */
1562         if (!urb->setup_packet)
1563                 return -EINVAL;
1564
1565         if (!in_interrupt())
1566                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
1567                                 slot_id, ep_index);
1568         /* 1 TRB for setup, 1 for status */
1569         num_trbs = 2;
1570         /*
1571          * Don't need to check if we need additional event data and normal TRBs,
1572          * since data in control transfers will never get bigger than 16MB
1573          * XXX: can we get a buffer that crosses 64KB boundaries?
1574          */
1575         if (urb->transfer_buffer_length > 0)
1576                 num_trbs++;
1577         ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs,
1578                         urb, &td, mem_flags);
1579         if (ret < 0)
1580                 return ret;
1581
1582         /*
1583          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1584          * until we've finished creating all the other TRBs.  The ring's cycle
1585          * state may change as we enqueue the other TRBs, so save it too.
1586          */
1587         start_trb = &ep_ring->enqueue->generic;
1588         start_cycle = ep_ring->cycle_state;
1589
1590         /* Queue setup TRB - see section 6.4.1.2.1 */
1591         /* FIXME better way to translate setup_packet into two u32 fields? */
1592         setup = (struct usb_ctrlrequest *) urb->setup_packet;
1593         queue_trb(xhci, ep_ring, false,
1594                         /* FIXME endianness is probably going to bite my ass here. */
1595                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
1596                         setup->wIndex | setup->wLength << 16,
1597                         TRB_LEN(8) | TRB_INTR_TARGET(0),
1598                         /* Immediate data in pointer */
1599                         TRB_IDT | TRB_TYPE(TRB_SETUP));
1600
1601         /* If there's data, queue data TRBs */
1602         field = 0;
1603         length_field = TRB_LEN(urb->transfer_buffer_length) |
1604                 TD_REMAINDER(urb->transfer_buffer_length) |
1605                 TRB_INTR_TARGET(0);
1606         if (urb->transfer_buffer_length > 0) {
1607                 if (setup->bRequestType & USB_DIR_IN)
1608                         field |= TRB_DIR_IN;
1609                 queue_trb(xhci, ep_ring, false,
1610                                 lower_32_bits(urb->transfer_dma),
1611                                 upper_32_bits(urb->transfer_dma),
1612                                 length_field,
1613                                 /* Event on short tx */
1614                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
1615         }
1616
1617         /* Save the DMA address of the last TRB in the TD */
1618         td->last_trb = ep_ring->enqueue;
1619
1620         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1621         /* If the device sent data, the status stage is an OUT transfer */
1622         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
1623                 field = 0;
1624         else
1625                 field = TRB_DIR_IN;
1626         queue_trb(xhci, ep_ring, false,
1627                         0,
1628                         0,
1629                         TRB_INTR_TARGET(0),
1630                         /* Event on completion */
1631                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
1632
1633         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1634         return 0;
1635 }
1636
1637 /****           Command Ring Operations         ****/
1638
1639 /* Generic function for queueing a command TRB on the command ring */
1640 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, u32 field3, u32 field4)
1641 {
1642         if (!room_on_ring(xhci, xhci->cmd_ring, 1)) {
1643                 if (!in_interrupt())
1644                         xhci_err(xhci, "ERR: No room for command on command ring\n");
1645                 return -ENOMEM;
1646         }
1647         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
1648                         field4 | xhci->cmd_ring->cycle_state);
1649         return 0;
1650 }
1651
1652 /* Queue a no-op command on the command ring */
1653 static int queue_cmd_noop(struct xhci_hcd *xhci)
1654 {
1655         return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP));
1656 }
1657
1658 /*
1659  * Place a no-op command on the command ring to test the command and
1660  * event ring.
1661  */
1662 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
1663 {
1664         if (queue_cmd_noop(xhci) < 0)
1665                 return NULL;
1666         xhci->noops_submitted++;
1667         return xhci_ring_cmd_db;
1668 }
1669
1670 /* Queue a slot enable or disable request on the command ring */
1671 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
1672 {
1673         return queue_command(xhci, 0, 0, 0,
1674                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id));
1675 }
1676
1677 /* Queue an address device command TRB */
1678 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1679                 u32 slot_id)
1680 {
1681         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1682                         upper_32_bits(in_ctx_ptr), 0,
1683                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id));
1684 }
1685
1686 /* Queue a configure endpoint command TRB */
1687 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1688                 u32 slot_id)
1689 {
1690         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1691                         upper_32_bits(in_ctx_ptr), 0,
1692                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id));
1693 }
1694
1695 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1696                 unsigned int ep_index)
1697 {
1698         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1699         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1700         u32 type = TRB_TYPE(TRB_STOP_RING);
1701
1702         return queue_command(xhci, 0, 0, 0,
1703                         trb_slot_id | trb_ep_index | type);
1704 }
1705
1706 /* Set Transfer Ring Dequeue Pointer command.
1707  * This should not be used for endpoints that have streams enabled.
1708  */
1709 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
1710                 unsigned int ep_index, struct xhci_segment *deq_seg,
1711                 union xhci_trb *deq_ptr, u32 cycle_state)
1712 {
1713         dma_addr_t addr;
1714         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1715         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1716         u32 type = TRB_TYPE(TRB_SET_DEQ);
1717
1718         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
1719         if (addr == 0)
1720                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
1721                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
1722                                 deq_seg, deq_ptr);
1723         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
1724                         upper_32_bits(addr), 0,
1725                         trb_slot_id | trb_ep_index | type);
1726 }
1727
1728 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1729                 unsigned int ep_index)
1730 {
1731         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1732         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1733         u32 type = TRB_TYPE(TRB_RESET_EP);
1734
1735         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type);
1736 }