drivers/usb/host/xhci-dbg.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include "xhci.h"
  24
  25 #define XHCI_INIT_VALUE 0x0
  26
  27 /* Add verbose debugging later, just print everything for now */
  28
  29 void xhci_dbg_regs(struct xhci_hcd *xhci)
  30 {
  31         u32 temp;
  32
  33         xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
  34                         xhci->cap_regs);
  35         temp = readl(&xhci->cap_regs->hc_capbase);
  36         xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
  37                         &xhci->cap_regs->hc_capbase, temp);
  38         xhci_dbg(xhci, "//   CAPLENGTH: 0x%x\n",
  39                         (unsigned int) HC_LENGTH(temp));
  40 #if 0
  41         xhci_dbg(xhci, "//   HCIVERSION: 0x%x\n",
  42                         (unsigned int) HC_VERSION(temp));
  43 #endif
  44
  45         xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
  46
  47         temp = readl(&xhci->cap_regs->run_regs_off);
  48         xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
  49                         &xhci->cap_regs->run_regs_off,
  50                         (unsigned int) temp & RTSOFF_MASK);
  51         xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
  52
  53         temp = readl(&xhci->cap_regs->db_off);
  54         xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
  55         xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
  56 }
  57
  58 static void xhci_print_cap_regs(struct xhci_hcd *xhci)
  59 {
  60         u32 temp;
  61
  62         xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
  63
  64         temp = readl(&xhci->cap_regs->hc_capbase);
  65         xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
  66                         (unsigned int) temp);
  67         xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
  68                         (unsigned int) HC_LENGTH(temp));
  69         xhci_dbg(xhci, "HCIVERSION: 0x%x\n",
  70                         (unsigned int) HC_VERSION(temp));
  71
  72         temp = readl(&xhci->cap_regs->hcs_params1);
  73         xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
  74                         (unsigned int) temp);
  75         xhci_dbg(xhci, "  Max device slots: %u\n",
  76                         (unsigned int) HCS_MAX_SLOTS(temp));
  77         xhci_dbg(xhci, "  Max interrupters: %u\n",
  78                         (unsigned int) HCS_MAX_INTRS(temp));
  79         xhci_dbg(xhci, "  Max ports: %u\n",
  80                         (unsigned int) HCS_MAX_PORTS(temp));
  81
  82         temp = readl(&xhci->cap_regs->hcs_params2);
  83         xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
  84                         (unsigned int) temp);
  85         xhci_dbg(xhci, "  Isoc scheduling threshold: %u\n",
  86                         (unsigned int) HCS_IST(temp));
  87         xhci_dbg(xhci, "  Maximum allowed segments in event ring: %u\n",
  88                         (unsigned int) HCS_ERST_MAX(temp));
  89
  90         temp = readl(&xhci->cap_regs->hcs_params3);
  91         xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
  92                         (unsigned int) temp);
  93         xhci_dbg(xhci, "  Worst case U1 device exit latency: %u\n",
  94                         (unsigned int) HCS_U1_LATENCY(temp));
  95         xhci_dbg(xhci, "  Worst case U2 device exit latency: %u\n",
  96                         (unsigned int) HCS_U2_LATENCY(temp));
  97
  98         temp = readl(&xhci->cap_regs->hcc_params);
  99         xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
 100         xhci_dbg(xhci, "  HC generates %s bit addresses\n",
 101                         HCC_64BIT_ADDR(temp) ? "64" : "32");
 102         xhci_dbg(xhci, "  HC %s Contiguous Frame ID Capability\n",
 103                         HCC_CFC(temp) ? "has" : "hasn't");
 104         /* FIXME */
 105         xhci_dbg(xhci, "  FIXME: more HCCPARAMS debugging\n");
 106
 107         temp = readl(&xhci->cap_regs->run_regs_off);
 108         xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
 109 }
 110
 111 static void xhci_print_command_reg(struct xhci_hcd *xhci)
 112 {
 113         u32 temp;
 114
 115         temp = readl(&xhci->op_regs->command);
 116         xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
 117         xhci_dbg(xhci, "  HC is %s\n",
 118                         (temp & CMD_RUN) ? "running" : "being stopped");
 119         xhci_dbg(xhci, "  HC has %sfinished hard reset\n",
 120                         (temp & CMD_RESET) ? "not " : "");
 121         xhci_dbg(xhci, "  Event Interrupts %s\n",
 122                         (temp & CMD_EIE) ? "enabled " : "disabled");
 123         xhci_dbg(xhci, "  Host System Error Interrupts %s\n",
 124                         (temp & CMD_HSEIE) ? "enabled " : "disabled");
 125         xhci_dbg(xhci, "  HC has %sfinished light reset\n",
 126                         (temp & CMD_LRESET) ? "not " : "");
 127 }
 128
 129 static void xhci_print_status(struct xhci_hcd *xhci)
 130 {
 131         u32 temp;
 132
 133         temp = readl(&xhci->op_regs->status);
 134         xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
 135         xhci_dbg(xhci, "  Event ring is %sempty\n",
 136                         (temp & STS_EINT) ? "not " : "");
 137         xhci_dbg(xhci, "  %sHost System Error\n",
 138                         (temp & STS_FATAL) ? "WARNING: " : "No ");
 139         xhci_dbg(xhci, "  HC is %s\n",
 140                         (temp & STS_HALT) ? "halted" : "running");
 141 }
 142
 143 static void xhci_print_op_regs(struct xhci_hcd *xhci)
 144 {
 145         xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
 146         xhci_print_command_reg(xhci);
 147         xhci_print_status(xhci);
 148 }
 149
 150 static void xhci_print_ports(struct xhci_hcd *xhci)
 151 {
 152         __le32 __iomem *addr;
 153         int i, j;
 154         int ports;
 155         char *names[NUM_PORT_REGS] = {
 156                 "status",
 157                 "power",
 158                 "link",
 159                 "reserved",
 160         };
 161
 162         ports = HCS_MAX_PORTS(xhci->hcs_params1);
 163         addr = &xhci->op_regs->port_status_base;
 164         for (i = 0; i < ports; i++) {
 165                 for (j = 0; j < NUM_PORT_REGS; ++j) {
 166                         xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
 167                                         addr, names[j],
 168                                         (unsigned int) readl(addr));
 169                         addr++;
 170                 }
 171         }
 172 }
 173
 174 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
 175 {
 176         struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num];
 177         void __iomem *addr;
 178         u32 temp;
 179         u64 temp_64;
 180
 181         addr = &ir_set->irq_pending;
 182         temp = readl(addr);
 183         if (temp == XHCI_INIT_VALUE)
 184                 return;
 185
 186         xhci_dbg(xhci, "  %p: ir_set[%i]\n", ir_set, set_num);
 187
 188         xhci_dbg(xhci, "  %p: ir_set.pending = 0x%x\n", addr,
 189                         (unsigned int)temp);
 190
 191         addr = &ir_set->irq_control;
 192         temp = readl(addr);
 193         xhci_dbg(xhci, "  %p: ir_set.control = 0x%x\n", addr,
 194                         (unsigned int)temp);
 195
 196         addr = &ir_set->erst_size;
 197         temp = readl(addr);
 198         xhci_dbg(xhci, "  %p: ir_set.erst_size = 0x%x\n", addr,
 199                         (unsigned int)temp);
 200
 201         addr = &ir_set->rsvd;
 202         temp = readl(addr);
 203         if (temp != XHCI_INIT_VALUE)
 204                 xhci_dbg(xhci, "  WARN: %p: ir_set.rsvd = 0x%x\n",
 205                                 addr, (unsigned int)temp);
 206
 207         addr = &ir_set->erst_base;
 208         temp_64 = xhci_read_64(xhci, addr);
 209         xhci_dbg(xhci, "  %p: ir_set.erst_base = @%08llx\n",
 210                         addr, temp_64);
 211
 212         addr = &ir_set->erst_dequeue;
 213         temp_64 = xhci_read_64(xhci, addr);
 214         xhci_dbg(xhci, "  %p: ir_set.erst_dequeue = @%08llx\n",
 215                         addr, temp_64);
 216 }
 217
 218 void xhci_print_run_regs(struct xhci_hcd *xhci)
 219 {
 220         u32 temp;
 221         int i;
 222
 223         xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
 224         temp = readl(&xhci->run_regs->microframe_index);
 225         xhci_dbg(xhci, "  %p: Microframe index = 0x%x\n",
 226                         &xhci->run_regs->microframe_index,
 227                         (unsigned int) temp);
 228         for (i = 0; i < 7; ++i) {
 229                 temp = readl(&xhci->run_regs->rsvd[i]);
 230                 if (temp != XHCI_INIT_VALUE)
 231                         xhci_dbg(xhci, "  WARN: %p: Rsvd[%i] = 0x%x\n",
 232                                         &xhci->run_regs->rsvd[i],
 233                                         i, (unsigned int) temp);
 234         }
 235 }
 236
 237 void xhci_print_registers(struct xhci_hcd *xhci)
 238 {
 239         xhci_print_cap_regs(xhci);
 240         xhci_print_op_regs(xhci);
 241         xhci_print_ports(xhci);
 242 }
 243
 244 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb)
 245 {
 246         int i;
 247         for (i = 0; i < 4; ++i)
 248                 xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
 249                                 i*4, trb->generic.field[i]);
 250 }
 251
 252 /**
 253  * Debug a transfer request block (TRB).
 254  */
 255 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
 256 {
 257         u64     address;
 258         u32     type = le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK;
 259
 260         switch (type) {
 261         case TRB_TYPE(TRB_LINK):
 262                 xhci_dbg(xhci, "Link TRB:\n");
 263                 xhci_print_trb_offsets(xhci, trb);
 264
 265                 address = le64_to_cpu(trb->link.segment_ptr);
 266                 xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
 267
 268                 xhci_dbg(xhci, "Interrupter target = 0x%x\n",
 269                          GET_INTR_TARGET(le32_to_cpu(trb->link.intr_target)));
 270                 xhci_dbg(xhci, "Cycle bit = %u\n",
 271                          le32_to_cpu(trb->link.control) & TRB_CYCLE);
 272                 xhci_dbg(xhci, "Toggle cycle bit = %u\n",
 273                          le32_to_cpu(trb->link.control) & LINK_TOGGLE);
 274                 xhci_dbg(xhci, "No Snoop bit = %u\n",
 275                          le32_to_cpu(trb->link.control) & TRB_NO_SNOOP);
 276                 break;
 277         case TRB_TYPE(TRB_TRANSFER):
 278                 address = le64_to_cpu(trb->trans_event.buffer);
 279                 /*
 280                  * FIXME: look at flags to figure out if it's an address or if
 281                  * the data is directly in the buffer field.
 282                  */
 283                 xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
 284                 break;
 285         case TRB_TYPE(TRB_COMPLETION):
 286                 address = le64_to_cpu(trb->event_cmd.cmd_trb);
 287                 xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
 288                 xhci_dbg(xhci, "Completion status = %u\n",
 289                          GET_COMP_CODE(le32_to_cpu(trb->event_cmd.status)));
 290                 xhci_dbg(xhci, "Flags = 0x%x\n",
 291                          le32_to_cpu(trb->event_cmd.flags));
 292                 break;
 293         default:
 294                 xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
 295                                 (unsigned int) type>>10);
 296                 xhci_print_trb_offsets(xhci, trb);
 297                 break;
 298         }
 299 }
 300
 301 /**
 302  * Debug a segment with an xHCI ring.
 303  *
 304  * @return The Link TRB of the segment, or NULL if there is no Link TRB
 305  * (which is a bug, since all segments must have a Link TRB).
 306  *
 307  * Prints out all TRBs in the segment, even those after the Link TRB.
 308  *
 309  * XXX: should we print out TRBs that the HC owns?  As long as we don't
 310  * write, that should be fine...  We shouldn't expect that the memory pointed to
 311  * by the TRB is valid at all.  Do we care about ones the HC owns?  Probably,
 312  * for HC debugging.
 313  */
 314 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
 315 {
 316         int i;
 317         u64 addr = seg->dma;
 318         union xhci_trb *trb = seg->trbs;
 319
 320         for (i = 0; i < TRBS_PER_SEGMENT; ++i) {
 321                 trb = &seg->trbs[i];
 322                 xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", addr,
 323                          lower_32_bits(le64_to_cpu(trb->link.segment_ptr)),
 324                          upper_32_bits(le64_to_cpu(trb->link.segment_ptr)),
 325                          le32_to_cpu(trb->link.intr_target),
 326                          le32_to_cpu(trb->link.control));
 327                 addr += sizeof(*trb);
 328         }
 329 }
 330
 331 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring)
 332 {
 333         xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",
 334                         ring->dequeue,
 335                         (unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg,
 336                                                             ring->dequeue));
 337         xhci_dbg(xhci, "Ring deq updated %u times\n",
 338                         ring->deq_updates);
 339         xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",
 340                         ring->enqueue,
 341                         (unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg,
 342                                                             ring->enqueue));
 343         xhci_dbg(xhci, "Ring enq updated %u times\n",
 344                         ring->enq_updates);
 345 }
 346
 347 /**
 348  * Debugging for an xHCI ring, which is a queue broken into multiple segments.
 349  *
 350  * Print out each segment in the ring.  Check that the DMA address in
 351  * each link segment actually matches the segment's stored DMA address.
 352  * Check that the link end bit is only set at the end of the ring.
 353  * Check that the dequeue and enqueue pointers point to real data in this ring
 354  * (not some other ring).
 355  */
 356 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring)
 357 {
 358         /* FIXME: Throw an error if any segment doesn't have a Link TRB */
 359         struct xhci_segment *seg;
 360         struct xhci_segment *first_seg = ring->first_seg;
 361         xhci_debug_segment(xhci, first_seg);
 362
 363         if (!ring->enq_updates && !ring->deq_updates) {
 364                 xhci_dbg(xhci, "  Ring has not been updated\n");
 365                 return;
 366         }
 367         for (seg = first_seg->next; seg != first_seg; seg = seg->next)
 368                 xhci_debug_segment(xhci, seg);
 369 }
 370
 371 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
 372                 unsigned int slot_id, unsigned int ep_index,
 373                 struct xhci_virt_ep *ep)
 374 {
 375         int i;
 376         struct xhci_ring *ring;
 377
 378         if (ep->ep_state & EP_HAS_STREAMS) {
 379                 for (i = 1; i < ep->stream_info->num_streams; i++) {
 380                         ring = ep->stream_info->stream_rings[i];
 381                         xhci_dbg(xhci, "Dev %d endpoint %d stream ID %d:\n",
 382                                 slot_id, ep_index, i);
 383                         xhci_debug_segment(xhci, ring->deq_seg);
 384                 }
 385         } else {
 386                 ring = ep->ring;
 387                 if (!ring)
 388                         return;
 389                 xhci_dbg(xhci, "Dev %d endpoint ring %d:\n",
 390                                 slot_id, ep_index);
 391                 xhci_debug_segment(xhci, ring->deq_seg);
 392         }
 393 }
 394
 395 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
 396 {
 397         u64 addr = erst->erst_dma_addr;
 398         int i;
 399         struct xhci_erst_entry *entry;
 400
 401         for (i = 0; i < erst->num_entries; ++i) {
 402                 entry = &erst->entries[i];
 403                 xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n",
 404                          addr,
 405                          lower_32_bits(le64_to_cpu(entry->seg_addr)),
 406                          upper_32_bits(le64_to_cpu(entry->seg_addr)),
 407                          le32_to_cpu(entry->seg_size),
 408                          le32_to_cpu(entry->rsvd));
 409                 addr += sizeof(*entry);
 410         }
 411 }
 412
 413 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
 414 {
 415         u64 val;
 416
 417         val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 418         xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
 419                         lower_32_bits(val));
 420         xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
 421                         upper_32_bits(val));
 422 }
 423
 424 /* Print the last 32 bytes for 64-byte contexts */
 425 static void dbg_rsvd64(struct xhci_hcd *xhci, u64 *ctx, dma_addr_t dma)
 426 {
 427         int i;
 428         for (i = 0; i < 4; ++i) {
 429                 xhci_dbg(xhci, "@%p (virt) @%08llx "
 430                          "(dma) %#08llx - rsvd64[%d]\n",
 431                          &ctx[4 + i], (unsigned long long)dma,
 432                          ctx[4 + i], i);
 433                 dma += 8;
 434         }
 435 }
 436
 437 char *xhci_get_slot_state(struct xhci_hcd *xhci,
 438                 struct xhci_container_ctx *ctx)
 439 {
 440         struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
 441
 442         switch (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state))) {
 443         case SLOT_STATE_ENABLED:
 444                 return "enabled/disabled";
 445         case SLOT_STATE_DEFAULT:
 446                 return "default";
 447         case SLOT_STATE_ADDRESSED:
 448                 return "addressed";
 449         case SLOT_STATE_CONFIGURED:
 450                 return "configured";
 451         default:
 452                 return "reserved";
 453         }
 454 }
 455
 456 static void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
 457 {
 458         /* Fields are 32 bits wide, DMA addresses are in bytes */
 459         int field_size = 32 / 8;
 460         int i;
 461
 462         struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
 463         dma_addr_t dma = ctx->dma +
 464                 ((unsigned long)slot_ctx - (unsigned long)ctx->bytes);
 465         int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
 466
 467         xhci_dbg(xhci, "Slot Context:\n");
 468         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",
 469                         &slot_ctx->dev_info,
 470                         (unsigned long long)dma, slot_ctx->dev_info);
 471         dma += field_size;
 472         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",
 473                         &slot_ctx->dev_info2,
 474                         (unsigned long long)dma, slot_ctx->dev_info2);
 475         dma += field_size;
 476         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",
 477                         &slot_ctx->tt_info,
 478                         (unsigned long long)dma, slot_ctx->tt_info);
 479         dma += field_size;
 480         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",
 481                         &slot_ctx->dev_state,
 482                         (unsigned long long)dma, slot_ctx->dev_state);
 483         dma += field_size;
 484         for (i = 0; i < 4; ++i) {
 485                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
 486                                 &slot_ctx->reserved[i], (unsigned long long)dma,
 487                                 slot_ctx->reserved[i], i);
 488                 dma += field_size;
 489         }
 490
 491         if (csz)
 492                 dbg_rsvd64(xhci, (u64 *)slot_ctx, dma);
 493 }
 494
 495 static void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
 496                      struct xhci_container_ctx *ctx,
 497                      unsigned int last_ep)
 498 {
 499         int i, j;
 500         int last_ep_ctx = 31;
 501         /* Fields are 32 bits wide, DMA addresses are in bytes */
 502         int field_size = 32 / 8;
 503         int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
 504
 505         if (last_ep < 31)
 506                 last_ep_ctx = last_ep + 1;
 507         for (i = 0; i < last_ep_ctx; ++i) {
 508                 unsigned int epaddr = xhci_get_endpoint_address(i);
 509                 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i);
 510                 dma_addr_t dma = ctx->dma +
 511                         ((unsigned long)ep_ctx - (unsigned long)ctx->bytes);
 512
 513                 xhci_dbg(xhci, "%s Endpoint %02d Context (ep_index %02d):\n",
 514                                 usb_endpoint_out(epaddr) ? "OUT" : "IN",
 515                                 epaddr & USB_ENDPOINT_NUMBER_MASK, i);
 516                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
 517                                 &ep_ctx->ep_info,
 518                                 (unsigned long long)dma, ep_ctx->ep_info);
 519                 dma += field_size;
 520                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",
 521                                 &ep_ctx->ep_info2,
 522                                 (unsigned long long)dma, ep_ctx->ep_info2);
 523                 dma += field_size;
 524                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n",
 525                                 &ep_ctx->deq,
 526                                 (unsigned long long)dma, ep_ctx->deq);
 527                 dma += 2*field_size;
 528                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",
 529                                 &ep_ctx->tx_info,
 530                                 (unsigned long long)dma, ep_ctx->tx_info);
 531                 dma += field_size;
 532                 for (j = 0; j < 3; ++j) {
 533                         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
 534                                         &ep_ctx->reserved[j],
 535                                         (unsigned long long)dma,
 536                                         ep_ctx->reserved[j], j);
 537                         dma += field_size;
 538                 }
 539
 540                 if (csz)
 541                         dbg_rsvd64(xhci, (u64 *)ep_ctx, dma);
 542         }
 543 }
 544
 545 void xhci_dbg_ctx(struct xhci_hcd *xhci,
 546                   struct xhci_container_ctx *ctx,
 547                   unsigned int last_ep)
 548 {
 549         int i;
 550         /* Fields are 32 bits wide, DMA addresses are in bytes */
 551         int field_size = 32 / 8;
 552         dma_addr_t dma = ctx->dma;
 553         int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
 554
 555         if (ctx->type == XHCI_CTX_TYPE_INPUT) {
 556                 struct xhci_input_control_ctx *ctrl_ctx =
 557                         xhci_get_input_control_ctx(ctx);
 558                 if (!ctrl_ctx) {
 559                         xhci_warn(xhci, "Could not get input context, bad type.\n");
 560                         return;
 561                 }
 562
 563                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",
 564                          &ctrl_ctx->drop_flags, (unsigned long long)dma,
 565                          ctrl_ctx->drop_flags);
 566                 dma += field_size;
 567                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",
 568                          &ctrl_ctx->add_flags, (unsigned long long)dma,
 569                          ctrl_ctx->add_flags);
 570                 dma += field_size;
 571                 for (i = 0; i < 6; ++i) {
 572                         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",
 573                                  &ctrl_ctx->rsvd2[i], (unsigned long long)dma,
 574                                  ctrl_ctx->rsvd2[i], i);
 575                         dma += field_size;
 576                 }
 577
 578                 if (csz)
 579                         dbg_rsvd64(xhci, (u64 *)ctrl_ctx, dma);
 580         }
 581
 582         xhci_dbg_slot_ctx(xhci, ctx);
 583         xhci_dbg_ep_ctx(xhci, ctx, last_ep);
 584 }
 585
 586 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
 587                         const char *fmt, ...)
 588 {
 589         struct va_format vaf;
 590         va_list args;
 591
 592         va_start(args, fmt);
 593         vaf.fmt = fmt;
 594         vaf.va = &args;
 595         xhci_dbg(xhci, "%pV\n", &vaf);
 596         trace(&vaf);
 597         va_end(args);
 598 }
 599 EXPORT_SYMBOL_GPL(xhci_dbg_trace);