drivers/usb/host/xhci-dbg.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include "xhci.h"
  24
  25 #define XHCI_INIT_VALUE 0x0
  26
  27 /* Add verbose debugging later, just print everything for now */
  28
  29 void xhci_dbg_regs(struct xhci_hcd *xhci)
  30 {
  31         u32 temp;
  32
  33         xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
  34                         xhci->cap_regs);
  35         temp = readl(&xhci->cap_regs->hc_capbase);
  36         xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
  37                         &xhci->cap_regs->hc_capbase, temp);
  38         xhci_dbg(xhci, "//   CAPLENGTH: 0x%x\n",
  39                         (unsigned int) HC_LENGTH(temp));
  40 #if 0
  41         xhci_dbg(xhci, "//   HCIVERSION: 0x%x\n",
  42                         (unsigned int) HC_VERSION(temp));
  43 #endif
  44
  45         xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
  46
  47         temp = readl(&xhci->cap_regs->run_regs_off);
  48         xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
  49                         &xhci->cap_regs->run_regs_off,
  50                         (unsigned int) temp & RTSOFF_MASK);
  51         xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
  52
  53         temp = readl(&xhci->cap_regs->db_off);
  54         xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
  55         xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
  56 }
  57
  58 static void xhci_print_cap_regs(struct xhci_hcd *xhci)
  59 {
  60         u32 temp;
  61
  62         xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
  63
  64         temp = readl(&xhci->cap_regs->hc_capbase);
  65         xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
  66                         (unsigned int) temp);
  67         xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
  68                         (unsigned int) HC_LENGTH(temp));
  69         xhci_dbg(xhci, "HCIVERSION: 0x%x\n",
  70                         (unsigned int) HC_VERSION(temp));
  71
  72         temp = readl(&xhci->cap_regs->hcs_params1);
  73         xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
  74                         (unsigned int) temp);
  75         xhci_dbg(xhci, "  Max device slots: %u\n",
  76                         (unsigned int) HCS_MAX_SLOTS(temp));
  77         xhci_dbg(xhci, "  Max interrupters: %u\n",
  78                         (unsigned int) HCS_MAX_INTRS(temp));
  79         xhci_dbg(xhci, "  Max ports: %u\n",
  80                         (unsigned int) HCS_MAX_PORTS(temp));
  81
  82         temp = readl(&xhci->cap_regs->hcs_params2);
  83         xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
  84                         (unsigned int) temp);
  85         xhci_dbg(xhci, "  Isoc scheduling threshold: %u\n",
  86                         (unsigned int) HCS_IST(temp));
  87         xhci_dbg(xhci, "  Maximum allowed segments in event ring: %u\n",
  88                         (unsigned int) HCS_ERST_MAX(temp));
  89
  90         temp = readl(&xhci->cap_regs->hcs_params3);
  91         xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
  92                         (unsigned int) temp);
  93         xhci_dbg(xhci, "  Worst case U1 device exit latency: %u\n",
  94                         (unsigned int) HCS_U1_LATENCY(temp));
  95         xhci_dbg(xhci, "  Worst case U2 device exit latency: %u\n",
  96                         (unsigned int) HCS_U2_LATENCY(temp));
  97
  98         temp = readl(&xhci->cap_regs->hcc_params);
  99         xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
 100         xhci_dbg(xhci, "  HC generates %s bit addresses\n",
 101                         HCC_64BIT_ADDR(temp) ? "64" : "32");
 102         xhci_dbg(xhci, "  HC %s Contiguous Frame ID Capability\n",
 103                         HCC_CFC(temp) ? "has" : "hasn't");
 104         xhci_dbg(xhci, "  HC %s generate Stopped - Short Package event\n",
 105                         HCC_SPC(temp) ? "can" : "can't");
 106         /* FIXME */
 107         xhci_dbg(xhci, "  FIXME: more HCCPARAMS debugging\n");
 108
 109         temp = readl(&xhci->cap_regs->run_regs_off);
 110         xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
 111 }
 112
 113 static void xhci_print_command_reg(struct xhci_hcd *xhci)
 114 {
 115         u32 temp;
 116
 117         temp = readl(&xhci->op_regs->command);
 118         xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
 119         xhci_dbg(xhci, "  HC is %s\n",
 120                         (temp & CMD_RUN) ? "running" : "being stopped");
 121         xhci_dbg(xhci, "  HC has %sfinished hard reset\n",
 122                         (temp & CMD_RESET) ? "not " : "");
 123         xhci_dbg(xhci, "  Event Interrupts %s\n",
 124                         (temp & CMD_EIE) ? "enabled " : "disabled");
 125         xhci_dbg(xhci, "  Host System Error Interrupts %s\n",
 126                         (temp & CMD_HSEIE) ? "enabled " : "disabled");
 127         xhci_dbg(xhci, "  HC has %sfinished light reset\n",
 128                         (temp & CMD_LRESET) ? "not " : "");
 129 }
 130
 131 static void xhci_print_status(struct xhci_hcd *xhci)
 132 {
 133         u32 temp;
 134
 135         temp = readl(&xhci->op_regs->status);
 136         xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
 137         xhci_dbg(xhci, "  Event ring is %sempty\n",
 138                         (temp & STS_EINT) ? "not " : "");
 139         xhci_dbg(xhci, "  %sHost System Error\n",
 140                         (temp & STS_FATAL) ? "WARNING: " : "No ");
 141         xhci_dbg(xhci, "  HC is %s\n",
 142                         (temp & STS_HALT) ? "halted" : "running");
 143 }
 144
 145 static void xhci_print_op_regs(struct xhci_hcd *xhci)
 146 {
 147         xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
 148         xhci_print_command_reg(xhci);
 149         xhci_print_status(xhci);
 150 }
 151
 152 static void xhci_print_ports(struct xhci_hcd *xhci)
 153 {
 154         __le32 __iomem *addr;
 155         int i, j;
 156         int ports;
 157         char *names[NUM_PORT_REGS] = {
 158                 "status",
 159                 "power",
 160                 "link",
 161                 "reserved",
 162         };
 163
 164         ports = HCS_MAX_PORTS(xhci->hcs_params1);
 165         addr = &xhci->op_regs->port_status_base;
 166         for (i = 0; i < ports; i++) {
 167                 for (j = 0; j < NUM_PORT_REGS; ++j) {
 168                         xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
 169                                         addr, names[j],
 170                                         (unsigned int) readl(addr));
 171                         addr++;
 172                 }
 173         }
 174 }
 175
 176 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
 177 {
 178         struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num];
 179         void __iomem *addr;
 180         u32 temp;
 181         u64 temp_64;
 182
 183         addr = &ir_set->irq_pending;
 184         temp = readl(addr);
 185         if (temp == XHCI_INIT_VALUE)
 186                 return;
 187
 188         xhci_dbg(xhci, "  %p: ir_set[%i]\n", ir_set, set_num);
 189
 190         xhci_dbg(xhci, "  %p: ir_set.pending = 0x%x\n", addr,
 191                         (unsigned int)temp);
 192
 193         addr = &ir_set->irq_control;
 194         temp = readl(addr);
 195         xhci_dbg(xhci, "  %p: ir_set.control = 0x%x\n", addr,
 196                         (unsigned int)temp);
 197
 198         addr = &ir_set->erst_size;
 199         temp = readl(addr);
 200         xhci_dbg(xhci, "  %p: ir_set.erst_size = 0x%x\n", addr,
 201                         (unsigned int)temp);
 202
 203         addr = &ir_set->rsvd;
 204         temp = readl(addr);
 205         if (temp != XHCI_INIT_VALUE)
 206                 xhci_dbg(xhci, "  WARN: %p: ir_set.rsvd = 0x%x\n",
 207                                 addr, (unsigned int)temp);
 208
 209         addr = &ir_set->erst_base;
 210         temp_64 = xhci_read_64(xhci, addr);
 211         xhci_dbg(xhci, "  %p: ir_set.erst_base = @%08llx\n",
 212                         addr, temp_64);
 213
 214         addr = &ir_set->erst_dequeue;
 215         temp_64 = xhci_read_64(xhci, addr);
 216         xhci_dbg(xhci, "  %p: ir_set.erst_dequeue = @%08llx\n",
 217                         addr, temp_64);
 218 }
 219
 220 void xhci_print_run_regs(struct xhci_hcd *xhci)
 221 {
 222         u32 temp;
 223         int i;
 224
 225         xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
 226         temp = readl(&xhci->run_regs->microframe_index);
 227         xhci_dbg(xhci, "  %p: Microframe index = 0x%x\n",
 228                         &xhci->run_regs->microframe_index,
 229                         (unsigned int) temp);
 230         for (i = 0; i < 7; ++i) {
 231                 temp = readl(&xhci->run_regs->rsvd[i]);
 232                 if (temp != XHCI_INIT_VALUE)
 233                         xhci_dbg(xhci, "  WARN: %p: Rsvd[%i] = 0x%x\n",
 234                                         &xhci->run_regs->rsvd[i],
 235                                         i, (unsigned int) temp);
 236         }
 237 }
 238
 239 void xhci_print_registers(struct xhci_hcd *xhci)
 240 {
 241         xhci_print_cap_regs(xhci);
 242         xhci_print_op_regs(xhci);
 243         xhci_print_ports(xhci);
 244 }
 245
 246 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb)
 247 {
 248         int i;
 249         for (i = 0; i < 4; ++i)
 250                 xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
 251                                 i*4, trb->generic.field[i]);
 252 }
 253
 254 /**
 255  * Debug a transfer request block (TRB).
 256  */
 257 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
 258 {
 259         u64     address;
 260         u32     type = le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK;
 261
 262         switch (type) {
 263         case TRB_TYPE(TRB_LINK):
 264                 xhci_dbg(xhci, "Link TRB:\n");
 265                 xhci_print_trb_offsets(xhci, trb);
 266
 267                 address = le64_to_cpu(trb->link.segment_ptr);
 268                 xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
 269
 270                 xhci_dbg(xhci, "Interrupter target = 0x%x\n",
 271                          GET_INTR_TARGET(le32_to_cpu(trb->link.intr_target)));
 272                 xhci_dbg(xhci, "Cycle bit = %u\n",
 273                          le32_to_cpu(trb->link.control) & TRB_CYCLE);
 274                 xhci_dbg(xhci, "Toggle cycle bit = %u\n",
 275                          le32_to_cpu(trb->link.control) & LINK_TOGGLE);
 276                 xhci_dbg(xhci, "No Snoop bit = %u\n",
 277                          le32_to_cpu(trb->link.control) & TRB_NO_SNOOP);
 278                 break;
 279         case TRB_TYPE(TRB_TRANSFER):
 280                 address = le64_to_cpu(trb->trans_event.buffer);
 281                 /*
 282                  * FIXME: look at flags to figure out if it's an address or if
 283                  * the data is directly in the buffer field.
 284                  */
 285                 xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
 286                 break;
 287         case TRB_TYPE(TRB_COMPLETION):
 288                 address = le64_to_cpu(trb->event_cmd.cmd_trb);
 289                 xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
 290                 xhci_dbg(xhci, "Completion status = %u\n",
 291                          GET_COMP_CODE(le32_to_cpu(trb->event_cmd.status)));
 292                 xhci_dbg(xhci, "Flags = 0x%x\n",
 293                          le32_to_cpu(trb->event_cmd.flags));
 294                 break;
 295         default:
 296                 xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
 297                                 (unsigned int) type>>10);
 298                 xhci_print_trb_offsets(xhci, trb);
 299                 break;
 300         }
 301 }
 302
 303 /**
 304  * Debug a segment with an xHCI ring.
 305  *
 306  * @return The Link TRB of the segment, or NULL if there is no Link TRB
 307  * (which is a bug, since all segments must have a Link TRB).
 308  *
 309  * Prints out all TRBs in the segment, even those after the Link TRB.
 310  *
 311  * XXX: should we print out TRBs that the HC owns?  As long as we don't
 312  * write, that should be fine...  We shouldn't expect that the memory pointed to
 313  * by the TRB is valid at all.  Do we care about ones the HC owns?  Probably,
 314  * for HC debugging.
 315  */
 316 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
 317 {
 318         int i;
 319         u64 addr = seg->dma;
 320         union xhci_trb *trb = seg->trbs;
 321
 322         for (i = 0; i < TRBS_PER_SEGMENT; ++i) {
 323                 trb = &seg->trbs[i];
 324                 xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", addr,
 325                          lower_32_bits(le64_to_cpu(trb->link.segment_ptr)),
 326                          upper_32_bits(le64_to_cpu(trb->link.segment_ptr)),
 327                          le32_to_cpu(trb->link.intr_target),
 328                          le32_to_cpu(trb->link.control));
 329                 addr += sizeof(*trb);
 330         }
 331 }
 332
 333 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring)
 334 {
 335         xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",
 336                         ring->dequeue,
 337                         (unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg,
 338                                                             ring->dequeue));
 339         xhci_dbg(xhci, "Ring deq updated %u times\n",
 340                         ring->deq_updates);
 341         xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",
 342                         ring->enqueue,
 343                         (unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg,
 344                                                             ring->enqueue));
 345         xhci_dbg(xhci, "Ring enq updated %u times\n",
 346                         ring->enq_updates);
 347 }
 348
 349 /**
 350  * Debugging for an xHCI ring, which is a queue broken into multiple segments.
 351  *
 352  * Print out each segment in the ring.  Check that the DMA address in
 353  * each link segment actually matches the segment's stored DMA address.
 354  * Check that the link end bit is only set at the end of the ring.
 355  * Check that the dequeue and enqueue pointers point to real data in this ring
 356  * (not some other ring).
 357  */
 358 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring)
 359 {
 360         /* FIXME: Throw an error if any segment doesn't have a Link TRB */
 361         struct xhci_segment *seg;
 362         struct xhci_segment *first_seg = ring->first_seg;
 363         xhci_debug_segment(xhci, first_seg);
 364
 365         if (!ring->enq_updates && !ring->deq_updates) {
 366                 xhci_dbg(xhci, "  Ring has not been updated\n");
 367                 return;
 368         }
 369         for (seg = first_seg->next; seg != first_seg; seg = seg->next)
 370                 xhci_debug_segment(xhci, seg);
 371 }
 372
 373 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
 374                 unsigned int slot_id, unsigned int ep_index,
 375                 struct xhci_virt_ep *ep)
 376 {
 377         int i;
 378         struct xhci_ring *ring;
 379
 380         if (ep->ep_state & EP_HAS_STREAMS) {
 381                 for (i = 1; i < ep->stream_info->num_streams; i++) {
 382                         ring = ep->stream_info->stream_rings[i];
 383                         xhci_dbg(xhci, "Dev %d endpoint %d stream ID %d:\n",
 384                                 slot_id, ep_index, i);
 385                         xhci_debug_segment(xhci, ring->deq_seg);
 386                 }
 387         } else {
 388                 ring = ep->ring;
 389                 if (!ring)
 390                         return;
 391                 xhci_dbg(xhci, "Dev %d endpoint ring %d:\n",
 392                                 slot_id, ep_index);
 393                 xhci_debug_segment(xhci, ring->deq_seg);
 394         }
 395 }
 396
 397 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
 398 {
 399         u64 addr = erst->erst_dma_addr;
 400         int i;
 401         struct xhci_erst_entry *entry;
 402
 403         for (i = 0; i < erst->num_entries; ++i) {
 404                 entry = &erst->entries[i];
 405                 xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n",
 406                          addr,
 407                          lower_32_bits(le64_to_cpu(entry->seg_addr)),
 408                          upper_32_bits(le64_to_cpu(entry->seg_addr)),
 409                          le32_to_cpu(entry->seg_size),
 410                          le32_to_cpu(entry->rsvd));
 411                 addr += sizeof(*entry);
 412         }
 413 }
 414
 415 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
 416 {
 417         u64 val;
 418
 419         val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 420         xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
 421                         lower_32_bits(val));
 422         xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
 423                         upper_32_bits(val));
 424 }
 425
 426 /* Print the last 32 bytes for 64-byte contexts */
 427 static void dbg_rsvd64(struct xhci_hcd *xhci, u64 *ctx, dma_addr_t dma)
 428 {
 429         int i;
 430         for (i = 0; i < 4; ++i) {
 431                 xhci_dbg(xhci, "@%p (virt) @%08llx "
 432                          "(dma) %#08llx - rsvd64[%d]\n",
 433                          &ctx[4 + i], (unsigned long long)dma,
 434                          ctx[4 + i], i);
 435                 dma += 8;
 436         }
 437 }
 438
 439 char *xhci_get_slot_state(struct xhci_hcd *xhci,
 440                 struct xhci_container_ctx *ctx)
 441 {
 442         struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
 443
 444         switch (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state))) {
 445         case SLOT_STATE_ENABLED:
 446                 return "enabled/disabled";
 447         case SLOT_STATE_DEFAULT:
 448                 return "default";
 449         case SLOT_STATE_ADDRESSED:
 450                 return "addressed";
 451         case SLOT_STATE_CONFIGURED:
 452                 return "configured";
 453         default:
 454                 return "reserved";
 455         }
 456 }
 457
 458 static void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
 459 {
 460         /* Fields are 32 bits wide, DMA addresses are in bytes */
 461         int field_size = 32 / 8;
 462         int i;
 463
 464         struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
 465         dma_addr_t dma = ctx->dma +
 466                 ((unsigned long)slot_ctx - (unsigned long)ctx->bytes);
 467         int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
 468
 469         xhci_dbg(xhci, "Slot Context:\n");
 470         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",
 471                         &slot_ctx->dev_info,
 472                         (unsigned long long)dma, slot_ctx->dev_info);
 473         dma += field_size;
 474         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",
 475                         &slot_ctx->dev_info2,
 476                         (unsigned long long)dma, slot_ctx->dev_info2);
 477         dma += field_size;
 478         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",
 479                         &slot_ctx->tt_info,
 480                         (unsigned long long)dma, slot_ctx->tt_info);
 481         dma += field_size;
 482         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",
 483                         &slot_ctx->dev_state,
 484                         (unsigned long long)dma, slot_ctx->dev_state);
 485         dma += field_size;
 486         for (i = 0; i < 4; ++i) {
 487                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
 488                                 &slot_ctx->reserved[i], (unsigned long long)dma,
 489                                 slot_ctx->reserved[i], i);
 490                 dma += field_size;
 491         }
 492
 493         if (csz)
 494                 dbg_rsvd64(xhci, (u64 *)slot_ctx, dma);
 495 }
 496
 497 static void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
 498                      struct xhci_container_ctx *ctx,
 499                      unsigned int last_ep)
 500 {
 501         int i, j;
 502         int last_ep_ctx = 31;
 503         /* Fields are 32 bits wide, DMA addresses are in bytes */
 504         int field_size = 32 / 8;
 505         int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
 506
 507         if (last_ep < 31)
 508                 last_ep_ctx = last_ep + 1;
 509         for (i = 0; i < last_ep_ctx; ++i) {
 510                 unsigned int epaddr = xhci_get_endpoint_address(i);
 511                 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i);
 512                 dma_addr_t dma = ctx->dma +
 513                         ((unsigned long)ep_ctx - (unsigned long)ctx->bytes);
 514
 515                 xhci_dbg(xhci, "%s Endpoint %02d Context (ep_index %02d):\n",
 516                                 usb_endpoint_out(epaddr) ? "OUT" : "IN",
 517                                 epaddr & USB_ENDPOINT_NUMBER_MASK, i);
 518                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
 519                                 &ep_ctx->ep_info,
 520                                 (unsigned long long)dma, ep_ctx->ep_info);
 521                 dma += field_size;
 522                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",
 523                                 &ep_ctx->ep_info2,
 524                                 (unsigned long long)dma, ep_ctx->ep_info2);
 525                 dma += field_size;
 526                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n",
 527                                 &ep_ctx->deq,
 528                                 (unsigned long long)dma, ep_ctx->deq);
 529                 dma += 2*field_size;
 530                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",
 531                                 &ep_ctx->tx_info,
 532                                 (unsigned long long)dma, ep_ctx->tx_info);
 533                 dma += field_size;
 534                 for (j = 0; j < 3; ++j) {
 535                         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
 536                                         &ep_ctx->reserved[j],
 537                                         (unsigned long long)dma,
 538                                         ep_ctx->reserved[j], j);
 539                         dma += field_size;
 540                 }
 541
 542                 if (csz)
 543                         dbg_rsvd64(xhci, (u64 *)ep_ctx, dma);
 544         }
 545 }
 546
 547 void xhci_dbg_ctx(struct xhci_hcd *xhci,
 548                   struct xhci_container_ctx *ctx,
 549                   unsigned int last_ep)
 550 {
 551         int i;
 552         /* Fields are 32 bits wide, DMA addresses are in bytes */
 553         int field_size = 32 / 8;
 554         dma_addr_t dma = ctx->dma;
 555         int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
 556
 557         if (ctx->type == XHCI_CTX_TYPE_INPUT) {
 558                 struct xhci_input_control_ctx *ctrl_ctx =
 559                         xhci_get_input_control_ctx(ctx);
 560                 if (!ctrl_ctx) {
 561                         xhci_warn(xhci, "Could not get input context, bad type.\n");
 562                         return;
 563                 }
 564
 565                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",
 566                          &ctrl_ctx->drop_flags, (unsigned long long)dma,
 567                          ctrl_ctx->drop_flags);
 568                 dma += field_size;
 569                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",
 570                          &ctrl_ctx->add_flags, (unsigned long long)dma,
 571                          ctrl_ctx->add_flags);
 572                 dma += field_size;
 573                 for (i = 0; i < 6; ++i) {
 574                         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",
 575                                  &ctrl_ctx->rsvd2[i], (unsigned long long)dma,
 576                                  ctrl_ctx->rsvd2[i], i);
 577                         dma += field_size;
 578                 }
 579
 580                 if (csz)
 581                         dbg_rsvd64(xhci, (u64 *)ctrl_ctx, dma);
 582         }
 583
 584         xhci_dbg_slot_ctx(xhci, ctx);
 585         xhci_dbg_ep_ctx(xhci, ctx, last_ep);
 586 }
 587
 588 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
 589                         const char *fmt, ...)
 590 {
 591         struct va_format vaf;
 592         va_list args;
 593
 594         va_start(args, fmt);
 595         vaf.fmt = fmt;
 596         vaf.va = &args;
 597         xhci_dbg(xhci, "%pV\n", &vaf);
 598         trace(&vaf);
 599         va_end(args);
 600 }
 601 EXPORT_SYMBOL_GPL(xhci_dbg_trace);