2 * Open Host Controller Interface (OHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
20 * This file is licenced under the GPL.
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pci.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/usb.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmapool.h>
40 #include <linux/workqueue.h>
41 #include <linux/debugfs.h>
45 #include <asm/system.h>
46 #include <asm/unaligned.h>
47 #include <asm/byteorder.h>
50 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
51 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
53 /*-------------------------------------------------------------------------*/
55 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
57 /* For initializing controller (mask in an HCFS mode too) */
58 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
59 #define OHCI_INTR_INIT \
60 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
61 | OHCI_INTR_RD | OHCI_INTR_WDH)
64 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
68 #ifdef CONFIG_ARCH_OMAP
69 /* OMAP doesn't support IR (no SMM; not needed) */
73 /*-------------------------------------------------------------------------*/
75 static const char hcd_name [] = "ohci_hcd";
77 #define STATECHANGE_DELAY msecs_to_jiffies(300)
80 #include "pci-quirks.h"
82 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
83 static int ohci_init (struct ohci_hcd *ohci);
84 static void ohci_stop (struct usb_hcd *hcd);
86 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
87 static int ohci_restart (struct ohci_hcd *ohci);
91 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
93 static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
100 #include "ohci-hub.c"
101 #include "ohci-dbg.c"
102 #include "ohci-mem.c"
107 * On architectures with edge-triggered interrupts we must never return
110 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
111 #define IRQ_NOTMINE IRQ_HANDLED
113 #define IRQ_NOTMINE IRQ_NONE
117 /* Some boards misreport power switching/overcurrent */
118 static int distrust_firmware = 1;
119 module_param (distrust_firmware, bool, 0);
120 MODULE_PARM_DESC (distrust_firmware,
121 "true to distrust firmware power/overcurrent setup");
123 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
124 static int no_handshake = 0;
125 module_param (no_handshake, bool, 0);
126 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
128 /*-------------------------------------------------------------------------*/
131 * queue up an urb for anything except the root hub
133 static int ohci_urb_enqueue (
138 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
140 urb_priv_t *urb_priv;
141 unsigned int pipe = urb->pipe;
146 #ifdef OHCI_VERBOSE_DEBUG
147 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
150 /* every endpoint has a ed, locate and maybe (re)initialize it */
151 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
154 /* for the private part of the URB we need the number of TDs (size) */
157 /* td_submit_urb() doesn't yet handle these */
158 if (urb->transfer_buffer_length > 4096)
161 /* 1 TD for setup, 1 for ACK, plus ... */
164 // case PIPE_INTERRUPT:
167 /* one TD for every 4096 Bytes (can be up to 8K) */
168 size += urb->transfer_buffer_length / 4096;
169 /* ... and for any remaining bytes ... */
170 if ((urb->transfer_buffer_length % 4096) != 0)
172 /* ... and maybe a zero length packet to wrap it up */
175 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
176 && (urb->transfer_buffer_length
177 % usb_maxpacket (urb->dev, pipe,
178 usb_pipeout (pipe))) == 0)
181 case PIPE_ISOCHRONOUS: /* number of packets from URB */
182 size = urb->number_of_packets;
186 /* allocate the private part of the URB */
187 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
191 INIT_LIST_HEAD (&urb_priv->pending);
192 urb_priv->length = size;
195 /* allocate the TDs (deferring hash chain updates) */
196 for (i = 0; i < size; i++) {
197 urb_priv->td [i] = td_alloc (ohci, mem_flags);
198 if (!urb_priv->td [i]) {
199 urb_priv->length = i;
200 urb_free_priv (ohci, urb_priv);
205 spin_lock_irqsave (&ohci->lock, flags);
207 /* don't submit to a dead HC */
208 if (!HCD_HW_ACCESSIBLE(hcd)) {
212 if (!HC_IS_RUNNING(hcd->state)) {
216 retval = usb_hcd_link_urb_to_ep(hcd, urb);
220 /* schedule the ed if needed */
221 if (ed->state == ED_IDLE) {
222 retval = ed_schedule (ohci, ed);
224 usb_hcd_unlink_urb_from_ep(hcd, urb);
227 if (ed->type == PIPE_ISOCHRONOUS) {
228 u16 frame = ohci_frame_no(ohci);
230 /* delay a few frames before the first TD */
231 frame += max_t (u16, 8, ed->interval);
232 frame &= ~(ed->interval - 1);
234 urb->start_frame = frame;
236 /* yes, only URB_ISO_ASAP is supported, and
237 * urb->start_frame is never used as input.
240 } else if (ed->type == PIPE_ISOCHRONOUS)
241 urb->start_frame = ed->last_iso + ed->interval;
243 /* fill the TDs and link them to the ed; and
244 * enable that part of the schedule, if needed
245 * and update count of queued periodic urbs
247 urb->hcpriv = urb_priv;
248 td_submit_urb (ohci, urb);
252 urb_free_priv (ohci, urb_priv);
253 spin_unlock_irqrestore (&ohci->lock, flags);
258 * decouple the URB from the HC queues (TDs, urb_priv).
259 * reporting is always done
260 * asynchronously, and we might be dealing with an urb that's
261 * partially transferred, or an ED with other urbs being unlinked.
263 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
265 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
269 #ifdef OHCI_VERBOSE_DEBUG
270 urb_print(urb, "UNLINK", 1, status);
273 spin_lock_irqsave (&ohci->lock, flags);
274 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
277 } else if (HC_IS_RUNNING(hcd->state)) {
278 urb_priv_t *urb_priv;
280 /* Unless an IRQ completed the unlink while it was being
281 * handed to us, flag it for unlink and giveback, and force
282 * some upcoming INTR_SF to call finish_unlinks()
284 urb_priv = urb->hcpriv;
286 if (urb_priv->ed->state == ED_OPER)
287 start_ed_unlink (ohci, urb_priv->ed);
291 * with HC dead, we won't respect hc queue pointers
292 * any more ... just clean up every urb's memory.
295 finish_urb(ohci, urb, status);
297 spin_unlock_irqrestore (&ohci->lock, flags);
301 /*-------------------------------------------------------------------------*/
303 /* frees config/altsetting state for endpoints,
304 * including ED memory, dummy TD, and bulk/intr data toggle
308 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
310 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
312 struct ed *ed = ep->hcpriv;
313 unsigned limit = 1000;
315 /* ASSERT: any requests/urbs are being unlinked */
316 /* ASSERT: nobody can be submitting urbs for this any more */
322 spin_lock_irqsave (&ohci->lock, flags);
324 if (!HC_IS_RUNNING (hcd->state)) {
327 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
328 ohci->eds_scheduled--;
329 finish_unlinks (ohci, 0);
333 case ED_UNLINK: /* wait for hw to finish? */
334 /* major IRQ delivery trouble loses INTR_SF too... */
336 ohci_warn(ohci, "ED unlink timeout\n");
337 if (quirk_zfmicro(ohci)) {
338 ohci_warn(ohci, "Attempting ZF TD recovery\n");
339 ohci->ed_to_check = ed;
344 spin_unlock_irqrestore (&ohci->lock, flags);
345 schedule_timeout_uninterruptible(1);
347 case ED_IDLE: /* fully unlinked */
348 if (list_empty (&ed->td_list)) {
349 td_free (ohci, ed->dummy);
353 /* else FALL THROUGH */
355 /* caller was supposed to have unlinked any requests;
356 * that's not our job. can't recover; must leak ed.
358 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
359 ed, ep->desc.bEndpointAddress, ed->state,
360 list_empty (&ed->td_list) ? "" : " (has tds)");
361 td_free (ohci, ed->dummy);
365 spin_unlock_irqrestore (&ohci->lock, flags);
368 static int ohci_get_frame (struct usb_hcd *hcd)
370 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
372 return ohci_frame_no(ohci);
375 static void ohci_usb_reset (struct ohci_hcd *ohci)
377 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
378 ohci->hc_control &= OHCI_CTRL_RWC;
379 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
382 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
383 * other cases where the next software may expect clean state from the
384 * "firmware". this is bus-neutral, unlike shutdown() methods.
387 ohci_shutdown (struct usb_hcd *hcd)
389 struct ohci_hcd *ohci;
391 ohci = hcd_to_ohci (hcd);
392 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
393 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
395 /* If the SHUTDOWN quirk is set, don't put the controller in RESET */
396 ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ?
397 OHCI_CTRL_RWC | OHCI_CTRL_HCFS :
399 ohci_writel(ohci, ohci->hc_control, &ohci->regs->control);
401 /* flush the writes */
402 (void) ohci_readl (ohci, &ohci->regs->control);
405 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
407 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
408 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
409 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
410 && !list_empty(&ed->td_list);
413 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
414 * an interrupt TD but neglects to add it to the donelist. On systems with
415 * this chipset, we need to periodically check the state of the queues to look
416 * for such "lost" TDs.
418 static void unlink_watchdog_func(unsigned long _ohci)
422 unsigned seen_count = 0;
424 struct ed **seen = NULL;
425 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
427 spin_lock_irqsave(&ohci->lock, flags);
428 max = ohci->eds_scheduled;
432 if (ohci->ed_to_check)
435 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
439 for (i = 0; i < NUM_INTS; i++) {
440 struct ed *ed = ohci->periodic[i];
445 /* scan this branch of the periodic schedule tree */
446 for (temp = 0; temp < seen_count; temp++) {
447 if (seen[temp] == ed) {
448 /* we've checked it and what's after */
455 seen[seen_count++] = ed;
456 if (!check_ed(ohci, ed)) {
461 /* HC's TD list is empty, but HCD sees at least one
462 * TD that's not been sent through the donelist.
464 ohci->ed_to_check = ed;
467 /* The HC may wait until the next frame to report the
468 * TD as done through the donelist and INTR_WDH. (We
469 * just *assume* it's not a multi-TD interrupt URB;
470 * those could defer the IRQ more than one frame, using
471 * DI...) Check again after the next INTR_SF.
473 ohci_writel(ohci, OHCI_INTR_SF,
474 &ohci->regs->intrstatus);
475 ohci_writel(ohci, OHCI_INTR_SF,
476 &ohci->regs->intrenable);
478 /* flush those writes */
479 (void) ohci_readl(ohci, &ohci->regs->control);
486 if (ohci->eds_scheduled)
487 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
489 spin_unlock_irqrestore(&ohci->lock, flags);
492 /*-------------------------------------------------------------------------*
494 *-------------------------------------------------------------------------*/
496 /* init memory, and kick BIOS/SMM off */
498 static int ohci_init (struct ohci_hcd *ohci)
501 struct usb_hcd *hcd = ohci_to_hcd(ohci);
503 if (distrust_firmware)
504 ohci->flags |= OHCI_QUIRK_HUB_POWER;
507 ohci->regs = hcd->regs;
509 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
510 * was never needed for most non-PCI systems ... remove the code?
514 /* SMM owns the HC? not for long! */
515 if (!no_handshake && ohci_readl (ohci,
516 &ohci->regs->control) & OHCI_CTRL_IR) {
519 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
521 /* this timeout is arbitrary. we make it long, so systems
522 * depending on usb keyboards may be usable even if the
523 * BIOS/SMM code seems pretty broken.
525 temp = 500; /* arbitrary: five seconds */
527 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
528 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
529 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
532 ohci_err (ohci, "USB HC takeover failed!"
533 " (BIOS/SMM bug)\n");
537 ohci_usb_reset (ohci);
541 /* Disable HC interrupts */
542 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
544 /* flush the writes, and save key bits like RWC */
545 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
546 ohci->hc_control |= OHCI_CTRL_RWC;
548 /* Read the number of ports unless overridden */
549 if (ohci->num_ports == 0)
550 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
555 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
556 sizeof *ohci->hcca, &ohci->hcca_dma, 0);
560 if ((ret = ohci_mem_init (ohci)) < 0)
563 create_debug_files (ohci);
569 /*-------------------------------------------------------------------------*/
571 /* Start an OHCI controller, set the BUS operational
572 * resets USB and controller
575 static int ohci_run (struct ohci_hcd *ohci)
578 int first = ohci->fminterval == 0;
579 struct usb_hcd *hcd = ohci_to_hcd(ohci);
583 /* boot firmware should have set this up (5.1.1.3.1) */
586 val = ohci_readl (ohci, &ohci->regs->fminterval);
587 ohci->fminterval = val & 0x3fff;
588 if (ohci->fminterval != FI)
589 ohci_dbg (ohci, "fminterval delta %d\n",
590 ohci->fminterval - FI);
591 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
592 /* also: power/overcurrent flags in roothub.a */
595 /* Reset USB nearly "by the book". RemoteWakeupConnected has
596 * to be checked in case boot firmware (BIOS/SMM/...) has set up
597 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
598 * If the bus glue detected wakeup capability then it should
599 * already be enabled; if so we'll just enable it again.
601 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
602 device_set_wakeup_capable(hcd->self.controller, 1);
604 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
608 case OHCI_USB_SUSPEND:
609 case OHCI_USB_RESUME:
610 ohci->hc_control &= OHCI_CTRL_RWC;
611 ohci->hc_control |= OHCI_USB_RESUME;
612 val = 10 /* msec wait */;
614 // case OHCI_USB_RESET:
616 ohci->hc_control &= OHCI_CTRL_RWC;
617 ohci->hc_control |= OHCI_USB_RESET;
618 val = 50 /* msec wait */;
621 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
623 (void) ohci_readl (ohci, &ohci->regs->control);
626 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
628 /* 2msec timelimit here means no irqs/preempt */
629 spin_lock_irq (&ohci->lock);
632 /* HC Reset requires max 10 us delay */
633 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
634 val = 30; /* ... allow extra time */
635 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
637 spin_unlock_irq (&ohci->lock);
638 ohci_err (ohci, "USB HC reset timed out!\n");
644 /* now we're in the SUSPEND state ... must go OPERATIONAL
645 * within 2msec else HC enters RESUME
647 * ... but some hardware won't init fmInterval "by the book"
648 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
649 * this if we write fmInterval after we're OPERATIONAL.
650 * Unclear about ALi, ServerWorks, and others ... this could
651 * easily be a longstanding bug in chip init on Linux.
653 if (ohci->flags & OHCI_QUIRK_INITRESET) {
654 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
655 // flush those writes
656 (void) ohci_readl (ohci, &ohci->regs->control);
659 /* Tell the controller where the control and bulk lists are
660 * The lists are empty now. */
661 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
662 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
664 /* a reset clears this */
665 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
667 periodic_reinit (ohci);
669 /* some OHCI implementations are finicky about how they init.
670 * bogus values here mean not even enumeration could work.
672 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
673 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
674 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
675 ohci->flags |= OHCI_QUIRK_INITRESET;
676 ohci_dbg (ohci, "enabling initreset quirk\n");
679 spin_unlock_irq (&ohci->lock);
680 ohci_err (ohci, "init err (%08x %04x)\n",
681 ohci_readl (ohci, &ohci->regs->fminterval),
682 ohci_readl (ohci, &ohci->regs->periodicstart));
686 /* use rhsc irqs after khubd is fully initialized */
687 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
688 hcd->uses_new_polling = 1;
690 /* start controller operations */
691 ohci->hc_control &= OHCI_CTRL_RWC;
692 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
693 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
694 hcd->state = HC_STATE_RUNNING;
696 /* wake on ConnectStatusChange, matching external hubs */
697 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
699 /* Choose the interrupts we care about now, others later on demand */
700 mask = OHCI_INTR_INIT;
701 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
702 ohci_writel (ohci, mask, &ohci->regs->intrenable);
704 /* handle root hub init quirks ... */
705 val = roothub_a (ohci);
706 val &= ~(RH_A_PSM | RH_A_OCPM);
707 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
708 /* NSC 87560 and maybe others */
710 val &= ~(RH_A_POTPGT | RH_A_NPS);
711 ohci_writel (ohci, val, &ohci->regs->roothub.a);
712 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
713 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
714 /* hub power always on; required for AMD-756 and some
715 * Mac platforms. ganged overcurrent reporting, if any.
718 ohci_writel (ohci, val, &ohci->regs->roothub.a);
720 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
721 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
722 &ohci->regs->roothub.b);
723 // flush those writes
724 (void) ohci_readl (ohci, &ohci->regs->control);
726 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
727 spin_unlock_irq (&ohci->lock);
729 // POTPGT delay is bits 24-31, in 2 ms units.
730 mdelay ((val >> 23) & 0x1fe);
731 hcd->state = HC_STATE_RUNNING;
733 if (quirk_zfmicro(ohci)) {
734 /* Create timer to watch for bad queue state on ZF Micro */
735 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
736 (unsigned long) ohci);
738 ohci->eds_scheduled = 0;
739 ohci->ed_to_check = NULL;
747 /*-------------------------------------------------------------------------*/
749 /* an interrupt happens */
751 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
753 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
754 struct ohci_regs __iomem *regs = ohci->regs;
757 /* Read interrupt status (and flush pending writes). We ignore the
758 * optimization of checking the LSB of hcca->done_head; it doesn't
759 * work on all systems (edge triggering for OHCI can be a factor).
761 ints = ohci_readl(ohci, ®s->intrstatus);
763 /* Check for an all 1's result which is a typical consequence
764 * of dead, unclocked, or unplugged (CardBus...) devices
766 if (ints == ~(u32)0) {
768 ohci_dbg (ohci, "device removed!\n");
773 /* We only care about interrupts that are enabled */
774 ints &= ohci_readl(ohci, ®s->intrenable);
776 /* interrupt for some other device? */
777 if (ints == 0 || unlikely(hcd->state == HC_STATE_HALT))
780 if (ints & OHCI_INTR_UE) {
781 // e.g. due to PCI Master/Target Abort
782 if (quirk_nec(ohci)) {
783 /* Workaround for a silicon bug in some NEC chips used
784 * in Apple's PowerBooks. Adapted from Darwin code.
786 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
788 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
790 schedule_work (&ohci->nec_work);
793 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
798 ohci_usb_reset (ohci);
801 if (ints & OHCI_INTR_RHSC) {
802 ohci_vdbg(ohci, "rhsc\n");
803 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
804 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
807 /* NOTE: Vendors didn't always make the same implementation
808 * choices for RHSC. Many followed the spec; RHSC triggers
809 * on an edge, like setting and maybe clearing a port status
810 * change bit. With others it's level-triggered, active
811 * until khubd clears all the port status change bits. We'll
812 * always disable it here and rely on polling until khubd
815 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
816 usb_hcd_poll_rh_status(hcd);
819 /* For connect and disconnect events, we expect the controller
820 * to turn on RHSC along with RD. But for remote wakeup events
821 * this might not happen.
823 else if (ints & OHCI_INTR_RD) {
824 ohci_vdbg(ohci, "resume detect\n");
825 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
826 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
827 if (ohci->autostop) {
828 spin_lock (&ohci->lock);
829 ohci_rh_resume (ohci);
830 spin_unlock (&ohci->lock);
832 usb_hcd_resume_root_hub(hcd);
835 if (ints & OHCI_INTR_WDH) {
836 spin_lock (&ohci->lock);
838 spin_unlock (&ohci->lock);
841 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
842 spin_lock(&ohci->lock);
843 if (ohci->ed_to_check) {
844 struct ed *ed = ohci->ed_to_check;
846 if (check_ed(ohci, ed)) {
847 /* HC thinks the TD list is empty; HCD knows
848 * at least one TD is outstanding
850 if (--ohci->zf_delay == 0) {
851 struct td *td = list_entry(
855 "Reclaiming orphan TD %p\n",
857 takeback_td(ohci, td);
858 ohci->ed_to_check = NULL;
861 ohci->ed_to_check = NULL;
863 spin_unlock(&ohci->lock);
866 /* could track INTR_SO to reduce available PCI/... bandwidth */
868 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
869 * when there's still unlinking to be done (next frame).
871 spin_lock (&ohci->lock);
872 if (ohci->ed_rm_list)
873 finish_unlinks (ohci, ohci_frame_no(ohci));
874 if ((ints & OHCI_INTR_SF) != 0
876 && !ohci->ed_to_check
877 && HC_IS_RUNNING(hcd->state))
878 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
879 spin_unlock (&ohci->lock);
881 if (HC_IS_RUNNING(hcd->state)) {
882 ohci_writel (ohci, ints, ®s->intrstatus);
883 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
884 // flush those writes
885 (void) ohci_readl (ohci, &ohci->regs->control);
891 /*-------------------------------------------------------------------------*/
893 static void ohci_stop (struct usb_hcd *hcd)
895 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
900 flush_work_sync(&ohci->nec_work);
902 ohci_usb_reset (ohci);
903 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
904 free_irq(hcd->irq, hcd);
907 if (quirk_zfmicro(ohci))
908 del_timer(&ohci->unlink_watchdog);
909 if (quirk_amdiso(ohci))
912 remove_debug_files (ohci);
913 ohci_mem_cleanup (ohci);
915 dma_free_coherent (hcd->self.controller,
917 ohci->hcca, ohci->hcca_dma);
923 /*-------------------------------------------------------------------------*/
925 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
927 /* must not be called from interrupt context */
928 static int ohci_restart (struct ohci_hcd *ohci)
932 struct urb_priv *priv;
934 spin_lock_irq(&ohci->lock);
937 /* Recycle any "live" eds/tds (and urbs). */
938 if (!list_empty (&ohci->pending))
939 ohci_dbg(ohci, "abort schedule...\n");
940 list_for_each_entry (priv, &ohci->pending, pending) {
941 struct urb *urb = priv->td[0]->urb;
942 struct ed *ed = priv->ed;
946 ed->state = ED_UNLINK;
947 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
948 ed_deschedule (ohci, ed);
950 ed->ed_next = ohci->ed_rm_list;
952 ohci->ed_rm_list = ed;
957 ohci_dbg(ohci, "bogus ed %p state %d\n",
962 urb->unlinked = -ESHUTDOWN;
964 finish_unlinks (ohci, 0);
965 spin_unlock_irq(&ohci->lock);
967 /* paranoia, in case that didn't work: */
969 /* empty the interrupt branches */
970 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
971 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
973 /* no EDs to remove */
974 ohci->ed_rm_list = NULL;
976 /* empty control and bulk lists */
977 ohci->ed_controltail = NULL;
978 ohci->ed_bulktail = NULL;
980 if ((temp = ohci_run (ohci)) < 0) {
981 ohci_err (ohci, "can't restart, %d\n", temp);
984 ohci_dbg(ohci, "restart complete\n");
990 /*-------------------------------------------------------------------------*/
992 MODULE_AUTHOR (DRIVER_AUTHOR);
993 MODULE_DESCRIPTION(DRIVER_DESC);
994 MODULE_LICENSE ("GPL");
997 #include "ohci-pci.c"
998 #define PCI_DRIVER ohci_pci_driver
1001 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1002 #include "ohci-sa1111.c"
1003 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1006 #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX)
1007 #include "ohci-s3c2410.c"
1008 #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1011 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1012 #include "ohci-omap.c"
1013 #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver
1016 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1017 #include "ohci-omap3.c"
1018 #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver
1021 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1022 #include "ohci-pxa27x.c"
1023 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1026 #ifdef CONFIG_ARCH_EP93XX
1027 #include "ohci-ep93xx.c"
1028 #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1031 #ifdef CONFIG_MIPS_ALCHEMY
1032 #include "ohci-au1xxx.c"
1033 #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver
1036 #ifdef CONFIG_PNX8550
1037 #include "ohci-pnx8550.c"
1038 #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver
1041 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
1042 #include "ohci-ppc-soc.c"
1043 #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver
1046 #ifdef CONFIG_ARCH_AT91
1047 #include "ohci-at91.c"
1048 #define PLATFORM_DRIVER ohci_hcd_at91_driver
1051 #ifdef CONFIG_ARCH_PNX4008
1052 #include "ohci-pnx4008.c"
1053 #define PLATFORM_DRIVER usb_hcd_pnx4008_driver
1056 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1057 #include "ohci-da8xx.c"
1058 #define PLATFORM_DRIVER ohci_hcd_da8xx_driver
1061 #ifdef CONFIG_USB_OHCI_SH
1062 #include "ohci-sh.c"
1063 #define PLATFORM_DRIVER ohci_hcd_sh_driver
1067 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1068 #include "ohci-ppc-of.c"
1069 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1072 #ifdef CONFIG_PLAT_SPEAR
1073 #include "ohci-spear.c"
1074 #define PLATFORM_DRIVER spear_ohci_hcd_driver
1077 #ifdef CONFIG_PPC_PS3
1078 #include "ohci-ps3.c"
1079 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1082 #ifdef CONFIG_USB_OHCI_HCD_SSB
1083 #include "ohci-ssb.c"
1084 #define SSB_OHCI_DRIVER ssb_ohci_driver
1087 #ifdef CONFIG_MFD_SM501
1088 #include "ohci-sm501.c"
1089 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1092 #ifdef CONFIG_MFD_TC6393XB
1093 #include "ohci-tmio.c"
1094 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1097 #ifdef CONFIG_MACH_JZ4740
1098 #include "ohci-jz4740.c"
1099 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1102 #ifdef CONFIG_USB_OCTEON_OHCI
1103 #include "ohci-octeon.c"
1104 #define PLATFORM_DRIVER ohci_octeon_driver
1107 #ifdef CONFIG_USB_CNS3XXX_OHCI
1108 #include "ohci-cns3xxx.c"
1109 #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver
1112 #ifdef CONFIG_USB_OHCI_ATH79
1113 #include "ohci-ath79.c"
1114 #define PLATFORM_DRIVER ohci_hcd_ath79_driver
1117 #if !defined(PCI_DRIVER) && \
1118 !defined(PLATFORM_DRIVER) && \
1119 !defined(OMAP1_PLATFORM_DRIVER) && \
1120 !defined(OMAP3_PLATFORM_DRIVER) && \
1121 !defined(OF_PLATFORM_DRIVER) && \
1122 !defined(SA1111_DRIVER) && \
1123 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1124 !defined(SM501_OHCI_DRIVER) && \
1125 !defined(TMIO_OHCI_DRIVER) && \
1126 !defined(SSB_OHCI_DRIVER)
1127 #error "missing bus glue for ohci-hcd"
1130 static int __init ohci_hcd_mod_init(void)
1137 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1138 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1139 sizeof (struct ed), sizeof (struct td));
1140 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1143 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1144 if (!ohci_debug_root) {
1150 #ifdef PS3_SYSTEM_BUS_DRIVER
1151 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1156 #ifdef PLATFORM_DRIVER
1157 retval = platform_driver_register(&PLATFORM_DRIVER);
1159 goto error_platform;
1162 #ifdef OMAP1_PLATFORM_DRIVER
1163 retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1165 goto error_omap1_platform;
1168 #ifdef OMAP3_PLATFORM_DRIVER
1169 retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1171 goto error_omap3_platform;
1174 #ifdef OF_PLATFORM_DRIVER
1175 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1177 goto error_of_platform;
1180 #ifdef SA1111_DRIVER
1181 retval = sa1111_driver_register(&SA1111_DRIVER);
1187 retval = pci_register_driver(&PCI_DRIVER);
1192 #ifdef SSB_OHCI_DRIVER
1193 retval = ssb_driver_register(&SSB_OHCI_DRIVER);
1198 #ifdef SM501_OHCI_DRIVER
1199 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1204 #ifdef TMIO_OHCI_DRIVER
1205 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1213 #ifdef TMIO_OHCI_DRIVER
1214 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1217 #ifdef SM501_OHCI_DRIVER
1218 platform_driver_unregister(&SM501_OHCI_DRIVER);
1221 #ifdef SSB_OHCI_DRIVER
1222 ssb_driver_unregister(&SSB_OHCI_DRIVER);
1226 pci_unregister_driver(&PCI_DRIVER);
1229 #ifdef SA1111_DRIVER
1230 sa1111_driver_unregister(&SA1111_DRIVER);
1233 #ifdef OF_PLATFORM_DRIVER
1234 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1237 #ifdef PLATFORM_DRIVER
1238 platform_driver_unregister(&PLATFORM_DRIVER);
1241 #ifdef OMAP1_PLATFORM_DRIVER
1242 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1243 error_omap1_platform:
1245 #ifdef OMAP3_PLATFORM_DRIVER
1246 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1247 error_omap3_platform:
1249 #ifdef PS3_SYSTEM_BUS_DRIVER
1250 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1254 debugfs_remove(ohci_debug_root);
1255 ohci_debug_root = NULL;
1259 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1262 module_init(ohci_hcd_mod_init);
1264 static void __exit ohci_hcd_mod_exit(void)
1266 #ifdef TMIO_OHCI_DRIVER
1267 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1269 #ifdef SM501_OHCI_DRIVER
1270 platform_driver_unregister(&SM501_OHCI_DRIVER);
1272 #ifdef SSB_OHCI_DRIVER
1273 ssb_driver_unregister(&SSB_OHCI_DRIVER);
1276 pci_unregister_driver(&PCI_DRIVER);
1278 #ifdef SA1111_DRIVER
1279 sa1111_driver_unregister(&SA1111_DRIVER);
1281 #ifdef OF_PLATFORM_DRIVER
1282 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1284 #ifdef PLATFORM_DRIVER
1285 platform_driver_unregister(&PLATFORM_DRIVER);
1287 #ifdef OMAP3_PLATFORM_DRIVER
1288 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1290 #ifdef PS3_SYSTEM_BUS_DRIVER
1291 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1294 debugfs_remove(ohci_debug_root);
1296 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1298 module_exit(ohci_hcd_mod_exit);