2 * Copyright (c) 2001-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
22 /* definitions used for the EHCI driver */
24 /* statistics can be kept for for tuning/monitoring */
29 unsigned long reclaim;
30 unsigned long lost_iaa;
32 /* termination of urbs from core */
33 unsigned long complete;
37 /* ehci_hcd->lock guards shared data against other CPUs:
38 * ehci_hcd: async, reclaim, periodic (and shadow), ...
39 * usb_host_endpoint: hcpriv
40 * ehci_qh: qh_next, qtd_list
43 * Also, hold this lock when talking to HC registers or
44 * when updating hw_* fields in shared qh/qtd/... structures.
47 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
49 struct ehci_hcd { /* one per controller */
50 /* glue to PCI and HCD framework */
51 struct ehci_caps __iomem *caps;
52 struct ehci_regs __iomem *regs;
53 struct ehci_dbg_port __iomem *debug;
55 __u32 hcs_params; /* cached register copy */
58 /* async schedule support */
59 struct ehci_qh *async;
60 struct ehci_qh *reclaim;
61 unsigned scanning : 1;
63 /* periodic schedule support */
64 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
65 unsigned periodic_size;
66 __le32 *periodic; /* hw periodic table */
67 dma_addr_t periodic_dma;
68 unsigned i_thresh; /* uframes HC might cache */
70 union ehci_shadow *pshadow; /* mirror hw periodic table */
71 int next_uframe; /* scan periodic, start here */
72 unsigned periodic_sched; /* periodic activity count */
74 /* per root hub port */
75 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
77 /* per-HC memory pools (could be per-bus, but ...) */
78 struct dma_pool *qh_pool; /* qh per active urb */
79 struct dma_pool *qtd_pool; /* one or more per qh */
80 struct dma_pool *itd_pool; /* itd per iso urb */
81 struct dma_pool *sitd_pool; /* sitd per split iso urb */
83 struct timer_list iaa_watchdog;
84 struct timer_list watchdog;
85 unsigned long actions;
87 unsigned long next_statechange;
91 unsigned is_tdi_rh_tt:1; /* TDI roothub with TT */
92 unsigned no_selective_suspend:1;
93 unsigned has_fsl_port_bug:1; /* FreeScale */
95 u8 sbrn; /* packed release number */
99 struct ehci_stats stats;
100 # define COUNT(x) do { (x)++; } while (0)
102 # define COUNT(x) do {} while (0)
106 /* convert between an HCD pointer and the corresponding EHCI_HCD */
107 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
109 return (struct ehci_hcd *) (hcd->hcd_priv);
111 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
113 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
118 iaa_watchdog_start (struct ehci_hcd *ehci)
120 WARN_ON(timer_pending(&ehci->iaa_watchdog));
121 mod_timer (&ehci->iaa_watchdog,
122 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
125 static inline void iaa_watchdog_done (struct ehci_hcd *ehci)
127 del_timer (&ehci->iaa_watchdog);
130 enum ehci_timer_action {
137 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
139 clear_bit (action, &ehci->actions);
143 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
145 if (!test_and_set_bit (action, &ehci->actions)) {
149 case TIMER_IO_WATCHDOG:
152 case TIMER_ASYNC_OFF:
153 t = EHCI_ASYNC_JIFFIES;
155 // case TIMER_ASYNC_SHRINK:
157 t = EHCI_SHRINK_JIFFIES;
161 // all timings except IAA watchdog can be overridden.
162 // async queue SHRINK often precedes IAA. while it's ready
163 // to go OFF neither can matter, and afterwards the IO
164 // watchdog stops unless there's still periodic traffic.
165 if (time_before_eq(t, ehci->watchdog.expires)
166 && timer_pending (&ehci->watchdog))
168 mod_timer (&ehci->watchdog, t);
172 /*-------------------------------------------------------------------------*/
174 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
176 /* Section 2.2 Host Controller Capability Registers */
178 /* these fields are specified as 8 and 16 bit registers,
179 * but some hosts can't perform 8 or 16 bit PCI accesses.
182 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
183 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
184 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
185 #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
186 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
187 #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
188 #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
189 #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
190 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
191 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
193 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
194 #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
195 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
196 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
197 #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
198 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
199 #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
200 u8 portroute [8]; /* nibbles for routing - offset 0xC */
201 } __attribute__ ((packed));
204 /* Section 2.3 Host Controller Operational Registers */
207 /* USBCMD: offset 0x00 */
209 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
210 #define CMD_PARK (1<<11) /* enable "park" on async qh */
211 #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
212 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
213 #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
214 #define CMD_ASE (1<<5) /* async schedule enable */
215 #define CMD_PSE (1<<4) /* periodic schedule enable */
216 /* 3:2 is periodic frame list size */
217 #define CMD_RESET (1<<1) /* reset HC not bus */
218 #define CMD_RUN (1<<0) /* start/stop HC */
220 /* USBSTS: offset 0x04 */
222 #define STS_ASS (1<<15) /* Async Schedule Status */
223 #define STS_PSS (1<<14) /* Periodic Schedule Status */
224 #define STS_RECL (1<<13) /* Reclamation */
225 #define STS_HALT (1<<12) /* Not running (any reason) */
226 /* some bits reserved */
227 /* these STS_* flags are also intr_enable bits (USBINTR) */
228 #define STS_IAA (1<<5) /* Interrupted on async advance */
229 #define STS_FATAL (1<<4) /* such as some PCI access errors */
230 #define STS_FLR (1<<3) /* frame list rolled over */
231 #define STS_PCD (1<<2) /* port change detect */
232 #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
233 #define STS_INT (1<<0) /* "normal" completion (short, ...) */
235 /* USBINTR: offset 0x08 */
238 /* FRINDEX: offset 0x0C */
239 u32 frame_index; /* current microframe number */
240 /* CTRLDSSEGMENT: offset 0x10 */
241 u32 segment; /* address bits 63:32 if needed */
242 /* PERIODICLISTBASE: offset 0x14 */
243 u32 frame_list; /* points to periodic list */
244 /* ASYNCLISTADDR: offset 0x18 */
245 u32 async_next; /* address of next async queue head */
249 /* CONFIGFLAG: offset 0x40 */
251 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
253 /* PORTSC: offset 0x44 */
254 u32 port_status [0]; /* up to N_PORTS */
256 #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
257 #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
258 #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
259 /* 19:16 for port testing */
260 #define PORT_LED_OFF (0<<14)
261 #define PORT_LED_AMBER (1<<14)
262 #define PORT_LED_GREEN (2<<14)
263 #define PORT_LED_MASK (3<<14)
264 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
265 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
266 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */
267 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
269 #define PORT_RESET (1<<8) /* reset port */
270 #define PORT_SUSPEND (1<<7) /* suspend port */
271 #define PORT_RESUME (1<<6) /* resume it */
272 #define PORT_OCC (1<<5) /* over current change */
273 #define PORT_OC (1<<4) /* over current active */
274 #define PORT_PEC (1<<3) /* port enable change */
275 #define PORT_PE (1<<2) /* port enable */
276 #define PORT_CSC (1<<1) /* connect status change */
277 #define PORT_CONNECT (1<<0) /* device connected */
278 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
279 } __attribute__ ((packed));
281 /* Appendix C, Debug port ... intended for use with special "debug devices"
282 * that can help if there's no serial console. (nonstandard enumeration.)
284 struct ehci_dbg_port {
286 #define DBGP_OWNER (1<<30)
287 #define DBGP_ENABLED (1<<28)
288 #define DBGP_DONE (1<<16)
289 #define DBGP_INUSE (1<<10)
290 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
291 # define DBGP_ERR_BAD 1
292 # define DBGP_ERR_SIGNAL 2
293 #define DBGP_ERROR (1<<6)
294 #define DBGP_GO (1<<5)
295 #define DBGP_OUT (1<<4)
296 #define DBGP_LEN(x) (((x)>>0)&0x0f)
298 #define DBGP_PID_GET(x) (((x)>>16)&0xff)
299 #define DBGP_PID_SET(data,tok) (((data)<<8)|(tok))
303 #define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep))
304 } __attribute__ ((packed));
306 /*-------------------------------------------------------------------------*/
308 #define QTD_NEXT(dma) cpu_to_le32((u32)dma)
311 * EHCI Specification 0.95 Section 3.5
312 * QTD: describe data transfer components (buffer, direction, ...)
313 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
315 * These are associated only with "QH" (Queue Head) structures,
316 * used with control, bulk, and interrupt transfers.
319 /* first part defined by EHCI spec */
320 __le32 hw_next; /* see EHCI 3.5.1 */
321 __le32 hw_alt_next; /* see EHCI 3.5.2 */
322 __le32 hw_token; /* see EHCI 3.5.3 */
323 #define QTD_TOGGLE (1 << 31) /* data toggle */
324 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
325 #define QTD_IOC (1 << 15) /* interrupt on complete */
326 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
327 #define QTD_PID(tok) (((tok)>>8) & 0x3)
328 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
329 #define QTD_STS_HALT (1 << 6) /* halted on error */
330 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
331 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
332 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
333 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
334 #define QTD_STS_STS (1 << 1) /* split transaction state */
335 #define QTD_STS_PING (1 << 0) /* issue PING? */
336 __le32 hw_buf [5]; /* see EHCI 3.5.4 */
337 __le32 hw_buf_hi [5]; /* Appendix B */
339 /* the rest is HCD-private */
340 dma_addr_t qtd_dma; /* qtd address */
341 struct list_head qtd_list; /* sw qtd list */
342 struct urb *urb; /* qtd's urb */
343 size_t length; /* length of buffer */
344 } __attribute__ ((aligned (32)));
346 /* mask NakCnt+T in qh->hw_alt_next */
347 #define QTD_MASK __constant_cpu_to_le32 (~0x1f)
349 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
351 /*-------------------------------------------------------------------------*/
353 /* type tag from {qh,itd,sitd,fstn}->hw_next */
354 #define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
356 /* values for that type tag */
357 #define Q_TYPE_ITD __constant_cpu_to_le32 (0 << 1)
358 #define Q_TYPE_QH __constant_cpu_to_le32 (1 << 1)
359 #define Q_TYPE_SITD __constant_cpu_to_le32 (2 << 1)
360 #define Q_TYPE_FSTN __constant_cpu_to_le32 (3 << 1)
362 /* next async queue entry, or pointer to interrupt/periodic QH */
363 #define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
365 /* for periodic/async schedules and qtd lists, mark end of list */
366 #define EHCI_LIST_END __constant_cpu_to_le32(1) /* "null pointer" to hw */
369 * Entries in periodic shadow table are pointers to one of four kinds
370 * of data structure. That's dictated by the hardware; a type tag is
371 * encoded in the low bits of the hardware's periodic schedule. Use
372 * Q_NEXT_TYPE to get the tag.
374 * For entries in the async schedule, the type tag always says "qh".
377 struct ehci_qh *qh; /* Q_TYPE_QH */
378 struct ehci_itd *itd; /* Q_TYPE_ITD */
379 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
380 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
381 __le32 *hw_next; /* (all types) */
385 /*-------------------------------------------------------------------------*/
388 * EHCI Specification 0.95 Section 3.6
389 * QH: describes control/bulk/interrupt endpoints
390 * See Fig 3-7 "Queue Head Structure Layout".
392 * These appear in both the async and (for interrupt) periodic schedules.
396 /* first part defined by EHCI spec */
397 __le32 hw_next; /* see EHCI 3.6.1 */
398 __le32 hw_info1; /* see EHCI 3.6.2 */
399 #define QH_HEAD 0x00008000
400 __le32 hw_info2; /* see EHCI 3.6.2 */
401 #define QH_SMASK 0x000000ff
402 #define QH_CMASK 0x0000ff00
403 #define QH_HUBADDR 0x007f0000
404 #define QH_HUBPORT 0x3f800000
405 #define QH_MULT 0xc0000000
406 __le32 hw_current; /* qtd list - see EHCI 3.6.4 */
408 /* qtd overlay (hardware parts of a struct ehci_qtd) */
413 __le32 hw_buf_hi [5];
415 /* the rest is HCD-private */
416 dma_addr_t qh_dma; /* address of qh */
417 union ehci_shadow qh_next; /* ptr to qh; or periodic */
418 struct list_head qtd_list; /* sw qtd list */
419 struct ehci_qtd *dummy;
420 struct ehci_qh *reclaim; /* next to reclaim */
422 struct ehci_hcd *ehci;
427 #define QH_STATE_LINKED 1 /* HC sees this */
428 #define QH_STATE_UNLINK 2 /* HC may still see this */
429 #define QH_STATE_IDLE 3 /* HC doesn't see this */
430 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
431 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
433 /* periodic schedule info */
434 u8 usecs; /* intr bandwidth */
435 u8 gap_uf; /* uframes split/csplit gap */
436 u8 c_usecs; /* ... split completion bw */
437 u16 tt_usecs; /* tt downstream bandwidth */
438 unsigned short period; /* polling interval */
439 unsigned short start; /* where polling starts */
440 #define NO_FRAME ((unsigned short)~0) /* pick new start */
441 struct usb_device *dev; /* access to TT */
442 } __attribute__ ((aligned (32)));
444 /*-------------------------------------------------------------------------*/
446 /* description of one iso transaction (up to 3 KB data if highspeed) */
447 struct ehci_iso_packet {
448 /* These will be copied to iTD when scheduling */
449 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
450 __le32 transaction; /* itd->hw_transaction[i] |= */
451 u8 cross; /* buf crosses pages */
452 /* for full speed OUT splits */
456 /* temporary schedule data for packets from iso urbs (both speeds)
457 * each packet is one logical usb transaction to the device (not TT),
458 * beginning at stream->next_uframe
460 struct ehci_iso_sched {
461 struct list_head td_list;
463 struct ehci_iso_packet packet [0];
467 * ehci_iso_stream - groups all (s)itds for this endpoint.
468 * acts like a qh would, if EHCI had them for ISO.
470 struct ehci_iso_stream {
471 /* first two fields match QH, but info1 == 0 */
478 u16 depth; /* depth in uframes */
479 struct list_head td_list; /* queued itds/sitds */
480 struct list_head free_list; /* list of unused itds/sitds */
481 struct usb_device *udev;
482 struct usb_host_endpoint *ep;
484 /* output of (re)scheduling */
485 unsigned long start; /* jiffies */
486 unsigned long rescheduled;
490 /* the rest is derived from the endpoint descriptor,
491 * trusting urb->interval == f(epdesc->bInterval) and
492 * including the extra info for hw_bufp[0..2]
501 /* This is used to initialize iTD's hw_bufp fields */
506 /* this is used to initialize sITD's tt info */
510 /*-------------------------------------------------------------------------*/
513 * EHCI Specification 0.95 Section 3.3
514 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
516 * Schedule records for high speed iso xfers
519 /* first part defined by EHCI spec */
520 __le32 hw_next; /* see EHCI 3.3.1 */
521 __le32 hw_transaction [8]; /* see EHCI 3.3.2 */
522 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
523 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
524 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
525 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
526 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
527 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
529 #define ITD_ACTIVE __constant_cpu_to_le32(EHCI_ISOC_ACTIVE)
531 __le32 hw_bufp [7]; /* see EHCI 3.3.3 */
532 __le32 hw_bufp_hi [7]; /* Appendix B */
534 /* the rest is HCD-private */
535 dma_addr_t itd_dma; /* for this itd */
536 union ehci_shadow itd_next; /* ptr to periodic q entry */
539 struct ehci_iso_stream *stream; /* endpoint's queue */
540 struct list_head itd_list; /* list of stream's itds */
542 /* any/all hw_transactions here may be used by that urb */
543 unsigned frame; /* where scheduled */
545 unsigned index[8]; /* in urb->iso_frame_desc */
547 } __attribute__ ((aligned (32)));
549 /*-------------------------------------------------------------------------*/
552 * EHCI Specification 0.95 Section 3.4
553 * siTD, aka split-transaction isochronous Transfer Descriptor
554 * ... describe full speed iso xfers through TT in hubs
555 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
558 /* first part defined by EHCI spec */
560 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
561 __le32 hw_fullspeed_ep; /* EHCI table 3-9 */
562 __le32 hw_uframe; /* EHCI table 3-10 */
563 __le32 hw_results; /* EHCI table 3-11 */
564 #define SITD_IOC (1 << 31) /* interrupt on completion */
565 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
566 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
567 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
568 #define SITD_STS_ERR (1 << 6) /* error from TT */
569 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
570 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
571 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
572 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
573 #define SITD_STS_STS (1 << 1) /* split transaction state */
575 #define SITD_ACTIVE __constant_cpu_to_le32(SITD_STS_ACTIVE)
577 __le32 hw_buf [2]; /* EHCI table 3-12 */
578 __le32 hw_backpointer; /* EHCI table 3-13 */
579 __le32 hw_buf_hi [2]; /* Appendix B */
581 /* the rest is HCD-private */
583 union ehci_shadow sitd_next; /* ptr to periodic q entry */
586 struct ehci_iso_stream *stream; /* endpoint's queue */
587 struct list_head sitd_list; /* list of stream's sitds */
590 } __attribute__ ((aligned (32)));
592 /*-------------------------------------------------------------------------*/
595 * EHCI Specification 0.96 Section 3.7
596 * Periodic Frame Span Traversal Node (FSTN)
598 * Manages split interrupt transactions (using TT) that span frame boundaries
599 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
600 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
601 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
604 __le32 hw_next; /* any periodic q entry */
605 __le32 hw_prev; /* qh or EHCI_LIST_END */
607 /* the rest is HCD-private */
609 union ehci_shadow fstn_next; /* ptr to periodic q entry */
610 } __attribute__ ((aligned (32)));
612 /*-------------------------------------------------------------------------*/
614 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
617 * Some EHCI controllers have a Transaction Translator built into the
618 * root hub. This is a non-standard feature. Each controller will need
619 * to add code to the following inline functions, and call them as
620 * needed (mostly in root hub code).
623 #define ehci_is_TDI(e) ((e)->is_tdi_rh_tt)
625 /* Returns the speed of a device attached to a port on the root hub. */
626 static inline unsigned int
627 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
629 if (ehci_is_TDI(ehci)) {
630 switch ((portsc>>26)&3) {
634 return (1<<USB_PORT_FEAT_LOWSPEED);
637 return (1<<USB_PORT_FEAT_HIGHSPEED);
640 return (1<<USB_PORT_FEAT_HIGHSPEED);
645 #define ehci_is_TDI(e) (0)
647 #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED)
650 /*-------------------------------------------------------------------------*/
652 #ifdef CONFIG_PPC_83xx
653 /* Some Freescale processors have an erratum in which the TT
654 * port number in the queue head was 0..N-1 instead of 1..N.
656 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
658 #define ehci_has_fsl_portno_bug(e) (0)
662 /*-------------------------------------------------------------------------*/
665 #define STUB_DEBUG_FILES
668 /*-------------------------------------------------------------------------*/
670 #endif /* __LINUX_EHCI_HCD_H */