2 * Enhanced Host Controller Interface (EHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * Copyright (c) 2000-2004 by David Brownell
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/dmapool.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/vmalloc.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/ktime.h>
35 #include <linux/list.h>
36 #include <linux/interrupt.h>
37 #include <linux/usb.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/moduleparam.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/debugfs.h>
42 #include <linux/slab.h>
43 #include <linux/uaccess.h>
45 #include <asm/byteorder.h>
48 #include <asm/unaligned.h>
50 #if defined(CONFIG_PPC_PS3)
51 #include <asm/firmware.h>
54 /*-------------------------------------------------------------------------*/
57 * EHCI hc_driver implementation ... experimental, incomplete.
58 * Based on the final 1.0 register interface specification.
60 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
61 * First was PCMCIA, like ISA; then CardBus, which is PCI.
62 * Next comes "CardBay", using USB 2.0 signals.
64 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
65 * Special thanks to Intel and VIA for providing host controllers to
66 * test this driver on, and Cypress (including In-System Design) for
67 * providing early devices for those host controllers to talk to!
70 #define DRIVER_AUTHOR "David Brownell"
71 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
73 static const char hcd_name [] = "ehci_hcd";
83 /* magic numbers that can affect system performance */
84 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
85 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
86 #define EHCI_TUNE_RL_TT 0
87 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
88 #define EHCI_TUNE_MULT_TT 1
90 * Some drivers think it's safe to schedule isochronous transfers more than
91 * 256 ms into the future (partly as a result of an old bug in the scheduling
92 * code). In an attempt to avoid trouble, we will use a minimum scheduling
93 * length of 512 frames instead of 256.
95 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
97 #define EHCI_IAA_MSECS 10 /* arbitrary */
98 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
99 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
100 #define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1)
101 /* 5-ms async qh unlink delay */
103 /* Initial IRQ latency: faster than hw default */
104 static int log2_irq_thresh = 0; // 0 to 6
105 module_param (log2_irq_thresh, int, S_IRUGO);
106 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
108 /* initial park setting: slower than hw default */
109 static unsigned park = 0;
110 module_param (park, uint, S_IRUGO);
111 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
113 /* for flakey hardware, ignore overcurrent indicators */
114 static bool ignore_oc = 0;
115 module_param (ignore_oc, bool, S_IRUGO);
116 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
118 /* for link power management(LPM) feature */
119 static unsigned int hird;
120 module_param(hird, int, S_IRUGO);
121 MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
123 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
125 /*-------------------------------------------------------------------------*/
128 #include "ehci-dbg.c"
129 #include "pci-quirks.h"
131 /*-------------------------------------------------------------------------*/
134 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
136 /* Don't override timeouts which shrink or (later) disable
137 * the async ring; just the I/O watchdog. Note that if a
138 * SHRINK were pending, OFF would never be requested.
140 if (timer_pending(&ehci->watchdog)
141 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
145 if (!test_and_set_bit(action, &ehci->actions)) {
149 case TIMER_IO_WATCHDOG:
150 if (!ehci->need_io_watchdog)
154 case TIMER_ASYNC_OFF:
155 t = EHCI_ASYNC_JIFFIES;
157 /* case TIMER_ASYNC_SHRINK: */
159 t = EHCI_SHRINK_JIFFIES;
162 mod_timer(&ehci->watchdog, t + jiffies);
166 /*-------------------------------------------------------------------------*/
169 * handshake - spin reading hc until handshake completes or fails
170 * @ptr: address of hc register to be read
171 * @mask: bits to look at in result of read
172 * @done: value of those bits when handshake succeeds
173 * @usec: timeout in microseconds
175 * Returns negative errno, or zero on success
177 * Success happens when the "mask" bits have the specified value (hardware
178 * handshake done). There are two failure modes: "usec" have passed (major
179 * hardware flakeout), or the register reads as all-ones (hardware removed).
181 * That last failure should_only happen in cases like physical cardbus eject
182 * before driver shutdown. But it also seems to be caused by bugs in cardbus
183 * bridge shutdown: shutting down the bridge before the devices using it.
185 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
186 u32 mask, u32 done, int usec)
191 result = ehci_readl(ehci, ptr);
192 if (result == ~(u32)0) /* card removed */
203 /* check TDI/ARC silicon is in host mode */
204 static int tdi_in_host_mode (struct ehci_hcd *ehci)
208 tmp = ehci_readl(ehci, &ehci->regs->usbmode);
209 return (tmp & 3) == USBMODE_CM_HC;
212 /* force HC to halt state from unknown (EHCI spec section 2.3) */
213 static int ehci_halt (struct ehci_hcd *ehci)
215 u32 temp = ehci_readl(ehci, &ehci->regs->status);
217 /* disable any irqs left enabled by previous code */
218 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
220 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) {
224 if ((temp & STS_HALT) != 0)
228 * This routine gets called during probe before ehci->command
229 * has been initialized, so we can't rely on its value.
231 ehci->command &= ~CMD_RUN;
232 temp = ehci_readl(ehci, &ehci->regs->command);
233 temp &= ~(CMD_RUN | CMD_IAAD);
234 ehci_writel(ehci, temp, &ehci->regs->command);
235 return handshake (ehci, &ehci->regs->status,
236 STS_HALT, STS_HALT, 16 * 125);
239 #if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_PPC_PS3)
242 * The EHCI controller of the Cell Super Companion Chip used in the
243 * PS3 will stop the root hub after all root hub ports are suspended.
244 * When in this condition handshake will return -ETIMEDOUT. The
245 * STS_HLT bit will not be set, so inspection of the frame index is
246 * used here to test for the condition. If the condition is found
247 * return success to allow the USB suspend to complete.
250 static int handshake_for_broken_root_hub(struct ehci_hcd *ehci,
251 void __iomem *ptr, u32 mask, u32 done,
254 unsigned int old_index;
257 if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
260 old_index = ehci_read_frame_index(ehci);
262 error = handshake(ehci, ptr, mask, done, usec);
264 if (error == -ETIMEDOUT && ehci_read_frame_index(ehci) == old_index)
272 static int handshake_for_broken_root_hub(struct ehci_hcd *ehci,
273 void __iomem *ptr, u32 mask, u32 done,
281 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
282 u32 mask, u32 done, int usec)
286 error = handshake(ehci, ptr, mask, done, usec);
287 if (error == -ETIMEDOUT)
288 error = handshake_for_broken_root_hub(ehci, ptr, mask, done,
293 ehci->rh_state = EHCI_RH_HALTED;
294 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
295 ptr, mask, done, error);
301 /* put TDI/ARC silicon into EHCI mode */
302 static void tdi_reset (struct ehci_hcd *ehci)
306 tmp = ehci_readl(ehci, &ehci->regs->usbmode);
307 tmp |= USBMODE_CM_HC;
308 /* The default byte access to MMR space is LE after
309 * controller reset. Set the required endian mode
310 * for transfer buffers to match the host microprocessor
312 if (ehci_big_endian_mmio(ehci))
314 ehci_writel(ehci, tmp, &ehci->regs->usbmode);
317 /* reset a non-running (STS_HALT == 1) controller */
318 static int ehci_reset (struct ehci_hcd *ehci)
321 u32 command = ehci_readl(ehci, &ehci->regs->command);
323 /* If the EHCI debug controller is active, special care must be
324 * taken before and after a host controller reset */
325 if (ehci->debug && !dbgp_reset_prep())
328 command |= CMD_RESET;
329 dbg_cmd (ehci, "reset", command);
330 ehci_writel(ehci, command, &ehci->regs->command);
331 ehci->rh_state = EHCI_RH_HALTED;
332 ehci->next_statechange = jiffies;
333 retval = handshake (ehci, &ehci->regs->command,
334 CMD_RESET, 0, 250 * 1000);
336 if (ehci->has_hostpc) {
337 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
338 &ehci->regs->usbmode_ex);
339 ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
344 if (ehci_is_TDI(ehci))
348 dbgp_external_startup();
350 ehci->port_c_suspend = ehci->suspended_ports =
351 ehci->resuming_ports = 0;
355 /* idle the controller (from running) */
356 static void ehci_quiesce (struct ehci_hcd *ehci)
361 if (ehci->rh_state != EHCI_RH_RUNNING)
365 /* wait for any schedule enables/disables to take effect */
366 temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
367 if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
368 STS_ASS | STS_PSS, temp, 16 * 125))
371 /* then disable anything that's still active */
372 ehci->command &= ~(CMD_ASE | CMD_PSE);
373 ehci_writel(ehci, ehci->command, &ehci->regs->command);
375 /* hardware can take 16 microframes to turn off ... */
376 handshake_on_error_set_halt(ehci, &ehci->regs->status,
377 STS_ASS | STS_PSS, 0, 16 * 125);
380 /*-------------------------------------------------------------------------*/
382 static void end_unlink_async(struct ehci_hcd *ehci);
383 static void ehci_work(struct ehci_hcd *ehci);
385 #include "ehci-hub.c"
386 #include "ehci-lpm.c"
387 #include "ehci-mem.c"
389 #include "ehci-sched.c"
390 #include "ehci-sysfs.c"
392 /*-------------------------------------------------------------------------*/
394 static void ehci_iaa_watchdog(unsigned long param)
396 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
399 spin_lock_irqsave (&ehci->lock, flags);
401 /* Lost IAA irqs wedge things badly; seen first with a vt8235.
402 * So we need this watchdog, but must protect it against both
403 * (a) SMP races against real IAA firing and retriggering, and
404 * (b) clean HC shutdown, when IAA watchdog was pending.
407 && !timer_pending(&ehci->iaa_watchdog)
408 && ehci->rh_state == EHCI_RH_RUNNING) {
411 /* If we get here, IAA is *REALLY* late. It's barely
412 * conceivable that the system is so busy that CMD_IAAD
413 * is still legitimately set, so let's be sure it's
414 * clear before we read STS_IAA. (The HC should clear
415 * CMD_IAAD when it sets STS_IAA.)
417 cmd = ehci_readl(ehci, &ehci->regs->command);
419 /* If IAA is set here it either legitimately triggered
420 * before we cleared IAAD above (but _way_ late, so we'll
421 * still count it as lost) ... or a silicon erratum:
422 * - VIA seems to set IAA without triggering the IRQ;
423 * - IAAD potentially cleared without setting IAA.
425 status = ehci_readl(ehci, &ehci->regs->status);
426 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
427 COUNT (ehci->stats.lost_iaa);
428 ehci_writel(ehci, STS_IAA, &ehci->regs->status);
431 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
433 end_unlink_async(ehci);
436 spin_unlock_irqrestore(&ehci->lock, flags);
439 static void ehci_watchdog(unsigned long param)
441 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
444 spin_lock_irqsave(&ehci->lock, flags);
446 /* stop async processing after it's idled a bit */
447 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
448 start_unlink_async (ehci, ehci->async);
450 /* ehci could run by timer, without IRQs ... */
453 spin_unlock_irqrestore (&ehci->lock, flags);
456 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
457 * The firmware seems to think that powering off is a wakeup event!
458 * This routine turns off remote wakeup and everything else, on all ports.
460 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
462 int port = HCS_N_PORTS(ehci->hcs_params);
465 ehci_writel(ehci, PORT_RWC_BITS,
466 &ehci->regs->port_status[port]);
470 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
471 * Should be called with ehci->lock held.
473 static void ehci_silence_controller(struct ehci_hcd *ehci)
476 ehci_turn_off_all_ports(ehci);
478 /* make BIOS/etc use companion controller during reboot */
479 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
481 /* unblock posted writes */
482 ehci_readl(ehci, &ehci->regs->configured_flag);
485 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
486 * This forcibly disables dma and IRQs, helping kexec and other cases
487 * where the next system software may expect clean state.
489 static void ehci_shutdown(struct usb_hcd *hcd)
491 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
493 del_timer_sync(&ehci->watchdog);
494 del_timer_sync(&ehci->iaa_watchdog);
496 spin_lock_irq(&ehci->lock);
497 ehci_silence_controller(ehci);
498 spin_unlock_irq(&ehci->lock);
501 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
505 if (!HCS_PPC (ehci->hcs_params))
508 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
509 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
510 (void) ehci_hub_control(ehci_to_hcd(ehci),
511 is_on ? SetPortFeature : ClearPortFeature,
514 /* Flush those writes */
515 ehci_readl(ehci, &ehci->regs->command);
519 /*-------------------------------------------------------------------------*/
522 * ehci_work is called from some interrupts, timers, and so on.
523 * it calls driver completion functions, after dropping ehci->lock.
525 static void ehci_work (struct ehci_hcd *ehci)
527 timer_action_done (ehci, TIMER_IO_WATCHDOG);
529 /* another CPU may drop ehci->lock during a schedule scan while
530 * it reports urb completions. this flag guards against bogus
531 * attempts at re-entrant schedule scanning.
537 if (ehci->next_uframe != -1)
538 scan_periodic (ehci);
541 /* the IO watchdog guards against hardware or driver bugs that
542 * misplace IRQs, and should let us run completely without IRQs.
543 * such lossage has been observed on both VT6202 and VT8235.
545 if (ehci->rh_state == EHCI_RH_RUNNING &&
546 (ehci->async->qh_next.ptr != NULL ||
547 ehci->periodic_sched != 0))
548 timer_action (ehci, TIMER_IO_WATCHDOG);
552 * Called when the ehci_hcd module is removed.
554 static void ehci_stop (struct usb_hcd *hcd)
556 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
558 ehci_dbg (ehci, "stop\n");
560 /* no more interrupts ... */
561 del_timer_sync (&ehci->watchdog);
562 del_timer_sync(&ehci->iaa_watchdog);
564 spin_lock_irq(&ehci->lock);
565 if (ehci->rh_state == EHCI_RH_RUNNING)
568 ehci_silence_controller(ehci);
570 spin_unlock_irq(&ehci->lock);
572 remove_sysfs_files(ehci);
573 remove_debug_files (ehci);
575 /* root hub is shut down separately (first, when possible) */
576 spin_lock_irq (&ehci->lock);
579 spin_unlock_irq (&ehci->lock);
580 ehci_mem_cleanup (ehci);
582 if (ehci->amd_pll_fix == 1)
586 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
587 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
588 ehci->stats.lost_iaa);
589 ehci_dbg (ehci, "complete %ld unlink %ld\n",
590 ehci->stats.complete, ehci->stats.unlink);
593 dbg_status (ehci, "ehci_stop completed",
594 ehci_readl(ehci, &ehci->regs->status));
597 /* one-time init, only for memory state */
598 static int ehci_init(struct usb_hcd *hcd)
600 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
604 struct ehci_qh_hw *hw;
606 spin_lock_init(&ehci->lock);
609 * keep io watchdog by default, those good HCDs could turn off it later
611 ehci->need_io_watchdog = 1;
612 init_timer(&ehci->watchdog);
613 ehci->watchdog.function = ehci_watchdog;
614 ehci->watchdog.data = (unsigned long) ehci;
616 init_timer(&ehci->iaa_watchdog);
617 ehci->iaa_watchdog.function = ehci_iaa_watchdog;
618 ehci->iaa_watchdog.data = (unsigned long) ehci;
620 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
623 * by default set standard 80% (== 100 usec/uframe) max periodic
624 * bandwidth as required by USB 2.0
626 ehci->uframe_periodic_max = 100;
629 * hw default: 1K periodic list heads, one per frame.
630 * periodic_size can shrink by USBCMD update if hcc_params allows.
632 ehci->periodic_size = DEFAULT_I_TDPS;
633 INIT_LIST_HEAD(&ehci->cached_itd_list);
634 INIT_LIST_HEAD(&ehci->cached_sitd_list);
636 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
637 /* periodic schedule size can be smaller than default */
638 switch (EHCI_TUNE_FLS) {
639 case 0: ehci->periodic_size = 1024; break;
640 case 1: ehci->periodic_size = 512; break;
641 case 2: ehci->periodic_size = 256; break;
645 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
648 /* controllers may cache some of the periodic schedule ... */
649 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
650 ehci->i_thresh = 2 + 8;
651 else // N microframes cached
652 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
654 ehci->reclaim = NULL;
655 ehci->next_uframe = -1;
656 ehci->clock_frame = -1;
659 * dedicate a qh for the async ring head, since we couldn't unlink
660 * a 'real' qh without stopping the async schedule [4.8]. use it
661 * as the 'reclamation list head' too.
662 * its dummy is used in hw_alt_next of many tds, to prevent the qh
663 * from automatically advancing to the next td after short reads.
665 ehci->async->qh_next.qh = NULL;
666 hw = ehci->async->hw;
667 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
668 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
669 #if defined(CONFIG_PPC_PS3)
670 hw->hw_info1 |= cpu_to_hc32(ehci, (1 << 7)); /* I = 1 */
672 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
673 hw->hw_qtd_next = EHCI_LIST_END(ehci);
674 ehci->async->qh_state = QH_STATE_LINKED;
675 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
677 /* clear interrupt enables, set irq latency */
678 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
680 temp = 1 << (16 + log2_irq_thresh);
681 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
683 ehci_dbg(ehci, "enable per-port change event\n");
686 if (HCC_CANPARK(hcc_params)) {
687 /* HW default park == 3, on hardware that supports it (like
688 * NVidia and ALI silicon), maximizes throughput on the async
689 * schedule by avoiding QH fetches between transfers.
691 * With fast usb storage devices and NForce2, "park" seems to
692 * make problems: throughput reduction (!), data errors...
695 park = min(park, (unsigned) 3);
699 ehci_dbg(ehci, "park %d\n", park);
701 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
702 /* periodic schedule size can be smaller than default */
704 temp |= (EHCI_TUNE_FLS << 2);
706 if (HCC_LPM(hcc_params)) {
707 /* support link power management EHCI 1.1 addendum */
708 ehci_dbg(ehci, "support lpm\n");
711 ehci_dbg(ehci, "hird %d invalid, use default 0",
717 ehci->command = temp;
719 /* Accept arbitrarily long scatter-gather lists */
720 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
721 hcd->self.sg_tablesize = ~0;
725 /* start HC running; it's halted, ehci_init() has been run (once) */
726 static int ehci_run (struct usb_hcd *hcd)
728 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
732 hcd->uses_new_polling = 1;
734 /* EHCI spec section 4.1 */
736 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
737 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
740 * hcc_params controls whether ehci->regs->segment must (!!!)
741 * be used; it constrains QH/ITD/SITD and QTD locations.
742 * pci_pool consistent memory always uses segment zero.
743 * streaming mappings for I/O buffers, like pci_map_single(),
744 * can return segments above 4GB, if the device allows.
746 * NOTE: the dma mask is visible through dma_supported(), so
747 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
748 * Scsi_Host.highmem_io, and so forth. It's readonly to all
749 * host side drivers though.
751 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
752 if (HCC_64BIT_ADDR(hcc_params)) {
753 ehci_writel(ehci, 0, &ehci->regs->segment);
755 // this is deeply broken on almost all architectures
756 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
757 ehci_info(ehci, "enabled 64bit DMA\n");
762 // Philips, Intel, and maybe others need CMD_RUN before the
763 // root hub will detect new devices (why?); NEC doesn't
764 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
765 ehci->command |= CMD_RUN;
766 ehci_writel(ehci, ehci->command, &ehci->regs->command);
767 dbg_cmd (ehci, "init", ehci->command);
770 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
771 * are explicitly handed to companion controller(s), so no TT is
772 * involved with the root hub. (Except where one is integrated,
773 * and there's no companion controller unless maybe for USB OTG.)
775 * Turning on the CF flag will transfer ownership of all ports
776 * from the companions to the EHCI controller. If any of the
777 * companions are in the middle of a port reset at the time, it
778 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
779 * guarantees that no resets are in progress. After we set CF,
780 * a short delay lets the hardware catch up; new resets shouldn't
781 * be started before the port switching actions could complete.
783 down_write(&ehci_cf_port_reset_rwsem);
784 ehci->rh_state = EHCI_RH_RUNNING;
785 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
786 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
788 up_write(&ehci_cf_port_reset_rwsem);
789 ehci->last_periodic_enable = ktime_get_real();
791 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
793 "USB %x.%x started, EHCI %x.%02x%s\n",
794 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
795 temp >> 8, temp & 0xff,
796 ignore_oc ? ", overcurrent ignored" : "");
798 ehci_writel(ehci, INTR_MASK,
799 &ehci->regs->intr_enable); /* Turn On Interrupts */
801 /* GRR this is run-once init(), being done every time the HC starts.
802 * So long as they're part of class devices, we can't do it init()
803 * since the class device isn't created that early.
805 create_debug_files(ehci);
806 create_sysfs_files(ehci);
811 static int __maybe_unused ehci_setup (struct usb_hcd *hcd)
813 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
816 ehci->regs = (void __iomem *)ehci->caps +
817 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
818 dbg_hcs_params(ehci, "reset");
819 dbg_hcc_params(ehci, "reset");
821 /* cache this readonly data; minimize chip reads */
822 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
824 ehci->sbrn = HCD_USB2;
826 retval = ehci_halt(ehci);
830 /* data structure init */
831 retval = ehci_init(hcd);
840 /*-------------------------------------------------------------------------*/
842 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
844 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
845 u32 status, masked_status, pcd_status = 0, cmd;
848 spin_lock (&ehci->lock);
850 status = ehci_readl(ehci, &ehci->regs->status);
852 /* e.g. cardbus physical eject */
853 if (status == ~(u32) 0) {
854 ehci_dbg (ehci, "device removed\n");
859 * We don't use STS_FLR, but some controllers don't like it to
860 * remain on, so mask it out along with the other status bits.
862 masked_status = status & (INTR_MASK | STS_FLR);
865 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
866 spin_unlock(&ehci->lock);
870 /* clear (just) interrupts */
871 ehci_writel(ehci, masked_status, &ehci->regs->status);
872 cmd = ehci_readl(ehci, &ehci->regs->command);
876 /* unrequested/ignored: Frame List Rollover */
877 dbg_status (ehci, "irq", status);
880 /* INT, ERR, and IAA interrupt rates can be throttled */
882 /* normal [4.15.1.2] or error [4.15.1.1] completion */
883 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
884 if (likely ((status & STS_ERR) == 0))
885 COUNT (ehci->stats.normal);
887 COUNT (ehci->stats.error);
891 /* complete the unlinking of some qh [4.15.2.3] */
892 if (status & STS_IAA) {
893 /* guard against (alleged) silicon errata */
895 ehci_dbg(ehci, "IAA with IAAD still set?\n");
897 COUNT(ehci->stats.reclaim);
898 end_unlink_async(ehci);
900 ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
903 /* remote wakeup [4.3.1] */
904 if (status & STS_PCD) {
905 unsigned i = HCS_N_PORTS (ehci->hcs_params);
908 /* kick root hub later */
911 /* resume root hub? */
912 if (ehci->rh_state == EHCI_RH_SUSPENDED)
913 usb_hcd_resume_root_hub(hcd);
915 /* get per-port change detect bits */
922 /* leverage per-port change bits feature */
923 if (ehci->has_ppcd && !(ppcd & (1 << i)))
925 pstatus = ehci_readl(ehci,
926 &ehci->regs->port_status[i]);
928 if (pstatus & PORT_OWNER)
930 if (!(test_bit(i, &ehci->suspended_ports) &&
931 ((pstatus & PORT_RESUME) ||
932 !(pstatus & PORT_SUSPEND)) &&
933 (pstatus & PORT_PE) &&
934 ehci->reset_done[i] == 0))
937 /* start 20 msec resume signaling from this port,
938 * and make khubd collect PORT_STAT_C_SUSPEND to
939 * stop that signaling. Use 5 ms extra for safety,
940 * like usb_port_resume() does.
942 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
943 set_bit(i, &ehci->resuming_ports);
944 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
945 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
949 /* PCI errors [4.15.2.4] */
950 if (unlikely ((status & STS_FATAL) != 0)) {
951 ehci_err(ehci, "fatal error\n");
952 dbg_cmd(ehci, "fatal", cmd);
953 dbg_status(ehci, "fatal", status);
957 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
959 /* generic layer kills/unlinks all urbs, then
960 * uses ehci_stop to clean up the rest
967 spin_unlock (&ehci->lock);
969 usb_hcd_poll_rh_status(hcd);
973 /*-------------------------------------------------------------------------*/
976 * non-error returns are a promise to giveback() the urb later
977 * we drop ownership so next owner (or urb unlink) can get it
979 * urb + dev is in hcd.self.controller.urb_list
980 * we're queueing TDs onto software and hardware lists
982 * hcd-specific init for hcpriv hasn't been done yet
984 * NOTE: control, bulk, and interrupt share the same code to append TDs
985 * to a (possibly active) QH, and the same QH scanning code.
987 static int ehci_urb_enqueue (
992 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
993 struct list_head qtd_list;
995 INIT_LIST_HEAD (&qtd_list);
997 switch (usb_pipetype (urb->pipe)) {
999 /* qh_completions() code doesn't handle all the fault cases
1000 * in multi-TD control transfers. Even 1KB is rare anyway.
1002 if (urb->transfer_buffer_length > (16 * 1024))
1005 /* case PIPE_BULK: */
1007 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1009 return submit_async(ehci, urb, &qtd_list, mem_flags);
1011 case PIPE_INTERRUPT:
1012 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1014 return intr_submit(ehci, urb, &qtd_list, mem_flags);
1016 case PIPE_ISOCHRONOUS:
1017 if (urb->dev->speed == USB_SPEED_HIGH)
1018 return itd_submit (ehci, urb, mem_flags);
1020 return sitd_submit (ehci, urb, mem_flags);
1024 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
1027 if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim)
1028 end_unlink_async(ehci);
1030 /* If the QH isn't linked then there's nothing we can do
1031 * unless we were called during a giveback, in which case
1032 * qh_completions() has to deal with it.
1034 if (qh->qh_state != QH_STATE_LINKED) {
1035 if (qh->qh_state == QH_STATE_COMPLETING)
1036 qh->needs_rescan = 1;
1040 /* defer till later if busy */
1041 if (ehci->reclaim) {
1042 struct ehci_qh *last;
1044 for (last = ehci->reclaim;
1046 last = last->reclaim)
1048 qh->qh_state = QH_STATE_UNLINK_WAIT;
1051 /* start IAA cycle */
1053 start_unlink_async (ehci, qh);
1056 /* remove from hardware lists
1057 * completions normally happen asynchronously
1060 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1062 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1064 unsigned long flags;
1067 spin_lock_irqsave (&ehci->lock, flags);
1068 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
1072 switch (usb_pipetype (urb->pipe)) {
1073 // case PIPE_CONTROL:
1076 qh = (struct ehci_qh *) urb->hcpriv;
1079 switch (qh->qh_state) {
1080 case QH_STATE_LINKED:
1081 case QH_STATE_COMPLETING:
1082 unlink_async(ehci, qh);
1084 case QH_STATE_UNLINK:
1085 case QH_STATE_UNLINK_WAIT:
1086 /* already started */
1089 /* QH might be waiting for a Clear-TT-Buffer */
1090 qh_completions(ehci, qh);
1095 case PIPE_INTERRUPT:
1096 qh = (struct ehci_qh *) urb->hcpriv;
1099 switch (qh->qh_state) {
1100 case QH_STATE_LINKED:
1101 case QH_STATE_COMPLETING:
1102 intr_deschedule (ehci, qh);
1105 qh_completions (ehci, qh);
1108 ehci_dbg (ehci, "bogus qh %p state %d\n",
1114 case PIPE_ISOCHRONOUS:
1117 // wait till next completion, do it then.
1118 // completion irqs can wait up to 1024 msec,
1122 spin_unlock_irqrestore (&ehci->lock, flags);
1126 /*-------------------------------------------------------------------------*/
1128 // bulk qh holds the data toggle
1131 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1133 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1134 unsigned long flags;
1135 struct ehci_qh *qh, *tmp;
1137 /* ASSERT: any requests/urbs are being unlinked */
1138 /* ASSERT: nobody can be submitting urbs for this any more */
1141 spin_lock_irqsave (&ehci->lock, flags);
1146 /* endpoints can be iso streams. for now, we don't
1147 * accelerate iso completions ... so spin a while.
1149 if (qh->hw == NULL) {
1150 ehci_vdbg (ehci, "iso delay\n");
1154 if (ehci->rh_state != EHCI_RH_RUNNING)
1155 qh->qh_state = QH_STATE_IDLE;
1156 switch (qh->qh_state) {
1157 case QH_STATE_LINKED:
1158 case QH_STATE_COMPLETING:
1159 for (tmp = ehci->async->qh_next.qh;
1161 tmp = tmp->qh_next.qh)
1163 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1164 * may already be unlinked.
1167 unlink_async(ehci, qh);
1169 case QH_STATE_UNLINK: /* wait for hw to finish? */
1170 case QH_STATE_UNLINK_WAIT:
1172 spin_unlock_irqrestore (&ehci->lock, flags);
1173 schedule_timeout_uninterruptible(1);
1175 case QH_STATE_IDLE: /* fully unlinked */
1176 if (qh->clearing_tt)
1178 if (list_empty (&qh->qtd_list)) {
1182 /* else FALL THROUGH */
1184 /* caller was supposed to have unlinked any requests;
1185 * that's not our job. just leak this memory.
1187 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1188 qh, ep->desc.bEndpointAddress, qh->qh_state,
1189 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1194 spin_unlock_irqrestore (&ehci->lock, flags);
1198 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1200 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1202 int eptype = usb_endpoint_type(&ep->desc);
1203 int epnum = usb_endpoint_num(&ep->desc);
1204 int is_out = usb_endpoint_dir_out(&ep->desc);
1205 unsigned long flags;
1207 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1210 spin_lock_irqsave(&ehci->lock, flags);
1213 /* For Bulk and Interrupt endpoints we maintain the toggle state
1214 * in the hardware; the toggle bits in udev aren't used at all.
1215 * When an endpoint is reset by usb_clear_halt() we must reset
1216 * the toggle bit in the QH.
1219 usb_settoggle(qh->dev, epnum, is_out, 0);
1220 if (!list_empty(&qh->qtd_list)) {
1221 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1222 } else if (qh->qh_state == QH_STATE_LINKED ||
1223 qh->qh_state == QH_STATE_COMPLETING) {
1225 /* The toggle value in the QH can't be updated
1226 * while the QH is active. Unlink it now;
1227 * re-linking will call qh_refresh().
1229 if (eptype == USB_ENDPOINT_XFER_BULK)
1230 unlink_async(ehci, qh);
1232 intr_deschedule(ehci, qh);
1235 spin_unlock_irqrestore(&ehci->lock, flags);
1238 static int ehci_get_frame (struct usb_hcd *hcd)
1240 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1241 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
1244 /*-------------------------------------------------------------------------*/
1246 * The EHCI in ChipIdea HDRC cannot be a separate module or device,
1247 * because its registers (and irq) are shared between host/gadget/otg
1248 * functions and in order to facilitate role switching we cannot
1249 * give the ehci driver exclusive access to those.
1251 #ifndef CHIPIDEA_EHCI
1253 MODULE_DESCRIPTION(DRIVER_DESC);
1254 MODULE_AUTHOR (DRIVER_AUTHOR);
1255 MODULE_LICENSE ("GPL");
1258 #include "ehci-pci.c"
1259 #define PCI_DRIVER ehci_pci_driver
1262 #ifdef CONFIG_USB_EHCI_FSL
1263 #include "ehci-fsl.c"
1264 #define PLATFORM_DRIVER ehci_fsl_driver
1267 #ifdef CONFIG_USB_EHCI_MXC
1268 #include "ehci-mxc.c"
1269 #define PLATFORM_DRIVER ehci_mxc_driver
1272 #ifdef CONFIG_USB_EHCI_SH
1273 #include "ehci-sh.c"
1274 #define PLATFORM_DRIVER ehci_hcd_sh_driver
1277 #ifdef CONFIG_MIPS_ALCHEMY
1278 #include "ehci-au1xxx.c"
1279 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1282 #ifdef CONFIG_USB_EHCI_HCD_OMAP
1283 #include "ehci-omap.c"
1284 #define PLATFORM_DRIVER ehci_hcd_omap_driver
1287 #ifdef CONFIG_PPC_PS3
1288 #include "ehci-ps3.c"
1289 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1292 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1293 #include "ehci-ppc-of.c"
1294 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1297 #ifdef CONFIG_XPS_USB_HCD_XILINX
1298 #include "ehci-xilinx-of.c"
1299 #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
1302 #ifdef CONFIG_PLAT_ORION
1303 #include "ehci-orion.c"
1304 #define PLATFORM_DRIVER ehci_orion_driver
1307 #ifdef CONFIG_ARCH_IXP4XX
1308 #include "ehci-ixp4xx.c"
1309 #define PLATFORM_DRIVER ixp4xx_ehci_driver
1312 #ifdef CONFIG_USB_W90X900_EHCI
1313 #include "ehci-w90x900.c"
1314 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1317 #ifdef CONFIG_ARCH_AT91
1318 #include "ehci-atmel.c"
1319 #define PLATFORM_DRIVER ehci_atmel_driver
1322 #ifdef CONFIG_USB_OCTEON_EHCI
1323 #include "ehci-octeon.c"
1324 #define PLATFORM_DRIVER ehci_octeon_driver
1327 #ifdef CONFIG_USB_CNS3XXX_EHCI
1328 #include "ehci-cns3xxx.c"
1329 #define PLATFORM_DRIVER cns3xxx_ehci_driver
1332 #ifdef CONFIG_ARCH_VT8500
1333 #include "ehci-vt8500.c"
1334 #define PLATFORM_DRIVER vt8500_ehci_driver
1337 #ifdef CONFIG_PLAT_SPEAR
1338 #include "ehci-spear.c"
1339 #define PLATFORM_DRIVER spear_ehci_hcd_driver
1342 #ifdef CONFIG_USB_EHCI_MSM
1343 #include "ehci-msm.c"
1344 #define PLATFORM_DRIVER ehci_msm_driver
1347 #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1348 #include "ehci-pmcmsp.c"
1349 #define PLATFORM_DRIVER ehci_hcd_msp_driver
1352 #ifdef CONFIG_USB_EHCI_TEGRA
1353 #include "ehci-tegra.c"
1354 #define PLATFORM_DRIVER tegra_ehci_driver
1357 #ifdef CONFIG_USB_EHCI_S5P
1358 #include "ehci-s5p.c"
1359 #define PLATFORM_DRIVER s5p_ehci_driver
1362 #ifdef CONFIG_SPARC_LEON
1363 #include "ehci-grlib.c"
1364 #define PLATFORM_DRIVER ehci_grlib_driver
1367 #ifdef CONFIG_CPU_XLR
1368 #include "ehci-xls.c"
1369 #define PLATFORM_DRIVER ehci_xls_driver
1372 #ifdef CONFIG_USB_EHCI_MV
1373 #include "ehci-mv.c"
1374 #define PLATFORM_DRIVER ehci_mv_driver
1377 #ifdef CONFIG_MACH_LOONGSON1
1378 #include "ehci-ls1x.c"
1379 #define PLATFORM_DRIVER ehci_ls1x_driver
1382 #ifdef CONFIG_MIPS_SEAD3
1383 #include "ehci-sead3.c"
1384 #define PLATFORM_DRIVER ehci_hcd_sead3_driver
1387 #ifdef CONFIG_USB_EHCI_HCD_PLATFORM
1388 #include "ehci-platform.c"
1389 #define PLATFORM_DRIVER ehci_platform_driver
1392 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1393 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1394 !defined(XILINX_OF_PLATFORM_DRIVER)
1395 #error "missing bus glue for ehci-hcd"
1398 static int __init ehci_hcd_init(void)
1405 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1406 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1407 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1408 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1409 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1410 " before uhci_hcd and ohci_hcd, not after\n");
1412 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1414 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1415 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1418 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1419 if (!ehci_debug_root) {
1425 #ifdef PLATFORM_DRIVER
1426 retval = platform_driver_register(&PLATFORM_DRIVER);
1432 retval = pci_register_driver(&PCI_DRIVER);
1437 #ifdef PS3_SYSTEM_BUS_DRIVER
1438 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1443 #ifdef OF_PLATFORM_DRIVER
1444 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1449 #ifdef XILINX_OF_PLATFORM_DRIVER
1450 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
1456 #ifdef XILINX_OF_PLATFORM_DRIVER
1457 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1460 #ifdef OF_PLATFORM_DRIVER
1461 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1464 #ifdef PS3_SYSTEM_BUS_DRIVER
1465 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1469 pci_unregister_driver(&PCI_DRIVER);
1472 #ifdef PLATFORM_DRIVER
1473 platform_driver_unregister(&PLATFORM_DRIVER);
1477 debugfs_remove(ehci_debug_root);
1478 ehci_debug_root = NULL;
1481 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1484 module_init(ehci_hcd_init);
1486 static void __exit ehci_hcd_cleanup(void)
1488 #ifdef XILINX_OF_PLATFORM_DRIVER
1489 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
1491 #ifdef OF_PLATFORM_DRIVER
1492 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1494 #ifdef PLATFORM_DRIVER
1495 platform_driver_unregister(&PLATFORM_DRIVER);
1498 pci_unregister_driver(&PCI_DRIVER);
1500 #ifdef PS3_SYSTEM_BUS_DRIVER
1501 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1504 debugfs_remove(ehci_debug_root);
1506 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1508 module_exit(ehci_hcd_cleanup);
1510 #endif /* CHIPIDEA_EHCI */