drivers/usb/host/ehci-hcd.c

   1 /*
   2  * Enhanced Host Controller Interface (EHCI) driver for USB.
   3  *
   4  * Maintainer: Alan Stern <stern@rowland.harvard.edu>
   5  *
   6  * Copyright (c) 2000-2004 by David Brownell
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the
  10  * Free Software Foundation; either version 2 of the License, or (at your
  11  * option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/dmapool.h>
  26 #include <linux/kernel.h>
  27 #include <linux/delay.h>
  28 #include <linux/ioport.h>
  29 #include <linux/sched.h>
  30 #include <linux/vmalloc.h>
  31 #include <linux/errno.h>
  32 #include <linux/init.h>
  33 #include <linux/timer.h>
  34 #include <linux/ktime.h>
  35 #include <linux/list.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/usb.h>
  38 #include <linux/usb/hcd.h>
  39 #include <linux/moduleparam.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/debugfs.h>
  42 #include <linux/slab.h>
  43 #include <linux/uaccess.h>
  44
  45 #include <asm/byteorder.h>
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48 #include <asm/unaligned.h>
  49
  50 #if defined(CONFIG_PPC_PS3)
  51 #include <asm/firmware.h>
  52 #endif
  53
  54 /*-------------------------------------------------------------------------*/
  55
  56 /*
  57  * EHCI hc_driver implementation ... experimental, incomplete.
  58  * Based on the final 1.0 register interface specification.
  59  *
  60  * USB 2.0 shows up in upcoming www.pcmcia.org technology.
  61  * First was PCMCIA, like ISA; then CardBus, which is PCI.
  62  * Next comes "CardBay", using USB 2.0 signals.
  63  *
  64  * Contains additional contributions by Brad Hards, Rory Bolt, and others.
  65  * Special thanks to Intel and VIA for providing host controllers to
  66  * test this driver on, and Cypress (including In-System Design) for
  67  * providing early devices for those host controllers to talk to!
  68  */
  69
  70 #define DRIVER_AUTHOR "David Brownell"
  71 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
  72
  73 static const char       hcd_name [] = "ehci_hcd";
  74
  75
  76 #undef VERBOSE_DEBUG
  77 #undef EHCI_URB_TRACE
  78
  79 #ifdef DEBUG
  80 #define EHCI_STATS
  81 #endif
  82
  83 /* magic numbers that can affect system performance */
  84 #define EHCI_TUNE_CERR          3       /* 0-3 qtd retries; 0 == don't stop */
  85 #define EHCI_TUNE_RL_HS         4       /* nak throttle; see 4.9 */
  86 #define EHCI_TUNE_RL_TT         0
  87 #define EHCI_TUNE_MULT_HS       1       /* 1-3 transactions/uframe; 4.10.3 */
  88 #define EHCI_TUNE_MULT_TT       1
  89 /*
  90  * Some drivers think it's safe to schedule isochronous transfers more than
  91  * 256 ms into the future (partly as a result of an old bug in the scheduling
  92  * code).  In an attempt to avoid trouble, we will use a minimum scheduling
  93  * length of 512 frames instead of 256.
  94  */
  95 #define EHCI_TUNE_FLS           1       /* (medium) 512-frame schedule */
  96
  97 #define EHCI_IAA_MSECS          10              /* arbitrary */
  98 #define EHCI_IO_JIFFIES         (HZ/10)         /* io watchdog > irq_thresh */
  99 #define EHCI_ASYNC_JIFFIES      (HZ/20)         /* async idle timeout */
 100 #define EHCI_SHRINK_JIFFIES     (DIV_ROUND_UP(HZ, 200) + 1)
 101                                                 /* 5-ms async qh unlink delay */
 102
 103 /* Initial IRQ latency:  faster than hw default */
 104 static int log2_irq_thresh = 0;         // 0 to 6
 105 module_param (log2_irq_thresh, int, S_IRUGO);
 106 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
 107
 108 /* initial park setting:  slower than hw default */
 109 static unsigned park = 0;
 110 module_param (park, uint, S_IRUGO);
 111 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
 112
 113 /* for flakey hardware, ignore overcurrent indicators */
 114 static bool ignore_oc = 0;
 115 module_param (ignore_oc, bool, S_IRUGO);
 116 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
 117
 118 /* for link power management(LPM) feature */
 119 static unsigned int hird;
 120 module_param(hird, int, S_IRUGO);
 121 MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
 122
 123 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
 124
 125 /*-------------------------------------------------------------------------*/
 126
 127 #include "ehci.h"
 128 #include "ehci-dbg.c"
 129 #include "pci-quirks.h"
 130
 131 /*-------------------------------------------------------------------------*/
 132
 133 static void
 134 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
 135 {
 136         /* Don't override timeouts which shrink or (later) disable
 137          * the async ring; just the I/O watchdog.  Note that if a
 138          * SHRINK were pending, OFF would never be requested.
 139          */
 140         if (timer_pending(&ehci->watchdog)
 141                         && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
 142                                 & ehci->actions))
 143                 return;
 144
 145         if (!test_and_set_bit(action, &ehci->actions)) {
 146                 unsigned long t;
 147
 148                 switch (action) {
 149                 case TIMER_IO_WATCHDOG:
 150                         if (!ehci->need_io_watchdog)
 151                                 return;
 152                         t = EHCI_IO_JIFFIES;
 153                         break;
 154                 case TIMER_ASYNC_OFF:
 155                         t = EHCI_ASYNC_JIFFIES;
 156                         break;
 157                 /* case TIMER_ASYNC_SHRINK: */
 158                 default:
 159                         t = EHCI_SHRINK_JIFFIES;
 160                         break;
 161                 }
 162                 mod_timer(&ehci->watchdog, t + jiffies);
 163         }
 164 }
 165
 166 /*-------------------------------------------------------------------------*/
 167
 168 /*
 169  * handshake - spin reading hc until handshake completes or fails
 170  * @ptr: address of hc register to be read
 171  * @mask: bits to look at in result of read
 172  * @done: value of those bits when handshake succeeds
 173  * @usec: timeout in microseconds
 174  *
 175  * Returns negative errno, or zero on success
 176  *
 177  * Success happens when the "mask" bits have the specified value (hardware
 178  * handshake done).  There are two failure modes:  "usec" have passed (major
 179  * hardware flakeout), or the register reads as all-ones (hardware removed).
 180  *
 181  * That last failure should_only happen in cases like physical cardbus eject
 182  * before driver shutdown. But it also seems to be caused by bugs in cardbus
 183  * bridge shutdown:  shutting down the bridge before the devices using it.
 184  */
 185 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
 186                       u32 mask, u32 done, int usec)
 187 {
 188         u32     result;
 189
 190         do {
 191                 result = ehci_readl(ehci, ptr);
 192                 if (result == ~(u32)0)          /* card removed */
 193                         return -ENODEV;
 194                 result &= mask;
 195                 if (result == done)
 196                         return 0;
 197                 udelay (1);
 198                 usec--;
 199         } while (usec > 0);
 200         return -ETIMEDOUT;
 201 }
 202
 203 /* check TDI/ARC silicon is in host mode */
 204 static int tdi_in_host_mode (struct ehci_hcd *ehci)
 205 {
 206         u32             tmp;
 207
 208         tmp = ehci_readl(ehci, &ehci->regs->usbmode);
 209         return (tmp & 3) == USBMODE_CM_HC;
 210 }
 211
 212 /* force HC to halt state from unknown (EHCI spec section 2.3) */
 213 static int ehci_halt (struct ehci_hcd *ehci)
 214 {
 215         u32     temp = ehci_readl(ehci, &ehci->regs->status);
 216
 217         /* disable any irqs left enabled by previous code */
 218         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 219
 220         if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) {
 221                 return 0;
 222         }
 223
 224         if ((temp & STS_HALT) != 0)
 225                 return 0;
 226
 227         /*
 228          * This routine gets called during probe before ehci->command
 229          * has been initialized, so we can't rely on its value.
 230          */
 231         ehci->command &= ~CMD_RUN;
 232         temp = ehci_readl(ehci, &ehci->regs->command);
 233         temp &= ~(CMD_RUN | CMD_IAAD);
 234         ehci_writel(ehci, temp, &ehci->regs->command);
 235         return handshake (ehci, &ehci->regs->status,
 236                           STS_HALT, STS_HALT, 16 * 125);
 237 }
 238
 239 #if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_PPC_PS3)
 240
 241 /*
 242  * The EHCI controller of the Cell Super Companion Chip used in the
 243  * PS3 will stop the root hub after all root hub ports are suspended.
 244  * When in this condition handshake will return -ETIMEDOUT.  The
 245  * STS_HLT bit will not be set, so inspection of the frame index is
 246  * used here to test for the condition.  If the condition is found
 247  * return success to allow the USB suspend to complete.
 248  */
 249
 250 static int handshake_for_broken_root_hub(struct ehci_hcd *ehci,
 251                                          void __iomem *ptr, u32 mask, u32 done,
 252                                          int usec)
 253 {
 254         unsigned int old_index;
 255         int error;
 256
 257         if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
 258                 return -ETIMEDOUT;
 259
 260         old_index = ehci_read_frame_index(ehci);
 261
 262         error = handshake(ehci, ptr, mask, done, usec);
 263
 264         if (error == -ETIMEDOUT && ehci_read_frame_index(ehci) == old_index)
 265                 return 0;
 266
 267         return error;
 268 }
 269
 270 #else
 271
 272 static int handshake_for_broken_root_hub(struct ehci_hcd *ehci,
 273                                          void __iomem *ptr, u32 mask, u32 done,
 274                                          int usec)
 275 {
 276         return -ETIMEDOUT;
 277 }
 278
 279 #endif
 280
 281 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
 282                                        u32 mask, u32 done, int usec)
 283 {
 284         int error;
 285
 286         error = handshake(ehci, ptr, mask, done, usec);
 287         if (error == -ETIMEDOUT)
 288                 error = handshake_for_broken_root_hub(ehci, ptr, mask, done,
 289                                                       usec);
 290
 291         if (error) {
 292                 ehci_halt(ehci);
 293                 ehci->rh_state = EHCI_RH_HALTED;
 294                 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
 295                         ptr, mask, done, error);
 296         }
 297
 298         return error;
 299 }
 300
 301 /* put TDI/ARC silicon into EHCI mode */
 302 static void tdi_reset (struct ehci_hcd *ehci)
 303 {
 304         u32             tmp;
 305
 306         tmp = ehci_readl(ehci, &ehci->regs->usbmode);
 307         tmp |= USBMODE_CM_HC;
 308         /* The default byte access to MMR space is LE after
 309          * controller reset. Set the required endian mode
 310          * for transfer buffers to match the host microprocessor
 311          */
 312         if (ehci_big_endian_mmio(ehci))
 313                 tmp |= USBMODE_BE;
 314         ehci_writel(ehci, tmp, &ehci->regs->usbmode);
 315 }
 316
 317 /* reset a non-running (STS_HALT == 1) controller */
 318 static int ehci_reset (struct ehci_hcd *ehci)
 319 {
 320         int     retval;
 321         u32     command = ehci_readl(ehci, &ehci->regs->command);
 322
 323         /* If the EHCI debug controller is active, special care must be
 324          * taken before and after a host controller reset */
 325         if (ehci->debug && !dbgp_reset_prep())
 326                 ehci->debug = NULL;
 327
 328         command |= CMD_RESET;
 329         dbg_cmd (ehci, "reset", command);
 330         ehci_writel(ehci, command, &ehci->regs->command);
 331         ehci->rh_state = EHCI_RH_HALTED;
 332         ehci->next_statechange = jiffies;
 333         retval = handshake (ehci, &ehci->regs->command,
 334                             CMD_RESET, 0, 250 * 1000);
 335
 336         if (ehci->has_hostpc) {
 337                 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
 338                                 &ehci->regs->usbmode_ex);
 339                 ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
 340         }
 341         if (retval)
 342                 return retval;
 343
 344         if (ehci_is_TDI(ehci))
 345                 tdi_reset (ehci);
 346
 347         if (ehci->debug)
 348                 dbgp_external_startup();
 349
 350         ehci->port_c_suspend = ehci->suspended_ports =
 351                         ehci->resuming_ports = 0;
 352         return retval;
 353 }
 354
 355 /* idle the controller (from running) */
 356 static void ehci_quiesce (struct ehci_hcd *ehci)
 357 {
 358         u32     temp;
 359
 360 #ifdef DEBUG
 361         if (ehci->rh_state != EHCI_RH_RUNNING)
 362                 BUG ();
 363 #endif
 364
 365         /* wait for any schedule enables/disables to take effect */
 366         temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
 367         if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
 368                                         STS_ASS | STS_PSS, temp, 16 * 125))
 369                 return;
 370
 371         /* then disable anything that's still active */
 372         ehci->command &= ~(CMD_ASE | CMD_PSE);
 373         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 374
 375         /* hardware can take 16 microframes to turn off ... */
 376         handshake_on_error_set_halt(ehci, &ehci->regs->status,
 377                                     STS_ASS | STS_PSS, 0, 16 * 125);
 378 }
 379
 380 /*-------------------------------------------------------------------------*/
 381
 382 static void end_unlink_async(struct ehci_hcd *ehci);
 383 static void ehci_work(struct ehci_hcd *ehci);
 384
 385 #include "ehci-hub.c"
 386 #include "ehci-lpm.c"
 387 #include "ehci-mem.c"
 388 #include "ehci-q.c"
 389 #include "ehci-sched.c"
 390 #include "ehci-sysfs.c"
 391
 392 /*-------------------------------------------------------------------------*/
 393
 394 static void ehci_iaa_watchdog(unsigned long param)
 395 {
 396         struct ehci_hcd         *ehci = (struct ehci_hcd *) param;
 397         unsigned long           flags;
 398
 399         spin_lock_irqsave (&ehci->lock, flags);
 400
 401         /* Lost IAA irqs wedge things badly; seen first with a vt8235.
 402          * So we need this watchdog, but must protect it against both
 403          * (a) SMP races against real IAA firing and retriggering, and
 404          * (b) clean HC shutdown, when IAA watchdog was pending.
 405          */
 406         if (ehci->reclaim
 407                         && !timer_pending(&ehci->iaa_watchdog)
 408                         && ehci->rh_state == EHCI_RH_RUNNING) {
 409                 u32 cmd, status;
 410
 411                 /* If we get here, IAA is *REALLY* late.  It's barely
 412                  * conceivable that the system is so busy that CMD_IAAD
 413                  * is still legitimately set, so let's be sure it's
 414                  * clear before we read STS_IAA.  (The HC should clear
 415                  * CMD_IAAD when it sets STS_IAA.)
 416                  */
 417                 cmd = ehci_readl(ehci, &ehci->regs->command);
 418
 419                 /* If IAA is set here it either legitimately triggered
 420                  * before we cleared IAAD above (but _way_ late, so we'll
 421                  * still count it as lost) ... or a silicon erratum:
 422                  * - VIA seems to set IAA without triggering the IRQ;
 423                  * - IAAD potentially cleared without setting IAA.
 424                  */
 425                 status = ehci_readl(ehci, &ehci->regs->status);
 426                 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
 427                         COUNT (ehci->stats.lost_iaa);
 428                         ehci_writel(ehci, STS_IAA, &ehci->regs->status);
 429                 }
 430
 431                 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
 432                                 status, cmd);
 433                 end_unlink_async(ehci);
 434         }
 435
 436         spin_unlock_irqrestore(&ehci->lock, flags);
 437 }
 438
 439 static void ehci_watchdog(unsigned long param)
 440 {
 441         struct ehci_hcd         *ehci = (struct ehci_hcd *) param;
 442         unsigned long           flags;
 443
 444         spin_lock_irqsave(&ehci->lock, flags);
 445
 446         /* stop async processing after it's idled a bit */
 447         if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
 448                 start_unlink_async (ehci, ehci->async);
 449
 450         /* ehci could run by timer, without IRQs ... */
 451         ehci_work (ehci);
 452
 453         spin_unlock_irqrestore (&ehci->lock, flags);
 454 }
 455
 456 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
 457  * The firmware seems to think that powering off is a wakeup event!
 458  * This routine turns off remote wakeup and everything else, on all ports.
 459  */
 460 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
 461 {
 462         int     port = HCS_N_PORTS(ehci->hcs_params);
 463
 464         while (port--)
 465                 ehci_writel(ehci, PORT_RWC_BITS,
 466                                 &ehci->regs->port_status[port]);
 467 }
 468
 469 /*
 470  * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
 471  * Should be called with ehci->lock held.
 472  */
 473 static void ehci_silence_controller(struct ehci_hcd *ehci)
 474 {
 475         ehci_halt(ehci);
 476         ehci_turn_off_all_ports(ehci);
 477
 478         /* make BIOS/etc use companion controller during reboot */
 479         ehci_writel(ehci, 0, &ehci->regs->configured_flag);
 480
 481         /* unblock posted writes */
 482         ehci_readl(ehci, &ehci->regs->configured_flag);
 483 }
 484
 485 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
 486  * This forcibly disables dma and IRQs, helping kexec and other cases
 487  * where the next system software may expect clean state.
 488  */
 489 static void ehci_shutdown(struct usb_hcd *hcd)
 490 {
 491         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 492
 493         del_timer_sync(&ehci->watchdog);
 494         del_timer_sync(&ehci->iaa_watchdog);
 495
 496         spin_lock_irq(&ehci->lock);
 497         ehci_silence_controller(ehci);
 498         spin_unlock_irq(&ehci->lock);
 499 }
 500
 501 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
 502 {
 503         unsigned port;
 504
 505         if (!HCS_PPC (ehci->hcs_params))
 506                 return;
 507
 508         ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
 509         for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
 510                 (void) ehci_hub_control(ehci_to_hcd(ehci),
 511                                 is_on ? SetPortFeature : ClearPortFeature,
 512                                 USB_PORT_FEAT_POWER,
 513                                 port--, NULL, 0);
 514         /* Flush those writes */
 515         ehci_readl(ehci, &ehci->regs->command);
 516         msleep(20);
 517 }
 518
 519 /*-------------------------------------------------------------------------*/
 520
 521 /*
 522  * ehci_work is called from some interrupts, timers, and so on.
 523  * it calls driver completion functions, after dropping ehci->lock.
 524  */
 525 static void ehci_work (struct ehci_hcd *ehci)
 526 {
 527         timer_action_done (ehci, TIMER_IO_WATCHDOG);
 528
 529         /* another CPU may drop ehci->lock during a schedule scan while
 530          * it reports urb completions.  this flag guards against bogus
 531          * attempts at re-entrant schedule scanning.
 532          */
 533         if (ehci->scanning)
 534                 return;
 535         ehci->scanning = 1;
 536         scan_async (ehci);
 537         if (ehci->next_uframe != -1)
 538                 scan_periodic (ehci);
 539         ehci->scanning = 0;
 540
 541         /* the IO watchdog guards against hardware or driver bugs that
 542          * misplace IRQs, and should let us run completely without IRQs.
 543          * such lossage has been observed on both VT6202 and VT8235.
 544          */
 545         if (ehci->rh_state == EHCI_RH_RUNNING &&
 546                         (ehci->async->qh_next.ptr != NULL ||
 547                          ehci->periodic_sched != 0))
 548                 timer_action (ehci, TIMER_IO_WATCHDOG);
 549 }
 550
 551 /*
 552  * Called when the ehci_hcd module is removed.
 553  */
 554 static void ehci_stop (struct usb_hcd *hcd)
 555 {
 556         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 557
 558         ehci_dbg (ehci, "stop\n");
 559
 560         /* no more interrupts ... */
 561         del_timer_sync (&ehci->watchdog);
 562         del_timer_sync(&ehci->iaa_watchdog);
 563
 564         spin_lock_irq(&ehci->lock);
 565         if (ehci->rh_state == EHCI_RH_RUNNING)
 566                 ehci_quiesce (ehci);
 567
 568         ehci_silence_controller(ehci);
 569         ehci_reset (ehci);
 570         spin_unlock_irq(&ehci->lock);
 571
 572         remove_sysfs_files(ehci);
 573         remove_debug_files (ehci);
 574
 575         /* root hub is shut down separately (first, when possible) */
 576         spin_lock_irq (&ehci->lock);
 577         if (ehci->async)
 578                 ehci_work (ehci);
 579         spin_unlock_irq (&ehci->lock);
 580         ehci_mem_cleanup (ehci);
 581
 582         if (ehci->amd_pll_fix == 1)
 583                 usb_amd_dev_put();
 584
 585 #ifdef  EHCI_STATS
 586         ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
 587                 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
 588                 ehci->stats.lost_iaa);
 589         ehci_dbg (ehci, "complete %ld unlink %ld\n",
 590                 ehci->stats.complete, ehci->stats.unlink);
 591 #endif
 592
 593         dbg_status (ehci, "ehci_stop completed",
 594                     ehci_readl(ehci, &ehci->regs->status));
 595 }
 596
 597 /* one-time init, only for memory state */
 598 static int ehci_init(struct usb_hcd *hcd)
 599 {
 600         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 601         u32                     temp;
 602         int                     retval;
 603         u32                     hcc_params;
 604         struct ehci_qh_hw       *hw;
 605
 606         spin_lock_init(&ehci->lock);
 607
 608         /*
 609          * keep io watchdog by default, those good HCDs could turn off it later
 610          */
 611         ehci->need_io_watchdog = 1;
 612         init_timer(&ehci->watchdog);
 613         ehci->watchdog.function = ehci_watchdog;
 614         ehci->watchdog.data = (unsigned long) ehci;
 615
 616         init_timer(&ehci->iaa_watchdog);
 617         ehci->iaa_watchdog.function = ehci_iaa_watchdog;
 618         ehci->iaa_watchdog.data = (unsigned long) ehci;
 619
 620         hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
 621
 622         /*
 623          * by default set standard 80% (== 100 usec/uframe) max periodic
 624          * bandwidth as required by USB 2.0
 625          */
 626         ehci->uframe_periodic_max = 100;
 627
 628         /*
 629          * hw default: 1K periodic list heads, one per frame.
 630          * periodic_size can shrink by USBCMD update if hcc_params allows.
 631          */
 632         ehci->periodic_size = DEFAULT_I_TDPS;
 633         INIT_LIST_HEAD(&ehci->cached_itd_list);
 634         INIT_LIST_HEAD(&ehci->cached_sitd_list);
 635
 636         if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
 637                 /* periodic schedule size can be smaller than default */
 638                 switch (EHCI_TUNE_FLS) {
 639                 case 0: ehci->periodic_size = 1024; break;
 640                 case 1: ehci->periodic_size = 512; break;
 641                 case 2: ehci->periodic_size = 256; break;
 642                 default:        BUG();
 643                 }
 644         }
 645         if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
 646                 return retval;
 647
 648         /* controllers may cache some of the periodic schedule ... */
 649         if (HCC_ISOC_CACHE(hcc_params))         // full frame cache
 650                 ehci->i_thresh = 2 + 8;
 651         else                                    // N microframes cached
 652                 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
 653
 654         ehci->reclaim = NULL;
 655         ehci->next_uframe = -1;
 656         ehci->clock_frame = -1;
 657
 658         /*
 659          * dedicate a qh for the async ring head, since we couldn't unlink
 660          * a 'real' qh without stopping the async schedule [4.8].  use it
 661          * as the 'reclamation list head' too.
 662          * its dummy is used in hw_alt_next of many tds, to prevent the qh
 663          * from automatically advancing to the next td after short reads.
 664          */
 665         ehci->async->qh_next.qh = NULL;
 666         hw = ehci->async->hw;
 667         hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
 668         hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
 669 #if defined(CONFIG_PPC_PS3)
 670         hw->hw_info1 |= cpu_to_hc32(ehci, QH_INACTIVATE);
 671 #endif
 672         hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
 673         hw->hw_qtd_next = EHCI_LIST_END(ehci);
 674         ehci->async->qh_state = QH_STATE_LINKED;
 675         hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
 676
 677         /* clear interrupt enables, set irq latency */
 678         if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
 679                 log2_irq_thresh = 0;
 680         temp = 1 << (16 + log2_irq_thresh);
 681         if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
 682                 ehci->has_ppcd = 1;
 683                 ehci_dbg(ehci, "enable per-port change event\n");
 684                 temp |= CMD_PPCEE;
 685         }
 686         if (HCC_CANPARK(hcc_params)) {
 687                 /* HW default park == 3, on hardware that supports it (like
 688                  * NVidia and ALI silicon), maximizes throughput on the async
 689                  * schedule by avoiding QH fetches between transfers.
 690                  *
 691                  * With fast usb storage devices and NForce2, "park" seems to
 692                  * make problems:  throughput reduction (!), data errors...
 693                  */
 694                 if (park) {
 695                         park = min(park, (unsigned) 3);
 696                         temp |= CMD_PARK;
 697                         temp |= park << 8;
 698                 }
 699                 ehci_dbg(ehci, "park %d\n", park);
 700         }
 701         if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
 702                 /* periodic schedule size can be smaller than default */
 703                 temp &= ~(3 << 2);
 704                 temp |= (EHCI_TUNE_FLS << 2);
 705         }
 706         if (HCC_LPM(hcc_params)) {
 707                 /* support link power management EHCI 1.1 addendum */
 708                 ehci_dbg(ehci, "support lpm\n");
 709                 ehci->has_lpm = 1;
 710                 if (hird > 0xf) {
 711                         ehci_dbg(ehci, "hird %d invalid, use default 0",
 712                         hird);
 713                         hird = 0;
 714                 }
 715                 temp |= hird << 24;
 716         }
 717         ehci->command = temp;
 718
 719         /* Accept arbitrarily long scatter-gather lists */
 720         if (!(hcd->driver->flags & HCD_LOCAL_MEM))
 721                 hcd->self.sg_tablesize = ~0;
 722         return 0;
 723 }
 724
 725 /* start HC running; it's halted, ehci_init() has been run (once) */
 726 static int ehci_run (struct usb_hcd *hcd)
 727 {
 728         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 729         u32                     temp;
 730         u32                     hcc_params;
 731
 732         hcd->uses_new_polling = 1;
 733
 734         /* EHCI spec section 4.1 */
 735
 736         ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
 737         ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
 738
 739         /*
 740          * hcc_params controls whether ehci->regs->segment must (!!!)
 741          * be used; it constrains QH/ITD/SITD and QTD locations.
 742          * pci_pool consistent memory always uses segment zero.
 743          * streaming mappings for I/O buffers, like pci_map_single(),
 744          * can return segments above 4GB, if the device allows.
 745          *
 746          * NOTE:  the dma mask is visible through dma_supported(), so
 747          * drivers can pass this info along ... like NETIF_F_HIGHDMA,
 748          * Scsi_Host.highmem_io, and so forth.  It's readonly to all
 749          * host side drivers though.
 750          */
 751         hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
 752         if (HCC_64BIT_ADDR(hcc_params)) {
 753                 ehci_writel(ehci, 0, &ehci->regs->segment);
 754 #if 0
 755 // this is deeply broken on almost all architectures
 756                 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
 757                         ehci_info(ehci, "enabled 64bit DMA\n");
 758 #endif
 759         }
 760
 761
 762         // Philips, Intel, and maybe others need CMD_RUN before the
 763         // root hub will detect new devices (why?); NEC doesn't
 764         ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
 765         ehci->command |= CMD_RUN;
 766         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 767         dbg_cmd (ehci, "init", ehci->command);
 768
 769         /*
 770          * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
 771          * are explicitly handed to companion controller(s), so no TT is
 772          * involved with the root hub.  (Except where one is integrated,
 773          * and there's no companion controller unless maybe for USB OTG.)
 774          *
 775          * Turning on the CF flag will transfer ownership of all ports
 776          * from the companions to the EHCI controller.  If any of the
 777          * companions are in the middle of a port reset at the time, it
 778          * could cause trouble.  Write-locking ehci_cf_port_reset_rwsem
 779          * guarantees that no resets are in progress.  After we set CF,
 780          * a short delay lets the hardware catch up; new resets shouldn't
 781          * be started before the port switching actions could complete.
 782          */
 783         down_write(&ehci_cf_port_reset_rwsem);
 784         ehci->rh_state = EHCI_RH_RUNNING;
 785         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 786         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
 787         msleep(5);
 788         up_write(&ehci_cf_port_reset_rwsem);
 789         ehci->last_periodic_enable = ktime_get_real();
 790
 791         temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
 792         ehci_info (ehci,
 793                 "USB %x.%x started, EHCI %x.%02x%s\n",
 794                 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
 795                 temp >> 8, temp & 0xff,
 796                 ignore_oc ? ", overcurrent ignored" : "");
 797
 798         ehci_writel(ehci, INTR_MASK,
 799                     &ehci->regs->intr_enable); /* Turn On Interrupts */
 800
 801         /* GRR this is run-once init(), being done every time the HC starts.
 802          * So long as they're part of class devices, we can't do it init()
 803          * since the class device isn't created that early.
 804          */
 805         create_debug_files(ehci);
 806         create_sysfs_files(ehci);
 807
 808         return 0;
 809 }
 810
 811 static int ehci_setup(struct usb_hcd *hcd)
 812 {
 813         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 814         int retval;
 815
 816         ehci->regs = (void __iomem *)ehci->caps +
 817             HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
 818         dbg_hcs_params(ehci, "reset");
 819         dbg_hcc_params(ehci, "reset");
 820
 821         /* cache this readonly data; minimize chip reads */
 822         ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
 823
 824         ehci->sbrn = HCD_USB2;
 825
 826         /* data structure init */
 827         retval = ehci_init(hcd);
 828         if (retval)
 829                 return retval;
 830
 831         retval = ehci_halt(ehci);
 832         if (retval)
 833                 return retval;
 834
 835         if (ehci_is_TDI(ehci))
 836                 tdi_reset(ehci);
 837
 838         ehci_reset(ehci);
 839
 840         return 0;
 841 }
 842
 843 /*-------------------------------------------------------------------------*/
 844
 845 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
 846 {
 847         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 848         u32                     status, masked_status, pcd_status = 0, cmd;
 849         int                     bh;
 850
 851         spin_lock (&ehci->lock);
 852
 853         status = ehci_readl(ehci, &ehci->regs->status);
 854
 855         /* e.g. cardbus physical eject */
 856         if (status == ~(u32) 0) {
 857                 ehci_dbg (ehci, "device removed\n");
 858                 goto dead;
 859         }
 860
 861         /*
 862          * We don't use STS_FLR, but some controllers don't like it to
 863          * remain on, so mask it out along with the other status bits.
 864          */
 865         masked_status = status & (INTR_MASK | STS_FLR);
 866
 867         /* Shared IRQ? */
 868         if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
 869                 spin_unlock(&ehci->lock);
 870                 return IRQ_NONE;
 871         }
 872
 873         /* clear (just) interrupts */
 874         ehci_writel(ehci, masked_status, &ehci->regs->status);
 875         cmd = ehci_readl(ehci, &ehci->regs->command);
 876         bh = 0;
 877
 878 #ifdef  VERBOSE_DEBUG
 879         /* unrequested/ignored: Frame List Rollover */
 880         dbg_status (ehci, "irq", status);
 881 #endif
 882
 883         /* INT, ERR, and IAA interrupt rates can be throttled */
 884
 885         /* normal [4.15.1.2] or error [4.15.1.1] completion */
 886         if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
 887                 if (likely ((status & STS_ERR) == 0))
 888                         COUNT (ehci->stats.normal);
 889                 else
 890                         COUNT (ehci->stats.error);
 891                 bh = 1;
 892         }
 893
 894         /* complete the unlinking of some qh [4.15.2.3] */
 895         if (status & STS_IAA) {
 896                 /* guard against (alleged) silicon errata */
 897                 if (cmd & CMD_IAAD)
 898                         ehci_dbg(ehci, "IAA with IAAD still set?\n");
 899                 if (ehci->reclaim) {
 900                         COUNT(ehci->stats.reclaim);
 901                         end_unlink_async(ehci);
 902                 } else
 903                         ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
 904         }
 905
 906         /* remote wakeup [4.3.1] */
 907         if (status & STS_PCD) {
 908                 unsigned        i = HCS_N_PORTS (ehci->hcs_params);
 909                 u32             ppcd = 0;
 910
 911                 /* kick root hub later */
 912                 pcd_status = status;
 913
 914                 /* resume root hub? */
 915                 if (ehci->rh_state == EHCI_RH_SUSPENDED)
 916                         usb_hcd_resume_root_hub(hcd);
 917
 918                 /* get per-port change detect bits */
 919                 if (ehci->has_ppcd)
 920                         ppcd = status >> 16;
 921
 922                 while (i--) {
 923                         int pstatus;
 924
 925                         /* leverage per-port change bits feature */
 926                         if (ehci->has_ppcd && !(ppcd & (1 << i)))
 927                                 continue;
 928                         pstatus = ehci_readl(ehci,
 929                                          &ehci->regs->port_status[i]);
 930
 931                         if (pstatus & PORT_OWNER)
 932                                 continue;
 933                         if (!(test_bit(i, &ehci->suspended_ports) &&
 934                                         ((pstatus & PORT_RESUME) ||
 935                                                 !(pstatus & PORT_SUSPEND)) &&
 936                                         (pstatus & PORT_PE) &&
 937                                         ehci->reset_done[i] == 0))
 938                                 continue;
 939
 940                         /* start 20 msec resume signaling from this port,
 941                          * and make khubd collect PORT_STAT_C_SUSPEND to
 942                          * stop that signaling.  Use 5 ms extra for safety,
 943                          * like usb_port_resume() does.
 944                          */
 945                         ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
 946                         set_bit(i, &ehci->resuming_ports);
 947                         ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
 948                         mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
 949                 }
 950         }
 951
 952         /* PCI errors [4.15.2.4] */
 953         if (unlikely ((status & STS_FATAL) != 0)) {
 954                 ehci_err(ehci, "fatal error\n");
 955                 dbg_cmd(ehci, "fatal", cmd);
 956                 dbg_status(ehci, "fatal", status);
 957                 ehci_halt(ehci);
 958 dead:
 959                 ehci_reset(ehci);
 960                 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
 961                 usb_hc_died(hcd);
 962                 /* generic layer kills/unlinks all urbs, then
 963                  * uses ehci_stop to clean up the rest
 964                  */
 965                 bh = 1;
 966         }
 967
 968         if (bh)
 969                 ehci_work (ehci);
 970         spin_unlock (&ehci->lock);
 971         if (pcd_status)
 972                 usb_hcd_poll_rh_status(hcd);
 973         return IRQ_HANDLED;
 974 }
 975
 976 /*-------------------------------------------------------------------------*/
 977
 978 /*
 979  * non-error returns are a promise to giveback() the urb later
 980  * we drop ownership so next owner (or urb unlink) can get it
 981  *
 982  * urb + dev is in hcd.self.controller.urb_list
 983  * we're queueing TDs onto software and hardware lists
 984  *
 985  * hcd-specific init for hcpriv hasn't been done yet
 986  *
 987  * NOTE:  control, bulk, and interrupt share the same code to append TDs
 988  * to a (possibly active) QH, and the same QH scanning code.
 989  */
 990 static int ehci_urb_enqueue (
 991         struct usb_hcd  *hcd,
 992         struct urb      *urb,
 993         gfp_t           mem_flags
 994 ) {
 995         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 996         struct list_head        qtd_list;
 997
 998         INIT_LIST_HEAD (&qtd_list);
 999
1000         switch (usb_pipetype (urb->pipe)) {
1001         case PIPE_CONTROL:
1002                 /* qh_completions() code doesn't handle all the fault cases
1003                  * in multi-TD control transfers.  Even 1KB is rare anyway.
1004                  */
1005                 if (urb->transfer_buffer_length > (16 * 1024))
1006                         return -EMSGSIZE;
1007                 /* FALLTHROUGH */
1008         /* case PIPE_BULK: */
1009         default:
1010                 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1011                         return -ENOMEM;
1012                 return submit_async(ehci, urb, &qtd_list, mem_flags);
1013
1014         case PIPE_INTERRUPT:
1015                 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1016                         return -ENOMEM;
1017                 return intr_submit(ehci, urb, &qtd_list, mem_flags);
1018
1019         case PIPE_ISOCHRONOUS:
1020                 if (urb->dev->speed == USB_SPEED_HIGH)
1021                         return itd_submit (ehci, urb, mem_flags);
1022                 else
1023                         return sitd_submit (ehci, urb, mem_flags);
1024         }
1025 }
1026
1027 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
1028 {
1029         /* failfast */
1030         if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim)
1031                 end_unlink_async(ehci);
1032
1033         /* If the QH isn't linked then there's nothing we can do
1034          * unless we were called during a giveback, in which case
1035          * qh_completions() has to deal with it.
1036          */
1037         if (qh->qh_state != QH_STATE_LINKED) {
1038                 if (qh->qh_state == QH_STATE_COMPLETING)
1039                         qh->needs_rescan = 1;
1040                 return;
1041         }
1042
1043         /* defer till later if busy */
1044         if (ehci->reclaim) {
1045                 struct ehci_qh          *last;
1046
1047                 for (last = ehci->reclaim;
1048                                 last->reclaim;
1049                                 last = last->reclaim)
1050                         continue;
1051                 qh->qh_state = QH_STATE_UNLINK_WAIT;
1052                 last->reclaim = qh;
1053
1054         /* start IAA cycle */
1055         } else
1056                 start_unlink_async (ehci, qh);
1057 }
1058
1059 /* remove from hardware lists
1060  * completions normally happen asynchronously
1061  */
1062
1063 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1064 {
1065         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
1066         struct ehci_qh          *qh;
1067         unsigned long           flags;
1068         int                     rc;
1069
1070         spin_lock_irqsave (&ehci->lock, flags);
1071         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
1072         if (rc)
1073                 goto done;
1074
1075         switch (usb_pipetype (urb->pipe)) {
1076         // case PIPE_CONTROL:
1077         // case PIPE_BULK:
1078         default:
1079                 qh = (struct ehci_qh *) urb->hcpriv;
1080                 if (!qh)
1081                         break;
1082                 switch (qh->qh_state) {
1083                 case QH_STATE_LINKED:
1084                 case QH_STATE_COMPLETING:
1085                         unlink_async(ehci, qh);
1086                         break;
1087                 case QH_STATE_UNLINK:
1088                 case QH_STATE_UNLINK_WAIT:
1089                         /* already started */
1090                         break;
1091                 case QH_STATE_IDLE:
1092                         /* QH might be waiting for a Clear-TT-Buffer */
1093                         qh_completions(ehci, qh);
1094                         break;
1095                 }
1096                 break;
1097
1098         case PIPE_INTERRUPT:
1099                 qh = (struct ehci_qh *) urb->hcpriv;
1100                 if (!qh)
1101                         break;
1102                 switch (qh->qh_state) {
1103                 case QH_STATE_LINKED:
1104                 case QH_STATE_COMPLETING:
1105                         intr_deschedule (ehci, qh);
1106                         break;
1107                 case QH_STATE_IDLE:
1108                         qh_completions (ehci, qh);
1109                         break;
1110                 default:
1111                         ehci_dbg (ehci, "bogus qh %p state %d\n",
1112                                         qh, qh->qh_state);
1113                         goto done;
1114                 }
1115                 break;
1116
1117         case PIPE_ISOCHRONOUS:
1118                 // itd or sitd ...
1119
1120                 // wait till next completion, do it then.
1121                 // completion irqs can wait up to 1024 msec,
1122                 break;
1123         }
1124 done:
1125         spin_unlock_irqrestore (&ehci->lock, flags);
1126         return rc;
1127 }
1128
1129 /*-------------------------------------------------------------------------*/
1130
1131 // bulk qh holds the data toggle
1132
1133 static void
1134 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1135 {
1136         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
1137         unsigned long           flags;
1138         struct ehci_qh          *qh, *tmp;
1139
1140         /* ASSERT:  any requests/urbs are being unlinked */
1141         /* ASSERT:  nobody can be submitting urbs for this any more */
1142
1143 rescan:
1144         spin_lock_irqsave (&ehci->lock, flags);
1145         qh = ep->hcpriv;
1146         if (!qh)
1147                 goto done;
1148
1149         /* endpoints can be iso streams.  for now, we don't
1150          * accelerate iso completions ... so spin a while.
1151          */
1152         if (qh->hw == NULL) {
1153                 ehci_vdbg (ehci, "iso delay\n");
1154                 goto idle_timeout;
1155         }
1156
1157         if (ehci->rh_state != EHCI_RH_RUNNING)
1158                 qh->qh_state = QH_STATE_IDLE;
1159         switch (qh->qh_state) {
1160         case QH_STATE_LINKED:
1161         case QH_STATE_COMPLETING:
1162                 for (tmp = ehci->async->qh_next.qh;
1163                                 tmp && tmp != qh;
1164                                 tmp = tmp->qh_next.qh)
1165                         continue;
1166                 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1167                  * may already be unlinked.
1168                  */
1169                 if (tmp)
1170                         unlink_async(ehci, qh);
1171                 /* FALL THROUGH */
1172         case QH_STATE_UNLINK:           /* wait for hw to finish? */
1173         case QH_STATE_UNLINK_WAIT:
1174 idle_timeout:
1175                 spin_unlock_irqrestore (&ehci->lock, flags);
1176                 schedule_timeout_uninterruptible(1);
1177                 goto rescan;
1178         case QH_STATE_IDLE:             /* fully unlinked */
1179                 if (qh->clearing_tt)
1180                         goto idle_timeout;
1181                 if (list_empty (&qh->qtd_list)) {
1182                         qh_destroy(ehci, qh);
1183                         break;
1184                 }
1185                 /* else FALL THROUGH */
1186         default:
1187                 /* caller was supposed to have unlinked any requests;
1188                  * that's not our job.  just leak this memory.
1189                  */
1190                 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1191                         qh, ep->desc.bEndpointAddress, qh->qh_state,
1192                         list_empty (&qh->qtd_list) ? "" : "(has tds)");
1193                 break;
1194         }
1195         ep->hcpriv = NULL;
1196 done:
1197         spin_unlock_irqrestore (&ehci->lock, flags);
1198 }
1199
1200 static void
1201 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1202 {
1203         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
1204         struct ehci_qh          *qh;
1205         int                     eptype = usb_endpoint_type(&ep->desc);
1206         int                     epnum = usb_endpoint_num(&ep->desc);
1207         int                     is_out = usb_endpoint_dir_out(&ep->desc);
1208         unsigned long           flags;
1209
1210         if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1211                 return;
1212
1213         spin_lock_irqsave(&ehci->lock, flags);
1214         qh = ep->hcpriv;
1215
1216         /* For Bulk and Interrupt endpoints we maintain the toggle state
1217          * in the hardware; the toggle bits in udev aren't used at all.
1218          * When an endpoint is reset by usb_clear_halt() we must reset
1219          * the toggle bit in the QH.
1220          */
1221         if (qh) {
1222                 usb_settoggle(qh->dev, epnum, is_out, 0);
1223                 if (!list_empty(&qh->qtd_list)) {
1224                         WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1225                 } else if (qh->qh_state == QH_STATE_LINKED ||
1226                                 qh->qh_state == QH_STATE_COMPLETING) {
1227
1228                         /* The toggle value in the QH can't be updated
1229                          * while the QH is active.  Unlink it now;
1230                          * re-linking will call qh_refresh().
1231                          */
1232                         if (eptype == USB_ENDPOINT_XFER_BULK)
1233                                 unlink_async(ehci, qh);
1234                         else
1235                                 intr_deschedule(ehci, qh);
1236                 }
1237         }
1238         spin_unlock_irqrestore(&ehci->lock, flags);
1239 }
1240
1241 static int ehci_get_frame (struct usb_hcd *hcd)
1242 {
1243         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
1244         return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
1245 }
1246
1247 /*-------------------------------------------------------------------------*/
1248
1249 #ifdef  CONFIG_PM
1250
1251 /* suspend/resume, section 4.3 */
1252
1253 /* These routines handle the generic parts of controller suspend/resume */
1254
1255 static int __maybe_unused ehci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1256 {
1257         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
1258
1259         if (time_before(jiffies, ehci->next_statechange))
1260                 msleep(10);
1261
1262         /*
1263          * Root hub was already suspended.  Disable IRQ emission and
1264          * mark HW unaccessible.  The PM and USB cores make sure that
1265          * the root hub is either suspended or stopped.
1266          */
1267         ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
1268
1269         spin_lock_irq(&ehci->lock);
1270         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
1271         (void) ehci_readl(ehci, &ehci->regs->intr_enable);
1272
1273         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1274         spin_unlock_irq(&ehci->lock);
1275
1276         return 0;
1277 }
1278
1279 /* Returns 0 if power was preserved, 1 if power was lost */
1280 static int __maybe_unused ehci_resume(struct usb_hcd *hcd, bool hibernated)
1281 {
1282         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
1283
1284         if (time_before(jiffies, ehci->next_statechange))
1285                 msleep(100);
1286
1287         /* Mark hardware accessible again as we are back to full power by now */
1288         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1289
1290         /*
1291          * If CF is still set and we aren't resuming from hibernation
1292          * then we maintained suspend power.
1293          * Just undo the effect of ehci_suspend().
1294          */
1295         if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
1296                         !hibernated) {
1297                 int     mask = INTR_MASK;
1298
1299                 ehci_prepare_ports_for_controller_resume(ehci);
1300                 if (!hcd->self.root_hub->do_remote_wakeup)
1301                         mask &= ~STS_PCD;
1302                 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
1303                 ehci_readl(ehci, &ehci->regs->intr_enable);
1304                 return 0;
1305         }
1306
1307         /*
1308          * Else reset, to cope with power loss or resume from hibernation
1309          * having let the firmware kick in during reboot.
1310          */
1311         usb_root_hub_lost_power(hcd->self.root_hub);
1312         (void) ehci_halt(ehci);
1313         (void) ehci_reset(ehci);
1314
1315         ehci_writel(ehci, ehci->command, &ehci->regs->command);
1316         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
1317         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
1318
1319         /* here we "know" root ports should always stay powered */
1320         ehci_port_power(ehci, 1);
1321
1322         ehci->rh_state = EHCI_RH_SUSPENDED;
1323         return 1;
1324 }
1325
1326 #endif
1327
1328 /*-------------------------------------------------------------------------*/
1329
1330 /*
1331  * The EHCI in ChipIdea HDRC cannot be a separate module or device,
1332  * because its registers (and irq) are shared between host/gadget/otg
1333  * functions  and in order to facilitate role switching we cannot
1334  * give the ehci driver exclusive access to those.
1335  */
1336 #ifndef CHIPIDEA_EHCI
1337
1338 MODULE_DESCRIPTION(DRIVER_DESC);
1339 MODULE_AUTHOR (DRIVER_AUTHOR);
1340 MODULE_LICENSE ("GPL");
1341
1342 #ifdef CONFIG_PCI
1343 #include "ehci-pci.c"
1344 #define PCI_DRIVER              ehci_pci_driver
1345 #endif
1346
1347 #ifdef CONFIG_USB_EHCI_FSL
1348 #include "ehci-fsl.c"
1349 #define PLATFORM_DRIVER         ehci_fsl_driver
1350 #endif
1351
1352 #ifdef CONFIG_USB_EHCI_MXC
1353 #include "ehci-mxc.c"
1354 #define PLATFORM_DRIVER         ehci_mxc_driver
1355 #endif
1356
1357 #ifdef CONFIG_USB_EHCI_SH
1358 #include "ehci-sh.c"
1359 #define PLATFORM_DRIVER         ehci_hcd_sh_driver
1360 #endif
1361
1362 #ifdef CONFIG_MIPS_ALCHEMY
1363 #include "ehci-au1xxx.c"
1364 #define PLATFORM_DRIVER         ehci_hcd_au1xxx_driver
1365 #endif
1366
1367 #ifdef CONFIG_USB_EHCI_HCD_OMAP
1368 #include "ehci-omap.c"
1369 #define        PLATFORM_DRIVER         ehci_hcd_omap_driver
1370 #endif
1371
1372 #ifdef CONFIG_PPC_PS3
1373 #include "ehci-ps3.c"
1374 #define PS3_SYSTEM_BUS_DRIVER   ps3_ehci_driver
1375 #endif
1376
1377 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1378 #include "ehci-ppc-of.c"
1379 #define OF_PLATFORM_DRIVER      ehci_hcd_ppc_of_driver
1380 #endif
1381
1382 #ifdef CONFIG_XPS_USB_HCD_XILINX
1383 #include "ehci-xilinx-of.c"
1384 #define XILINX_OF_PLATFORM_DRIVER       ehci_hcd_xilinx_of_driver
1385 #endif
1386
1387 #ifdef CONFIG_PLAT_ORION
1388 #include "ehci-orion.c"
1389 #define PLATFORM_DRIVER         ehci_orion_driver
1390 #endif
1391
1392 #ifdef CONFIG_ARCH_IXP4XX
1393 #include "ehci-ixp4xx.c"
1394 #define PLATFORM_DRIVER         ixp4xx_ehci_driver
1395 #endif
1396
1397 #ifdef CONFIG_USB_W90X900_EHCI
1398 #include "ehci-w90x900.c"
1399 #define PLATFORM_DRIVER         ehci_hcd_w90x900_driver
1400 #endif
1401
1402 #ifdef CONFIG_ARCH_AT91
1403 #include "ehci-atmel.c"
1404 #define PLATFORM_DRIVER         ehci_atmel_driver
1405 #endif
1406
1407 #ifdef CONFIG_USB_OCTEON_EHCI
1408 #include "ehci-octeon.c"
1409 #define PLATFORM_DRIVER         ehci_octeon_driver
1410 #endif
1411
1412 #ifdef CONFIG_USB_CNS3XXX_EHCI
1413 #include "ehci-cns3xxx.c"
1414 #define PLATFORM_DRIVER         cns3xxx_ehci_driver
1415 #endif
1416
1417 #ifdef CONFIG_ARCH_VT8500
1418 #include "ehci-vt8500.c"
1419 #define PLATFORM_DRIVER         vt8500_ehci_driver
1420 #endif
1421
1422 #ifdef CONFIG_PLAT_SPEAR
1423 #include "ehci-spear.c"
1424 #define PLATFORM_DRIVER         spear_ehci_hcd_driver
1425 #endif
1426
1427 #ifdef CONFIG_USB_EHCI_MSM
1428 #include "ehci-msm.c"
1429 #define PLATFORM_DRIVER         ehci_msm_driver
1430 #endif
1431
1432 #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1433 #include "ehci-pmcmsp.c"
1434 #define PLATFORM_DRIVER         ehci_hcd_msp_driver
1435 #endif
1436
1437 #ifdef CONFIG_USB_EHCI_TEGRA
1438 #include "ehci-tegra.c"
1439 #define PLATFORM_DRIVER         tegra_ehci_driver
1440 #endif
1441
1442 #ifdef CONFIG_USB_EHCI_S5P
1443 #include "ehci-s5p.c"
1444 #define PLATFORM_DRIVER         s5p_ehci_driver
1445 #endif
1446
1447 #ifdef CONFIG_SPARC_LEON
1448 #include "ehci-grlib.c"
1449 #define PLATFORM_DRIVER         ehci_grlib_driver
1450 #endif
1451
1452 #ifdef CONFIG_CPU_XLR
1453 #include "ehci-xls.c"
1454 #define PLATFORM_DRIVER         ehci_xls_driver
1455 #endif
1456
1457 #ifdef CONFIG_USB_EHCI_MV
1458 #include "ehci-mv.c"
1459 #define        PLATFORM_DRIVER         ehci_mv_driver
1460 #endif
1461
1462 #ifdef CONFIG_MACH_LOONGSON1
1463 #include "ehci-ls1x.c"
1464 #define PLATFORM_DRIVER         ehci_ls1x_driver
1465 #endif
1466
1467 #ifdef CONFIG_MIPS_SEAD3
1468 #include "ehci-sead3.c"
1469 #define PLATFORM_DRIVER         ehci_hcd_sead3_driver
1470 #endif
1471
1472 #ifdef CONFIG_USB_EHCI_HCD_PLATFORM
1473 #include "ehci-platform.c"
1474 #define PLATFORM_DRIVER         ehci_platform_driver
1475 #endif
1476
1477 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1478     !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1479     !defined(XILINX_OF_PLATFORM_DRIVER)
1480 #error "missing bus glue for ehci-hcd"
1481 #endif
1482
1483 static int __init ehci_hcd_init(void)
1484 {
1485         int retval = 0;
1486
1487         if (usb_disabled())
1488                 return -ENODEV;
1489
1490         printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1491         set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1492         if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1493                         test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1494                 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1495                                 " before uhci_hcd and ohci_hcd, not after\n");
1496
1497         pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1498                  hcd_name,
1499                  sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1500                  sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1501
1502 #ifdef DEBUG
1503         ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1504         if (!ehci_debug_root) {
1505                 retval = -ENOENT;
1506                 goto err_debug;
1507         }
1508 #endif
1509
1510 #ifdef PLATFORM_DRIVER
1511         retval = platform_driver_register(&PLATFORM_DRIVER);
1512         if (retval < 0)
1513                 goto clean0;
1514 #endif
1515
1516 #ifdef PCI_DRIVER
1517         retval = pci_register_driver(&PCI_DRIVER);
1518         if (retval < 0)
1519                 goto clean1;
1520 #endif
1521
1522 #ifdef PS3_SYSTEM_BUS_DRIVER
1523         retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1524         if (retval < 0)
1525                 goto clean2;
1526 #endif
1527
1528 #ifdef OF_PLATFORM_DRIVER
1529         retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1530         if (retval < 0)
1531                 goto clean3;
1532 #endif
1533
1534 #ifdef XILINX_OF_PLATFORM_DRIVER
1535         retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
1536         if (retval < 0)
1537                 goto clean4;
1538 #endif
1539         return retval;
1540
1541 #ifdef XILINX_OF_PLATFORM_DRIVER
1542         /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1543 clean4:
1544 #endif
1545 #ifdef OF_PLATFORM_DRIVER
1546         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1547 clean3:
1548 #endif
1549 #ifdef PS3_SYSTEM_BUS_DRIVER
1550         ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1551 clean2:
1552 #endif
1553 #ifdef PCI_DRIVER
1554         pci_unregister_driver(&PCI_DRIVER);
1555 clean1:
1556 #endif
1557 #ifdef PLATFORM_DRIVER
1558         platform_driver_unregister(&PLATFORM_DRIVER);
1559 clean0:
1560 #endif
1561 #ifdef DEBUG
1562         debugfs_remove(ehci_debug_root);
1563         ehci_debug_root = NULL;
1564 err_debug:
1565 #endif
1566         clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1567         return retval;
1568 }
1569 module_init(ehci_hcd_init);
1570
1571 static void __exit ehci_hcd_cleanup(void)
1572 {
1573 #ifdef XILINX_OF_PLATFORM_DRIVER
1574         platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
1575 #endif
1576 #ifdef OF_PLATFORM_DRIVER
1577         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1578 #endif
1579 #ifdef PLATFORM_DRIVER
1580         platform_driver_unregister(&PLATFORM_DRIVER);
1581 #endif
1582 #ifdef PCI_DRIVER
1583         pci_unregister_driver(&PCI_DRIVER);
1584 #endif
1585 #ifdef PS3_SYSTEM_BUS_DRIVER
1586         ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1587 #endif
1588 #ifdef DEBUG
1589         debugfs_remove(ehci_debug_root);
1590 #endif
1591         clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1592 }
1593 module_exit(ehci_hcd_cleanup);
1594
1595 #endif /* CHIPIDEA_EHCI */