2 * Enhanced Host Controller Interface (EHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * Copyright (c) 2000-2004 by David Brownell
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/dmapool.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/vmalloc.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/ktime.h>
35 #include <linux/list.h>
36 #include <linux/interrupt.h>
37 #include <linux/usb.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/moduleparam.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/debugfs.h>
42 #include <linux/slab.h>
43 #include <linux/uaccess.h>
45 #include <asm/byteorder.h>
48 #include <asm/system.h>
49 #include <asm/unaligned.h>
51 /*-------------------------------------------------------------------------*/
54 * EHCI hc_driver implementation ... experimental, incomplete.
55 * Based on the final 1.0 register interface specification.
57 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
58 * First was PCMCIA, like ISA; then CardBus, which is PCI.
59 * Next comes "CardBay", using USB 2.0 signals.
61 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
62 * Special thanks to Intel and VIA for providing host controllers to
63 * test this driver on, and Cypress (including In-System Design) for
64 * providing early devices for those host controllers to talk to!
67 #define DRIVER_AUTHOR "David Brownell"
68 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
70 static const char hcd_name [] = "ehci_hcd";
80 /* magic numbers that can affect system performance */
81 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
82 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
83 #define EHCI_TUNE_RL_TT 0
84 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
85 #define EHCI_TUNE_MULT_TT 1
87 * Some drivers think it's safe to schedule isochronous transfers more than
88 * 256 ms into the future (partly as a result of an old bug in the scheduling
89 * code). In an attempt to avoid trouble, we will use a minimum scheduling
90 * length of 512 frames instead of 256.
92 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
94 #define EHCI_IAA_MSECS 10 /* arbitrary */
95 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
96 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
97 #define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */
99 /* Initial IRQ latency: faster than hw default */
100 static int log2_irq_thresh = 0; // 0 to 6
101 module_param (log2_irq_thresh, int, S_IRUGO);
102 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
104 /* initial park setting: slower than hw default */
105 static unsigned park = 0;
106 module_param (park, uint, S_IRUGO);
107 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
109 /* for flakey hardware, ignore overcurrent indicators */
110 static int ignore_oc = 0;
111 module_param (ignore_oc, bool, S_IRUGO);
112 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
114 /* for link power management(LPM) feature */
115 static unsigned int hird;
116 module_param(hird, int, S_IRUGO);
117 MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us\n");
119 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
121 /*-------------------------------------------------------------------------*/
124 #include "ehci-dbg.c"
125 #include "pci-quirks.h"
127 /*-------------------------------------------------------------------------*/
130 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
132 /* Don't override timeouts which shrink or (later) disable
133 * the async ring; just the I/O watchdog. Note that if a
134 * SHRINK were pending, OFF would never be requested.
136 if (timer_pending(&ehci->watchdog)
137 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
141 if (!test_and_set_bit(action, &ehci->actions)) {
145 case TIMER_IO_WATCHDOG:
146 if (!ehci->need_io_watchdog)
150 case TIMER_ASYNC_OFF:
151 t = EHCI_ASYNC_JIFFIES;
153 /* case TIMER_ASYNC_SHRINK: */
155 /* add a jiffie since we synch against the
156 * 8 KHz uframe counter.
158 t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1;
161 mod_timer(&ehci->watchdog, t + jiffies);
165 /*-------------------------------------------------------------------------*/
168 * handshake - spin reading hc until handshake completes or fails
169 * @ptr: address of hc register to be read
170 * @mask: bits to look at in result of read
171 * @done: value of those bits when handshake succeeds
172 * @usec: timeout in microseconds
174 * Returns negative errno, or zero on success
176 * Success happens when the "mask" bits have the specified value (hardware
177 * handshake done). There are two failure modes: "usec" have passed (major
178 * hardware flakeout), or the register reads as all-ones (hardware removed).
180 * That last failure should_only happen in cases like physical cardbus eject
181 * before driver shutdown. But it also seems to be caused by bugs in cardbus
182 * bridge shutdown: shutting down the bridge before the devices using it.
184 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
185 u32 mask, u32 done, int usec)
190 result = ehci_readl(ehci, ptr);
191 if (result == ~(u32)0) /* card removed */
202 /* check TDI/ARC silicon is in host mode */
203 static int tdi_in_host_mode (struct ehci_hcd *ehci)
205 u32 __iomem *reg_ptr;
208 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
209 tmp = ehci_readl(ehci, reg_ptr);
210 return (tmp & 3) == USBMODE_CM_HC;
213 /* force HC to halt state from unknown (EHCI spec section 2.3) */
214 static int ehci_halt (struct ehci_hcd *ehci)
216 u32 temp = ehci_readl(ehci, &ehci->regs->status);
218 /* disable any irqs left enabled by previous code */
219 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
221 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) {
225 if ((temp & STS_HALT) != 0)
228 temp = ehci_readl(ehci, &ehci->regs->command);
230 ehci_writel(ehci, temp, &ehci->regs->command);
231 return handshake (ehci, &ehci->regs->status,
232 STS_HALT, STS_HALT, 16 * 125);
235 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
236 u32 mask, u32 done, int usec)
240 error = handshake(ehci, ptr, mask, done, usec);
243 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
244 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
245 ptr, mask, done, error);
251 /* put TDI/ARC silicon into EHCI mode */
252 static void tdi_reset (struct ehci_hcd *ehci)
254 u32 __iomem *reg_ptr;
257 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
258 tmp = ehci_readl(ehci, reg_ptr);
259 tmp |= USBMODE_CM_HC;
260 /* The default byte access to MMR space is LE after
261 * controller reset. Set the required endian mode
262 * for transfer buffers to match the host microprocessor
264 if (ehci_big_endian_mmio(ehci))
266 ehci_writel(ehci, tmp, reg_ptr);
269 /* reset a non-running (STS_HALT == 1) controller */
270 static int ehci_reset (struct ehci_hcd *ehci)
273 u32 command = ehci_readl(ehci, &ehci->regs->command);
275 /* If the EHCI debug controller is active, special care must be
276 * taken before and after a host controller reset */
277 if (ehci->debug && !dbgp_reset_prep())
280 command |= CMD_RESET;
281 dbg_cmd (ehci, "reset", command);
282 ehci_writel(ehci, command, &ehci->regs->command);
283 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
284 ehci->next_statechange = jiffies;
285 retval = handshake (ehci, &ehci->regs->command,
286 CMD_RESET, 0, 250 * 1000);
288 if (ehci->has_hostpc) {
289 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
290 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));
291 ehci_writel(ehci, TXFIFO_DEFAULT,
292 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
297 if (ehci_is_TDI(ehci))
301 dbgp_external_startup();
306 /* idle the controller (from running) */
307 static void ehci_quiesce (struct ehci_hcd *ehci)
312 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
316 /* wait for any schedule enables/disables to take effect */
317 temp = ehci_readl(ehci, &ehci->regs->command) << 10;
318 temp &= STS_ASS | STS_PSS;
319 if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
320 STS_ASS | STS_PSS, temp, 16 * 125))
323 /* then disable anything that's still active */
324 temp = ehci_readl(ehci, &ehci->regs->command);
325 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
326 ehci_writel(ehci, temp, &ehci->regs->command);
328 /* hardware can take 16 microframes to turn off ... */
329 handshake_on_error_set_halt(ehci, &ehci->regs->status,
330 STS_ASS | STS_PSS, 0, 16 * 125);
333 /*-------------------------------------------------------------------------*/
335 static void end_unlink_async(struct ehci_hcd *ehci);
336 static void ehci_work(struct ehci_hcd *ehci);
338 #include "ehci-hub.c"
339 #include "ehci-lpm.c"
340 #include "ehci-mem.c"
342 #include "ehci-sched.c"
344 /*-------------------------------------------------------------------------*/
346 static void ehci_iaa_watchdog(unsigned long param)
348 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
351 spin_lock_irqsave (&ehci->lock, flags);
353 /* Lost IAA irqs wedge things badly; seen first with a vt8235.
354 * So we need this watchdog, but must protect it against both
355 * (a) SMP races against real IAA firing and retriggering, and
356 * (b) clean HC shutdown, when IAA watchdog was pending.
359 && !timer_pending(&ehci->iaa_watchdog)
360 && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
363 /* If we get here, IAA is *REALLY* late. It's barely
364 * conceivable that the system is so busy that CMD_IAAD
365 * is still legitimately set, so let's be sure it's
366 * clear before we read STS_IAA. (The HC should clear
367 * CMD_IAAD when it sets STS_IAA.)
369 cmd = ehci_readl(ehci, &ehci->regs->command);
371 ehci_writel(ehci, cmd & ~CMD_IAAD,
372 &ehci->regs->command);
374 /* If IAA is set here it either legitimately triggered
375 * before we cleared IAAD above (but _way_ late, so we'll
376 * still count it as lost) ... or a silicon erratum:
377 * - VIA seems to set IAA without triggering the IRQ;
378 * - IAAD potentially cleared without setting IAA.
380 status = ehci_readl(ehci, &ehci->regs->status);
381 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
382 COUNT (ehci->stats.lost_iaa);
383 ehci_writel(ehci, STS_IAA, &ehci->regs->status);
386 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
388 end_unlink_async(ehci);
391 spin_unlock_irqrestore(&ehci->lock, flags);
394 static void ehci_watchdog(unsigned long param)
396 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
399 spin_lock_irqsave(&ehci->lock, flags);
401 /* stop async processing after it's idled a bit */
402 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
403 start_unlink_async (ehci, ehci->async);
405 /* ehci could run by timer, without IRQs ... */
408 spin_unlock_irqrestore (&ehci->lock, flags);
411 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
412 * The firmware seems to think that powering off is a wakeup event!
413 * This routine turns off remote wakeup and everything else, on all ports.
415 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
417 int port = HCS_N_PORTS(ehci->hcs_params);
420 ehci_writel(ehci, PORT_RWC_BITS,
421 &ehci->regs->port_status[port]);
425 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
426 * Should be called with ehci->lock held.
428 static void ehci_silence_controller(struct ehci_hcd *ehci)
431 ehci_turn_off_all_ports(ehci);
433 /* make BIOS/etc use companion controller during reboot */
434 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
436 /* unblock posted writes */
437 ehci_readl(ehci, &ehci->regs->configured_flag);
440 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
441 * This forcibly disables dma and IRQs, helping kexec and other cases
442 * where the next system software may expect clean state.
444 static void ehci_shutdown(struct usb_hcd *hcd)
446 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
448 del_timer_sync(&ehci->watchdog);
449 del_timer_sync(&ehci->iaa_watchdog);
451 spin_lock_irq(&ehci->lock);
452 ehci_silence_controller(ehci);
453 spin_unlock_irq(&ehci->lock);
456 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
460 if (!HCS_PPC (ehci->hcs_params))
463 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
464 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
465 (void) ehci_hub_control(ehci_to_hcd(ehci),
466 is_on ? SetPortFeature : ClearPortFeature,
469 /* Flush those writes */
470 ehci_readl(ehci, &ehci->regs->command);
474 /*-------------------------------------------------------------------------*/
477 * ehci_work is called from some interrupts, timers, and so on.
478 * it calls driver completion functions, after dropping ehci->lock.
480 static void ehci_work (struct ehci_hcd *ehci)
482 timer_action_done (ehci, TIMER_IO_WATCHDOG);
484 /* another CPU may drop ehci->lock during a schedule scan while
485 * it reports urb completions. this flag guards against bogus
486 * attempts at re-entrant schedule scanning.
492 if (ehci->next_uframe != -1)
493 scan_periodic (ehci);
496 /* the IO watchdog guards against hardware or driver bugs that
497 * misplace IRQs, and should let us run completely without IRQs.
498 * such lossage has been observed on both VT6202 and VT8235.
500 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
501 (ehci->async->qh_next.ptr != NULL ||
502 ehci->periodic_sched != 0))
503 timer_action (ehci, TIMER_IO_WATCHDOG);
507 * Called when the ehci_hcd module is removed.
509 static void ehci_stop (struct usb_hcd *hcd)
511 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
513 ehci_dbg (ehci, "stop\n");
515 /* no more interrupts ... */
516 del_timer_sync (&ehci->watchdog);
517 del_timer_sync(&ehci->iaa_watchdog);
519 spin_lock_irq(&ehci->lock);
520 if (HC_IS_RUNNING (hcd->state))
523 ehci_silence_controller(ehci);
525 spin_unlock_irq(&ehci->lock);
527 remove_companion_file(ehci);
528 remove_debug_files (ehci);
530 /* root hub is shut down separately (first, when possible) */
531 spin_lock_irq (&ehci->lock);
534 spin_unlock_irq (&ehci->lock);
535 ehci_mem_cleanup (ehci);
537 if (ehci->amd_pll_fix == 1)
541 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
542 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
543 ehci->stats.lost_iaa);
544 ehci_dbg (ehci, "complete %ld unlink %ld\n",
545 ehci->stats.complete, ehci->stats.unlink);
548 dbg_status (ehci, "ehci_stop completed",
549 ehci_readl(ehci, &ehci->regs->status));
552 /* one-time init, only for memory state */
553 static int ehci_init(struct usb_hcd *hcd)
555 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
559 struct ehci_qh_hw *hw;
561 spin_lock_init(&ehci->lock);
564 * keep io watchdog by default, those good HCDs could turn off it later
566 ehci->need_io_watchdog = 1;
567 init_timer(&ehci->watchdog);
568 ehci->watchdog.function = ehci_watchdog;
569 ehci->watchdog.data = (unsigned long) ehci;
571 init_timer(&ehci->iaa_watchdog);
572 ehci->iaa_watchdog.function = ehci_iaa_watchdog;
573 ehci->iaa_watchdog.data = (unsigned long) ehci;
575 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
578 * hw default: 1K periodic list heads, one per frame.
579 * periodic_size can shrink by USBCMD update if hcc_params allows.
581 ehci->periodic_size = DEFAULT_I_TDPS;
582 INIT_LIST_HEAD(&ehci->cached_itd_list);
583 INIT_LIST_HEAD(&ehci->cached_sitd_list);
585 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
586 /* periodic schedule size can be smaller than default */
587 switch (EHCI_TUNE_FLS) {
588 case 0: ehci->periodic_size = 1024; break;
589 case 1: ehci->periodic_size = 512; break;
590 case 2: ehci->periodic_size = 256; break;
594 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
597 /* controllers may cache some of the periodic schedule ... */
598 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
599 ehci->i_thresh = 2 + 8;
600 else // N microframes cached
601 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
603 ehci->reclaim = NULL;
604 ehci->next_uframe = -1;
605 ehci->clock_frame = -1;
608 * dedicate a qh for the async ring head, since we couldn't unlink
609 * a 'real' qh without stopping the async schedule [4.8]. use it
610 * as the 'reclamation list head' too.
611 * its dummy is used in hw_alt_next of many tds, to prevent the qh
612 * from automatically advancing to the next td after short reads.
614 ehci->async->qh_next.qh = NULL;
615 hw = ehci->async->hw;
616 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
617 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
618 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
619 hw->hw_qtd_next = EHCI_LIST_END(ehci);
620 ehci->async->qh_state = QH_STATE_LINKED;
621 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
623 /* clear interrupt enables, set irq latency */
624 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
626 temp = 1 << (16 + log2_irq_thresh);
627 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
629 ehci_dbg(ehci, "enable per-port change event\n");
632 if (HCC_CANPARK(hcc_params)) {
633 /* HW default park == 3, on hardware that supports it (like
634 * NVidia and ALI silicon), maximizes throughput on the async
635 * schedule by avoiding QH fetches between transfers.
637 * With fast usb storage devices and NForce2, "park" seems to
638 * make problems: throughput reduction (!), data errors...
641 park = min(park, (unsigned) 3);
645 ehci_dbg(ehci, "park %d\n", park);
647 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
648 /* periodic schedule size can be smaller than default */
650 temp |= (EHCI_TUNE_FLS << 2);
652 if (HCC_LPM(hcc_params)) {
653 /* support link power management EHCI 1.1 addendum */
654 ehci_dbg(ehci, "support lpm\n");
657 ehci_dbg(ehci, "hird %d invalid, use default 0",
663 ehci->command = temp;
665 /* Accept arbitrarily long scatter-gather lists */
666 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
667 hcd->self.sg_tablesize = ~0;
671 /* start HC running; it's halted, ehci_init() has been run (once) */
672 static int ehci_run (struct usb_hcd *hcd)
674 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
679 hcd->uses_new_polling = 1;
681 /* EHCI spec section 4.1 */
683 * TDI driver does the ehci_reset in their reset callback.
684 * Don't reset here, because configuration settings will
687 if (!ehci_is_TDI(ehci) && (retval = ehci_reset(ehci)) != 0) {
688 ehci_mem_cleanup(ehci);
691 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
692 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
695 * hcc_params controls whether ehci->regs->segment must (!!!)
696 * be used; it constrains QH/ITD/SITD and QTD locations.
697 * pci_pool consistent memory always uses segment zero.
698 * streaming mappings for I/O buffers, like pci_map_single(),
699 * can return segments above 4GB, if the device allows.
701 * NOTE: the dma mask is visible through dma_supported(), so
702 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
703 * Scsi_Host.highmem_io, and so forth. It's readonly to all
704 * host side drivers though.
706 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
707 if (HCC_64BIT_ADDR(hcc_params)) {
708 ehci_writel(ehci, 0, &ehci->regs->segment);
710 // this is deeply broken on almost all architectures
711 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
712 ehci_info(ehci, "enabled 64bit DMA\n");
717 // Philips, Intel, and maybe others need CMD_RUN before the
718 // root hub will detect new devices (why?); NEC doesn't
719 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
720 ehci->command |= CMD_RUN;
721 ehci_writel(ehci, ehci->command, &ehci->regs->command);
722 dbg_cmd (ehci, "init", ehci->command);
725 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
726 * are explicitly handed to companion controller(s), so no TT is
727 * involved with the root hub. (Except where one is integrated,
728 * and there's no companion controller unless maybe for USB OTG.)
730 * Turning on the CF flag will transfer ownership of all ports
731 * from the companions to the EHCI controller. If any of the
732 * companions are in the middle of a port reset at the time, it
733 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
734 * guarantees that no resets are in progress. After we set CF,
735 * a short delay lets the hardware catch up; new resets shouldn't
736 * be started before the port switching actions could complete.
738 down_write(&ehci_cf_port_reset_rwsem);
739 hcd->state = HC_STATE_RUNNING;
740 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
741 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
743 up_write(&ehci_cf_port_reset_rwsem);
744 ehci->last_periodic_enable = ktime_get_real();
746 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
748 "USB %x.%x started, EHCI %x.%02x%s\n",
749 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
750 temp >> 8, temp & 0xff,
751 ignore_oc ? ", overcurrent ignored" : "");
753 ehci_writel(ehci, INTR_MASK,
754 &ehci->regs->intr_enable); /* Turn On Interrupts */
756 /* GRR this is run-once init(), being done every time the HC starts.
757 * So long as they're part of class devices, we can't do it init()
758 * since the class device isn't created that early.
760 create_debug_files(ehci);
761 create_companion_file(ehci);
766 /*-------------------------------------------------------------------------*/
768 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
770 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
771 u32 status, masked_status, pcd_status = 0, cmd;
774 spin_lock (&ehci->lock);
776 status = ehci_readl(ehci, &ehci->regs->status);
778 /* e.g. cardbus physical eject */
779 if (status == ~(u32) 0) {
780 ehci_dbg (ehci, "device removed\n");
785 masked_status = status & INTR_MASK;
786 if (!masked_status || unlikely(hcd->state == HC_STATE_HALT)) {
787 spin_unlock(&ehci->lock);
791 /* clear (just) interrupts */
792 ehci_writel(ehci, masked_status, &ehci->regs->status);
793 cmd = ehci_readl(ehci, &ehci->regs->command);
797 /* unrequested/ignored: Frame List Rollover */
798 dbg_status (ehci, "irq", status);
801 /* INT, ERR, and IAA interrupt rates can be throttled */
803 /* normal [4.15.1.2] or error [4.15.1.1] completion */
804 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
805 if (likely ((status & STS_ERR) == 0))
806 COUNT (ehci->stats.normal);
808 COUNT (ehci->stats.error);
812 /* complete the unlinking of some qh [4.15.2.3] */
813 if (status & STS_IAA) {
814 /* guard against (alleged) silicon errata */
815 if (cmd & CMD_IAAD) {
816 ehci_writel(ehci, cmd & ~CMD_IAAD,
817 &ehci->regs->command);
818 ehci_dbg(ehci, "IAA with IAAD still set?\n");
821 COUNT(ehci->stats.reclaim);
822 end_unlink_async(ehci);
824 ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
827 /* remote wakeup [4.3.1] */
828 if (status & STS_PCD) {
829 unsigned i = HCS_N_PORTS (ehci->hcs_params);
832 /* kick root hub later */
835 /* resume root hub? */
836 if (!(cmd & CMD_RUN))
837 usb_hcd_resume_root_hub(hcd);
839 /* get per-port change detect bits */
846 /* leverage per-port change bits feature */
847 if (ehci->has_ppcd && !(ppcd & (1 << i)))
849 pstatus = ehci_readl(ehci,
850 &ehci->regs->port_status[i]);
852 if (pstatus & PORT_OWNER)
854 if (!(test_bit(i, &ehci->suspended_ports) &&
855 ((pstatus & PORT_RESUME) ||
856 !(pstatus & PORT_SUSPEND)) &&
857 (pstatus & PORT_PE) &&
858 ehci->reset_done[i] == 0))
861 /* start 20 msec resume signaling from this port,
862 * and make khubd collect PORT_STAT_C_SUSPEND to
863 * stop that signaling. Use 5 ms extra for safety,
864 * like usb_port_resume() does.
866 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
867 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
868 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
872 /* PCI errors [4.15.2.4] */
873 if (unlikely ((status & STS_FATAL) != 0)) {
874 ehci_err(ehci, "fatal error\n");
875 dbg_cmd(ehci, "fatal", cmd);
876 dbg_status(ehci, "fatal", status);
880 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
882 /* generic layer kills/unlinks all urbs, then
883 * uses ehci_stop to clean up the rest
890 spin_unlock (&ehci->lock);
892 usb_hcd_poll_rh_status(hcd);
896 /*-------------------------------------------------------------------------*/
899 * non-error returns are a promise to giveback() the urb later
900 * we drop ownership so next owner (or urb unlink) can get it
902 * urb + dev is in hcd.self.controller.urb_list
903 * we're queueing TDs onto software and hardware lists
905 * hcd-specific init for hcpriv hasn't been done yet
907 * NOTE: control, bulk, and interrupt share the same code to append TDs
908 * to a (possibly active) QH, and the same QH scanning code.
910 static int ehci_urb_enqueue (
915 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
916 struct list_head qtd_list;
918 INIT_LIST_HEAD (&qtd_list);
920 switch (usb_pipetype (urb->pipe)) {
922 /* qh_completions() code doesn't handle all the fault cases
923 * in multi-TD control transfers. Even 1KB is rare anyway.
925 if (urb->transfer_buffer_length > (16 * 1024))
928 /* case PIPE_BULK: */
930 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
932 return submit_async(ehci, urb, &qtd_list, mem_flags);
935 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
937 return intr_submit(ehci, urb, &qtd_list, mem_flags);
939 case PIPE_ISOCHRONOUS:
940 if (urb->dev->speed == USB_SPEED_HIGH)
941 return itd_submit (ehci, urb, mem_flags);
943 return sitd_submit (ehci, urb, mem_flags);
947 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
950 if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim)
951 end_unlink_async(ehci);
953 /* If the QH isn't linked then there's nothing we can do
954 * unless we were called during a giveback, in which case
955 * qh_completions() has to deal with it.
957 if (qh->qh_state != QH_STATE_LINKED) {
958 if (qh->qh_state == QH_STATE_COMPLETING)
959 qh->needs_rescan = 1;
963 /* defer till later if busy */
965 struct ehci_qh *last;
967 for (last = ehci->reclaim;
969 last = last->reclaim)
971 qh->qh_state = QH_STATE_UNLINK_WAIT;
974 /* start IAA cycle */
976 start_unlink_async (ehci, qh);
979 /* remove from hardware lists
980 * completions normally happen asynchronously
983 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
985 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
990 spin_lock_irqsave (&ehci->lock, flags);
991 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
995 switch (usb_pipetype (urb->pipe)) {
996 // case PIPE_CONTROL:
999 qh = (struct ehci_qh *) urb->hcpriv;
1002 switch (qh->qh_state) {
1003 case QH_STATE_LINKED:
1004 case QH_STATE_COMPLETING:
1005 unlink_async(ehci, qh);
1007 case QH_STATE_UNLINK:
1008 case QH_STATE_UNLINK_WAIT:
1009 /* already started */
1012 /* QH might be waiting for a Clear-TT-Buffer */
1013 qh_completions(ehci, qh);
1018 case PIPE_INTERRUPT:
1019 qh = (struct ehci_qh *) urb->hcpriv;
1022 switch (qh->qh_state) {
1023 case QH_STATE_LINKED:
1024 case QH_STATE_COMPLETING:
1025 intr_deschedule (ehci, qh);
1028 qh_completions (ehci, qh);
1031 ehci_dbg (ehci, "bogus qh %p state %d\n",
1037 case PIPE_ISOCHRONOUS:
1040 // wait till next completion, do it then.
1041 // completion irqs can wait up to 1024 msec,
1045 spin_unlock_irqrestore (&ehci->lock, flags);
1049 /*-------------------------------------------------------------------------*/
1051 // bulk qh holds the data toggle
1054 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1056 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1057 unsigned long flags;
1058 struct ehci_qh *qh, *tmp;
1060 /* ASSERT: any requests/urbs are being unlinked */
1061 /* ASSERT: nobody can be submitting urbs for this any more */
1064 spin_lock_irqsave (&ehci->lock, flags);
1069 /* endpoints can be iso streams. for now, we don't
1070 * accelerate iso completions ... so spin a while.
1072 if (qh->hw == NULL) {
1073 ehci_vdbg (ehci, "iso delay\n");
1077 if (!HC_IS_RUNNING (hcd->state))
1078 qh->qh_state = QH_STATE_IDLE;
1079 switch (qh->qh_state) {
1080 case QH_STATE_LINKED:
1081 case QH_STATE_COMPLETING:
1082 for (tmp = ehci->async->qh_next.qh;
1084 tmp = tmp->qh_next.qh)
1086 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1087 * may already be unlinked.
1090 unlink_async(ehci, qh);
1092 case QH_STATE_UNLINK: /* wait for hw to finish? */
1093 case QH_STATE_UNLINK_WAIT:
1095 spin_unlock_irqrestore (&ehci->lock, flags);
1096 schedule_timeout_uninterruptible(1);
1098 case QH_STATE_IDLE: /* fully unlinked */
1099 if (qh->clearing_tt)
1101 if (list_empty (&qh->qtd_list)) {
1105 /* else FALL THROUGH */
1107 /* caller was supposed to have unlinked any requests;
1108 * that's not our job. just leak this memory.
1110 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1111 qh, ep->desc.bEndpointAddress, qh->qh_state,
1112 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1117 spin_unlock_irqrestore (&ehci->lock, flags);
1121 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1123 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1125 int eptype = usb_endpoint_type(&ep->desc);
1126 int epnum = usb_endpoint_num(&ep->desc);
1127 int is_out = usb_endpoint_dir_out(&ep->desc);
1128 unsigned long flags;
1130 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1133 spin_lock_irqsave(&ehci->lock, flags);
1136 /* For Bulk and Interrupt endpoints we maintain the toggle state
1137 * in the hardware; the toggle bits in udev aren't used at all.
1138 * When an endpoint is reset by usb_clear_halt() we must reset
1139 * the toggle bit in the QH.
1142 usb_settoggle(qh->dev, epnum, is_out, 0);
1143 if (!list_empty(&qh->qtd_list)) {
1144 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1145 } else if (qh->qh_state == QH_STATE_LINKED ||
1146 qh->qh_state == QH_STATE_COMPLETING) {
1148 /* The toggle value in the QH can't be updated
1149 * while the QH is active. Unlink it now;
1150 * re-linking will call qh_refresh().
1152 if (eptype == USB_ENDPOINT_XFER_BULK)
1153 unlink_async(ehci, qh);
1155 intr_deschedule(ehci, qh);
1158 spin_unlock_irqrestore(&ehci->lock, flags);
1161 static int ehci_get_frame (struct usb_hcd *hcd)
1163 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1164 return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) %
1165 ehci->periodic_size;
1168 /*-------------------------------------------------------------------------*/
1170 MODULE_DESCRIPTION(DRIVER_DESC);
1171 MODULE_AUTHOR (DRIVER_AUTHOR);
1172 MODULE_LICENSE ("GPL");
1175 #include "ehci-pci.c"
1176 #define PCI_DRIVER ehci_pci_driver
1179 #ifdef CONFIG_USB_EHCI_FSL
1180 #include "ehci-fsl.c"
1181 #define PLATFORM_DRIVER ehci_fsl_driver
1184 #ifdef CONFIG_USB_EHCI_MXC
1185 #include "ehci-mxc.c"
1186 #define PLATFORM_DRIVER ehci_mxc_driver
1189 #ifdef CONFIG_USB_EHCI_SH
1190 #include "ehci-sh.c"
1191 #define PLATFORM_DRIVER ehci_hcd_sh_driver
1194 #ifdef CONFIG_SOC_AU1200
1195 #include "ehci-au1xxx.c"
1196 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1199 #ifdef CONFIG_USB_EHCI_HCD_OMAP
1200 #include "ehci-omap.c"
1201 #define PLATFORM_DRIVER ehci_hcd_omap_driver
1204 #ifdef CONFIG_PPC_PS3
1205 #include "ehci-ps3.c"
1206 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1209 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1210 #include "ehci-ppc-of.c"
1211 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1214 #ifdef CONFIG_XPS_USB_HCD_XILINX
1215 #include "ehci-xilinx-of.c"
1216 #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
1219 #ifdef CONFIG_PLAT_ORION
1220 #include "ehci-orion.c"
1221 #define PLATFORM_DRIVER ehci_orion_driver
1224 #ifdef CONFIG_ARCH_IXP4XX
1225 #include "ehci-ixp4xx.c"
1226 #define PLATFORM_DRIVER ixp4xx_ehci_driver
1229 #ifdef CONFIG_USB_W90X900_EHCI
1230 #include "ehci-w90x900.c"
1231 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1234 #ifdef CONFIG_ARCH_AT91
1235 #include "ehci-atmel.c"
1236 #define PLATFORM_DRIVER ehci_atmel_driver
1239 #ifdef CONFIG_USB_OCTEON_EHCI
1240 #include "ehci-octeon.c"
1241 #define PLATFORM_DRIVER ehci_octeon_driver
1244 #ifdef CONFIG_USB_CNS3XXX_EHCI
1245 #include "ehci-cns3xxx.c"
1246 #define PLATFORM_DRIVER cns3xxx_ehci_driver
1249 #ifdef CONFIG_ARCH_VT8500
1250 #include "ehci-vt8500.c"
1251 #define PLATFORM_DRIVER vt8500_ehci_driver
1254 #ifdef CONFIG_PLAT_SPEAR
1255 #include "ehci-spear.c"
1256 #define PLATFORM_DRIVER spear_ehci_hcd_driver
1259 #ifdef CONFIG_USB_EHCI_MSM
1260 #include "ehci-msm.c"
1261 #define PLATFORM_DRIVER ehci_msm_driver
1264 #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1265 #include "ehci-pmcmsp.c"
1266 #define PLATFORM_DRIVER ehci_hcd_msp_driver
1269 #ifdef CONFIG_USB_EHCI_TEGRA
1270 #include "ehci-tegra.c"
1271 #define PLATFORM_DRIVER tegra_ehci_driver
1274 #ifdef CONFIG_USB_EHCI_S5P
1275 #include "ehci-s5p.c"
1276 #define PLATFORM_DRIVER s5p_ehci_driver
1279 #ifdef CONFIG_USB_EHCI_ATH79
1280 #include "ehci-ath79.c"
1281 #define PLATFORM_DRIVER ehci_ath79_driver
1284 #ifdef CONFIG_SPARC_LEON
1285 #include "ehci-grlib.c"
1286 #define PLATFORM_DRIVER ehci_grlib_driver
1289 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1290 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1291 !defined(XILINX_OF_PLATFORM_DRIVER)
1292 #error "missing bus glue for ehci-hcd"
1295 static int __init ehci_hcd_init(void)
1302 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1303 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1304 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1305 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1306 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1307 " before uhci_hcd and ohci_hcd, not after\n");
1309 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1311 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1312 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1315 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1316 if (!ehci_debug_root) {
1322 #ifdef PLATFORM_DRIVER
1323 retval = platform_driver_register(&PLATFORM_DRIVER);
1329 retval = pci_register_driver(&PCI_DRIVER);
1334 #ifdef PS3_SYSTEM_BUS_DRIVER
1335 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1340 #ifdef OF_PLATFORM_DRIVER
1341 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1346 #ifdef XILINX_OF_PLATFORM_DRIVER
1347 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
1353 #ifdef XILINX_OF_PLATFORM_DRIVER
1354 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1357 #ifdef OF_PLATFORM_DRIVER
1358 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1361 #ifdef PS3_SYSTEM_BUS_DRIVER
1362 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1366 pci_unregister_driver(&PCI_DRIVER);
1369 #ifdef PLATFORM_DRIVER
1370 platform_driver_unregister(&PLATFORM_DRIVER);
1374 debugfs_remove(ehci_debug_root);
1375 ehci_debug_root = NULL;
1378 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1381 module_init(ehci_hcd_init);
1383 static void __exit ehci_hcd_cleanup(void)
1385 #ifdef XILINX_OF_PLATFORM_DRIVER
1386 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
1388 #ifdef OF_PLATFORM_DRIVER
1389 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1391 #ifdef PLATFORM_DRIVER
1392 platform_driver_unregister(&PLATFORM_DRIVER);
1395 pci_unregister_driver(&PCI_DRIVER);
1397 #ifdef PS3_SYSTEM_BUS_DRIVER
1398 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1401 debugfs_remove(ehci_debug_root);
1403 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1405 module_exit(ehci_hcd_cleanup);