drivers/usb/host/ehci-fsl.c

   1 /*
   2  * Copyright 2005-2009 MontaVista Software, Inc.
   3  * Copyright 2008,2012,2015      Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software Foundation,
  17  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
  20  * by Hunter Wu.
  21  * Power Management support by Dave Liu <daveliu@freescale.com>,
  22  * Jerry Huang <Chang-Ming.Huang@freescale.com> and
  23  * Anton Vorontsov <avorontsov@ru.mvista.com>.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/types.h>
  29 #include <linux/delay.h>
  30 #include <linux/pm.h>
  31 #include <linux/err.h>
  32 #include <linux/usb.h>
  33 #include <linux/usb/ehci_def.h>
  34 #include <linux/usb/hcd.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/fsl_devices.h>
  38
  39 #include "ehci.h"
  40 #include "ehci-fsl.h"
  41
  42 #define DRIVER_DESC "Freescale EHCI Host controller driver"
  43 #define DRV_NAME "ehci-fsl"
  44
  45 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
  46
  47 /* configure so an HC device and id are always provided */
  48 /* always called with process context; sleeping is OK */
  49
  50 /*
  51  * fsl_ehci_drv_probe - initialize FSL-based HCDs
  52  * @pdev: USB Host Controller being probed
  53  * Context: !in_interrupt()
  54  *
  55  * Allocates basic resources for this USB host controller.
  56  *
  57  */
  58 static int fsl_ehci_drv_probe(struct platform_device *pdev)
  59 {
  60         struct fsl_usb2_platform_data *pdata;
  61         struct usb_hcd *hcd;
  62         struct resource *res;
  63         int irq;
  64         int retval;
  65
  66         pr_debug("initializing FSL-SOC USB Controller\n");
  67
  68         /* Need platform data for setup */
  69         pdata = dev_get_platdata(&pdev->dev);
  70         if (!pdata) {
  71                 dev_err(&pdev->dev,
  72                         "No platform data for %s.\n", dev_name(&pdev->dev));
  73                 return -ENODEV;
  74         }
  75
  76         /*
  77          * This is a host mode driver, verify that we're supposed to be
  78          * in host mode.
  79          */
  80         if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  81               (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
  82               (pdata->operating_mode == FSL_USB2_DR_OTG))) {
  83                 dev_err(&pdev->dev,
  84                         "Non Host Mode configured for %s. Wrong driver linked.\n",
  85                         dev_name(&pdev->dev));
  86                 return -ENODEV;
  87         }
  88
  89         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  90         if (!res) {
  91                 dev_err(&pdev->dev,
  92                         "Found HC with no IRQ. Check %s setup!\n",
  93                         dev_name(&pdev->dev));
  94                 return -ENODEV;
  95         }
  96         irq = res->start;
  97
  98         hcd = usb_create_hcd(&fsl_ehci_hc_driver, &pdev->dev,
  99                                 dev_name(&pdev->dev));
 100         if (!hcd) {
 101                 retval = -ENOMEM;
 102                 goto err1;
 103         }
 104
 105         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 106         hcd->regs = devm_ioremap_resource(&pdev->dev, res);
 107         if (IS_ERR(hcd->regs)) {
 108                 retval = PTR_ERR(hcd->regs);
 109                 goto err2;
 110         }
 111
 112         hcd->rsrc_start = res->start;
 113         hcd->rsrc_len = resource_size(res);
 114
 115         pdata->regs = hcd->regs;
 116
 117         if (pdata->power_budget)
 118                 hcd->power_budget = pdata->power_budget;
 119
 120         /*
 121          * do platform specific init: check the clock, grab/config pins, etc.
 122          */
 123         if (pdata->init && pdata->init(pdev)) {
 124                 retval = -ENODEV;
 125                 goto err2;
 126         }
 127
 128         /* Enable USB controller, 83xx or 8536 */
 129         if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
 130                 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
 131                                 CONTROL_REGISTER_W1C_MASK, 0x4);
 132
 133         /*
 134          * Enable UTMI phy and program PTS field in UTMI mode before asserting
 135          * controller reset for USB Controller version 2.5
 136          */
 137         if (pdata->has_fsl_erratum_a007792) {
 138                 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
 139                                 CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN);
 140                 writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
 141         }
 142
 143         /* Don't need to set host mode here. It will be done by tdi_reset() */
 144
 145         retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
 146         if (retval != 0)
 147                 goto err2;
 148         device_wakeup_enable(hcd->self.controller);
 149
 150 #ifdef CONFIG_USB_OTG
 151         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
 152                 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 153
 154                 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
 155                 dev_dbg(&pdev->dev, "hcd=0x%p  ehci=0x%p, phy=0x%p\n",
 156                         hcd, ehci, hcd->usb_phy);
 157
 158                 if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
 159                         retval = otg_set_host(hcd->usb_phy->otg,
 160                                               &ehci_to_hcd(ehci)->self);
 161                         if (retval) {
 162                                 usb_put_phy(hcd->usb_phy);
 163                                 goto err2;
 164                         }
 165                 } else {
 166                         dev_err(&pdev->dev, "can't find phy\n");
 167                         retval = -ENODEV;
 168                         goto err2;
 169                 }
 170         }
 171 #endif
 172         return retval;
 173
 174       err2:
 175         usb_put_hcd(hcd);
 176       err1:
 177         dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
 178         if (pdata->exit)
 179                 pdata->exit(pdev);
 180         return retval;
 181 }
 182
 183 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
 184                                enum fsl_usb2_phy_modes phy_mode,
 185                                unsigned int port_offset)
 186 {
 187         u32 portsc;
 188         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 189         void __iomem *non_ehci = hcd->regs;
 190         struct device *dev = hcd->self.controller;
 191         struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
 192
 193         if (pdata->controller_ver < 0) {
 194                 dev_warn(hcd->self.controller, "Could not get controller version\n");
 195                 return -ENODEV;
 196         }
 197
 198         portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
 199         portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
 200
 201         switch (phy_mode) {
 202         case FSL_USB2_PHY_ULPI:
 203                 if (pdata->have_sysif_regs && pdata->controller_ver) {
 204                         /* controller version 1.6 or above */
 205                         clrbits32(non_ehci + FSL_SOC_USB_CTRL,
 206                                   CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
 207                         clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
 208                                         CONTROL_REGISTER_W1C_MASK,
 209                                         ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
 210                 }
 211                 portsc |= PORT_PTS_ULPI;
 212                 break;
 213         case FSL_USB2_PHY_SERIAL:
 214                 portsc |= PORT_PTS_SERIAL;
 215                 break;
 216         case FSL_USB2_PHY_UTMI_WIDE:
 217                 portsc |= PORT_PTS_PTW;
 218                 /* fall through */
 219         case FSL_USB2_PHY_UTMI:
 220         case FSL_USB2_PHY_UTMI_DUAL:
 221                 if (pdata->have_sysif_regs && pdata->controller_ver) {
 222                         /* controller version 1.6 or above */
 223                         clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
 224                                         CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN);
 225                         mdelay(FSL_UTMI_PHY_DLY);  /* Delay for UTMI PHY CLK to
 226                                                 become stable - 10ms*/
 227                 }
 228                 /* enable UTMI PHY */
 229                 if (pdata->have_sysif_regs)
 230                         clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
 231                                         CONTROL_REGISTER_W1C_MASK,
 232                                         CTRL_UTMI_PHY_EN);
 233                 portsc |= PORT_PTS_UTMI;
 234                 break;
 235         case FSL_USB2_PHY_NONE:
 236                 break;
 237         }
 238
 239         /*
 240          * check PHY_CLK_VALID to determine phy clock presence before writing
 241          * to portsc
 242          */
 243         if (pdata->check_phy_clk_valid) {
 244                 if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID)) {
 245                         dev_warn(hcd->self.controller,
 246                                  "USB PHY clock invalid\n");
 247                         return -EINVAL;
 248                 }
 249         }
 250
 251         ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
 252
 253         if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
 254                 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
 255                                 CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN);
 256
 257         return 0;
 258 }
 259
 260 static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
 261 {
 262         struct usb_hcd *hcd = ehci_to_hcd(ehci);
 263         struct fsl_usb2_platform_data *pdata;
 264         void __iomem *non_ehci = hcd->regs;
 265
 266         pdata = dev_get_platdata(hcd->self.controller);
 267
 268         if (pdata->have_sysif_regs) {
 269                 /*
 270                 * Turn on cache snooping hardware, since some PowerPC platforms
 271                 * wholly rely on hardware to deal with cache coherent
 272                 */
 273
 274                 /* Setup Snooping for all the 4GB space */
 275                 /* SNOOP1 starts from 0x0, size 2G */
 276                 out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
 277                 /* SNOOP2 starts from 0x80000000, size 2G */
 278                 out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
 279         }
 280
 281         if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
 282                         (pdata->operating_mode == FSL_USB2_DR_OTG))
 283                 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
 284                         return -EINVAL;
 285
 286         if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
 287                 unsigned int chip, rev, svr;
 288
 289                 svr = mfspr(SPRN_SVR);
 290                 chip = svr >> 16;
 291                 rev = (svr >> 4) & 0xf;
 292
 293                 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
 294                 if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
 295                         ehci->has_fsl_port_bug = 1;
 296
 297                 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
 298                         if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
 299                                 return -EINVAL;
 300
 301                 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
 302                         if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
 303                                 return -EINVAL;
 304         }
 305
 306         if (pdata->have_sysif_regs) {
 307 #ifdef CONFIG_FSL_SOC_BOOKE
 308                 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
 309                 out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080);
 310 #else
 311                 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
 312                 out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
 313 #endif
 314                 out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
 315         }
 316
 317         return 0;
 318 }
 319
 320 /* called after powerup, by probe or system-pm "wakeup" */
 321 static int ehci_fsl_reinit(struct ehci_hcd *ehci)
 322 {
 323         if (ehci_fsl_usb_setup(ehci))
 324                 return -EINVAL;
 325
 326         return 0;
 327 }
 328
 329 /* called during probe() after chip reset completes */
 330 static int ehci_fsl_setup(struct usb_hcd *hcd)
 331 {
 332         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 333         int retval;
 334         struct fsl_usb2_platform_data *pdata;
 335         struct device *dev;
 336
 337         dev = hcd->self.controller;
 338         pdata = dev_get_platdata(hcd->self.controller);
 339         ehci->big_endian_desc = pdata->big_endian_desc;
 340         ehci->big_endian_mmio = pdata->big_endian_mmio;
 341
 342         /* EHCI registers start at offset 0x100 */
 343         ehci->caps = hcd->regs + 0x100;
 344
 345 #ifdef CONFIG_PPC_83xx
 346         /*
 347          * Deal with MPC834X that need port power to be cycled after the power
 348          * fault condition is removed. Otherwise the state machine does not
 349          * reflect PORTSC[CSC] correctly.
 350          */
 351         ehci->need_oc_pp_cycle = 1;
 352 #endif
 353
 354         hcd->has_tt = 1;
 355
 356         retval = ehci_setup(hcd);
 357         if (retval)
 358                 return retval;
 359
 360         if (of_device_is_compatible(dev->parent->of_node,
 361                                     "fsl,mpc5121-usb2-dr")) {
 362                 /*
 363                  * set SBUSCFG:AHBBRST so that control msgs don't
 364                  * fail when doing heavy PATA writes.
 365                  */
 366                 ehci_writel(ehci, SBUSCFG_INCR8,
 367                             hcd->regs + FSL_SOC_USB_SBUSCFG);
 368         }
 369
 370         retval = ehci_fsl_reinit(ehci);
 371         return retval;
 372 }
 373
 374 struct ehci_fsl {
 375         struct ehci_hcd ehci;
 376
 377 #ifdef CONFIG_PM
 378         /* Saved USB PHY settings, need to restore after deep sleep. */
 379         u32 usb_ctrl;
 380 #endif
 381 };
 382
 383 #ifdef CONFIG_PM
 384
 385 #ifdef CONFIG_PPC_MPC512x
 386 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
 387 {
 388         struct usb_hcd *hcd = dev_get_drvdata(dev);
 389         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 390         struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
 391         u32 tmp;
 392
 393 #ifdef CONFIG_DYNAMIC_DEBUG
 394         u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
 395         mode &= USBMODE_CM_MASK;
 396         tmp = ehci_readl(ehci, hcd->regs + 0x140);      /* usbcmd */
 397
 398         dev_dbg(dev, "suspend=%d already_suspended=%d "
 399                 "mode=%d  usbcmd %08x\n", pdata->suspended,
 400                 pdata->already_suspended, mode, tmp);
 401 #endif
 402
 403         /*
 404          * If the controller is already suspended, then this must be a
 405          * PM suspend.  Remember this fact, so that we will leave the
 406          * controller suspended at PM resume time.
 407          */
 408         if (pdata->suspended) {
 409                 dev_dbg(dev, "already suspended, leaving early\n");
 410                 pdata->already_suspended = 1;
 411                 return 0;
 412         }
 413
 414         dev_dbg(dev, "suspending...\n");
 415
 416         ehci->rh_state = EHCI_RH_SUSPENDED;
 417         dev->power.power_state = PMSG_SUSPEND;
 418
 419         /* ignore non-host interrupts */
 420         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 421
 422         /* stop the controller */
 423         tmp = ehci_readl(ehci, &ehci->regs->command);
 424         tmp &= ~CMD_RUN;
 425         ehci_writel(ehci, tmp, &ehci->regs->command);
 426
 427         /* save EHCI registers */
 428         pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
 429         pdata->pm_command &= ~CMD_RUN;
 430         pdata->pm_status  = ehci_readl(ehci, &ehci->regs->status);
 431         pdata->pm_intr_enable  = ehci_readl(ehci, &ehci->regs->intr_enable);
 432         pdata->pm_frame_index  = ehci_readl(ehci, &ehci->regs->frame_index);
 433         pdata->pm_segment  = ehci_readl(ehci, &ehci->regs->segment);
 434         pdata->pm_frame_list  = ehci_readl(ehci, &ehci->regs->frame_list);
 435         pdata->pm_async_next  = ehci_readl(ehci, &ehci->regs->async_next);
 436         pdata->pm_configured_flag  =
 437                 ehci_readl(ehci, &ehci->regs->configured_flag);
 438         pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
 439         pdata->pm_usbgenctrl = ehci_readl(ehci,
 440                                           hcd->regs + FSL_SOC_USB_USBGENCTRL);
 441
 442         /* clear the W1C bits */
 443         pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
 444
 445         pdata->suspended = 1;
 446
 447         /* clear PP to cut power to the port */
 448         tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
 449         tmp &= ~PORT_POWER;
 450         ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
 451
 452         return 0;
 453 }
 454
 455 static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
 456 {
 457         struct usb_hcd *hcd = dev_get_drvdata(dev);
 458         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 459         struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
 460         u32 tmp;
 461
 462         dev_dbg(dev, "suspend=%d already_suspended=%d\n",
 463                 pdata->suspended, pdata->already_suspended);
 464
 465         /*
 466          * If the controller was already suspended at suspend time,
 467          * then don't resume it now.
 468          */
 469         if (pdata->already_suspended) {
 470                 dev_dbg(dev, "already suspended, leaving early\n");
 471                 pdata->already_suspended = 0;
 472                 return 0;
 473         }
 474
 475         if (!pdata->suspended) {
 476                 dev_dbg(dev, "not suspended, leaving early\n");
 477                 return 0;
 478         }
 479
 480         pdata->suspended = 0;
 481
 482         dev_dbg(dev, "resuming...\n");
 483
 484         /* set host mode */
 485         tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
 486         ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
 487
 488         ehci_writel(ehci, pdata->pm_usbgenctrl,
 489                     hcd->regs + FSL_SOC_USB_USBGENCTRL);
 490         ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
 491                     hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
 492
 493         ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
 494
 495         /* restore EHCI registers */
 496         ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
 497         ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
 498         ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
 499         ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
 500         ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
 501         ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
 502         ehci_writel(ehci, pdata->pm_configured_flag,
 503                     &ehci->regs->configured_flag);
 504         ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
 505
 506         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 507         ehci->rh_state = EHCI_RH_RUNNING;
 508         dev->power.power_state = PMSG_ON;
 509
 510         tmp = ehci_readl(ehci, &ehci->regs->command);
 511         tmp |= CMD_RUN;
 512         ehci_writel(ehci, tmp, &ehci->regs->command);
 513
 514         usb_hcd_resume_root_hub(hcd);
 515
 516         return 0;
 517 }
 518 #else
 519 static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
 520 {
 521         return 0;
 522 }
 523
 524 static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
 525 {
 526         return 0;
 527 }
 528 #endif /* CONFIG_PPC_MPC512x */
 529
 530 static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
 531 {
 532         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 533
 534         return container_of(ehci, struct ehci_fsl, ehci);
 535 }
 536
 537 static int ehci_fsl_drv_suspend(struct device *dev)
 538 {
 539         struct usb_hcd *hcd = dev_get_drvdata(dev);
 540         struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
 541         void __iomem *non_ehci = hcd->regs;
 542
 543         if (of_device_is_compatible(dev->parent->of_node,
 544                                     "fsl,mpc5121-usb2-dr")) {
 545                 return ehci_fsl_mpc512x_drv_suspend(dev);
 546         }
 547
 548         ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
 549                         device_may_wakeup(dev));
 550         if (!fsl_deep_sleep())
 551                 return 0;
 552
 553         ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
 554         return 0;
 555 }
 556
 557 static int ehci_fsl_drv_resume(struct device *dev)
 558 {
 559         struct usb_hcd *hcd = dev_get_drvdata(dev);
 560         struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
 561         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 562         void __iomem *non_ehci = hcd->regs;
 563
 564         if (of_device_is_compatible(dev->parent->of_node,
 565                                     "fsl,mpc5121-usb2-dr")) {
 566                 return ehci_fsl_mpc512x_drv_resume(dev);
 567         }
 568
 569         ehci_prepare_ports_for_controller_resume(ehci);
 570         if (!fsl_deep_sleep())
 571                 return 0;
 572
 573         usb_root_hub_lost_power(hcd->self.root_hub);
 574
 575         /* Restore USB PHY settings and enable the controller. */
 576         out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
 577
 578         ehci_reset(ehci);
 579         ehci_fsl_reinit(ehci);
 580
 581         return 0;
 582 }
 583
 584 static int ehci_fsl_drv_restore(struct device *dev)
 585 {
 586         struct usb_hcd *hcd = dev_get_drvdata(dev);
 587
 588         usb_root_hub_lost_power(hcd->self.root_hub);
 589         return 0;
 590 }
 591
 592 static struct dev_pm_ops ehci_fsl_pm_ops = {
 593         .suspend = ehci_fsl_drv_suspend,
 594         .resume = ehci_fsl_drv_resume,
 595         .restore = ehci_fsl_drv_restore,
 596 };
 597
 598 #define EHCI_FSL_PM_OPS         (&ehci_fsl_pm_ops)
 599 #else
 600 #define EHCI_FSL_PM_OPS         NULL
 601 #endif /* CONFIG_PM */
 602
 603 #ifdef CONFIG_USB_OTG
 604 static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
 605 {
 606         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 607         u32 status;
 608
 609         if (!port)
 610                 return -EINVAL;
 611
 612         port--;
 613
 614         /* start port reset before HNP protocol time out */
 615         status = readl(&ehci->regs->port_status[port]);
 616         if (!(status & PORT_CONNECT))
 617                 return -ENODEV;
 618
 619         /* hub_wq will finish the reset later */
 620         if (ehci_is_TDI(ehci)) {
 621                 writel(PORT_RESET |
 622                        (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
 623                        &ehci->regs->port_status[port]);
 624         } else {
 625                 writel(PORT_RESET, &ehci->regs->port_status[port]);
 626         }
 627
 628         return 0;
 629 }
 630 #else
 631 #define ehci_start_port_reset   NULL
 632 #endif /* CONFIG_USB_OTG */
 633
 634 static struct ehci_driver_overrides ehci_fsl_overrides __initdata = {
 635         .extra_priv_size = sizeof(struct ehci_fsl),
 636         .reset = ehci_fsl_setup,
 637 };
 638
 639 /**
 640  * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs
 641  * @dev: USB Host Controller being removed
 642  * Context: !in_interrupt()
 643  *
 644  * Reverses the effect of usb_hcd_fsl_probe().
 645  *
 646  */
 647
 648 static int fsl_ehci_drv_remove(struct platform_device *pdev)
 649 {
 650         struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
 651         struct usb_hcd *hcd = platform_get_drvdata(pdev);
 652
 653         if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
 654                 otg_set_host(hcd->usb_phy->otg, NULL);
 655                 usb_put_phy(hcd->usb_phy);
 656         }
 657
 658         usb_remove_hcd(hcd);
 659
 660         /*
 661          * do platform specific un-initialization:
 662          * release iomux pins, disable clock, etc.
 663          */
 664         if (pdata->exit)
 665                 pdata->exit(pdev);
 666         usb_put_hcd(hcd);
 667
 668         return 0;
 669 }
 670
 671 static struct platform_driver ehci_fsl_driver = {
 672         .probe = fsl_ehci_drv_probe,
 673         .remove = fsl_ehci_drv_remove,
 674         .shutdown = usb_hcd_platform_shutdown,
 675         .driver = {
 676                 .name = "fsl-ehci",
 677                 .pm = EHCI_FSL_PM_OPS,
 678         },
 679 };
 680
 681 static int __init ehci_fsl_init(void)
 682 {
 683         if (usb_disabled())
 684                 return -ENODEV;
 685
 686         pr_info(DRV_NAME ": " DRIVER_DESC "\n");
 687
 688         ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides);
 689
 690         fsl_ehci_hc_driver.product_desc =
 691                         "Freescale On-Chip EHCI Host Controller";
 692         fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset;
 693
 694
 695         return platform_driver_register(&ehci_fsl_driver);
 696 }
 697 module_init(ehci_fsl_init);
 698
 699 static void __exit ehci_fsl_cleanup(void)
 700 {
 701         platform_driver_unregister(&ehci_fsl_driver);
 702 }
 703 module_exit(ehci_fsl_cleanup);
 704
 705 MODULE_DESCRIPTION(DRIVER_DESC);
 706 MODULE_LICENSE("GPL");
 707 MODULE_ALIAS("platform:" DRV_NAME);