drivers/usb/gadget/s3c-hsudc.c

   1 /* linux/drivers/usb/gadget/s3c-hsudc.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S3C24XX USB 2.0 High-speed USB controller gadget driver
   7  *
   8  * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
   9  * Each endpoint can be configured as either in or out endpoint. Endpoints
  10  * can be configured for Bulk or Interrupt transfer mode.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15 */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/delay.h>
  24 #include <linux/io.h>
  25 #include <linux/slab.h>
  26 #include <linux/clk.h>
  27 #include <linux/err.h>
  28 #include <linux/usb/ch9.h>
  29 #include <linux/usb/gadget.h>
  30 #include <linux/usb/otg.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/platform_data/s3c-hsudc.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/pm_runtime.h>
  35
  36 #include <mach/regs-s3c2443-clock.h>
  37
  38 #define S3C_HSUDC_REG(x)        (x)
  39
  40 /* Non-Indexed Registers */
  41 #define S3C_IR                          S3C_HSUDC_REG(0x00) /* Index Register */
  42 #define S3C_EIR                         S3C_HSUDC_REG(0x04) /* EP Intr Status */
  43 #define S3C_EIR_EP0                     (1<<0)
  44 #define S3C_EIER                        S3C_HSUDC_REG(0x08) /* EP Intr Enable */
  45 #define S3C_FAR                         S3C_HSUDC_REG(0x0c) /* Gadget Address */
  46 #define S3C_FNR                         S3C_HSUDC_REG(0x10) /* Frame Number */
  47 #define S3C_EDR                         S3C_HSUDC_REG(0x14) /* EP Direction */
  48 #define S3C_TR                          S3C_HSUDC_REG(0x18) /* Test Register */
  49 #define S3C_SSR                         S3C_HSUDC_REG(0x1c) /* System Status */
  50 #define S3C_SSR_DTZIEN_EN               (0xff8f)
  51 #define S3C_SSR_ERR                     (0xff80)
  52 #define S3C_SSR_VBUSON                  (1 << 8)
  53 #define S3C_SSR_HSP                     (1 << 4)
  54 #define S3C_SSR_SDE                     (1 << 3)
  55 #define S3C_SSR_RESUME                  (1 << 2)
  56 #define S3C_SSR_SUSPEND                 (1 << 1)
  57 #define S3C_SSR_RESET                   (1 << 0)
  58 #define S3C_SCR                         S3C_HSUDC_REG(0x20) /* System Control */
  59 #define S3C_SCR_DTZIEN_EN               (1 << 14)
  60 #define S3C_SCR_RRD_EN                  (1 << 5)
  61 #define S3C_SCR_SUS_EN                  (1 << 1)
  62 #define S3C_SCR_RST_EN                  (1 << 0)
  63 #define S3C_EP0SR                       S3C_HSUDC_REG(0x24) /* EP0 Status */
  64 #define S3C_EP0SR_EP0_LWO               (1 << 6)
  65 #define S3C_EP0SR_STALL                 (1 << 4)
  66 #define S3C_EP0SR_TX_SUCCESS            (1 << 1)
  67 #define S3C_EP0SR_RX_SUCCESS            (1 << 0)
  68 #define S3C_EP0CR                       S3C_HSUDC_REG(0x28) /* EP0 Control */
  69 #define S3C_BR(_x)                      S3C_HSUDC_REG(0x60 + (_x * 4))
  70
  71 /* Indexed Registers */
  72 #define S3C_ESR                         S3C_HSUDC_REG(0x2c) /* EPn Status */
  73 #define S3C_ESR_FLUSH                   (1 << 6)
  74 #define S3C_ESR_STALL                   (1 << 5)
  75 #define S3C_ESR_LWO                     (1 << 4)
  76 #define S3C_ESR_PSIF_ONE                (1 << 2)
  77 #define S3C_ESR_PSIF_TWO                (2 << 2)
  78 #define S3C_ESR_TX_SUCCESS              (1 << 1)
  79 #define S3C_ESR_RX_SUCCESS              (1 << 0)
  80 #define S3C_ECR                         S3C_HSUDC_REG(0x30) /* EPn Control */
  81 #define S3C_ECR_DUEN                    (1 << 7)
  82 #define S3C_ECR_FLUSH                   (1 << 6)
  83 #define S3C_ECR_STALL                   (1 << 1)
  84 #define S3C_ECR_IEMS                    (1 << 0)
  85 #define S3C_BRCR                        S3C_HSUDC_REG(0x34) /* Read Count */
  86 #define S3C_BWCR                        S3C_HSUDC_REG(0x38) /* Write Count */
  87 #define S3C_MPR                         S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
  88
  89 #define WAIT_FOR_SETUP                  (0)
  90 #define DATA_STATE_XMIT                 (1)
  91 #define DATA_STATE_RECV                 (2)
  92
  93 static const char * const s3c_hsudc_supply_names[] = {
  94         "vdda",         /* analog phy supply, 3.3V */
  95         "vddi",         /* digital phy supply, 1.2V */
  96         "vddosc",       /* oscillator supply, 1.8V - 3.3V */
  97 };
  98
  99 /**
 100  * struct s3c_hsudc_ep - Endpoint representation used by driver.
 101  * @ep: USB gadget layer representation of device endpoint.
 102  * @name: Endpoint name (as required by ep autoconfiguration).
 103  * @dev: Reference to the device controller to which this EP belongs.
 104  * @desc: Endpoint descriptor obtained from the gadget driver.
 105  * @queue: Transfer request queue for the endpoint.
 106  * @stopped: Maintains state of endpoint, set if EP is halted.
 107  * @bEndpointAddress: EP address (including direction bit).
 108  * @fifo: Base address of EP FIFO.
 109  */
 110 struct s3c_hsudc_ep {
 111         struct usb_ep ep;
 112         char name[20];
 113         struct s3c_hsudc *dev;
 114         struct list_head queue;
 115         u8 stopped;
 116         u8 wedge;
 117         u8 bEndpointAddress;
 118         void __iomem *fifo;
 119 };
 120
 121 /**
 122  * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
 123  * @req: Reference to USB gadget transfer request.
 124  * @queue: Used for inserting this request to the endpoint request queue.
 125  */
 126 struct s3c_hsudc_req {
 127         struct usb_request req;
 128         struct list_head queue;
 129 };
 130
 131 /**
 132  * struct s3c_hsudc - Driver's abstraction of the device controller.
 133  * @gadget: Instance of usb_gadget which is referenced by gadget driver.
 134  * @driver: Reference to currenty active gadget driver.
 135  * @dev: The device reference used by probe function.
 136  * @lock: Lock to synchronize the usage of Endpoints (EP's are indexed).
 137  * @regs: Remapped base address of controller's register space.
 138  * @mem_rsrc: Device memory resource used for remapping device register space.
 139  * irq: IRQ number used by the controller.
 140  * uclk: Reference to the controller clock.
 141  * ep0state: Current state of EP0.
 142  * ep: List of endpoints supported by the controller.
 143  */
 144 struct s3c_hsudc {
 145         struct usb_gadget gadget;
 146         struct usb_gadget_driver *driver;
 147         struct device *dev;
 148         struct s3c24xx_hsudc_platdata *pd;
 149         struct usb_phy *transceiver;
 150         struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsudc_supply_names)];
 151         spinlock_t lock;
 152         void __iomem *regs;
 153         struct resource *mem_rsrc;
 154         int irq;
 155         struct clk *uclk;
 156         int ep0state;
 157         struct s3c_hsudc_ep ep[];
 158 };
 159
 160 #define ep_maxpacket(_ep)       ((_ep)->ep.maxpacket)
 161 #define ep_is_in(_ep)           ((_ep)->bEndpointAddress & USB_DIR_IN)
 162 #define ep_index(_ep)           ((_ep)->bEndpointAddress & \
 163                                         USB_ENDPOINT_NUMBER_MASK)
 164
 165 static const char driver_name[] = "s3c-udc";
 166 static const char ep0name[] = "ep0-control";
 167
 168 static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
 169 {
 170         return container_of(req, struct s3c_hsudc_req, req);
 171 }
 172
 173 static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
 174 {
 175         return container_of(ep, struct s3c_hsudc_ep, ep);
 176 }
 177
 178 static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
 179 {
 180         return container_of(gadget, struct s3c_hsudc, gadget);
 181 }
 182
 183 static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
 184 {
 185         ep_addr &= USB_ENDPOINT_NUMBER_MASK;
 186         writel(ep_addr, hsudc->regs + S3C_IR);
 187 }
 188
 189 static inline void __orr32(void __iomem *ptr, u32 val)
 190 {
 191         writel(readl(ptr) | val, ptr);
 192 }
 193
 194 static void s3c_hsudc_init_phy(void)
 195 {
 196         u32 cfg;
 197
 198         cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
 199         writel(cfg, S3C2443_PWRCFG);
 200
 201         cfg = readl(S3C2443_URSTCON);
 202         cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
 203         writel(cfg, S3C2443_URSTCON);
 204         mdelay(1);
 205
 206         cfg = readl(S3C2443_URSTCON);
 207         cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
 208         writel(cfg, S3C2443_URSTCON);
 209
 210         cfg = readl(S3C2443_PHYCTRL);
 211         cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
 212         cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
 213         writel(cfg, S3C2443_PHYCTRL);
 214
 215         cfg = readl(S3C2443_PHYPWR);
 216         cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
 217                 S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
 218                 S3C2443_PHYPWR_ANALOG_PD);
 219         cfg |= S3C2443_PHYPWR_COMMON_ON;
 220         writel(cfg, S3C2443_PHYPWR);
 221
 222         cfg = readl(S3C2443_UCLKCON);
 223         cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
 224                 S3C2443_UCLKCON_TCLKEN);
 225         writel(cfg, S3C2443_UCLKCON);
 226 }
 227
 228 static void s3c_hsudc_uninit_phy(void)
 229 {
 230         u32 cfg;
 231
 232         cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
 233         writel(cfg, S3C2443_PWRCFG);
 234
 235         writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
 236
 237         cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
 238         writel(cfg, S3C2443_UCLKCON);
 239 }
 240
 241 /**
 242  * s3c_hsudc_complete_request - Complete a transfer request.
 243  * @hsep: Endpoint to which the request belongs.
 244  * @hsreq: Transfer request to be completed.
 245  * @status: Transfer completion status for the transfer request.
 246  */
 247 static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
 248                                 struct s3c_hsudc_req *hsreq, int status)
 249 {
 250         unsigned int stopped = hsep->stopped;
 251         struct s3c_hsudc *hsudc = hsep->dev;
 252
 253         list_del_init(&hsreq->queue);
 254         hsreq->req.status = status;
 255
 256         if (!ep_index(hsep)) {
 257                 hsudc->ep0state = WAIT_FOR_SETUP;
 258                 hsep->bEndpointAddress &= ~USB_DIR_IN;
 259         }
 260
 261         hsep->stopped = 1;
 262         spin_unlock(&hsudc->lock);
 263         if (hsreq->req.complete != NULL)
 264                 hsreq->req.complete(&hsep->ep, &hsreq->req);
 265         spin_lock(&hsudc->lock);
 266         hsep->stopped = stopped;
 267 }
 268
 269 /**
 270  * s3c_hsudc_nuke_ep - Terminate all requests queued for a endpoint.
 271  * @hsep: Endpoint for which queued requests have to be terminated.
 272  * @status: Transfer completion status for the transfer request.
 273  */
 274 static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
 275 {
 276         struct s3c_hsudc_req *hsreq;
 277
 278         while (!list_empty(&hsep->queue)) {
 279                 hsreq = list_entry(hsep->queue.next,
 280                                 struct s3c_hsudc_req, queue);
 281                 s3c_hsudc_complete_request(hsep, hsreq, status);
 282         }
 283 }
 284
 285 /**
 286  * s3c_hsudc_stop_activity - Stop activity on all endpoints.
 287  * @hsudc: Device controller for which EP activity is to be stopped.
 288  * @driver: Reference to the gadget driver which is currently active.
 289  *
 290  * All the endpoints are stopped and any pending transfer requests if any on
 291  * the endpoint are terminated.
 292  */
 293 static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc)
 294 {
 295         struct s3c_hsudc_ep *hsep;
 296         int epnum;
 297
 298         hsudc->gadget.speed = USB_SPEED_UNKNOWN;
 299
 300         for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
 301                 hsep = &hsudc->ep[epnum];
 302                 hsep->stopped = 1;
 303                 s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
 304         }
 305 }
 306
 307 /**
 308  * s3c_hsudc_read_setup_pkt - Read the received setup packet from EP0 fifo.
 309  * @hsudc: Device controller from which setup packet is to be read.
 310  * @buf: The buffer into which the setup packet is read.
 311  *
 312  * The setup packet received in the EP0 fifo is read and stored into a
 313  * given buffer address.
 314  */
 315
 316 static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
 317 {
 318         int count;
 319
 320         count = readl(hsudc->regs + S3C_BRCR);
 321         while (count--)
 322                 *buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
 323
 324         writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR);
 325 }
 326
 327 /**
 328  * s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
 329  * @hsep: Endpoint to which the data is to be written.
 330  * @hsreq: Transfer request from which the next chunk of data is written.
 331  *
 332  * Write the next chunk of data from a transfer request to the endpoint FIFO.
 333  * If the transfer request completes, 1 is returned, otherwise 0 is returned.
 334  */
 335 static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
 336                                 struct s3c_hsudc_req *hsreq)
 337 {
 338         u16 *buf;
 339         u32 max = ep_maxpacket(hsep);
 340         u32 count, length;
 341         bool is_last;
 342         void __iomem *fifo = hsep->fifo;
 343
 344         buf = hsreq->req.buf + hsreq->req.actual;
 345         prefetch(buf);
 346
 347         length = hsreq->req.length - hsreq->req.actual;
 348         length = min(length, max);
 349         hsreq->req.actual += length;
 350
 351         writel(length, hsep->dev->regs + S3C_BWCR);
 352         for (count = 0; count < length; count += 2)
 353                 writel(*buf++, fifo);
 354
 355         if (count != max) {
 356                 is_last = true;
 357         } else {
 358                 if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
 359                         is_last = false;
 360                 else
 361                         is_last = true;
 362         }
 363
 364         if (is_last) {
 365                 s3c_hsudc_complete_request(hsep, hsreq, 0);
 366                 return 1;
 367         }
 368
 369         return 0;
 370 }
 371
 372 /**
 373  * s3c_hsudc_read_fifo - Read the next chunk of data from EP fifo.
 374  * @hsep: Endpoint from which the data is to be read.
 375  * @hsreq: Transfer request to which the next chunk of data read is written.
 376  *
 377  * Read the next chunk of data from the endpoint FIFO and a write it to the
 378  * transfer request buffer. If the transfer request completes, 1 is returned,
 379  * otherwise 0 is returned.
 380  */
 381 static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
 382                                 struct s3c_hsudc_req *hsreq)
 383 {
 384         struct s3c_hsudc *hsudc = hsep->dev;
 385         u32 csr, offset;
 386         u16 *buf, word;
 387         u32 buflen, rcnt, rlen;
 388         void __iomem *fifo = hsep->fifo;
 389         u32 is_short = 0;
 390
 391         offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
 392         csr = readl(hsudc->regs + offset);
 393         if (!(csr & S3C_ESR_RX_SUCCESS))
 394                 return -EINVAL;
 395
 396         buf = hsreq->req.buf + hsreq->req.actual;
 397         prefetchw(buf);
 398         buflen = hsreq->req.length - hsreq->req.actual;
 399
 400         rcnt = readl(hsudc->regs + S3C_BRCR);
 401         rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
 402
 403         hsreq->req.actual += min(rlen, buflen);
 404         is_short = (rlen < hsep->ep.maxpacket);
 405
 406         while (rcnt-- != 0) {
 407                 word = (u16)readl(fifo);
 408                 if (buflen) {
 409                         *buf++ = word;
 410                         buflen--;
 411                 } else {
 412                         hsreq->req.status = -EOVERFLOW;
 413                 }
 414         }
 415
 416         writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
 417
 418         if (is_short || hsreq->req.actual == hsreq->req.length) {
 419                 s3c_hsudc_complete_request(hsep, hsreq, 0);
 420                 return 1;
 421         }
 422
 423         return 0;
 424 }
 425
 426 /**
 427  * s3c_hsudc_epin_intr - Handle in-endpoint interrupt.
 428  * @hsudc - Device controller for which the interrupt is to be handled.
 429  * @ep_idx - Endpoint number on which an interrupt is pending.
 430  *
 431  * Handles interrupt for a in-endpoint. The interrupts that are handled are
 432  * stall and data transmit complete interrupt.
 433  */
 434 static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
 435 {
 436         struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
 437         struct s3c_hsudc_req *hsreq;
 438         u32 csr;
 439
 440         csr = readl((u32)hsudc->regs + S3C_ESR);
 441         if (csr & S3C_ESR_STALL) {
 442                 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
 443                 return;
 444         }
 445
 446         if (csr & S3C_ESR_TX_SUCCESS) {
 447                 writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
 448                 if (list_empty(&hsep->queue))
 449                         return;
 450
 451                 hsreq = list_entry(hsep->queue.next,
 452                                 struct s3c_hsudc_req, queue);
 453                 if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
 454                                 (csr & S3C_ESR_PSIF_TWO))
 455                         s3c_hsudc_write_fifo(hsep, hsreq);
 456         }
 457 }
 458
 459 /**
 460  * s3c_hsudc_epout_intr - Handle out-endpoint interrupt.
 461  * @hsudc - Device controller for which the interrupt is to be handled.
 462  * @ep_idx - Endpoint number on which an interrupt is pending.
 463  *
 464  * Handles interrupt for a out-endpoint. The interrupts that are handled are
 465  * stall, flush and data ready interrupt.
 466  */
 467 static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
 468 {
 469         struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
 470         struct s3c_hsudc_req *hsreq;
 471         u32 csr;
 472
 473         csr = readl((u32)hsudc->regs + S3C_ESR);
 474         if (csr & S3C_ESR_STALL) {
 475                 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
 476                 return;
 477         }
 478
 479         if (csr & S3C_ESR_FLUSH) {
 480                 __orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
 481                 return;
 482         }
 483
 484         if (csr & S3C_ESR_RX_SUCCESS) {
 485                 if (list_empty(&hsep->queue))
 486                         return;
 487
 488                 hsreq = list_entry(hsep->queue.next,
 489                                 struct s3c_hsudc_req, queue);
 490                 if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
 491                                 (csr & S3C_ESR_PSIF_TWO))
 492                         s3c_hsudc_read_fifo(hsep, hsreq);
 493         }
 494 }
 495
 496 /** s3c_hsudc_set_halt - Set or clear a endpoint halt.
 497  * @_ep: Endpoint on which halt has to be set or cleared.
 498  * @value: 1 for setting halt on endpoint, 0 to clear halt.
 499  *
 500  * Set or clear endpoint halt. If halt is set, the endpoint is stopped.
 501  * If halt is cleared, for in-endpoints, if there are any pending
 502  * transfer requests, transfers are started.
 503  */
 504 static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
 505 {
 506         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 507         struct s3c_hsudc *hsudc = hsep->dev;
 508         struct s3c_hsudc_req *hsreq;
 509         unsigned long irqflags;
 510         u32 ecr;
 511         u32 offset;
 512
 513         if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
 514                 return -EAGAIN;
 515
 516         spin_lock_irqsave(&hsudc->lock, irqflags);
 517         set_index(hsudc, ep_index(hsep));
 518         offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
 519         ecr = readl(hsudc->regs + offset);
 520
 521         if (value) {
 522                 ecr |= S3C_ECR_STALL;
 523                 if (ep_index(hsep))
 524                         ecr |= S3C_ECR_FLUSH;
 525                 hsep->stopped = 1;
 526         } else {
 527                 ecr &= ~S3C_ECR_STALL;
 528                 hsep->stopped = hsep->wedge = 0;
 529         }
 530         writel(ecr, hsudc->regs + offset);
 531
 532         if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
 533                 hsreq = list_entry(hsep->queue.next,
 534                         struct s3c_hsudc_req, queue);
 535                 if (hsreq)
 536                         s3c_hsudc_write_fifo(hsep, hsreq);
 537         }
 538
 539         spin_unlock_irqrestore(&hsudc->lock, irqflags);
 540         return 0;
 541 }
 542
 543 /** s3c_hsudc_set_wedge - Sets the halt feature with the clear requests ignored
 544  * @_ep: Endpoint on which wedge has to be set.
 545  *
 546  * Sets the halt feature with the clear requests ignored.
 547  */
 548 static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
 549 {
 550         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 551
 552         if (!hsep)
 553                 return -EINVAL;
 554
 555         hsep->wedge = 1;
 556         return usb_ep_set_halt(_ep);
 557 }
 558
 559 /** s3c_hsudc_handle_reqfeat - Handle set feature or clear feature requests.
 560  * @_ep: Device controller on which the set/clear feature needs to be handled.
 561  * @ctrl: Control request as received on the endpoint 0.
 562  *
 563  * Handle set feature or clear feature control requests on the control endpoint.
 564  */
 565 static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
 566                                         struct usb_ctrlrequest *ctrl)
 567 {
 568         struct s3c_hsudc_ep *hsep;
 569         bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
 570         u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
 571
 572         if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
 573                 hsep = &hsudc->ep[ep_num];
 574                 switch (le16_to_cpu(ctrl->wValue)) {
 575                 case USB_ENDPOINT_HALT:
 576                         if (set || (!set && !hsep->wedge))
 577                                 s3c_hsudc_set_halt(&hsep->ep, set);
 578                         return 0;
 579                 }
 580         }
 581
 582         return -ENOENT;
 583 }
 584
 585 /**
 586  * s3c_hsudc_process_req_status - Handle get status control request.
 587  * @hsudc: Device controller on which get status request has be handled.
 588  * @ctrl: Control request as received on the endpoint 0.
 589  *
 590  * Handle get status control request received on control endpoint.
 591  */
 592 static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
 593                                         struct usb_ctrlrequest *ctrl)
 594 {
 595         struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
 596         struct s3c_hsudc_req hsreq;
 597         struct s3c_hsudc_ep *hsep;
 598         __le16 reply;
 599         u8 epnum;
 600
 601         switch (ctrl->bRequestType & USB_RECIP_MASK) {
 602         case USB_RECIP_DEVICE:
 603                 reply = cpu_to_le16(0);
 604                 break;
 605
 606         case USB_RECIP_INTERFACE:
 607                 reply = cpu_to_le16(0);
 608                 break;
 609
 610         case USB_RECIP_ENDPOINT:
 611                 epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
 612                 hsep = &hsudc->ep[epnum];
 613                 reply = cpu_to_le16(hsep->stopped ? 1 : 0);
 614                 break;
 615         }
 616
 617         INIT_LIST_HEAD(&hsreq.queue);
 618         hsreq.req.length = 2;
 619         hsreq.req.buf = &reply;
 620         hsreq.req.actual = 0;
 621         hsreq.req.complete = NULL;
 622         s3c_hsudc_write_fifo(hsep0, &hsreq);
 623 }
 624
 625 /**
 626  * s3c_hsudc_process_setup - Process control request received on endpoint 0.
 627  * @hsudc: Device controller on which control request has been received.
 628  *
 629  * Read the control request received on endpoint 0, decode it and handle
 630  * the request.
 631  */
 632 static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
 633 {
 634         struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
 635         struct usb_ctrlrequest ctrl = {0};
 636         int ret;
 637
 638         s3c_hsudc_nuke_ep(hsep, -EPROTO);
 639         s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
 640
 641         if (ctrl.bRequestType & USB_DIR_IN) {
 642                 hsep->bEndpointAddress |= USB_DIR_IN;
 643                 hsudc->ep0state = DATA_STATE_XMIT;
 644         } else {
 645                 hsep->bEndpointAddress &= ~USB_DIR_IN;
 646                 hsudc->ep0state = DATA_STATE_RECV;
 647         }
 648
 649         switch (ctrl.bRequest) {
 650         case USB_REQ_SET_ADDRESS:
 651                 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
 652                         break;
 653                 hsudc->ep0state = WAIT_FOR_SETUP;
 654                 return;
 655
 656         case USB_REQ_GET_STATUS:
 657                 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
 658                         break;
 659                 s3c_hsudc_process_req_status(hsudc, &ctrl);
 660                 return;
 661
 662         case USB_REQ_SET_FEATURE:
 663         case USB_REQ_CLEAR_FEATURE:
 664                 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
 665                         break;
 666                 s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
 667                 hsudc->ep0state = WAIT_FOR_SETUP;
 668                 return;
 669         }
 670
 671         if (hsudc->driver) {
 672                 spin_unlock(&hsudc->lock);
 673                 ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
 674                 spin_lock(&hsudc->lock);
 675
 676                 if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
 677                         hsep->bEndpointAddress &= ~USB_DIR_IN;
 678                         hsudc->ep0state = WAIT_FOR_SETUP;
 679                 }
 680
 681                 if (ret < 0) {
 682                         dev_err(hsudc->dev, "setup failed, returned %d\n",
 683                                                 ret);
 684                         s3c_hsudc_set_halt(&hsep->ep, 1);
 685                         hsudc->ep0state = WAIT_FOR_SETUP;
 686                         hsep->bEndpointAddress &= ~USB_DIR_IN;
 687                 }
 688         }
 689 }
 690
 691 /** s3c_hsudc_handle_ep0_intr - Handle endpoint 0 interrupt.
 692  * @hsudc: Device controller on which endpoint 0 interrupt has occured.
 693  *
 694  * Handle endpoint 0 interrupt when it occurs. EP0 interrupt could occur
 695  * when a stall handshake is sent to host or data is sent/received on
 696  * endpoint 0.
 697  */
 698 static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
 699 {
 700         struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
 701         struct s3c_hsudc_req *hsreq;
 702         u32 csr = readl(hsudc->regs + S3C_EP0SR);
 703         u32 ecr;
 704
 705         if (csr & S3C_EP0SR_STALL) {
 706                 ecr = readl(hsudc->regs + S3C_EP0CR);
 707                 ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
 708                 writel(ecr, hsudc->regs + S3C_EP0CR);
 709
 710                 writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
 711                 hsep->stopped = 0;
 712
 713                 s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
 714                 hsudc->ep0state = WAIT_FOR_SETUP;
 715                 hsep->bEndpointAddress &= ~USB_DIR_IN;
 716                 return;
 717         }
 718
 719         if (csr & S3C_EP0SR_TX_SUCCESS) {
 720                 writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
 721                 if (ep_is_in(hsep)) {
 722                         if (list_empty(&hsep->queue))
 723                                 return;
 724
 725                         hsreq = list_entry(hsep->queue.next,
 726                                         struct s3c_hsudc_req, queue);
 727                         s3c_hsudc_write_fifo(hsep, hsreq);
 728                 }
 729         }
 730
 731         if (csr & S3C_EP0SR_RX_SUCCESS) {
 732                 if (hsudc->ep0state == WAIT_FOR_SETUP)
 733                         s3c_hsudc_process_setup(hsudc);
 734                 else {
 735                         if (!ep_is_in(hsep)) {
 736                                 if (list_empty(&hsep->queue))
 737                                         return;
 738                                 hsreq = list_entry(hsep->queue.next,
 739                                         struct s3c_hsudc_req, queue);
 740                                 s3c_hsudc_read_fifo(hsep, hsreq);
 741                         }
 742                 }
 743         }
 744 }
 745
 746 /**
 747  * s3c_hsudc_ep_enable - Enable a endpoint.
 748  * @_ep: The endpoint to be enabled.
 749  * @desc: Endpoint descriptor.
 750  *
 751  * Enables a endpoint when called from the gadget driver. Endpoint stall if
 752  * any is cleared, transfer type is configured and endpoint interrupt is
 753  * enabled.
 754  */
 755 static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
 756                                 const struct usb_endpoint_descriptor *desc)
 757 {
 758         struct s3c_hsudc_ep *hsep;
 759         struct s3c_hsudc *hsudc;
 760         unsigned long flags;
 761         u32 ecr = 0;
 762
 763         hsep = our_ep(_ep);
 764         if (!_ep || !desc || _ep->name == ep0name
 765                 || desc->bDescriptorType != USB_DT_ENDPOINT
 766                 || hsep->bEndpointAddress != desc->bEndpointAddress
 767                 || ep_maxpacket(hsep) < usb_endpoint_maxp(desc))
 768                 return -EINVAL;
 769
 770         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 771                 && usb_endpoint_maxp(desc) != ep_maxpacket(hsep))
 772                 || !desc->wMaxPacketSize)
 773                 return -ERANGE;
 774
 775         hsudc = hsep->dev;
 776         if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
 777                 return -ESHUTDOWN;
 778
 779         spin_lock_irqsave(&hsudc->lock, flags);
 780
 781         set_index(hsudc, hsep->bEndpointAddress);
 782         ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
 783         writel(ecr, hsudc->regs + S3C_ECR);
 784
 785         hsep->stopped = hsep->wedge = 0;
 786         hsep->ep.desc = desc;
 787         hsep->ep.maxpacket = usb_endpoint_maxp(desc);
 788
 789         s3c_hsudc_set_halt(_ep, 0);
 790         __set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
 791
 792         spin_unlock_irqrestore(&hsudc->lock, flags);
 793         return 0;
 794 }
 795
 796 /**
 797  * s3c_hsudc_ep_disable - Disable a endpoint.
 798  * @_ep: The endpoint to be disabled.
 799  * @desc: Endpoint descriptor.
 800  *
 801  * Disables a endpoint when called from the gadget driver.
 802  */
 803 static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
 804 {
 805         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 806         struct s3c_hsudc *hsudc = hsep->dev;
 807         unsigned long flags;
 808
 809         if (!_ep || !hsep->ep.desc)
 810                 return -EINVAL;
 811
 812         spin_lock_irqsave(&hsudc->lock, flags);
 813
 814         set_index(hsudc, hsep->bEndpointAddress);
 815         __clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
 816
 817         s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
 818
 819         hsep->ep.desc = NULL;
 820         hsep->stopped = 1;
 821
 822         spin_unlock_irqrestore(&hsudc->lock, flags);
 823         return 0;
 824 }
 825
 826 /**
 827  * s3c_hsudc_alloc_request - Allocate a new request.
 828  * @_ep: Endpoint for which request is allocated (not used).
 829  * @gfp_flags: Flags used for the allocation.
 830  *
 831  * Allocates a single transfer request structure when called from gadget driver.
 832  */
 833 static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
 834                                                 gfp_t gfp_flags)
 835 {
 836         struct s3c_hsudc_req *hsreq;
 837
 838         hsreq = kzalloc(sizeof *hsreq, gfp_flags);
 839         if (!hsreq)
 840                 return 0;
 841
 842         INIT_LIST_HEAD(&hsreq->queue);
 843         return &hsreq->req;
 844 }
 845
 846 /**
 847  * s3c_hsudc_free_request - Deallocate a request.
 848  * @ep: Endpoint for which request is deallocated (not used).
 849  * @_req: Request to be deallocated.
 850  *
 851  * Allocates a single transfer request structure when called from gadget driver.
 852  */
 853 static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
 854 {
 855         struct s3c_hsudc_req *hsreq;
 856
 857         hsreq = our_req(_req);
 858         WARN_ON(!list_empty(&hsreq->queue));
 859         kfree(hsreq);
 860 }
 861
 862 /**
 863  * s3c_hsudc_queue - Queue a transfer request for the endpoint.
 864  * @_ep: Endpoint for which the request is queued.
 865  * @_req: Request to be queued.
 866  * @gfp_flags: Not used.
 867  *
 868  * Start or enqueue a request for a endpoint when called from gadget driver.
 869  */
 870 static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
 871                         gfp_t gfp_flags)
 872 {
 873         struct s3c_hsudc_req *hsreq;
 874         struct s3c_hsudc_ep *hsep;
 875         struct s3c_hsudc *hsudc;
 876         unsigned long flags;
 877         u32 offset;
 878         u32 csr;
 879
 880         hsreq = our_req(_req);
 881         if ((!_req || !_req->complete || !_req->buf ||
 882                 !list_empty(&hsreq->queue)))
 883                 return -EINVAL;
 884
 885         hsep = our_ep(_ep);
 886         hsudc = hsep->dev;
 887         if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
 888                 return -ESHUTDOWN;
 889
 890         spin_lock_irqsave(&hsudc->lock, flags);
 891         set_index(hsudc, hsep->bEndpointAddress);
 892
 893         _req->status = -EINPROGRESS;
 894         _req->actual = 0;
 895
 896         if (!ep_index(hsep) && _req->length == 0) {
 897                 hsudc->ep0state = WAIT_FOR_SETUP;
 898                 s3c_hsudc_complete_request(hsep, hsreq, 0);
 899                 spin_unlock_irqrestore(&hsudc->lock, flags);
 900                 return 0;
 901         }
 902
 903         if (list_empty(&hsep->queue) && !hsep->stopped) {
 904                 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
 905                 if (ep_is_in(hsep)) {
 906                         csr = readl((u32)hsudc->regs + offset);
 907                         if (!(csr & S3C_ESR_TX_SUCCESS) &&
 908                                 (s3c_hsudc_write_fifo(hsep, hsreq) == 1))
 909                                 hsreq = 0;
 910                 } else {
 911                         csr = readl((u32)hsudc->regs + offset);
 912                         if ((csr & S3C_ESR_RX_SUCCESS)
 913                                    && (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
 914                                 hsreq = 0;
 915                 }
 916         }
 917
 918         if (hsreq != 0)
 919                 list_add_tail(&hsreq->queue, &hsep->queue);
 920
 921         spin_unlock_irqrestore(&hsudc->lock, flags);
 922         return 0;
 923 }
 924
 925 /**
 926  * s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
 927  * @_ep: Endpoint from which the request is dequeued.
 928  * @_req: Request to be dequeued.
 929  *
 930  * Dequeue a request from a endpoint when called from gadget driver.
 931  */
 932 static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 933 {
 934         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 935         struct s3c_hsudc *hsudc = hsep->dev;
 936         struct s3c_hsudc_req *hsreq;
 937         unsigned long flags;
 938
 939         hsep = our_ep(_ep);
 940         if (!_ep || hsep->ep.name == ep0name)
 941                 return -EINVAL;
 942
 943         spin_lock_irqsave(&hsudc->lock, flags);
 944
 945         list_for_each_entry(hsreq, &hsep->queue, queue) {
 946                 if (&hsreq->req == _req)
 947                         break;
 948         }
 949         if (&hsreq->req != _req) {
 950                 spin_unlock_irqrestore(&hsudc->lock, flags);
 951                 return -EINVAL;
 952         }
 953
 954         set_index(hsudc, hsep->bEndpointAddress);
 955         s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
 956
 957         spin_unlock_irqrestore(&hsudc->lock, flags);
 958         return 0;
 959 }
 960
 961 static struct usb_ep_ops s3c_hsudc_ep_ops = {
 962         .enable = s3c_hsudc_ep_enable,
 963         .disable = s3c_hsudc_ep_disable,
 964         .alloc_request = s3c_hsudc_alloc_request,
 965         .free_request = s3c_hsudc_free_request,
 966         .queue = s3c_hsudc_queue,
 967         .dequeue = s3c_hsudc_dequeue,
 968         .set_halt = s3c_hsudc_set_halt,
 969         .set_wedge = s3c_hsudc_set_wedge,
 970 };
 971
 972 /**
 973  * s3c_hsudc_initep - Initialize a endpoint to default state.
 974  * @hsudc - Reference to the device controller.
 975  * @hsep - Endpoint to be initialized.
 976  * @epnum - Address to be assigned to the endpoint.
 977  *
 978  * Initialize a endpoint with default configuration.
 979  */
 980 static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
 981                                 struct s3c_hsudc_ep *hsep, int epnum)
 982 {
 983         char *dir;
 984
 985         if ((epnum % 2) == 0) {
 986                 dir = "out";
 987         } else {
 988                 dir = "in";
 989                 hsep->bEndpointAddress = USB_DIR_IN;
 990         }
 991
 992         hsep->bEndpointAddress |= epnum;
 993         if (epnum)
 994                 snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
 995         else
 996                 snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
 997
 998         INIT_LIST_HEAD(&hsep->queue);
 999         INIT_LIST_HEAD(&hsep->ep.ep_list);
1000         if (epnum)
1001                 list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
1002
1003         hsep->dev = hsudc;
1004         hsep->ep.name = hsep->name;
1005         hsep->ep.maxpacket = epnum ? 512 : 64;
1006         hsep->ep.ops = &s3c_hsudc_ep_ops;
1007         hsep->fifo = hsudc->regs + S3C_BR(epnum);
1008         hsep->ep.desc = NULL;
1009         hsep->stopped = 0;
1010         hsep->wedge = 0;
1011
1012         set_index(hsudc, epnum);
1013         writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
1014 }
1015
1016 /**
1017  * s3c_hsudc_setup_ep - Configure all endpoints to default state.
1018  * @hsudc: Reference to device controller.
1019  *
1020  * Configures all endpoints to default state.
1021  */
1022 static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
1023 {
1024         int epnum;
1025
1026         hsudc->ep0state = WAIT_FOR_SETUP;
1027         INIT_LIST_HEAD(&hsudc->gadget.ep_list);
1028         for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
1029                 s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
1030 }
1031
1032 /**
1033  * s3c_hsudc_reconfig - Reconfigure the device controller to default state.
1034  * @hsudc: Reference to device controller.
1035  *
1036  * Reconfigures the device controller registers to a default state.
1037  */
1038 static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
1039 {
1040         writel(0xAA, hsudc->regs + S3C_EDR);
1041         writel(1, hsudc->regs + S3C_EIER);
1042         writel(0, hsudc->regs + S3C_TR);
1043         writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN |
1044                         S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
1045         writel(0, hsudc->regs + S3C_EP0CR);
1046
1047         s3c_hsudc_setup_ep(hsudc);
1048 }
1049
1050 /**
1051  * s3c_hsudc_irq - Interrupt handler for device controller.
1052  * @irq: Not used.
1053  * @_dev: Reference to the device controller.
1054  *
1055  * Interrupt handler for the device controller. This handler handles controller
1056  * interrupts and endpoint interrupts.
1057  */
1058 static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
1059 {
1060         struct s3c_hsudc *hsudc = _dev;
1061         struct s3c_hsudc_ep *hsep;
1062         u32 ep_intr;
1063         u32 sys_status;
1064         u32 ep_idx;
1065
1066         spin_lock(&hsudc->lock);
1067
1068         sys_status = readl(hsudc->regs + S3C_SSR);
1069         ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
1070
1071         if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
1072                 spin_unlock(&hsudc->lock);
1073                 return IRQ_HANDLED;
1074         }
1075
1076         if (sys_status) {
1077                 if (sys_status & S3C_SSR_VBUSON)
1078                         writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
1079
1080                 if (sys_status & S3C_SSR_ERR)
1081                         writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
1082
1083                 if (sys_status & S3C_SSR_SDE) {
1084                         writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
1085                         hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
1086                                 USB_SPEED_HIGH : USB_SPEED_FULL;
1087                 }
1088
1089                 if (sys_status & S3C_SSR_SUSPEND) {
1090                         writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
1091                         if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1092                                 && hsudc->driver && hsudc->driver->suspend)
1093                                 hsudc->driver->suspend(&hsudc->gadget);
1094                 }
1095
1096                 if (sys_status & S3C_SSR_RESUME) {
1097                         writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
1098                         if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1099                                 && hsudc->driver && hsudc->driver->resume)
1100                                 hsudc->driver->resume(&hsudc->gadget);
1101                 }
1102
1103                 if (sys_status & S3C_SSR_RESET) {
1104                         writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
1105                         for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
1106                                 hsep = &hsudc->ep[ep_idx];
1107                                 hsep->stopped = 1;
1108                                 s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
1109                         }
1110                         s3c_hsudc_reconfig(hsudc);
1111                         hsudc->ep0state = WAIT_FOR_SETUP;
1112                 }
1113         }
1114
1115         if (ep_intr & S3C_EIR_EP0) {
1116                 writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
1117                 set_index(hsudc, 0);
1118                 s3c_hsudc_handle_ep0_intr(hsudc);
1119         }
1120
1121         ep_intr >>= 1;
1122         ep_idx = 1;
1123         while (ep_intr) {
1124                 if (ep_intr & 1)  {
1125                         hsep = &hsudc->ep[ep_idx];
1126                         set_index(hsudc, ep_idx);
1127                         writel(1 << ep_idx, hsudc->regs + S3C_EIR);
1128                         if (ep_is_in(hsep))
1129                                 s3c_hsudc_epin_intr(hsudc, ep_idx);
1130                         else
1131                                 s3c_hsudc_epout_intr(hsudc, ep_idx);
1132                 }
1133                 ep_intr >>= 1;
1134                 ep_idx++;
1135         }
1136
1137         spin_unlock(&hsudc->lock);
1138         return IRQ_HANDLED;
1139 }
1140
1141 static int s3c_hsudc_start(struct usb_gadget *gadget,
1142                 struct usb_gadget_driver *driver)
1143 {
1144         struct s3c_hsudc *hsudc = to_hsudc(gadget);
1145         int ret;
1146
1147         if (!driver
1148                 || driver->max_speed < USB_SPEED_FULL
1149                 || !driver->setup)
1150                 return -EINVAL;
1151
1152         if (!hsudc)
1153                 return -ENODEV;
1154
1155         if (hsudc->driver)
1156                 return -EBUSY;
1157
1158         hsudc->driver = driver;
1159         hsudc->gadget.dev.driver = &driver->driver;
1160
1161         ret = regulator_bulk_enable(ARRAY_SIZE(hsudc->supplies),
1162                                     hsudc->supplies);
1163         if (ret != 0) {
1164                 dev_err(hsudc->dev, "failed to enable supplies: %d\n", ret);
1165                 goto err_supplies;
1166         }
1167
1168         /* connect to bus through transceiver */
1169         if (!IS_ERR_OR_NULL(hsudc->transceiver)) {
1170                 ret = otg_set_peripheral(hsudc->transceiver->otg,
1171                                         &hsudc->gadget);
1172                 if (ret) {
1173                         dev_err(hsudc->dev, "%s: can't bind to transceiver\n",
1174                                         hsudc->gadget.name);
1175                         goto err_otg;
1176                 }
1177         }
1178
1179         enable_irq(hsudc->irq);
1180         dev_info(hsudc->dev, "bound driver %s\n", driver->driver.name);
1181
1182         s3c_hsudc_reconfig(hsudc);
1183
1184         pm_runtime_get_sync(hsudc->dev);
1185
1186         s3c_hsudc_init_phy();
1187         if (hsudc->pd->gpio_init)
1188                 hsudc->pd->gpio_init();
1189
1190         return 0;
1191 err_otg:
1192         regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1193 err_supplies:
1194         hsudc->driver = NULL;
1195         hsudc->gadget.dev.driver = NULL;
1196         return ret;
1197 }
1198
1199 static int s3c_hsudc_stop(struct usb_gadget *gadget,
1200                 struct usb_gadget_driver *driver)
1201 {
1202         struct s3c_hsudc *hsudc = to_hsudc(gadget);
1203         unsigned long flags;
1204
1205         if (!hsudc)
1206                 return -ENODEV;
1207
1208         if (!driver || driver != hsudc->driver)
1209                 return -EINVAL;
1210
1211         spin_lock_irqsave(&hsudc->lock, flags);
1212         hsudc->driver = NULL;
1213         hsudc->gadget.dev.driver = NULL;
1214         hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1215         s3c_hsudc_uninit_phy();
1216
1217         pm_runtime_put(hsudc->dev);
1218
1219         if (hsudc->pd->gpio_uninit)
1220                 hsudc->pd->gpio_uninit();
1221         s3c_hsudc_stop_activity(hsudc);
1222         spin_unlock_irqrestore(&hsudc->lock, flags);
1223
1224         if (!IS_ERR_OR_NULL(hsudc->transceiver))
1225                 (void) otg_set_peripheral(hsudc->transceiver->otg, NULL);
1226
1227         disable_irq(hsudc->irq);
1228
1229         regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1230
1231         dev_info(hsudc->dev, "unregistered gadget driver '%s'\n",
1232                         driver->driver.name);
1233         return 0;
1234 }
1235
1236 static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
1237 {
1238         return readl(hsudc->regs + S3C_FNR) & 0x3FF;
1239 }
1240
1241 static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
1242 {
1243         return s3c_hsudc_read_frameno(to_hsudc(gadget));
1244 }
1245
1246 static int s3c_hsudc_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1247 {
1248         struct s3c_hsudc *hsudc = to_hsudc(gadget);
1249
1250         if (!hsudc)
1251                 return -ENODEV;
1252
1253         if (!IS_ERR_OR_NULL(hsudc->transceiver))
1254                 return usb_phy_set_power(hsudc->transceiver, mA);
1255
1256         return -EOPNOTSUPP;
1257 }
1258
1259 static struct usb_gadget_ops s3c_hsudc_gadget_ops = {
1260         .get_frame      = s3c_hsudc_gadget_getframe,
1261         .udc_start      = s3c_hsudc_start,
1262         .udc_stop       = s3c_hsudc_stop,
1263         .vbus_draw      = s3c_hsudc_vbus_draw,
1264 };
1265
1266 static int __devinit s3c_hsudc_probe(struct platform_device *pdev)
1267 {
1268         struct device *dev = &pdev->dev;
1269         struct resource *res;
1270         struct s3c_hsudc *hsudc;
1271         struct s3c24xx_hsudc_platdata *pd = pdev->dev.platform_data;
1272         int ret, i;
1273
1274         hsudc = kzalloc(sizeof(struct s3c_hsudc) +
1275                         sizeof(struct s3c_hsudc_ep) * pd->epnum,
1276                         GFP_KERNEL);
1277         if (!hsudc) {
1278                 dev_err(dev, "cannot allocate memory\n");
1279                 return -ENOMEM;
1280         }
1281
1282         platform_set_drvdata(pdev, dev);
1283         hsudc->dev = dev;
1284         hsudc->pd = pdev->dev.platform_data;
1285
1286         hsudc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
1287
1288         for (i = 0; i < ARRAY_SIZE(hsudc->supplies); i++)
1289                 hsudc->supplies[i].supply = s3c_hsudc_supply_names[i];
1290
1291         ret = regulator_bulk_get(dev, ARRAY_SIZE(hsudc->supplies),
1292                                  hsudc->supplies);
1293         if (ret != 0) {
1294                 dev_err(dev, "failed to request supplies: %d\n", ret);
1295                 goto err_supplies;
1296         }
1297
1298         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1299         if (!res) {
1300                 dev_err(dev, "unable to obtain driver resource data\n");
1301                 ret = -ENODEV;
1302                 goto err_res;
1303         }
1304
1305         hsudc->mem_rsrc = request_mem_region(res->start, resource_size(res),
1306                                 dev_name(&pdev->dev));
1307         if (!hsudc->mem_rsrc) {
1308                 dev_err(dev, "failed to reserve register area\n");
1309                 ret = -ENODEV;
1310                 goto err_res;
1311         }
1312
1313         hsudc->regs = ioremap(res->start, resource_size(res));
1314         if (!hsudc->regs) {
1315                 dev_err(dev, "error mapping device register area\n");
1316                 ret = -EBUSY;
1317                 goto err_remap;
1318         }
1319
1320         spin_lock_init(&hsudc->lock);
1321
1322         dev_set_name(&hsudc->gadget.dev, "gadget");
1323
1324         hsudc->gadget.max_speed = USB_SPEED_HIGH;
1325         hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
1326         hsudc->gadget.name = dev_name(dev);
1327         hsudc->gadget.dev.parent = dev;
1328         hsudc->gadget.dev.dma_mask = dev->dma_mask;
1329         hsudc->gadget.ep0 = &hsudc->ep[0].ep;
1330
1331         hsudc->gadget.is_otg = 0;
1332         hsudc->gadget.is_a_peripheral = 0;
1333         hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1334
1335         s3c_hsudc_setup_ep(hsudc);
1336
1337         ret = platform_get_irq(pdev, 0);
1338         if (ret < 0) {
1339                 dev_err(dev, "unable to obtain IRQ number\n");
1340                 goto err_irq;
1341         }
1342         hsudc->irq = ret;
1343
1344         ret = request_irq(hsudc->irq, s3c_hsudc_irq, 0, driver_name, hsudc);
1345         if (ret < 0) {
1346                 dev_err(dev, "irq request failed\n");
1347                 goto err_irq;
1348         }
1349
1350         hsudc->uclk = clk_get(&pdev->dev, "usb-device");
1351         if (IS_ERR(hsudc->uclk)) {
1352                 dev_err(dev, "failed to find usb-device clock source\n");
1353                 ret = PTR_ERR(hsudc->uclk);
1354                 goto err_clk;
1355         }
1356         clk_enable(hsudc->uclk);
1357
1358         local_irq_disable();
1359
1360         disable_irq(hsudc->irq);
1361         local_irq_enable();
1362
1363         ret = device_register(&hsudc->gadget.dev);
1364         if (ret) {
1365                 put_device(&hsudc->gadget.dev);
1366                 goto err_add_device;
1367         }
1368
1369         ret = usb_add_gadget_udc(&pdev->dev, &hsudc->gadget);
1370         if (ret)
1371                 goto err_add_udc;
1372
1373         pm_runtime_enable(dev);
1374
1375         return 0;
1376 err_add_udc:
1377         device_unregister(&hsudc->gadget.dev);
1378 err_add_device:
1379         clk_disable(hsudc->uclk);
1380         clk_put(hsudc->uclk);
1381 err_clk:
1382         free_irq(hsudc->irq, hsudc);
1383 err_irq:
1384         iounmap(hsudc->regs);
1385
1386 err_remap:
1387         release_mem_region(res->start, resource_size(res));
1388 err_res:
1389         if (!IS_ERR_OR_NULL(hsudc->transceiver))
1390                 usb_put_phy(hsudc->transceiver);
1391
1392         regulator_bulk_free(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1393 err_supplies:
1394         kfree(hsudc);
1395         return ret;
1396 }
1397
1398 static struct platform_driver s3c_hsudc_driver = {
1399         .driver         = {
1400                 .owner  = THIS_MODULE,
1401                 .name   = "s3c-hsudc",
1402         },
1403         .probe          = s3c_hsudc_probe,
1404 };
1405
1406 module_platform_driver(s3c_hsudc_driver);
1407
1408 MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
1409 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1410 MODULE_LICENSE("GPL");
1411 MODULE_ALIAS("platform:s3c-hsudc");