drivers/usb/gadget/net2280.h

   1 /*
   2  * NetChip 2280 high/full speed USB device controller.
   3  * Unlike many such controllers, this one talks PCI.
   4  */
   5
   6 /*
   7  * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
   8  * Copyright (C) 2003 David Brownell
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  23  */
  24
  25 /*-------------------------------------------------------------------------*/
  26
  27 /* NET2280 MEMORY MAPPED REGISTERS
  28  *
  29  * The register layout came from the chip documentation, and the bit
  30  * number definitions were extracted from chip specification.
  31  *
  32  * Use the shift operator ('<<') to build bit masks, with readl/writel
  33  * to access the registers through PCI.
  34  */
  35
  36 /* main registers, BAR0 + 0x0000 */
  37 struct net2280_regs {
  38         // offset 0x0000
  39         u32             devinit;
  40 #define     LOCAL_CLOCK_FREQUENCY                               8
  41 #define     FORCE_PCI_RESET                                     7
  42 #define     PCI_ID                                              6
  43 #define     PCI_ENABLE                                          5
  44 #define     FIFO_SOFT_RESET                                     4
  45 #define     CFG_SOFT_RESET                                      3
  46 #define     PCI_SOFT_RESET                                      2
  47 #define     USB_SOFT_RESET                                      1
  48 #define     M8051_RESET                                         0
  49         u32             eectl;
  50 #define     EEPROM_ADDRESS_WIDTH                                23
  51 #define     EEPROM_CHIP_SELECT_ACTIVE                           22
  52 #define     EEPROM_PRESENT                                      21
  53 #define     EEPROM_VALID                                        20
  54 #define     EEPROM_BUSY                                         19
  55 #define     EEPROM_CHIP_SELECT_ENABLE                           18
  56 #define     EEPROM_BYTE_READ_START                              17
  57 #define     EEPROM_BYTE_WRITE_START                             16
  58 #define     EEPROM_READ_DATA                                    8
  59 #define     EEPROM_WRITE_DATA                                   0
  60         u32             eeclkfreq;
  61         u32             _unused0;
  62         // offset 0x0010
  63
  64         u32             pciirqenb0;             /* interrupt PCI master ... */
  65 #define     SETUP_PACKET_INTERRUPT_ENABLE                       7
  66 #define     ENDPOINT_F_INTERRUPT_ENABLE                         6
  67 #define     ENDPOINT_E_INTERRUPT_ENABLE                         5
  68 #define     ENDPOINT_D_INTERRUPT_ENABLE                         4
  69 #define     ENDPOINT_C_INTERRUPT_ENABLE                         3
  70 #define     ENDPOINT_B_INTERRUPT_ENABLE                         2
  71 #define     ENDPOINT_A_INTERRUPT_ENABLE                         1
  72 #define     ENDPOINT_0_INTERRUPT_ENABLE                         0
  73         u32             pciirqenb1;
  74 #define     PCI_INTERRUPT_ENABLE                                31
  75 #define     POWER_STATE_CHANGE_INTERRUPT_ENABLE                 27
  76 #define     PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE                26
  77 #define     PCI_PARITY_ERROR_INTERRUPT_ENABLE                   25
  78 #define     PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE          20
  79 #define     PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE          19
  80 #define     PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE          18
  81 #define     PCI_RETRY_ABORT_INTERRUPT_ENABLE                    17
  82 #define     PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE              16
  83 #define     GPIO_INTERRUPT_ENABLE                               13
  84 #define     DMA_D_INTERRUPT_ENABLE                              12
  85 #define     DMA_C_INTERRUPT_ENABLE                              11
  86 #define     DMA_B_INTERRUPT_ENABLE                              10
  87 #define     DMA_A_INTERRUPT_ENABLE                              9
  88 #define     EEPROM_DONE_INTERRUPT_ENABLE                        8
  89 #define     VBUS_INTERRUPT_ENABLE                               7
  90 #define     CONTROL_STATUS_INTERRUPT_ENABLE                     6
  91 #define     ROOT_PORT_RESET_INTERRUPT_ENABLE                    4
  92 #define     SUSPEND_REQUEST_INTERRUPT_ENABLE                    3
  93 #define     SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE             2
  94 #define     RESUME_INTERRUPT_ENABLE                             1
  95 #define     SOF_INTERRUPT_ENABLE                                0
  96         u32             cpu_irqenb0;            /* ... or onboard 8051 */
  97 #define     SETUP_PACKET_INTERRUPT_ENABLE                       7
  98 #define     ENDPOINT_F_INTERRUPT_ENABLE                         6
  99 #define     ENDPOINT_E_INTERRUPT_ENABLE                         5
 100 #define     ENDPOINT_D_INTERRUPT_ENABLE                         4
 101 #define     ENDPOINT_C_INTERRUPT_ENABLE                         3
 102 #define     ENDPOINT_B_INTERRUPT_ENABLE                         2
 103 #define     ENDPOINT_A_INTERRUPT_ENABLE                         1
 104 #define     ENDPOINT_0_INTERRUPT_ENABLE                         0
 105         u32             cpu_irqenb1;
 106 #define     CPU_INTERRUPT_ENABLE                                31
 107 #define     POWER_STATE_CHANGE_INTERRUPT_ENABLE                 27
 108 #define     PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE                26
 109 #define     PCI_PARITY_ERROR_INTERRUPT_ENABLE                   25
 110 #define     PCI_INTA_INTERRUPT_ENABLE                           24
 111 #define     PCI_PME_INTERRUPT_ENABLE                            23
 112 #define     PCI_SERR_INTERRUPT_ENABLE                           22
 113 #define     PCI_PERR_INTERRUPT_ENABLE                           21
 114 #define     PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE          20
 115 #define     PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE          19
 116 #define     PCI_RETRY_ABORT_INTERRUPT_ENABLE                    17
 117 #define     PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE              16
 118 #define     GPIO_INTERRUPT_ENABLE                               13
 119 #define     DMA_D_INTERRUPT_ENABLE                              12
 120 #define     DMA_C_INTERRUPT_ENABLE                              11
 121 #define     DMA_B_INTERRUPT_ENABLE                              10
 122 #define     DMA_A_INTERRUPT_ENABLE                              9
 123 #define     EEPROM_DONE_INTERRUPT_ENABLE                        8
 124 #define     VBUS_INTERRUPT_ENABLE                               7
 125 #define     CONTROL_STATUS_INTERRUPT_ENABLE                     6
 126 #define     ROOT_PORT_RESET_INTERRUPT_ENABLE                    4
 127 #define     SUSPEND_REQUEST_INTERRUPT_ENABLE                    3
 128 #define     SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE             2
 129 #define     RESUME_INTERRUPT_ENABLE                             1
 130 #define     SOF_INTERRUPT_ENABLE                                0
 131
 132         // offset 0x0020
 133         u32             _unused1;
 134         u32             usbirqenb1;
 135 #define     USB_INTERRUPT_ENABLE                                31
 136 #define     POWER_STATE_CHANGE_INTERRUPT_ENABLE                 27
 137 #define     PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE                26
 138 #define     PCI_PARITY_ERROR_INTERRUPT_ENABLE                   25
 139 #define     PCI_INTA_INTERRUPT_ENABLE                           24
 140 #define     PCI_PME_INTERRUPT_ENABLE                            23
 141 #define     PCI_SERR_INTERRUPT_ENABLE                           22
 142 #define     PCI_PERR_INTERRUPT_ENABLE                           21
 143 #define     PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE          20
 144 #define     PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE          19
 145 #define     PCI_RETRY_ABORT_INTERRUPT_ENABLE                    17
 146 #define     PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE              16
 147 #define     GPIO_INTERRUPT_ENABLE                               13
 148 #define     DMA_D_INTERRUPT_ENABLE                              12
 149 #define     DMA_C_INTERRUPT_ENABLE                              11
 150 #define     DMA_B_INTERRUPT_ENABLE                              10
 151 #define     DMA_A_INTERRUPT_ENABLE                              9
 152 #define     EEPROM_DONE_INTERRUPT_ENABLE                        8
 153 #define     VBUS_INTERRUPT_ENABLE                               7
 154 #define     CONTROL_STATUS_INTERRUPT_ENABLE                     6
 155 #define     ROOT_PORT_RESET_INTERRUPT_ENABLE                    4
 156 #define     SUSPEND_REQUEST_INTERRUPT_ENABLE                    3
 157 #define     SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE             2
 158 #define     RESUME_INTERRUPT_ENABLE                             1
 159 #define     SOF_INTERRUPT_ENABLE                                0
 160         u32             irqstat0;
 161 #define     INTA_ASSERTED                                       12
 162 #define     SETUP_PACKET_INTERRUPT                              7
 163 #define     ENDPOINT_F_INTERRUPT                                6
 164 #define     ENDPOINT_E_INTERRUPT                                5
 165 #define     ENDPOINT_D_INTERRUPT                                4
 166 #define     ENDPOINT_C_INTERRUPT                                3
 167 #define     ENDPOINT_B_INTERRUPT                                2
 168 #define     ENDPOINT_A_INTERRUPT                                1
 169 #define     ENDPOINT_0_INTERRUPT                                0
 170         u32             irqstat1;
 171 #define     POWER_STATE_CHANGE_INTERRUPT                        27
 172 #define     PCI_ARBITER_TIMEOUT_INTERRUPT                       26
 173 #define     PCI_PARITY_ERROR_INTERRUPT                          25
 174 #define     PCI_INTA_INTERRUPT                                  24
 175 #define     PCI_PME_INTERRUPT                                   23
 176 #define     PCI_SERR_INTERRUPT                                  22
 177 #define     PCI_PERR_INTERRUPT                                  21
 178 #define     PCI_MASTER_ABORT_RECEIVED_INTERRUPT                 20
 179 #define     PCI_TARGET_ABORT_RECEIVED_INTERRUPT                 19
 180 #define     PCI_RETRY_ABORT_INTERRUPT                           17
 181 #define     PCI_MASTER_CYCLE_DONE_INTERRUPT                     16
 182 #define     SOF_DOWN_INTERRUPT                                  14
 183 #define     GPIO_INTERRUPT                                      13
 184 #define     DMA_D_INTERRUPT                                     12
 185 #define     DMA_C_INTERRUPT                                     11
 186 #define     DMA_B_INTERRUPT                                     10
 187 #define     DMA_A_INTERRUPT                                     9
 188 #define     EEPROM_DONE_INTERRUPT                               8
 189 #define     VBUS_INTERRUPT                                      7
 190 #define     CONTROL_STATUS_INTERRUPT                            6
 191 #define     ROOT_PORT_RESET_INTERRUPT                           4
 192 #define     SUSPEND_REQUEST_INTERRUPT                           3
 193 #define     SUSPEND_REQUEST_CHANGE_INTERRUPT                    2
 194 #define     RESUME_INTERRUPT                                    1
 195 #define     SOF_INTERRUPT                                       0
 196         // offset 0x0030
 197         u32             idxaddr;
 198         u32             idxdata;
 199         u32             fifoctl;
 200 #define     PCI_BASE2_RANGE                                     16
 201 #define     IGNORE_FIFO_AVAILABILITY                            3
 202 #define     PCI_BASE2_SELECT                                    2
 203 #define     FIFO_CONFIGURATION_SELECT                           0
 204         u32             _unused2;
 205         // offset 0x0040
 206         u32             memaddr;
 207 #define     START                                               28
 208 #define     DIRECTION                                           27
 209 #define     FIFO_DIAGNOSTIC_SELECT                              24
 210 #define     MEMORY_ADDRESS                                      0
 211         u32             memdata0;
 212         u32             memdata1;
 213         u32             _unused3;
 214         // offset 0x0050
 215         u32             gpioctl;
 216 #define     GPIO3_LED_SELECT                                    12
 217 #define     GPIO3_INTERRUPT_ENABLE                              11
 218 #define     GPIO2_INTERRUPT_ENABLE                              10
 219 #define     GPIO1_INTERRUPT_ENABLE                              9
 220 #define     GPIO0_INTERRUPT_ENABLE                              8
 221 #define     GPIO3_OUTPUT_ENABLE                                 7
 222 #define     GPIO2_OUTPUT_ENABLE                                 6
 223 #define     GPIO1_OUTPUT_ENABLE                                 5
 224 #define     GPIO0_OUTPUT_ENABLE                                 4
 225 #define     GPIO3_DATA                                          3
 226 #define     GPIO2_DATA                                          2
 227 #define     GPIO1_DATA                                          1
 228 #define     GPIO0_DATA                                          0
 229         u32             gpiostat;
 230 #define     GPIO3_INTERRUPT                                     3
 231 #define     GPIO2_INTERRUPT                                     2
 232 #define     GPIO1_INTERRUPT                                     1
 233 #define     GPIO0_INTERRUPT                                     0
 234 } __attribute__ ((packed));
 235
 236 /* usb control, BAR0 + 0x0080 */
 237 struct net2280_usb_regs {
 238         // offset 0x0080
 239         u32             stdrsp;
 240 #define     STALL_UNSUPPORTED_REQUESTS                          31
 241 #define     SET_TEST_MODE                                       16
 242 #define     GET_OTHER_SPEED_CONFIGURATION                       15
 243 #define     GET_DEVICE_QUALIFIER                                14
 244 #define     SET_ADDRESS                                         13
 245 #define     ENDPOINT_SET_CLEAR_HALT                             12
 246 #define     DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP               11
 247 #define     GET_STRING_DESCRIPTOR_2                             10
 248 #define     GET_STRING_DESCRIPTOR_1                             9
 249 #define     GET_STRING_DESCRIPTOR_0                             8
 250 #define     GET_SET_INTERFACE                                   6
 251 #define     GET_SET_CONFIGURATION                               5
 252 #define     GET_CONFIGURATION_DESCRIPTOR                        4
 253 #define     GET_DEVICE_DESCRIPTOR                               3
 254 #define     GET_ENDPOINT_STATUS                                 2
 255 #define     GET_INTERFACE_STATUS                                1
 256 #define     GET_DEVICE_STATUS                                   0
 257         u32             prodvendid;
 258 #define     PRODUCT_ID                                          16
 259 #define     VENDOR_ID                                           0
 260         u32             relnum;
 261         u32             usbctl;
 262 #define     SERIAL_NUMBER_INDEX                                 16
 263 #define     PRODUCT_ID_STRING_ENABLE                            13
 264 #define     VENDOR_ID_STRING_ENABLE                             12
 265 #define     USB_ROOT_PORT_WAKEUP_ENABLE                         11
 266 #define     VBUS_PIN                                            10
 267 #define     TIMED_DISCONNECT                                    9
 268 #define     SUSPEND_IMMEDIATELY                                 7
 269 #define     SELF_POWERED_USB_DEVICE                             6
 270 #define     REMOTE_WAKEUP_SUPPORT                               5
 271 #define     PME_POLARITY                                        4
 272 #define     USB_DETECT_ENABLE                                   3
 273 #define     PME_WAKEUP_ENABLE                                   2
 274 #define     DEVICE_REMOTE_WAKEUP_ENABLE                         1
 275 #define     SELF_POWERED_STATUS                                 0
 276         // offset 0x0090
 277         u32             usbstat;
 278 #define     HIGH_SPEED                                          7
 279 #define     FULL_SPEED                                          6
 280 #define     GENERATE_RESUME                                     5
 281 #define     GENERATE_DEVICE_REMOTE_WAKEUP                       4
 282         u32             xcvrdiag;
 283 #define     FORCE_HIGH_SPEED_MODE                               31
 284 #define     FORCE_FULL_SPEED_MODE                               30
 285 #define     USB_TEST_MODE                                       24
 286 #define     LINE_STATE                                          16
 287 #define     TRANSCEIVER_OPERATION_MODE                          2
 288 #define     TRANSCEIVER_SELECT                                  1
 289 #define     TERMINATION_SELECT                                  0
 290         u32             setup0123;
 291         u32             setup4567;
 292         // offset 0x0090
 293         u32             _unused0;
 294         u32             ouraddr;
 295 #define     FORCE_IMMEDIATE                                     7
 296 #define     OUR_USB_ADDRESS                                     0
 297         u32             ourconfig;
 298 } __attribute__ ((packed));
 299
 300 /* pci control, BAR0 + 0x0100 */
 301 struct net2280_pci_regs {
 302         // offset 0x0100
 303         u32              pcimstctl;
 304 #define     PCI_ARBITER_PARK_SELECT                             13
 305 #define     PCI_MULTI LEVEL_ARBITER                             12
 306 #define     PCI_RETRY_ABORT_ENABLE                              11
 307 #define     DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE              10
 308 #define     DMA_READ_MULTIPLE_ENABLE                            9
 309 #define     DMA_READ_LINE_ENABLE                                8
 310 #define     PCI_MASTER_COMMAND_SELECT                           6
 311 #define         MEM_READ_OR_WRITE                                   0
 312 #define         IO_READ_OR_WRITE                                    1
 313 #define         CFG_READ_OR_WRITE                                   2
 314 #define     PCI_MASTER_START                                    5
 315 #define     PCI_MASTER_READ_WRITE                               4
 316 #define         PCI_MASTER_WRITE                                    0
 317 #define         PCI_MASTER_READ                                     1
 318 #define     PCI_MASTER_BYTE_WRITE_ENABLES                       0
 319         u32              pcimstaddr;
 320         u32              pcimstdata;
 321         u32              pcimststat;
 322 #define     PCI_ARBITER_CLEAR                                   2
 323 #define     PCI_EXTERNAL_ARBITER                                1
 324 #define     PCI_HOST_MODE                                       0
 325 } __attribute__ ((packed));
 326
 327 /* dma control, BAR0 + 0x0180 ... array of four structs like this,
 328  * for channels 0..3.  see also struct net2280_dma:  descriptor
 329  * that can be loaded into some of these registers.
 330  */
 331 struct net2280_dma_regs {       /* [11.7] */
 332         // offset 0x0180, 0x01a0, 0x01c0, 0x01e0,
 333         u32             dmactl;
 334 #define     DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE            25
 335 #define     DMA_CLEAR_COUNT_ENABLE                              21
 336 #define     DESCRIPTOR_POLLING_RATE                             19
 337 #define         POLL_CONTINUOUS                                     0
 338 #define         POLL_1_USEC                                         1
 339 #define         POLL_100_USEC                                       2
 340 #define         POLL_1_MSEC                                         3
 341 #define     DMA_VALID_BIT_POLLING_ENABLE                        18
 342 #define     DMA_VALID_BIT_ENABLE                                17
 343 #define     DMA_SCATTER_GATHER_ENABLE                           16
 344 #define     DMA_OUT_AUTO_START_ENABLE                           4
 345 #define     DMA_PREEMPT_ENABLE                                  3
 346 #define     DMA_FIFO_VALIDATE                                   2
 347 #define     DMA_ENABLE                                          1
 348 #define     DMA_ADDRESS_HOLD                                    0
 349         u32             dmastat;
 350 #define     DMA_ABORT_DONE_INTERRUPT                            27
 351 #define     DMA_SCATTER_GATHER_DONE_INTERRUPT                   25
 352 #define     DMA_TRANSACTION_DONE_INTERRUPT                      24
 353 #define     DMA_ABORT                                           1
 354 #define     DMA_START                                           0
 355         u32             _unused0 [2];
 356         // offset 0x0190, 0x01b0, 0x01d0, 0x01f0,
 357         u32             dmacount;
 358 #define     VALID_BIT                                           31
 359 #define     DMA_DIRECTION                                       30
 360 #define     DMA_DONE_INTERRUPT_ENABLE                           29
 361 #define     END_OF_CHAIN                                        28
 362 #define         DMA_BYTE_COUNT_MASK                                 ((1<<24)-1)
 363 #define     DMA_BYTE_COUNT                                      0
 364         u32             dmaaddr;
 365         u32             dmadesc;
 366         u32             _unused1;
 367 } __attribute__ ((packed));
 368
 369 /* dedicated endpoint registers, BAR0 + 0x0200 */
 370
 371 struct net2280_dep_regs {       /* [11.8] */
 372         // offset 0x0200, 0x0210, 0x220, 0x230, 0x240
 373         u32             dep_cfg;
 374         // offset 0x0204, 0x0214, 0x224, 0x234, 0x244
 375         u32             dep_rsp;
 376         u32             _unused [2];
 377 } __attribute__ ((packed));
 378
 379 /* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs
 380  * like this, for ep0 then the configurable endpoints A..F
 381  * ep0 reserved for control; E and F have only 64 bytes of fifo
 382  */
 383 struct net2280_ep_regs {        /* [11.9] */
 384         // offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0
 385         u32             ep_cfg;
 386 #define     ENDPOINT_BYTE_COUNT                                 16
 387 #define     ENDPOINT_ENABLE                                     10
 388 #define     ENDPOINT_TYPE                                       8
 389 #define     ENDPOINT_DIRECTION                                  7
 390 #define     ENDPOINT_NUMBER                                     0
 391         u32             ep_rsp;
 392 #define     SET_NAK_OUT_PACKETS                                 15
 393 #define     SET_EP_HIDE_STATUS_PHASE                            14
 394 #define     SET_EP_FORCE_CRC_ERROR                              13
 395 #define     SET_INTERRUPT_MODE                                  12
 396 #define     SET_CONTROL_STATUS_PHASE_HANDSHAKE                  11
 397 #define     SET_NAK_OUT_PACKETS_MODE                            10
 398 #define     SET_ENDPOINT_TOGGLE                                 9
 399 #define     SET_ENDPOINT_HALT                                   8
 400 #define     CLEAR_NAK_OUT_PACKETS                               7
 401 #define     CLEAR_EP_HIDE_STATUS_PHASE                          6
 402 #define     CLEAR_EP_FORCE_CRC_ERROR                            5
 403 #define     CLEAR_INTERRUPT_MODE                                4
 404 #define     CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE                3
 405 #define     CLEAR_NAK_OUT_PACKETS_MODE                          2
 406 #define     CLEAR_ENDPOINT_TOGGLE                               1
 407 #define     CLEAR_ENDPOINT_HALT                                 0
 408         u32             ep_irqenb;
 409 #define     SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE              6
 410 #define     SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE           5
 411 #define     DATA_PACKET_RECEIVED_INTERRUPT_ENABLE               3
 412 #define     DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE            2
 413 #define     DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE                1
 414 #define     DATA_IN_TOKEN_INTERRUPT_ENABLE                      0
 415         u32             ep_stat;
 416 #define     FIFO_VALID_COUNT                                    24
 417 #define     HIGH_BANDWIDTH_OUT_TRANSACTION_PID                  22
 418 #define     TIMEOUT                                             21
 419 #define     USB_STALL_SENT                                      20
 420 #define     USB_IN_NAK_SENT                                     19
 421 #define     USB_IN_ACK_RCVD                                     18
 422 #define     USB_OUT_PING_NAK_SENT                               17
 423 #define     USB_OUT_ACK_SENT                                    16
 424 #define     FIFO_OVERFLOW                                       13
 425 #define     FIFO_UNDERFLOW                                      12
 426 #define     FIFO_FULL                                           11
 427 #define     FIFO_EMPTY                                          10
 428 #define     FIFO_FLUSH                                          9
 429 #define     SHORT_PACKET_OUT_DONE_INTERRUPT                     6
 430 #define     SHORT_PACKET_TRANSFERRED_INTERRUPT                  5
 431 #define     NAK_OUT_PACKETS                                     4
 432 #define     DATA_PACKET_RECEIVED_INTERRUPT                      3
 433 #define     DATA_PACKET_TRANSMITTED_INTERRUPT                   2
 434 #define     DATA_OUT_PING_TOKEN_INTERRUPT                       1
 435 #define     DATA_IN_TOKEN_INTERRUPT                             0
 436         // offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0
 437         u32             ep_avail;
 438         u32             ep_data;
 439         u32             _unused0 [2];
 440 } __attribute__ ((packed));
 441
 442 /*-------------------------------------------------------------------------*/
 443
 444 #ifdef  __KERNEL__
 445
 446 /* indexed registers [11.10] are accessed indirectly
 447  * caller must own the device lock.
 448  */
 449
 450 static inline u32
 451 get_idx_reg (struct net2280_regs __iomem *regs, u32 index)
 452 {
 453         writel (index, &regs->idxaddr);
 454         /* NOTE:  synchs device/cpu memory views */
 455         return readl (&regs->idxdata);
 456 }
 457
 458 static inline void
 459 set_idx_reg (struct net2280_regs __iomem *regs, u32 index, u32 value)
 460 {
 461         writel (index, &regs->idxaddr);
 462         writel (value, &regs->idxdata);
 463         /* posted, may not be visible yet */
 464 }
 465
 466 #endif  /* __KERNEL__ */
 467
 468
 469 #define REG_DIAG                0x0
 470 #define     RETRY_COUNTER                                       16
 471 #define     FORCE_PCI_SERR                                      11
 472 #define     FORCE_PCI_INTERRUPT                                 10
 473 #define     FORCE_USB_INTERRUPT                                 9
 474 #define     FORCE_CPU_INTERRUPT                                 8
 475 #define     ILLEGAL_BYTE_ENABLES                                5
 476 #define     FAST_TIMES                                          4
 477 #define     FORCE_RECEIVE_ERROR                                 2
 478 #define     FORCE_TRANSMIT_CRC_ERROR                            0
 479 #define REG_FRAME               0x02    /* from last sof */
 480 #define REG_CHIPREV             0x03    /* in bcd */
 481 #define REG_HS_NAK_RATE         0x0a    /* NAK per N uframes */
 482
 483 #define CHIPREV_1       0x0100
 484 #define CHIPREV_1A      0x0110
 485
 486 #ifdef  __KERNEL__
 487
 488 /* ep a-f highspeed and fullspeed maxpacket, addresses
 489  * computed from ep->num
 490  */
 491 #define REG_EP_MAXPKT(dev,num) (((num) + 1) * 0x10 + \
 492                 (((dev)->gadget.speed == USB_SPEED_HIGH) ? 0 : 1))
 493
 494 /*-------------------------------------------------------------------------*/
 495
 496 /* [8.3] for scatter/gather i/o
 497  * use struct net2280_dma_regs bitfields
 498  */
 499 struct net2280_dma {
 500         __le32          dmacount;
 501         __le32          dmaaddr;                /* the buffer */
 502         __le32          dmadesc;                /* next dma descriptor */
 503         __le32          _reserved;
 504 } __attribute__ ((aligned (16)));
 505
 506 /*-------------------------------------------------------------------------*/
 507
 508 /* DRIVER DATA STRUCTURES and UTILITIES */
 509
 510 struct net2280_ep {
 511         struct usb_ep                           ep;
 512         struct net2280_ep_regs                  __iomem *regs;
 513         struct net2280_dma_regs                 __iomem *dma;
 514         struct net2280_dma                      *dummy;
 515         dma_addr_t                              td_dma; /* of dummy */
 516         struct net2280                          *dev;
 517         unsigned long                           irqs;
 518
 519         /* analogous to a host-side qh */
 520         struct list_head                        queue;
 521         const struct usb_endpoint_descriptor    *desc;
 522         unsigned                                num : 8,
 523                                                 fifo_size : 12,
 524                                                 in_fifo_validate : 1,
 525                                                 out_overflow : 1,
 526                                                 stopped : 1,
 527                                                 is_in : 1,
 528                                                 is_iso : 1;
 529 };
 530
 531 static inline void allow_status (struct net2280_ep *ep)
 532 {
 533         /* ep0 only */
 534         writel (  (1 << CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE)
 535                 | (1 << CLEAR_NAK_OUT_PACKETS)
 536                 | (1 << CLEAR_NAK_OUT_PACKETS_MODE)
 537                 , &ep->regs->ep_rsp);
 538         ep->stopped = 1;
 539 }
 540
 541 /* count (<= 4) bytes in the next fifo write will be valid */
 542 static inline void set_fifo_bytecount (struct net2280_ep *ep, unsigned count)
 543 {
 544         writeb (count, 2 + (u8 __iomem *) &ep->regs->ep_cfg);
 545 }
 546
 547 struct net2280_request {
 548         struct usb_request              req;
 549         struct net2280_dma              *td;
 550         dma_addr_t                      td_dma;
 551         struct list_head                queue;
 552         unsigned                        mapped : 1,
 553                                         valid : 1;
 554 };
 555
 556 struct net2280 {
 557         /* each pci device provides one gadget, several endpoints */
 558         struct usb_gadget               gadget;
 559         spinlock_t                      lock;
 560         struct net2280_ep               ep [7];
 561         struct usb_gadget_driver        *driver;
 562         unsigned                        enabled : 1,
 563                                         protocol_stall : 1,
 564                                         softconnect : 1,
 565                                         got_irq : 1,
 566                                         region : 1;
 567         u16                             chiprev;
 568
 569         /* pci state used to access those endpoints */
 570         struct pci_dev                  *pdev;
 571         struct net2280_regs             __iomem *regs;
 572         struct net2280_usb_regs         __iomem *usb;
 573         struct net2280_pci_regs         __iomem *pci;
 574         struct net2280_dma_regs         __iomem *dma;
 575         struct net2280_dep_regs         __iomem *dep;
 576         struct net2280_ep_regs          __iomem *epregs;
 577
 578         struct pci_pool                 *requests;
 579         // statistics...
 580 };
 581
 582 static inline void set_halt (struct net2280_ep *ep)
 583 {
 584         /* ep0 and bulk/intr endpoints */
 585         writel (  (1 << CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE)
 586                     /* set NAK_OUT for erratum 0114 */
 587                 | ((ep->dev->chiprev == CHIPREV_1) << SET_NAK_OUT_PACKETS)
 588                 | (1 << SET_ENDPOINT_HALT)
 589                 , &ep->regs->ep_rsp);
 590 }
 591
 592 static inline void clear_halt (struct net2280_ep *ep)
 593 {
 594         /* ep0 and bulk/intr endpoints */
 595         writel (  (1 << CLEAR_ENDPOINT_HALT)
 596                 | (1 << CLEAR_ENDPOINT_TOGGLE)
 597                     /* unless the gadget driver left a short packet in the
 598                      * fifo, this reverses the erratum 0114 workaround.
 599                      */
 600                 | ((ep->dev->chiprev == CHIPREV_1) << CLEAR_NAK_OUT_PACKETS)
 601                 , &ep->regs->ep_rsp);
 602 }
 603
 604 #ifdef USE_RDK_LEDS
 605
 606 static inline void net2280_led_init (struct net2280 *dev)
 607 {
 608         /* LED3 (green) is on during USB activity. note erratum 0113. */
 609         writel ((1 << GPIO3_LED_SELECT)
 610                 | (1 << GPIO3_OUTPUT_ENABLE)
 611                 | (1 << GPIO2_OUTPUT_ENABLE)
 612                 | (1 << GPIO1_OUTPUT_ENABLE)
 613                 | (1 << GPIO0_OUTPUT_ENABLE)
 614                 , &dev->regs->gpioctl);
 615 }
 616
 617 /* indicate speed with bi-color LED 0/1 */
 618 static inline
 619 void net2280_led_speed (struct net2280 *dev, enum usb_device_speed speed)
 620 {
 621         u32     val = readl (&dev->regs->gpioctl);
 622         switch (speed) {
 623         case USB_SPEED_HIGH:            /* green */
 624                 val &= ~(1 << GPIO0_DATA);
 625                 val |= (1 << GPIO1_DATA);
 626                 break;
 627         case USB_SPEED_FULL:            /* red */
 628                 val &= ~(1 << GPIO1_DATA);
 629                 val |= (1 << GPIO0_DATA);
 630                 break;
 631         default:                        /* (off/black) */
 632                 val &= ~((1 << GPIO1_DATA) | (1 << GPIO0_DATA));
 633                 break;
 634         }
 635         writel (val, &dev->regs->gpioctl);
 636 }
 637
 638 /* indicate power with LED 2 */
 639 static inline void net2280_led_active (struct net2280 *dev, int is_active)
 640 {
 641         u32     val = readl (&dev->regs->gpioctl);
 642
 643         // FIXME this LED never seems to turn on.
 644         if (is_active)
 645                 val |= GPIO2_DATA;
 646         else
 647                 val &= ~GPIO2_DATA;
 648         writel (val, &dev->regs->gpioctl);
 649 }
 650 static inline void net2280_led_shutdown (struct net2280 *dev)
 651 {
 652         /* turn off all four GPIO*_DATA bits */
 653         writel (readl (&dev->regs->gpioctl) & ~0x0f,
 654                         &dev->regs->gpioctl);
 655 }
 656
 657 #else
 658
 659 #define net2280_led_init(dev)           do { } while (0)
 660 #define net2280_led_speed(dev, speed)   do { } while (0)
 661 #define net2280_led_shutdown(dev)       do { } while (0)
 662
 663 #endif
 664
 665 /*-------------------------------------------------------------------------*/
 666
 667 #define xprintk(dev,level,fmt,args...) \
 668         printk(level "%s %s: " fmt , driver_name , \
 669                         pci_name(dev->pdev) , ## args)
 670
 671 #ifdef DEBUG
 672 #undef DEBUG
 673 #define DEBUG(dev,fmt,args...) \
 674         xprintk(dev , KERN_DEBUG , fmt , ## args)
 675 #else
 676 #define DEBUG(dev,fmt,args...) \
 677         do { } while (0)
 678 #endif /* DEBUG */
 679
 680 #ifdef VERBOSE
 681 #define VDEBUG DEBUG
 682 #else
 683 #define VDEBUG(dev,fmt,args...) \
 684         do { } while (0)
 685 #endif  /* VERBOSE */
 686
 687 #define ERROR(dev,fmt,args...) \
 688         xprintk(dev , KERN_ERR , fmt , ## args)
 689 #define WARN(dev,fmt,args...) \
 690         xprintk(dev , KERN_WARNING , fmt , ## args)
 691 #define INFO(dev,fmt,args...) \
 692         xprintk(dev , KERN_INFO , fmt , ## args)
 693
 694 /*-------------------------------------------------------------------------*/
 695
 696 static inline void start_out_naking (struct net2280_ep *ep)
 697 {
 698         /* NOTE:  hardware races lurk here, and PING protocol issues */
 699         writel ((1 << SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
 700         /* synch with device */
 701         readl (&ep->regs->ep_rsp);
 702 }
 703
 704 #ifdef DEBUG
 705 static inline void assert_out_naking (struct net2280_ep *ep, const char *where)
 706 {
 707         u32     tmp = readl (&ep->regs->ep_stat);
 708
 709         if ((tmp & (1 << NAK_OUT_PACKETS)) == 0) {
 710                 DEBUG (ep->dev, "%s %s %08x !NAK\n",
 711                                 ep->ep.name, where, tmp);
 712                 writel ((1 << SET_NAK_OUT_PACKETS),
 713                         &ep->regs->ep_rsp);
 714         }
 715 }
 716 #define ASSERT_OUT_NAKING(ep) assert_out_naking(ep,__FUNCTION__)
 717 #else
 718 #define ASSERT_OUT_NAKING(ep) do {} while (0)
 719 #endif
 720
 721 static inline void stop_out_naking (struct net2280_ep *ep)
 722 {
 723         u32     tmp;
 724
 725         tmp = readl (&ep->regs->ep_stat);
 726         if ((tmp & (1 << NAK_OUT_PACKETS)) != 0)
 727                 writel ((1 << CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
 728 }
 729
 730 #endif  /* __KERNEL__ */