2 * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
5 * Author: Li Yang <leoli@freescale.com>
6 * Jiang Bo <tanya.jiang@freescale.com>
9 * Freescale high-speed USB SOC DR module device controller driver.
10 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
11 * The driver is previously named as mpc_udc. Based on bare board
12 * code from Dave Liu and Shlomi Gridish.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/ioport.h>
25 #include <linux/types.h>
26 #include <linux/errno.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/list.h>
30 #include <linux/interrupt.h>
31 #include <linux/proc_fs.h>
33 #include <linux/moduleparam.h>
34 #include <linux/device.h>
35 #include <linux/usb/ch9.h>
36 #include <linux/usb/gadget.h>
37 #include <linux/usb/otg.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/platform_device.h>
40 #include <linux/fsl_devices.h>
41 #include <linux/dmapool.h>
42 #include <linux/delay.h>
44 #include <asm/byteorder.h>
46 #include <asm/system.h>
47 #include <asm/unaligned.h>
50 #include "fsl_usb2_udc.h"
52 #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
53 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
54 #define DRIVER_VERSION "Apr 20, 2007"
56 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
58 static const char driver_name[] = "fsl-usb2-udc";
59 static const char driver_desc[] = DRIVER_DESC;
61 static struct usb_dr_device *dr_regs;
62 #ifndef CONFIG_ARCH_MXC
63 static struct usb_sys_interface *usb_sys_regs;
66 /* it is initialized in probe() */
67 static struct fsl_udc *udc_controller = NULL;
69 static const struct usb_endpoint_descriptor
71 .bLength = USB_DT_ENDPOINT_SIZE,
72 .bDescriptorType = USB_DT_ENDPOINT,
73 .bEndpointAddress = 0,
74 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
75 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
78 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
82 * On some SoCs, the USB controller registers can be big or little endian,
83 * depending on the version of the chip. In order to be able to run the
84 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
85 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
86 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
87 * call through those pointers. Platform code for SoCs that have BE USB
88 * registers should set pdata->big_endian_mmio flag.
90 * This also applies to controller-to-cpu accessors for the USB descriptors,
91 * since their endianness is also SoC dependant. Platform code for SoCs that
92 * have BE USB descriptors should set pdata->big_endian_desc flag.
94 static u32 _fsl_readl_be(const unsigned __iomem *p)
99 static u32 _fsl_readl_le(const unsigned __iomem *p)
104 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
109 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
114 static u32 (*_fsl_readl)(const unsigned __iomem *p);
115 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
117 #define fsl_readl(p) (*_fsl_readl)((p))
118 #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
120 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
122 if (pdata->big_endian_mmio) {
123 _fsl_readl = _fsl_readl_be;
124 _fsl_writel = _fsl_writel_be;
126 _fsl_readl = _fsl_readl_le;
127 _fsl_writel = _fsl_writel_le;
131 static inline u32 cpu_to_hc32(const u32 x)
133 return udc_controller->pdata->big_endian_desc
134 ? (__force u32)cpu_to_be32(x)
135 : (__force u32)cpu_to_le32(x);
138 static inline u32 hc32_to_cpu(const u32 x)
140 return udc_controller->pdata->big_endian_desc
141 ? be32_to_cpu((__force __be32)x)
142 : le32_to_cpu((__force __le32)x);
144 #else /* !CONFIG_PPC32 */
145 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
147 #define fsl_readl(addr) readl(addr)
148 #define fsl_writel(val32, addr) writel(val32, addr)
149 #define cpu_to_hc32(x) cpu_to_le32(x)
150 #define hc32_to_cpu(x) le32_to_cpu(x)
151 #endif /* CONFIG_PPC32 */
153 /********************************************************************
154 * Internal Used Function
155 ********************************************************************/
156 /*-----------------------------------------------------------------
157 * done() - retire a request; caller blocked irqs
158 * @status : request status to be set, only works when
159 * request is still in progress.
160 *--------------------------------------------------------------*/
161 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
163 struct fsl_udc *udc = NULL;
164 unsigned char stopped = ep->stopped;
165 struct ep_td_struct *curr_td, *next_td;
168 udc = (struct fsl_udc *)ep->udc;
169 /* Removed the req from fsl_ep->queue */
170 list_del_init(&req->queue);
172 /* req.status should be set as -EINPROGRESS in ep_queue() */
173 if (req->req.status == -EINPROGRESS)
174 req->req.status = status;
176 status = req->req.status;
178 /* Free dtd for the request */
180 for (j = 0; j < req->dtd_count; j++) {
182 if (j != req->dtd_count - 1) {
183 next_td = curr_td->next_td_virt;
185 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
189 dma_unmap_single(ep->udc->gadget.dev.parent,
190 req->req.dma, req->req.length,
194 req->req.dma = DMA_ADDR_INVALID;
197 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
198 req->req.dma, req->req.length,
203 if (status && (status != -ESHUTDOWN))
204 VDBG("complete %s req %p stat %d len %u/%u",
205 ep->ep.name, &req->req, status,
206 req->req.actual, req->req.length);
210 spin_unlock(&ep->udc->lock);
211 /* complete() is from gadget layer,
212 * eg fsg->bulk_in_complete() */
213 if (req->req.complete)
214 req->req.complete(&ep->ep, &req->req);
216 spin_lock(&ep->udc->lock);
217 ep->stopped = stopped;
220 /*-----------------------------------------------------------------
221 * nuke(): delete all requests related to this ep
222 * called with spinlock held
223 *--------------------------------------------------------------*/
224 static void nuke(struct fsl_ep *ep, int status)
229 fsl_ep_fifo_flush(&ep->ep);
231 /* Whether this eq has request linked */
232 while (!list_empty(&ep->queue)) {
233 struct fsl_req *req = NULL;
235 req = list_entry(ep->queue.next, struct fsl_req, queue);
236 done(ep, req, status);
240 /*------------------------------------------------------------------
241 Internal Hardware related function
242 ------------------------------------------------------------------*/
244 static int dr_controller_setup(struct fsl_udc *udc)
246 unsigned int tmp, portctrl, ep_num;
247 unsigned int max_no_of_ep;
248 #ifndef CONFIG_ARCH_MXC
251 unsigned long timeout;
252 #define FSL_UDC_RESET_TIMEOUT 1000
254 /* Config PHY interface */
255 portctrl = fsl_readl(&dr_regs->portsc1);
256 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
257 switch (udc->phy_mode) {
258 case FSL_USB2_PHY_ULPI:
259 portctrl |= PORTSCX_PTS_ULPI;
261 case FSL_USB2_PHY_UTMI_WIDE:
262 portctrl |= PORTSCX_PTW_16BIT;
264 case FSL_USB2_PHY_UTMI:
265 portctrl |= PORTSCX_PTS_UTMI;
267 case FSL_USB2_PHY_SERIAL:
268 portctrl |= PORTSCX_PTS_FSLS;
273 fsl_writel(portctrl, &dr_regs->portsc1);
275 /* Stop and reset the usb controller */
276 tmp = fsl_readl(&dr_regs->usbcmd);
277 tmp &= ~USB_CMD_RUN_STOP;
278 fsl_writel(tmp, &dr_regs->usbcmd);
280 tmp = fsl_readl(&dr_regs->usbcmd);
281 tmp |= USB_CMD_CTRL_RESET;
282 fsl_writel(tmp, &dr_regs->usbcmd);
284 /* Wait for reset to complete */
285 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
286 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
287 if (time_after(jiffies, timeout)) {
288 ERR("udc reset timeout!\n");
294 /* Set the controller as device mode */
295 tmp = fsl_readl(&dr_regs->usbmode);
296 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
297 tmp |= USB_MODE_CTRL_MODE_DEVICE;
298 /* Disable Setup Lockout */
299 tmp |= USB_MODE_SETUP_LOCK_OFF;
302 fsl_writel(tmp, &dr_regs->usbmode);
304 /* Clear the setup status */
305 fsl_writel(0, &dr_regs->usbsts);
307 tmp = udc->ep_qh_dma;
308 tmp &= USB_EP_LIST_ADDRESS_MASK;
309 fsl_writel(tmp, &dr_regs->endpointlistaddr);
311 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
312 udc->ep_qh, (int)tmp,
313 fsl_readl(&dr_regs->endpointlistaddr));
315 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
316 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
317 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
318 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
319 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
320 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
321 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
323 /* Config control enable i/o output, cpu endian register */
324 #ifndef CONFIG_ARCH_MXC
325 if (udc->pdata->have_sysif_regs) {
326 ctrl = __raw_readl(&usb_sys_regs->control);
327 ctrl |= USB_CTRL_IOENB;
328 __raw_writel(ctrl, &usb_sys_regs->control);
332 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
333 /* Turn on cache snooping hardware, since some PowerPC platforms
334 * wholly rely on hardware to deal with cache coherent. */
336 if (udc->pdata->have_sysif_regs) {
337 /* Setup Snooping for all the 4GB space */
338 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
339 __raw_writel(tmp, &usb_sys_regs->snoop1);
340 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
341 __raw_writel(tmp, &usb_sys_regs->snoop2);
348 /* Enable DR irq and set controller to run state */
349 static void dr_controller_run(struct fsl_udc *udc)
353 /* Enable DR irq reg */
354 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
355 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
356 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
358 fsl_writel(temp, &dr_regs->usbintr);
360 /* Clear stopped bit */
363 /* Set the controller as device mode */
364 temp = fsl_readl(&dr_regs->usbmode);
365 temp |= USB_MODE_CTRL_MODE_DEVICE;
366 fsl_writel(temp, &dr_regs->usbmode);
368 /* Set controller to Run */
369 temp = fsl_readl(&dr_regs->usbcmd);
370 temp |= USB_CMD_RUN_STOP;
371 fsl_writel(temp, &dr_regs->usbcmd);
374 static void dr_controller_stop(struct fsl_udc *udc)
378 pr_debug("%s\n", __func__);
380 /* if we're in OTG mode, and the Host is currently using the port,
381 * stop now and don't rip the controller out from under the
384 if (udc->gadget.is_otg) {
385 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
386 pr_debug("udc: Leaving early\n");
391 /* disable all INTR */
392 fsl_writel(0, &dr_regs->usbintr);
394 /* Set stopped bit for isr */
397 /* disable IO output */
398 /* usb_sys_regs->control = 0; */
400 /* set controller to Stop */
401 tmp = fsl_readl(&dr_regs->usbcmd);
402 tmp &= ~USB_CMD_RUN_STOP;
403 fsl_writel(tmp, &dr_regs->usbcmd);
406 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
407 unsigned char ep_type)
409 unsigned int tmp_epctrl = 0;
411 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
414 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
415 tmp_epctrl |= EPCTRL_TX_ENABLE;
416 tmp_epctrl &= ~EPCTRL_TX_TYPE;
417 tmp_epctrl |= ((unsigned int)(ep_type)
418 << EPCTRL_TX_EP_TYPE_SHIFT);
421 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
422 tmp_epctrl |= EPCTRL_RX_ENABLE;
423 tmp_epctrl &= ~EPCTRL_RX_TYPE;
424 tmp_epctrl |= ((unsigned int)(ep_type)
425 << EPCTRL_RX_EP_TYPE_SHIFT);
428 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
432 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
436 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
439 /* set the stall bit */
441 tmp_epctrl |= EPCTRL_TX_EP_STALL;
443 tmp_epctrl |= EPCTRL_RX_EP_STALL;
445 /* clear the stall bit and reset data toggle */
447 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
448 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
450 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
451 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
454 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
457 /* Get stall status of a specific ep
458 Return: 0: not stalled; 1:stalled */
459 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
463 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
465 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
467 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
470 /********************************************************************
471 Internal Structure Build up functions
472 ********************************************************************/
474 /*------------------------------------------------------------------
475 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
476 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
478 ------------------------------------------------------------------*/
479 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
480 unsigned char dir, unsigned char ep_type,
481 unsigned int max_pkt_len,
482 unsigned int zlt, unsigned char mult)
484 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
485 unsigned int tmp = 0;
487 /* set the Endpoint Capabilites in QH */
489 case USB_ENDPOINT_XFER_CONTROL:
490 /* Interrupt On Setup (IOS). for control ep */
491 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
494 case USB_ENDPOINT_XFER_ISOC:
495 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
496 | (mult << EP_QUEUE_HEAD_MULT_POS);
498 case USB_ENDPOINT_XFER_BULK:
499 case USB_ENDPOINT_XFER_INT:
500 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
503 VDBG("error ep type is %d", ep_type);
507 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
509 p_QH->max_pkt_length = cpu_to_hc32(tmp);
510 p_QH->next_dtd_ptr = 1;
511 p_QH->size_ioc_int_sts = 0;
514 /* Setup qh structure and ep register for ep0. */
515 static void ep0_setup(struct fsl_udc *udc)
517 /* the intialization of an ep includes: fields in QH, Regs,
519 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
520 USB_MAX_CTRL_PAYLOAD, 0, 0);
521 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
522 USB_MAX_CTRL_PAYLOAD, 0, 0);
523 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
524 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
530 /***********************************************************************
531 Endpoint Management Functions
532 ***********************************************************************/
534 /*-------------------------------------------------------------------------
535 * when configurations are set, or when interface settings change
536 * for example the do_set_interface() in gadget layer,
537 * the driver will enable or disable the relevant endpoints
538 * ep0 doesn't use this routine. It is always enabled.
539 -------------------------------------------------------------------------*/
540 static int fsl_ep_enable(struct usb_ep *_ep,
541 const struct usb_endpoint_descriptor *desc)
543 struct fsl_udc *udc = NULL;
544 struct fsl_ep *ep = NULL;
545 unsigned short max = 0;
546 unsigned char mult = 0, zlt;
547 int retval = -EINVAL;
548 unsigned long flags = 0;
550 ep = container_of(_ep, struct fsl_ep, ep);
552 /* catch various bogus parameters */
553 if (!_ep || !desc || ep->desc
554 || (desc->bDescriptorType != USB_DT_ENDPOINT))
559 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
562 max = usb_endpoint_maxp(desc);
564 /* Disable automatic zlp generation. Driver is responsible to indicate
565 * explicitly through req->req.zero. This is needed to enable multi-td
569 /* Assume the max packet size from gadget is always correct */
570 switch (desc->bmAttributes & 0x03) {
571 case USB_ENDPOINT_XFER_CONTROL:
572 case USB_ENDPOINT_XFER_BULK:
573 case USB_ENDPOINT_XFER_INT:
574 /* mult = 0. Execute N Transactions as demonstrated by
575 * the USB variable length packet protocol where N is
576 * computed using the Maximum Packet Length (dQH) and
577 * the Total Bytes field (dTD) */
580 case USB_ENDPOINT_XFER_ISOC:
581 /* Calculate transactions needed for high bandwidth iso */
582 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
583 max = max & 0x7ff; /* bit 0~10 */
584 /* 3 transactions at most */
592 spin_lock_irqsave(&udc->lock, flags);
593 ep->ep.maxpacket = max;
597 /* Controller related setup */
598 /* Init EPx Queue Head (Ep Capabilites field in QH
599 * according to max, zlt, mult) */
600 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
601 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
602 ? USB_SEND : USB_RECV),
603 (unsigned char) (desc->bmAttributes
604 & USB_ENDPOINT_XFERTYPE_MASK),
607 /* Init endpoint ctrl register */
608 dr_ep_setup((unsigned char) ep_index(ep),
609 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
610 ? USB_SEND : USB_RECV),
611 (unsigned char) (desc->bmAttributes
612 & USB_ENDPOINT_XFERTYPE_MASK));
614 spin_unlock_irqrestore(&udc->lock, flags);
617 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
618 ep->desc->bEndpointAddress & 0x0f,
619 (desc->bEndpointAddress & USB_DIR_IN)
620 ? "in" : "out", max);
625 /*---------------------------------------------------------------------
626 * @ep : the ep being unconfigured. May not be ep0
627 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
628 *---------------------------------------------------------------------*/
629 static int fsl_ep_disable(struct usb_ep *_ep)
631 struct fsl_udc *udc = NULL;
632 struct fsl_ep *ep = NULL;
633 unsigned long flags = 0;
637 ep = container_of(_ep, struct fsl_ep, ep);
638 if (!_ep || !ep->desc) {
639 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
643 /* disable ep on controller */
644 ep_num = ep_index(ep);
645 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
647 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
648 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
650 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
651 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
653 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
655 udc = (struct fsl_udc *)ep->udc;
656 spin_lock_irqsave(&udc->lock, flags);
658 /* nuke all pending requests (does flush) */
659 nuke(ep, -ESHUTDOWN);
663 spin_unlock_irqrestore(&udc->lock, flags);
665 VDBG("disabled %s OK", _ep->name);
669 /*---------------------------------------------------------------------
670 * allocate a request object used by this endpoint
671 * the main operation is to insert the req->queue to the eq->queue
672 * Returns the request, or null if one could not be allocated
673 *---------------------------------------------------------------------*/
674 static struct usb_request *
675 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
677 struct fsl_req *req = NULL;
679 req = kzalloc(sizeof *req, gfp_flags);
683 req->req.dma = DMA_ADDR_INVALID;
684 INIT_LIST_HEAD(&req->queue);
689 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
691 struct fsl_req *req = NULL;
693 req = container_of(_req, struct fsl_req, req);
699 /* Actually add a dTD chain to an empty dQH and let go */
700 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
702 struct ep_queue_head *qh = get_qh_by_ep(ep);
704 /* Write dQH next pointer and terminate bit to 0 */
705 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
706 & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
708 /* Clear active and halt bit */
709 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
710 | EP_QUEUE_HEAD_STATUS_HALT));
712 /* Ensure that updates to the QH will occur before priming. */
715 /* Prime endpoint by writing correct bit to ENDPTPRIME */
716 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
717 : (1 << (ep_index(ep))), &dr_regs->endpointprime);
720 /* Add dTD chain to the dQH of an EP */
721 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
723 u32 temp, bitmask, tmp_stat;
725 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
726 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
728 bitmask = ep_is_in(ep)
729 ? (1 << (ep_index(ep) + 16))
730 : (1 << (ep_index(ep)));
732 /* check if the pipe is empty */
733 if (!(list_empty(&ep->queue))) {
734 /* Add td to the end */
735 struct fsl_req *lastreq;
736 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
737 lastreq->tail->next_td_ptr =
738 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
739 /* Read prime bit, if 1 goto done */
740 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
744 /* Set ATDTW bit in USBCMD */
745 temp = fsl_readl(&dr_regs->usbcmd);
746 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
748 /* Read correct status bit */
749 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
751 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
753 /* Write ATDTW bit to 0 */
754 temp = fsl_readl(&dr_regs->usbcmd);
755 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
761 fsl_prime_ep(ep, req->head);
764 /* Fill in the dTD structure
765 * @req: request that the transfer belongs to
766 * @length: return actually data length of the dTD
767 * @dma: return dma address of the dTD
768 * @is_last: return flag if it is the last dTD of the request
769 * return: pointer to the built dTD */
770 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
771 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
774 struct ep_td_struct *dtd;
776 /* how big will this transfer be? */
777 *length = min(req->req.length - req->req.actual,
778 (unsigned)EP_MAX_LENGTH_TRANSFER);
780 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
785 /* Clear reserved field */
786 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
787 swap_temp &= ~DTD_RESERVED_FIELDS;
788 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
790 /* Init all of buffer page pointers */
791 swap_temp = (u32) (req->req.dma + req->req.actual);
792 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
793 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
794 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
795 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
796 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
798 req->req.actual += *length;
800 /* zlp is needed if req->req.zero is set */
802 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
806 } else if (req->req.length == req->req.actual)
812 VDBG("multi-dtd request!");
813 /* Fill in the transfer size; set active bit */
814 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
816 /* Enable interrupt for the last dtd of a request */
817 if (*is_last && !req->req.no_interrupt)
818 swap_temp |= DTD_IOC;
820 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
824 VDBG("length = %d address= 0x%x", *length, (int)*dma);
829 /* Generate dtd chain for a request */
830 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
835 struct ep_td_struct *last_dtd = NULL, *dtd;
839 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
847 last_dtd->next_td_ptr = cpu_to_hc32(dma);
848 last_dtd->next_td_virt = dtd;
855 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
862 /* queues (submits) an I/O request to an endpoint */
864 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
866 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
867 struct fsl_req *req = container_of(_req, struct fsl_req, req);
871 /* catch various bogus parameters */
872 if (!_req || !req->req.complete || !req->req.buf
873 || !list_empty(&req->queue)) {
874 VDBG("%s, bad params", __func__);
877 if (unlikely(!_ep || !ep->desc)) {
878 VDBG("%s, bad ep", __func__);
881 if (usb_endpoint_xfer_isoc(ep->desc)) {
882 if (req->req.length > ep->ep.maxpacket)
887 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
892 /* map virtual address to hardware */
893 if (req->req.dma == DMA_ADDR_INVALID) {
894 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
896 req->req.length, ep_is_in(ep)
901 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
902 req->req.dma, req->req.length,
909 req->req.status = -EINPROGRESS;
913 /* build dtds and push them to device queue */
914 if (!fsl_req_to_dtd(req, gfp_flags)) {
915 spin_lock_irqsave(&udc->lock, flags);
916 fsl_queue_td(ep, req);
921 /* Update ep0 state */
922 if ((ep_index(ep) == 0))
923 udc->ep0_state = DATA_STATE_XMIT;
925 /* irq handler advances the queue */
927 list_add_tail(&req->queue, &ep->queue);
928 spin_unlock_irqrestore(&udc->lock, flags);
933 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
934 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
936 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
939 int ep_num, stopped, ret = 0;
945 spin_lock_irqsave(&ep->udc->lock, flags);
946 stopped = ep->stopped;
948 /* Stop the ep before we deal with the queue */
950 ep_num = ep_index(ep);
951 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
953 epctrl &= ~EPCTRL_TX_ENABLE;
955 epctrl &= ~EPCTRL_RX_ENABLE;
956 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
958 /* make sure it's actually queued on this endpoint */
959 list_for_each_entry(req, &ep->queue, queue) {
960 if (&req->req == _req)
963 if (&req->req != _req) {
968 /* The request is in progress, or completed but not dequeued */
969 if (ep->queue.next == &req->queue) {
970 _req->status = -ECONNRESET;
971 fsl_ep_fifo_flush(_ep); /* flush current transfer */
973 /* The request isn't the last request in this ep queue */
974 if (req->queue.next != &ep->queue) {
975 struct fsl_req *next_req;
977 next_req = list_entry(req->queue.next, struct fsl_req,
980 /* prime with dTD of next request */
981 fsl_prime_ep(ep, next_req->head);
983 /* The request hasn't been processed, patch up the TD chain */
985 struct fsl_req *prev_req;
987 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
988 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
991 done(ep, req, -ECONNRESET);
994 out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
996 epctrl |= EPCTRL_TX_ENABLE;
998 epctrl |= EPCTRL_RX_ENABLE;
999 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1000 ep->stopped = stopped;
1002 spin_unlock_irqrestore(&ep->udc->lock, flags);
1006 /*-------------------------------------------------------------------------*/
1008 /*-----------------------------------------------------------------
1009 * modify the endpoint halt feature
1010 * @ep: the non-isochronous endpoint being stalled
1011 * @value: 1--set halt 0--clear halt
1012 * Returns zero, or a negative error code.
1013 *----------------------------------------------------------------*/
1014 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1016 struct fsl_ep *ep = NULL;
1017 unsigned long flags = 0;
1018 int status = -EOPNOTSUPP; /* operation not supported */
1019 unsigned char ep_dir = 0, ep_num = 0;
1020 struct fsl_udc *udc = NULL;
1022 ep = container_of(_ep, struct fsl_ep, ep);
1024 if (!_ep || !ep->desc) {
1029 if (usb_endpoint_xfer_isoc(ep->desc)) {
1030 status = -EOPNOTSUPP;
1034 /* Attempt to halt IN ep will fail if any transfer requests
1035 * are still queue */
1036 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1042 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1043 ep_num = (unsigned char)(ep_index(ep));
1044 spin_lock_irqsave(&ep->udc->lock, flags);
1045 dr_ep_change_stall(ep_num, ep_dir, value);
1046 spin_unlock_irqrestore(&ep->udc->lock, flags);
1048 if (ep_index(ep) == 0) {
1049 udc->ep0_state = WAIT_FOR_SETUP;
1053 VDBG(" %s %s halt stat %d", ep->ep.name,
1054 value ? "set" : "clear", status);
1059 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1062 struct fsl_udc *udc;
1065 struct ep_queue_head *qh;
1067 ep = container_of(_ep, struct fsl_ep, ep);
1068 if (!_ep || (!ep->desc && ep_index(ep) != 0))
1071 udc = (struct fsl_udc *)ep->udc;
1073 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1076 qh = get_qh_by_ep(ep);
1078 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1079 (1 << (ep_index(ep)));
1081 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1082 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1083 >> DTD_LENGTH_BIT_POS;
1085 pr_debug("%s %u\n", __func__, size);
1089 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1094 unsigned long timeout;
1095 #define FSL_UDC_FLUSH_TIMEOUT 1000
1100 ep = container_of(_ep, struct fsl_ep, ep);
1104 ep_num = ep_index(ep);
1105 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1108 bits = (1 << 16) | 1;
1109 else if (ep_dir == USB_SEND)
1110 bits = 1 << (16 + ep_num);
1114 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1116 fsl_writel(bits, &dr_regs->endptflush);
1118 /* Wait until flush complete */
1119 while (fsl_readl(&dr_regs->endptflush)) {
1120 if (time_after(jiffies, timeout)) {
1121 ERR("ep flush timeout\n");
1126 /* See if we need to flush again */
1127 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1130 static struct usb_ep_ops fsl_ep_ops = {
1131 .enable = fsl_ep_enable,
1132 .disable = fsl_ep_disable,
1134 .alloc_request = fsl_alloc_request,
1135 .free_request = fsl_free_request,
1137 .queue = fsl_ep_queue,
1138 .dequeue = fsl_ep_dequeue,
1140 .set_halt = fsl_ep_set_halt,
1141 .fifo_status = fsl_ep_fifo_status,
1142 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1145 /*-------------------------------------------------------------------------
1146 Gadget Driver Layer Operations
1147 -------------------------------------------------------------------------*/
1149 /*----------------------------------------------------------------------
1150 * Get the current frame number (from DR frame_index Reg )
1151 *----------------------------------------------------------------------*/
1152 static int fsl_get_frame(struct usb_gadget *gadget)
1154 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1157 /*-----------------------------------------------------------------------
1158 * Tries to wake up the host connected to this gadget
1159 -----------------------------------------------------------------------*/
1160 static int fsl_wakeup(struct usb_gadget *gadget)
1162 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1165 /* Remote wakeup feature not enabled by host */
1166 if (!udc->remote_wakeup)
1169 portsc = fsl_readl(&dr_regs->portsc1);
1170 /* not suspended? */
1171 if (!(portsc & PORTSCX_PORT_SUSPEND))
1173 /* trigger force resume */
1174 portsc |= PORTSCX_PORT_FORCE_RESUME;
1175 fsl_writel(portsc, &dr_regs->portsc1);
1179 static int can_pullup(struct fsl_udc *udc)
1181 return udc->driver && udc->softconnect && udc->vbus_active;
1184 /* Notify controller that VBUS is powered, Called by whatever
1185 detects VBUS sessions */
1186 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1188 struct fsl_udc *udc;
1189 unsigned long flags;
1191 udc = container_of(gadget, struct fsl_udc, gadget);
1192 spin_lock_irqsave(&udc->lock, flags);
1193 VDBG("VBUS %s", is_active ? "on" : "off");
1194 udc->vbus_active = (is_active != 0);
1195 if (can_pullup(udc))
1196 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1199 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1201 spin_unlock_irqrestore(&udc->lock, flags);
1205 /* constrain controller's VBUS power usage
1206 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1207 * reporting how much power the device may consume. For example, this
1208 * could affect how quickly batteries are recharged.
1210 * Returns zero on success, else negative errno.
1212 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1214 struct fsl_udc *udc;
1216 udc = container_of(gadget, struct fsl_udc, gadget);
1217 if (udc->transceiver)
1218 return otg_set_power(udc->transceiver, mA);
1222 /* Change Data+ pullup status
1223 * this func is used by usb_gadget_connect/disconnet
1225 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1227 struct fsl_udc *udc;
1229 udc = container_of(gadget, struct fsl_udc, gadget);
1230 udc->softconnect = (is_on != 0);
1231 if (can_pullup(udc))
1232 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1235 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1241 static int fsl_start(struct usb_gadget_driver *driver,
1242 int (*bind)(struct usb_gadget *));
1243 static int fsl_stop(struct usb_gadget_driver *driver);
1244 /* defined in gadget.h */
1245 static struct usb_gadget_ops fsl_gadget_ops = {
1246 .get_frame = fsl_get_frame,
1247 .wakeup = fsl_wakeup,
1248 /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1249 .vbus_session = fsl_vbus_session,
1250 .vbus_draw = fsl_vbus_draw,
1251 .pullup = fsl_pullup,
1256 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1257 on new transaction */
1258 static void ep0stall(struct fsl_udc *udc)
1262 /* must set tx and rx to stall at the same time */
1263 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1264 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1265 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1266 udc->ep0_state = WAIT_FOR_SETUP;
1270 /* Prime a status phase for ep0 */
1271 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1273 struct fsl_req *req = udc->status_req;
1276 if (direction == EP_DIR_IN)
1277 udc->ep0_dir = USB_DIR_IN;
1279 udc->ep0_dir = USB_DIR_OUT;
1282 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1285 req->req.length = 0;
1286 req->req.status = -EINPROGRESS;
1287 req->req.actual = 0;
1288 req->req.complete = NULL;
1291 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1292 req->req.buf, req->req.length,
1293 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1296 if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1297 fsl_queue_td(ep, req);
1301 list_add_tail(&req->queue, &ep->queue);
1306 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1308 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1311 nuke(ep, -ESHUTDOWN);
1317 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1319 /* Save the new address to device struct */
1320 udc->device_address = (u8) value;
1321 /* Update usb state */
1322 udc->usb_state = USB_STATE_ADDRESS;
1324 if (ep0_prime_status(udc, EP_DIR_IN))
1331 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1332 u16 index, u16 length)
1334 u16 tmp = 0; /* Status, cpu endian */
1335 struct fsl_req *req;
1340 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1341 /* Get device status */
1342 tmp = 1 << USB_DEVICE_SELF_POWERED;
1343 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1344 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1345 /* Get interface status */
1346 /* We don't have interface information in udc driver */
1348 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1349 /* Get endpoint status */
1350 struct fsl_ep *target_ep;
1352 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1354 /* stall if endpoint doesn't exist */
1355 if (!target_ep->desc)
1357 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1358 << USB_ENDPOINT_HALT;
1361 udc->ep0_dir = USB_DIR_IN;
1362 /* Borrow the per device status_req */
1363 req = udc->status_req;
1364 /* Fill in the reqest structure */
1365 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1368 req->req.length = 2;
1369 req->req.status = -EINPROGRESS;
1370 req->req.actual = 0;
1371 req->req.complete = NULL;
1374 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1375 req->req.buf, req->req.length,
1376 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1379 /* prime the data phase */
1380 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1381 fsl_queue_td(ep, req);
1385 list_add_tail(&req->queue, &ep->queue);
1386 udc->ep0_state = DATA_STATE_XMIT;
1392 static void setup_received_irq(struct fsl_udc *udc,
1393 struct usb_ctrlrequest *setup)
1395 u16 wValue = le16_to_cpu(setup->wValue);
1396 u16 wIndex = le16_to_cpu(setup->wIndex);
1397 u16 wLength = le16_to_cpu(setup->wLength);
1399 udc_reset_ep_queue(udc, 0);
1401 /* We process some stardard setup requests here */
1402 switch (setup->bRequest) {
1403 case USB_REQ_GET_STATUS:
1404 /* Data+Status phase from udc */
1405 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1406 != (USB_DIR_IN | USB_TYPE_STANDARD))
1408 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1411 case USB_REQ_SET_ADDRESS:
1412 /* Status phase from udc */
1413 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1414 | USB_RECIP_DEVICE))
1416 ch9setaddress(udc, wValue, wIndex, wLength);
1419 case USB_REQ_CLEAR_FEATURE:
1420 case USB_REQ_SET_FEATURE:
1421 /* Status phase from udc */
1423 int rc = -EOPNOTSUPP;
1426 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1427 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1428 int pipe = get_pipe_by_windex(wIndex);
1431 if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
1433 ep = get_ep_by_pipe(udc, pipe);
1435 spin_unlock(&udc->lock);
1436 rc = fsl_ep_set_halt(&ep->ep,
1437 (setup->bRequest == USB_REQ_SET_FEATURE)
1439 spin_lock(&udc->lock);
1441 } else if ((setup->bRequestType & (USB_RECIP_MASK
1442 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1443 | USB_TYPE_STANDARD)) {
1444 /* Note: The driver has not include OTG support yet.
1445 * This will be set when OTG support is added */
1446 if (wValue == USB_DEVICE_TEST_MODE)
1448 else if (gadget_is_otg(&udc->gadget)) {
1449 if (setup->bRequest ==
1450 USB_DEVICE_B_HNP_ENABLE)
1451 udc->gadget.b_hnp_enable = 1;
1452 else if (setup->bRequest ==
1453 USB_DEVICE_A_HNP_SUPPORT)
1454 udc->gadget.a_hnp_support = 1;
1455 else if (setup->bRequest ==
1456 USB_DEVICE_A_ALT_HNP_SUPPORT)
1457 udc->gadget.a_alt_hnp_support = 1;
1464 if (ep0_prime_status(udc, EP_DIR_IN))
1471 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1472 fsl_writel(tmp, &dr_regs->portsc1);
1473 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1483 /* Requests handled by gadget */
1485 /* Data phase from gadget, status phase from udc */
1486 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1487 ? USB_DIR_IN : USB_DIR_OUT;
1488 spin_unlock(&udc->lock);
1489 if (udc->driver->setup(&udc->gadget,
1490 &udc->local_setup_buff) < 0)
1492 spin_lock(&udc->lock);
1493 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1494 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1496 /* No data phase, IN status from gadget */
1497 udc->ep0_dir = USB_DIR_IN;
1498 spin_unlock(&udc->lock);
1499 if (udc->driver->setup(&udc->gadget,
1500 &udc->local_setup_buff) < 0)
1502 spin_lock(&udc->lock);
1503 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1507 /* Process request for Data or Status phase of ep0
1508 * prime status phase if needed */
1509 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1510 struct fsl_req *req)
1512 if (udc->usb_state == USB_STATE_ADDRESS) {
1513 /* Set the new address */
1514 u32 new_address = (u32) udc->device_address;
1515 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1516 &dr_regs->deviceaddr);
1521 switch (udc->ep0_state) {
1522 case DATA_STATE_XMIT:
1523 /* receive status phase */
1524 if (ep0_prime_status(udc, EP_DIR_OUT))
1527 case DATA_STATE_RECV:
1528 /* send status phase */
1529 if (ep0_prime_status(udc, EP_DIR_IN))
1532 case WAIT_FOR_OUT_STATUS:
1533 udc->ep0_state = WAIT_FOR_SETUP;
1535 case WAIT_FOR_SETUP:
1536 ERR("Unexpect ep0 packets\n");
1544 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1545 * being corrupted by another incoming setup packet */
1546 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1549 struct ep_queue_head *qh;
1550 struct fsl_usb2_platform_data *pdata = udc->pdata;
1552 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1554 /* Clear bit in ENDPTSETUPSTAT */
1555 temp = fsl_readl(&dr_regs->endptsetupstat);
1556 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1558 /* while a hazard exists when setup package arrives */
1560 /* Set Setup Tripwire */
1561 temp = fsl_readl(&dr_regs->usbcmd);
1562 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1564 /* Copy the setup packet to local buffer */
1565 if (pdata->le_setup_buf) {
1566 u32 *p = (u32 *)buffer_ptr;
1567 u32 *s = (u32 *)qh->setup_buffer;
1569 /* Convert little endian setup buffer to CPU endian */
1570 *p++ = le32_to_cpu(*s++);
1571 *p = le32_to_cpu(*s);
1573 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1575 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1577 /* Clear Setup Tripwire */
1578 temp = fsl_readl(&dr_regs->usbcmd);
1579 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1582 /* process-ep_req(): free the completed Tds for this req */
1583 static int process_ep_req(struct fsl_udc *udc, int pipe,
1584 struct fsl_req *curr_req)
1586 struct ep_td_struct *curr_td;
1587 int td_complete, actual, remaining_length, j, tmp;
1590 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1591 int direction = pipe % 2;
1593 curr_td = curr_req->head;
1595 actual = curr_req->req.length;
1597 for (j = 0; j < curr_req->dtd_count; j++) {
1598 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1600 >> DTD_LENGTH_BIT_POS;
1601 actual -= remaining_length;
1603 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1604 if (errors & DTD_ERROR_MASK) {
1605 if (errors & DTD_STATUS_HALTED) {
1606 ERR("dTD error %08x QH=%d\n", errors, pipe);
1607 /* Clear the errors and Halt condition */
1608 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1610 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1612 /* FIXME: continue with next queued TD? */
1616 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1617 VDBG("Transfer overflow");
1620 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1625 ERR("Unknown error has occurred (0x%x)!\n",
1628 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1629 & DTD_STATUS_ACTIVE) {
1630 VDBG("Request not complete");
1631 status = REQ_UNCOMPLETE;
1633 } else if (remaining_length) {
1635 VDBG("Transmit dTD remaining length not zero");
1644 VDBG("dTD transmitted successful");
1647 if (j != curr_req->dtd_count - 1)
1648 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1654 curr_req->req.actual = actual;
1659 /* Process a DTD completion interrupt */
1660 static void dtd_complete_irq(struct fsl_udc *udc)
1663 int i, ep_num, direction, bit_mask, status;
1664 struct fsl_ep *curr_ep;
1665 struct fsl_req *curr_req, *temp_req;
1667 /* Clear the bits in the register */
1668 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1669 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1674 for (i = 0; i < udc->max_ep * 2; i++) {
1678 bit_mask = 1 << (ep_num + 16 * direction);
1680 if (!(bit_pos & bit_mask))
1683 curr_ep = get_ep_by_pipe(udc, i);
1685 /* If the ep is configured */
1686 if (curr_ep->name == NULL) {
1687 WARNING("Invalid EP?");
1691 /* process the req queue until an uncomplete request */
1692 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1694 status = process_ep_req(udc, i, curr_req);
1696 VDBG("status of process_ep_req= %d, ep = %d",
1698 if (status == REQ_UNCOMPLETE)
1700 /* write back status to req */
1701 curr_req->req.status = status;
1704 ep0_req_complete(udc, curr_ep, curr_req);
1707 done(curr_ep, curr_req, status);
1712 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1714 switch (reg & PORTSCX_PORT_SPEED_MASK) {
1715 case PORTSCX_PORT_SPEED_HIGH:
1716 return USB_SPEED_HIGH;
1717 case PORTSCX_PORT_SPEED_FULL:
1718 return USB_SPEED_FULL;
1719 case PORTSCX_PORT_SPEED_LOW:
1720 return USB_SPEED_LOW;
1722 return USB_SPEED_UNKNOWN;
1726 /* Process a port change interrupt */
1727 static void port_change_irq(struct fsl_udc *udc)
1732 /* Bus resetting is finished */
1733 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1736 portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1738 /* Update USB state */
1739 if (!udc->resume_state)
1740 udc->usb_state = USB_STATE_DEFAULT;
1743 /* Process suspend interrupt */
1744 static void suspend_irq(struct fsl_udc *udc)
1746 udc->resume_state = udc->usb_state;
1747 udc->usb_state = USB_STATE_SUSPENDED;
1749 /* report suspend to the driver, serial.c does not support this */
1750 if (udc->driver->suspend)
1751 udc->driver->suspend(&udc->gadget);
1754 static void bus_resume(struct fsl_udc *udc)
1756 udc->usb_state = udc->resume_state;
1757 udc->resume_state = 0;
1759 /* report resume to the driver, serial.c does not support this */
1760 if (udc->driver->resume)
1761 udc->driver->resume(&udc->gadget);
1764 /* Clear up all ep queues */
1765 static int reset_queues(struct fsl_udc *udc)
1769 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1770 udc_reset_ep_queue(udc, pipe);
1772 /* report disconnect; the driver is already quiesced */
1773 spin_unlock(&udc->lock);
1774 udc->driver->disconnect(&udc->gadget);
1775 spin_lock(&udc->lock);
1780 /* Process reset interrupt */
1781 static void reset_irq(struct fsl_udc *udc)
1784 unsigned long timeout;
1786 /* Clear the device address */
1787 temp = fsl_readl(&dr_regs->deviceaddr);
1788 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1790 udc->device_address = 0;
1792 /* Clear usb state */
1793 udc->resume_state = 0;
1795 udc->ep0_state = WAIT_FOR_SETUP;
1796 udc->remote_wakeup = 0; /* default to 0 on reset */
1797 udc->gadget.b_hnp_enable = 0;
1798 udc->gadget.a_hnp_support = 0;
1799 udc->gadget.a_alt_hnp_support = 0;
1801 /* Clear all the setup token semaphores */
1802 temp = fsl_readl(&dr_regs->endptsetupstat);
1803 fsl_writel(temp, &dr_regs->endptsetupstat);
1805 /* Clear all the endpoint complete status bits */
1806 temp = fsl_readl(&dr_regs->endptcomplete);
1807 fsl_writel(temp, &dr_regs->endptcomplete);
1809 timeout = jiffies + 100;
1810 while (fsl_readl(&dr_regs->endpointprime)) {
1811 /* Wait until all endptprime bits cleared */
1812 if (time_after(jiffies, timeout)) {
1813 ERR("Timeout for reset\n");
1819 /* Write 1s to the flush register */
1820 fsl_writel(0xffffffff, &dr_regs->endptflush);
1822 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1824 /* Bus is reseting */
1826 /* Reset all the queues, include XD, dTD, EP queue
1827 * head and TR Queue */
1829 udc->usb_state = USB_STATE_DEFAULT;
1831 VDBG("Controller reset");
1832 /* initialize usb hw reg except for regs for EP, not
1833 * touch usbintr reg */
1834 dr_controller_setup(udc);
1836 /* Reset all internal used Queues */
1841 /* Enable DR IRQ reg, Set Run bit, change udc state */
1842 dr_controller_run(udc);
1843 udc->usb_state = USB_STATE_ATTACHED;
1848 * USB device controller interrupt handler
1850 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1852 struct fsl_udc *udc = _udc;
1854 irqreturn_t status = IRQ_NONE;
1855 unsigned long flags;
1857 /* Disable ISR for OTG host mode */
1860 spin_lock_irqsave(&udc->lock, flags);
1861 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1862 /* Clear notification bits */
1863 fsl_writel(irq_src, &dr_regs->usbsts);
1865 /* VDBG("irq_src [0x%8x]", irq_src); */
1867 /* Need to resume? */
1868 if (udc->usb_state == USB_STATE_SUSPENDED)
1869 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1873 if (irq_src & USB_STS_INT) {
1875 /* Setup package, we only support ep0 as control ep */
1876 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1877 tripwire_handler(udc, 0,
1878 (u8 *) (&udc->local_setup_buff));
1879 setup_received_irq(udc, &udc->local_setup_buff);
1880 status = IRQ_HANDLED;
1883 /* completion of dtd */
1884 if (fsl_readl(&dr_regs->endptcomplete)) {
1885 dtd_complete_irq(udc);
1886 status = IRQ_HANDLED;
1890 /* SOF (for ISO transfer) */
1891 if (irq_src & USB_STS_SOF) {
1892 status = IRQ_HANDLED;
1896 if (irq_src & USB_STS_PORT_CHANGE) {
1897 port_change_irq(udc);
1898 status = IRQ_HANDLED;
1901 /* Reset Received */
1902 if (irq_src & USB_STS_RESET) {
1905 status = IRQ_HANDLED;
1908 /* Sleep Enable (Suspend) */
1909 if (irq_src & USB_STS_SUSPEND) {
1911 status = IRQ_HANDLED;
1914 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1915 VDBG("Error IRQ %x", irq_src);
1918 spin_unlock_irqrestore(&udc->lock, flags);
1922 /*----------------------------------------------------------------*
1923 * Hook to gadget drivers
1924 * Called by initialization code of gadget drivers
1925 *----------------------------------------------------------------*/
1926 static int fsl_start(struct usb_gadget_driver *driver,
1927 int (*bind)(struct usb_gadget *))
1929 int retval = -ENODEV;
1930 unsigned long flags = 0;
1932 if (!udc_controller)
1935 if (!driver || driver->speed < USB_SPEED_FULL
1936 || !bind || !driver->disconnect || !driver->setup)
1939 if (udc_controller->driver)
1942 /* lock is needed but whether should use this lock or another */
1943 spin_lock_irqsave(&udc_controller->lock, flags);
1945 driver->driver.bus = NULL;
1946 /* hook up the driver */
1947 udc_controller->driver = driver;
1948 udc_controller->gadget.dev.driver = &driver->driver;
1949 spin_unlock_irqrestore(&udc_controller->lock, flags);
1951 /* bind udc driver to gadget driver */
1952 retval = bind(&udc_controller->gadget);
1954 VDBG("bind to %s --> %d", driver->driver.name, retval);
1955 udc_controller->gadget.dev.driver = NULL;
1956 udc_controller->driver = NULL;
1960 if (udc_controller->transceiver) {
1961 /* Suspend the controller until OTG enable it */
1962 udc_controller->stopped = 1;
1963 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1965 /* connect to bus through transceiver */
1966 if (udc_controller->transceiver) {
1967 retval = otg_set_peripheral(udc_controller->transceiver,
1968 &udc_controller->gadget);
1970 ERR("can't bind to transceiver\n");
1971 driver->unbind(&udc_controller->gadget);
1972 udc_controller->gadget.dev.driver = 0;
1973 udc_controller->driver = 0;
1978 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1979 dr_controller_run(udc_controller);
1980 udc_controller->usb_state = USB_STATE_ATTACHED;
1981 udc_controller->ep0_state = WAIT_FOR_SETUP;
1982 udc_controller->ep0_dir = 0;
1984 printk(KERN_INFO "%s: bind to driver %s\n",
1985 udc_controller->gadget.name, driver->driver.name);
1989 printk(KERN_WARNING "gadget driver register failed %d\n",
1994 /* Disconnect from gadget driver */
1995 static int fsl_stop(struct usb_gadget_driver *driver)
1997 struct fsl_ep *loop_ep;
1998 unsigned long flags;
2000 if (!udc_controller)
2003 if (!driver || driver != udc_controller->driver || !driver->unbind)
2006 if (udc_controller->transceiver)
2007 otg_set_peripheral(udc_controller->transceiver, NULL);
2009 /* stop DR, disable intr */
2010 dr_controller_stop(udc_controller);
2012 /* in fact, no needed */
2013 udc_controller->usb_state = USB_STATE_ATTACHED;
2014 udc_controller->ep0_state = WAIT_FOR_SETUP;
2015 udc_controller->ep0_dir = 0;
2017 /* stand operation */
2018 spin_lock_irqsave(&udc_controller->lock, flags);
2019 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2020 nuke(&udc_controller->eps[0], -ESHUTDOWN);
2021 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2023 nuke(loop_ep, -ESHUTDOWN);
2024 spin_unlock_irqrestore(&udc_controller->lock, flags);
2026 /* report disconnect; the controller is already quiesced */
2027 driver->disconnect(&udc_controller->gadget);
2029 /* unbind gadget and unhook driver. */
2030 driver->unbind(&udc_controller->gadget);
2031 udc_controller->gadget.dev.driver = NULL;
2032 udc_controller->driver = NULL;
2034 printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2035 driver->driver.name);
2039 /*-------------------------------------------------------------------------
2040 PROC File System Support
2041 -------------------------------------------------------------------------*/
2042 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2044 #include <linux/seq_file.h>
2046 static const char proc_filename[] = "driver/fsl_usb2_udc";
2048 static int fsl_proc_read(char *page, char **start, off_t off, int count,
2049 int *eof, void *_dev)
2053 unsigned size = count;
2054 unsigned long flags;
2057 struct fsl_ep *ep = NULL;
2058 struct fsl_req *req;
2060 struct fsl_udc *udc = udc_controller;
2064 spin_lock_irqsave(&udc->lock, flags);
2066 /* ------basic driver information ---- */
2067 t = scnprintf(next, size,
2070 "Gadget driver: %s\n\n",
2071 driver_name, DRIVER_VERSION,
2072 udc->driver ? udc->driver->driver.name : "(none)");
2076 /* ------ DR Registers ----- */
2077 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2078 t = scnprintf(next, size,
2082 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2083 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2087 tmp_reg = fsl_readl(&dr_regs->usbsts);
2088 t = scnprintf(next, size,
2090 "Dr Suspend: %d Reset Received: %d System Error: %s "
2091 "USB Error Interrupt: %s\n\n",
2092 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2093 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2094 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2095 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2099 tmp_reg = fsl_readl(&dr_regs->usbintr);
2100 t = scnprintf(next, size,
2101 "USB Intrrupt Enable Reg:\n"
2102 "Sleep Enable: %d SOF Received Enable: %d "
2103 "Reset Enable: %d\n"
2104 "System Error Enable: %d "
2105 "Port Change Dectected Enable: %d\n"
2106 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2107 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2108 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2109 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2110 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2111 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2112 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2113 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2117 tmp_reg = fsl_readl(&dr_regs->frindex);
2118 t = scnprintf(next, size,
2119 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2120 (tmp_reg & USB_FRINDEX_MASKS));
2124 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2125 t = scnprintf(next, size,
2126 "USB Device Address Reg: Device Addr is 0x%x\n\n",
2127 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2131 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2132 t = scnprintf(next, size,
2133 "USB Endpoint List Address Reg: "
2134 "Device Addr is 0x%x\n\n",
2135 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2139 tmp_reg = fsl_readl(&dr_regs->portsc1);
2140 t = scnprintf(next, size,
2141 "USB Port Status&Control Reg:\n"
2142 "Port Transceiver Type : %s Port Speed: %s\n"
2143 "PHY Low Power Suspend: %s Port Reset: %s "
2144 "Port Suspend Mode: %s\n"
2145 "Over-current Change: %s "
2146 "Port Enable/Disable Change: %s\n"
2147 "Port Enabled/Disabled: %s "
2148 "Current Connect Status: %s\n\n", ( {
2150 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2151 case PORTSCX_PTS_UTMI:
2153 case PORTSCX_PTS_ULPI:
2155 case PORTSCX_PTS_FSLS:
2156 s = "FS/LS Serial"; break;
2161 usb_speed_string(portscx_device_speed(tmp_reg)),
2162 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2163 "Normal PHY mode" : "Low power mode",
2164 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2166 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2167 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2169 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2171 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2173 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2174 "Attached" : "Not-Att");
2178 tmp_reg = fsl_readl(&dr_regs->usbmode);
2179 t = scnprintf(next, size,
2180 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2182 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2183 case USB_MODE_CTRL_MODE_IDLE:
2185 case USB_MODE_CTRL_MODE_DEVICE:
2186 s = "Device Controller"; break;
2187 case USB_MODE_CTRL_MODE_HOST:
2188 s = "Host Controller"; break;
2197 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2198 t = scnprintf(next, size,
2199 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2200 (tmp_reg & EP_SETUP_STATUS_MASK));
2204 for (i = 0; i < udc->max_ep / 2; i++) {
2205 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2206 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2211 tmp_reg = fsl_readl(&dr_regs->endpointprime);
2212 t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2216 #ifndef CONFIG_ARCH_MXC
2217 if (udc->pdata->have_sysif_regs) {
2218 tmp_reg = usb_sys_regs->snoop1;
2219 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2223 tmp_reg = usb_sys_regs->control;
2224 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2231 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2233 t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2234 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2238 if (list_empty(&ep->queue)) {
2239 t = scnprintf(next, size, "its req queue is empty\n\n");
2243 list_for_each_entry(req, &ep->queue, queue) {
2244 t = scnprintf(next, size,
2245 "req %p actual 0x%x length 0x%x buf %p\n",
2246 &req->req, req->req.actual,
2247 req->req.length, req->req.buf);
2252 /* other gadget->eplist ep */
2253 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2255 t = scnprintf(next, size,
2256 "\nFor %s Maxpkt is 0x%x "
2258 ep->ep.name, ep_maxpacket(ep),
2263 if (list_empty(&ep->queue)) {
2264 t = scnprintf(next, size,
2265 "its req queue is empty\n\n");
2269 list_for_each_entry(req, &ep->queue, queue) {
2270 t = scnprintf(next, size,
2271 "req %p actual 0x%x length "
2273 &req->req, req->req.actual,
2274 req->req.length, req->req.buf);
2277 } /* end for each_entry of ep req */
2278 } /* end for else */
2279 } /* end for if(ep->queue) */
2280 } /* end (ep->desc) */
2282 spin_unlock_irqrestore(&udc->lock, flags);
2285 return count - size;
2288 #define create_proc_file() create_proc_read_entry(proc_filename, \
2289 0, NULL, fsl_proc_read, NULL)
2291 #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2293 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2295 #define create_proc_file() do {} while (0)
2296 #define remove_proc_file() do {} while (0)
2298 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2300 /*-------------------------------------------------------------------------*/
2302 /* Release udc structures */
2303 static void fsl_udc_release(struct device *dev)
2305 complete(udc_controller->done);
2306 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2307 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2308 kfree(udc_controller);
2311 /******************************************************************
2312 Internal structure setup functions
2313 *******************************************************************/
2314 /*------------------------------------------------------------------
2315 * init resource for globle controller
2316 * Return the udc handle on success or NULL on failure
2317 ------------------------------------------------------------------*/
2318 static int __init struct_udc_setup(struct fsl_udc *udc,
2319 struct platform_device *pdev)
2321 struct fsl_usb2_platform_data *pdata;
2324 pdata = pdev->dev.platform_data;
2325 udc->phy_mode = pdata->phy_mode;
2327 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2329 ERR("malloc fsl_ep failed\n");
2333 /* initialized QHs, take care of alignment */
2334 size = udc->max_ep * sizeof(struct ep_queue_head);
2335 if (size < QH_ALIGNMENT)
2336 size = QH_ALIGNMENT;
2337 else if ((size % QH_ALIGNMENT) != 0) {
2338 size += QH_ALIGNMENT + 1;
2339 size &= ~(QH_ALIGNMENT - 1);
2341 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2342 &udc->ep_qh_dma, GFP_KERNEL);
2344 ERR("malloc QHs for udc failed\n");
2349 udc->ep_qh_size = size;
2351 /* Initialize ep0 status request structure */
2352 /* FIXME: fsl_alloc_request() ignores ep argument */
2353 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2354 struct fsl_req, req);
2355 /* allocate a small amount of memory to get valid address */
2356 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2358 udc->resume_state = USB_STATE_NOTATTACHED;
2359 udc->usb_state = USB_STATE_POWERED;
2361 udc->remote_wakeup = 0; /* default to 0 on reset */
2366 /*----------------------------------------------------------------
2367 * Setup the fsl_ep struct for eps
2368 * Link fsl_ep->ep to gadget->ep_list
2369 * ep0out is not used so do nothing here
2370 * ep0in should be taken care
2371 *--------------------------------------------------------------*/
2372 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2373 char *name, int link)
2375 struct fsl_ep *ep = &udc->eps[index];
2378 strcpy(ep->name, name);
2379 ep->ep.name = ep->name;
2381 ep->ep.ops = &fsl_ep_ops;
2384 /* for ep0: maxP defined in desc
2385 * for other eps, maxP is set by epautoconfig() called by gadget layer
2387 ep->ep.maxpacket = (unsigned short) ~0;
2389 /* the queue lists any req for this ep */
2390 INIT_LIST_HEAD(&ep->queue);
2392 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2394 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2395 ep->gadget = &udc->gadget;
2396 ep->qh = &udc->ep_qh[index];
2401 /* Driver probe function
2402 * all intialization operations implemented here except enabling usb_intr reg
2403 * board setup should have been done in the platform code
2405 static int __init fsl_udc_probe(struct platform_device *pdev)
2407 struct fsl_usb2_platform_data *pdata;
2408 struct resource *res;
2413 if (strcmp(pdev->name, driver_name)) {
2414 VDBG("Wrong device");
2418 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2419 if (udc_controller == NULL) {
2420 ERR("malloc udc failed\n");
2424 pdata = pdev->dev.platform_data;
2425 udc_controller->pdata = pdata;
2426 spin_lock_init(&udc_controller->lock);
2427 udc_controller->stopped = 1;
2429 #ifdef CONFIG_USB_OTG
2430 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2431 udc_controller->transceiver = otg_get_transceiver();
2432 if (!udc_controller->transceiver) {
2433 ERR("Can't find OTG driver!\n");
2440 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2446 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2447 if (!request_mem_region(res->start, resource_size(res),
2449 ERR("request mem region for %s failed\n", pdev->name);
2455 dr_regs = ioremap(res->start, resource_size(res));
2458 goto err_release_mem_region;
2461 pdata->regs = (void *)dr_regs;
2464 * do platform specific init: check the clock, grab/config pins, etc.
2466 if (pdata->init && pdata->init(pdev)) {
2468 goto err_iounmap_noclk;
2471 /* Set accessors only after pdata->init() ! */
2472 fsl_set_accessors(pdata);
2474 #ifndef CONFIG_ARCH_MXC
2475 if (pdata->have_sysif_regs)
2476 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2479 /* Initialize USB clocks */
2480 ret = fsl_udc_clk_init(pdev);
2482 goto err_iounmap_noclk;
2484 /* Read Device Controller Capability Parameters register */
2485 dccparams = fsl_readl(&dr_regs->dccparams);
2486 if (!(dccparams & DCCPARAMS_DC)) {
2487 ERR("This SOC doesn't support device role\n");
2491 /* Get max device endpoints */
2492 /* DEN is bidirectional ep number, max_ep doubles the number */
2493 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2495 udc_controller->irq = platform_get_irq(pdev, 0);
2496 if (!udc_controller->irq) {
2501 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2502 driver_name, udc_controller);
2504 ERR("cannot request irq %d err %d\n",
2505 udc_controller->irq, ret);
2509 /* Initialize the udc structure including QH member and other member */
2510 if (struct_udc_setup(udc_controller, pdev)) {
2511 ERR("Can't initialize udc data structure\n");
2516 if (!udc_controller->transceiver) {
2517 /* initialize usb hw reg except for regs for EP,
2518 * leave usbintr reg untouched */
2519 dr_controller_setup(udc_controller);
2522 fsl_udc_clk_finalize(pdev);
2524 /* Setup gadget structure */
2525 udc_controller->gadget.ops = &fsl_gadget_ops;
2526 udc_controller->gadget.is_dualspeed = 1;
2527 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2528 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2529 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2530 udc_controller->gadget.name = driver_name;
2532 /* Setup gadget.dev and register with kernel */
2533 dev_set_name(&udc_controller->gadget.dev, "gadget");
2534 udc_controller->gadget.dev.release = fsl_udc_release;
2535 udc_controller->gadget.dev.parent = &pdev->dev;
2536 ret = device_register(&udc_controller->gadget.dev);
2540 if (udc_controller->transceiver)
2541 udc_controller->gadget.is_otg = 1;
2543 /* setup QH and epctrl for ep0 */
2544 ep0_setup(udc_controller);
2546 /* setup udc->eps[] for ep0 */
2547 struct_ep_setup(udc_controller, 0, "ep0", 0);
2548 /* for ep0: the desc defined here;
2549 * for other eps, gadget layer called ep_enable with defined desc
2551 udc_controller->eps[0].desc = &fsl_ep0_desc;
2552 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2554 /* setup the udc->eps[] for non-control endpoints and link
2555 * to gadget.ep_list */
2556 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2559 sprintf(name, "ep%dout", i);
2560 struct_ep_setup(udc_controller, i * 2, name, 1);
2561 sprintf(name, "ep%din", i);
2562 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2565 /* use dma_pool for TD management */
2566 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2567 sizeof(struct ep_td_struct),
2568 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2569 if (udc_controller->td_pool == NULL) {
2571 goto err_unregister;
2574 ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
2582 dma_pool_destroy(udc_controller->td_pool);
2584 device_unregister(&udc_controller->gadget.dev);
2586 free_irq(udc_controller->irq, udc_controller);
2590 fsl_udc_clk_release();
2593 err_release_mem_region:
2594 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2595 release_mem_region(res->start, resource_size(res));
2597 kfree(udc_controller);
2598 udc_controller = NULL;
2602 /* Driver removal function
2603 * Free resources and finish pending transactions
2605 static int __exit fsl_udc_remove(struct platform_device *pdev)
2607 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2608 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2610 DECLARE_COMPLETION(done);
2612 if (!udc_controller)
2615 usb_del_gadget_udc(&udc_controller->gadget);
2616 udc_controller->done = &done;
2618 fsl_udc_clk_release();
2620 /* DR has been stopped in usb_gadget_unregister_driver() */
2623 /* Free allocated memory */
2624 kfree(udc_controller->status_req->req.buf);
2625 kfree(udc_controller->status_req);
2626 kfree(udc_controller->eps);
2628 dma_pool_destroy(udc_controller->td_pool);
2629 free_irq(udc_controller->irq, udc_controller);
2631 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2632 release_mem_region(res->start, resource_size(res));
2634 device_unregister(&udc_controller->gadget.dev);
2635 /* free udc --wait for the release() finished */
2636 wait_for_completion(&done);
2639 * do platform specific un-initialization:
2640 * release iomux pins, etc.
2648 /*-----------------------------------------------------------------
2649 * Modify Power management attributes
2650 * Used by OTG statemachine to disable gadget temporarily
2651 -----------------------------------------------------------------*/
2652 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2654 dr_controller_stop(udc_controller);
2658 /*-----------------------------------------------------------------
2659 * Invoked on USB resume. May be called in_interrupt.
2660 * Here we start the DR controller and enable the irq
2661 *-----------------------------------------------------------------*/
2662 static int fsl_udc_resume(struct platform_device *pdev)
2664 /* Enable DR irq reg and set controller Run */
2665 if (udc_controller->stopped) {
2666 dr_controller_setup(udc_controller);
2667 dr_controller_run(udc_controller);
2669 udc_controller->usb_state = USB_STATE_ATTACHED;
2670 udc_controller->ep0_state = WAIT_FOR_SETUP;
2671 udc_controller->ep0_dir = 0;
2675 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2677 struct fsl_udc *udc = udc_controller;
2680 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2682 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2685 * If the controller is already stopped, then this must be a
2686 * PM suspend. Remember this fact, so that we will leave the
2687 * controller stopped at PM resume time.
2690 pr_debug("gadget already stopped, leaving early\n");
2691 udc->already_stopped = 1;
2695 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2696 pr_debug("gadget not in device mode, leaving early\n");
2700 /* stop the controller */
2701 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2702 fsl_writel(usbcmd, &dr_regs->usbcmd);
2706 pr_info("USB Gadget suspended\n");
2711 static int fsl_udc_otg_resume(struct device *dev)
2713 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2714 udc_controller->stopped, udc_controller->already_stopped);
2717 * If the controller was stopped at suspend time, then
2718 * don't resume it now.
2720 if (udc_controller->already_stopped) {
2721 udc_controller->already_stopped = 0;
2722 pr_debug("gadget was already stopped, leaving early\n");
2726 pr_info("USB Gadget resume\n");
2728 return fsl_udc_resume(NULL);
2731 /*-------------------------------------------------------------------------
2732 Register entry point for the peripheral controller driver
2733 --------------------------------------------------------------------------*/
2735 static struct platform_driver udc_driver = {
2736 .remove = __exit_p(fsl_udc_remove),
2737 /* these suspend and resume are not usb suspend and resume */
2738 .suspend = fsl_udc_suspend,
2739 .resume = fsl_udc_resume,
2741 .name = (char *)driver_name,
2742 .owner = THIS_MODULE,
2743 /* udc suspend/resume called from OTG driver */
2744 .suspend = fsl_udc_otg_suspend,
2745 .resume = fsl_udc_otg_resume,
2749 static int __init udc_init(void)
2751 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2752 return platform_driver_probe(&udc_driver, fsl_udc_probe);
2755 module_init(udc_init);
2757 static void __exit udc_exit(void)
2759 platform_driver_unregister(&udc_driver);
2760 printk(KERN_WARNING "%s unregistered\n", driver_desc);
2763 module_exit(udc_exit);
2765 MODULE_DESCRIPTION(DRIVER_DESC);
2766 MODULE_AUTHOR(DRIVER_AUTHOR);
2767 MODULE_LICENSE("GPL");
2768 MODULE_ALIAS("platform:fsl-usb2-udc");