2 * ci13xxx_udc.h - structures, registers, and macros MIPS USB IP core
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Description: MIPS USB IP core family device controller
13 * Structures, registers and logging macros
19 /******************************************************************************
21 *****************************************************************************/
22 #define CI13XXX_PAGE_SIZE 4096ul /* page size for TD's */
24 #define CTRL_PAYLOAD_MAX 64
25 #define RX 0 /* similar to USB_DIR_OUT but can be used as an index */
26 #define TX 1 /* similar to USB_DIR_IN but can be used as an index */
28 /******************************************************************************
30 *****************************************************************************/
31 /* DMA layout of transfer descriptors */
35 #define TD_TERMINATE BIT(0)
36 #define TD_ADDR_MASK (0xFFFFFFEUL << 5)
39 #define TD_STATUS (0x00FFUL << 0)
40 #define TD_STATUS_TR_ERR BIT(3)
41 #define TD_STATUS_DT_ERR BIT(5)
42 #define TD_STATUS_HALTED BIT(6)
43 #define TD_STATUS_ACTIVE BIT(7)
44 #define TD_MULTO (0x0003UL << 10)
45 #define TD_IOC BIT(15)
46 #define TD_TOTAL_BYTES (0x7FFFUL << 16)
49 #define TD_CURR_OFFSET (0x0FFFUL << 0)
50 #define TD_FRAME_NUM (0x07FFUL << 0)
51 #define TD_RESERVED_MASK (0x0FFFUL << 0)
52 } __attribute__ ((packed));
54 /* DMA layout of queue heads */
58 #define QH_IOS BIT(15)
59 #define QH_MAX_PKT (0x07FFUL << 16)
60 #define QH_ZLT BIT(29)
61 #define QH_MULT (0x0003UL << 30)
68 struct usb_ctrlrequest setup;
69 } __attribute__ ((packed));
71 /* Extension of usb_request */
73 struct usb_request req;
75 struct list_head queue;
76 struct ci13xxx_td *ptr;
78 struct ci13xxx_td *zptr;
82 /* Extension of usb_ep */
90 struct list_head queue;
91 struct ci13xxx_qh *ptr;
96 /* global resources */
99 struct device *device;
100 struct dma_pool *td_pool;
104 struct ci13xxx_udc_driver {
106 /* offset of the capability registers */
109 #define CI13XXX_REGS_SHARED BIT(0)
110 #define CI13XXX_REQUIRE_TRANSCEIVER BIT(1)
111 #define CI13XXX_PULLUP_ON_VBUS BIT(2)
112 #define CI13XXX_DISABLE_STREAMING BIT(3)
114 #define CI13XXX_CONTROLLER_RESET_EVENT 0
115 #define CI13XXX_CONTROLLER_STOPPED_EVENT 1
116 void (*notify_event) (struct ci13xxx *udc, unsigned event);
120 unsigned lpm; /* is LPM? */
121 void __iomem *abs; /* bus map offset */
122 void __iomem *cap; /* bus map offset + CAP offset */
123 void __iomem *op; /* bus map offset + OP offset */
124 size_t size; /* bank size */
125 void *__iomem *regmap;
128 /* CI13XXX UDC descriptor & global resources */
130 spinlock_t lock; /* ctrl register bank access */
131 void __iomem *regs; /* registers address space */
133 struct dma_pool *qh_pool; /* DMA pool for queue heads */
134 struct dma_pool *td_pool; /* DMA pool for transfer descs */
135 struct usb_request *status; /* ep0 status request */
138 struct usb_gadget gadget; /* USB slave device */
139 struct ci13xxx_ep ci13xxx_ep[ENDPT_MAX]; /* extended endpts */
140 u32 ep0_dir; /* ep0 direction */
141 struct ci13xxx_ep *ep0out, *ep0in;
142 unsigned hw_ep_max; /* number of hw endpoints */
144 u8 remote_wakeup; /* Is remote wakeup feature
145 enabled by the host? */
146 u8 suspended; /* suspended by the host */
147 u8 test_mode; /* the selected test mode */
149 struct hw_bank hw_bank;
151 struct usb_gadget_driver *driver; /* 3rd party gadget driver */
152 struct ci13xxx_udc_driver *udc_driver; /* device controller driver */
153 int vbus_active; /* is VBUS active */
154 struct usb_phy *transceiver; /* Transceiver struct */
157 /******************************************************************************
159 *****************************************************************************/
160 /* Default offset of capability registers */
161 #define DEF_CAPOFFSET 0x100
164 #define REG_BITS (32)
166 /* register indices */
172 CAP_LAST = CAP_TESTMODE,
187 /* endptctrl1..15 follow */
188 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
192 #define HCCPARAMS_LEN BIT(17)
195 #define DCCPARAMS_DEN (0x1F << 0)
196 #define DCCPARAMS_DC BIT(7)
199 #define TESTMODE_FORCE BIT(0)
202 #define USBCMD_RS BIT(0)
203 #define USBCMD_RST BIT(1)
204 #define USBCMD_SUTW BIT(13)
205 #define USBCMD_ATDTW BIT(14)
207 /* USBSTS & USBINTR */
208 #define USBi_UI BIT(0)
209 #define USBi_UEI BIT(1)
210 #define USBi_PCI BIT(2)
211 #define USBi_URI BIT(6)
212 #define USBi_SLI BIT(8)
215 #define DEVICEADDR_USBADRA BIT(24)
216 #define DEVICEADDR_USBADR (0x7FUL << 25)
219 #define PORTSC_FPR BIT(6)
220 #define PORTSC_SUSP BIT(7)
221 #define PORTSC_HSP BIT(9)
222 #define PORTSC_PTC (0x0FUL << 16)
225 #define DEVLC_PSPD (0x03UL << 25)
226 #define DEVLC_PSPD_HS (0x02UL << 25)
229 #define USBMODE_CM (0x03UL << 0)
230 #define USBMODE_CM_IDLE (0x00UL << 0)
231 #define USBMODE_CM_DEVICE (0x02UL << 0)
232 #define USBMODE_CM_HOST (0x03UL << 0)
233 #define USBMODE_SLOM BIT(3)
234 #define USBMODE_SDIS BIT(4)
237 #define ENDPTCTRL_RXS BIT(0)
238 #define ENDPTCTRL_RXT (0x03UL << 2)
239 #define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */
240 #define ENDPTCTRL_RXE BIT(7)
241 #define ENDPTCTRL_TXS BIT(16)
242 #define ENDPTCTRL_TXT (0x03UL << 18)
243 #define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */
244 #define ENDPTCTRL_TXE BIT(23)
246 /******************************************************************************
248 *****************************************************************************/
250 #define trace(dev, format, args...) \
253 pr_debug("[%s] " format "\n", __func__, \
256 dev_printk(KERN_DEBUG, dev, "[%s] " format "\n", \
257 __func__, ## args); \
260 #define trace(dev, format, args...) do {} while (0)
263 #endif /* _CI13XXX_h_ */