2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <linux/mii.h>
25 #include "usb_ether.h"
29 /* ASIX AX8817X based USB 2.0 Ethernet Devices */
31 #define AX_CMD_SET_SW_MII 0x06
32 #define AX_CMD_READ_MII_REG 0x07
33 #define AX_CMD_WRITE_MII_REG 0x08
34 #define AX_CMD_SET_HW_MII 0x0a
35 #define AX_CMD_READ_EEPROM 0x0b
36 #define AX_CMD_READ_RX_CTL 0x0f
37 #define AX_CMD_WRITE_RX_CTL 0x10
38 #define AX_CMD_WRITE_IPG0 0x12
39 #define AX_CMD_READ_NODE_ID 0x13
40 #define AX_CMD_WRITE_NODE_ID 0x14
41 #define AX_CMD_READ_PHY_ID 0x19
42 #define AX_CMD_WRITE_MEDIUM_MODE 0x1b
43 #define AX_CMD_WRITE_GPIOS 0x1f
44 #define AX_CMD_SW_RESET 0x20
45 #define AX_CMD_SW_PHY_SELECT 0x22
47 #define AX_SWRESET_CLEAR 0x00
48 #define AX_SWRESET_PRTE 0x04
49 #define AX_SWRESET_PRL 0x08
50 #define AX_SWRESET_IPRL 0x20
51 #define AX_SWRESET_IPPD 0x40
53 #define AX88772_IPG0_DEFAULT 0x15
54 #define AX88772_IPG1_DEFAULT 0x0c
55 #define AX88772_IPG2_DEFAULT 0x12
57 /* AX88772 & AX88178 Medium Mode Register */
58 #define AX_MEDIUM_PF 0x0080
59 #define AX_MEDIUM_JFE 0x0040
60 #define AX_MEDIUM_TFC 0x0020
61 #define AX_MEDIUM_RFC 0x0010
62 #define AX_MEDIUM_ENCK 0x0008
63 #define AX_MEDIUM_AC 0x0004
64 #define AX_MEDIUM_FD 0x0002
65 #define AX_MEDIUM_GM 0x0001
66 #define AX_MEDIUM_SM 0x1000
67 #define AX_MEDIUM_SBP 0x0800
68 #define AX_MEDIUM_PS 0x0200
69 #define AX_MEDIUM_RE 0x0100
71 #define AX88178_MEDIUM_DEFAULT \
72 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
73 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
76 #define AX88772_MEDIUM_DEFAULT \
77 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
78 AX_MEDIUM_TFC | AX_MEDIUM_PS | \
79 AX_MEDIUM_AC | AX_MEDIUM_RE)
81 /* AX88772 & AX88178 RX_CTL values */
82 #define AX_RX_CTL_SO 0x0080
83 #define AX_RX_CTL_AB 0x0008
85 #define AX_DEFAULT_RX_CTL \
86 (AX_RX_CTL_SO | AX_RX_CTL_AB)
89 #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
90 #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
91 #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
94 #define ASIX_BASE_NAME "asx"
95 #define USB_CTRL_SET_TIMEOUT 5000
96 #define USB_CTRL_GET_TIMEOUT 5000
97 #define USB_BULK_SEND_TIMEOUT 5000
98 #define USB_BULK_RECV_TIMEOUT 5000
100 #define AX_RX_URB_SIZE 2048
101 #define PHY_CONNECT_TIMEOUT 5000
103 /* asix_flags defines */
105 #define FLAG_TYPE_AX88172 (1U << 0)
106 #define FLAG_TYPE_AX88772 (1U << 1)
107 #define FLAG_TYPE_AX88772B (1U << 2)
108 #define FLAG_EEPROM_MAC (1U << 3) /* initial mac address in eeprom */
111 static int curr_eth_dev; /* index for name of next device detected */
114 struct asix_private {
119 * Asix infrastructure commands
121 static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
122 u16 size, void *data)
126 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x "
127 "size=%d\n", cmd, value, index, size);
129 len = usb_control_msg(
131 usb_sndctrlpipe(dev->pusb_dev, 0),
133 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
138 USB_CTRL_SET_TIMEOUT);
140 return len == size ? 0 : -1;
143 static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
144 u16 size, void *data)
148 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
149 cmd, value, index, size);
151 len = usb_control_msg(
153 usb_rcvctrlpipe(dev->pusb_dev, 0),
155 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
160 USB_CTRL_GET_TIMEOUT);
161 return len == size ? 0 : -1;
164 static inline int asix_set_sw_mii(struct ueth_data *dev)
168 ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
170 debug("Failed to enable software MII access\n");
174 static inline int asix_set_hw_mii(struct ueth_data *dev)
178 ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
180 debug("Failed to enable hardware MII access\n");
184 static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
186 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
188 asix_set_sw_mii(dev);
189 asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res);
190 asix_set_hw_mii(dev);
192 debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
193 phy_id, loc, le16_to_cpu(*res));
195 return le16_to_cpu(*res);
199 asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
201 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
202 *res = cpu_to_le16(val);
204 debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
206 asix_set_sw_mii(dev);
207 asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res);
208 asix_set_hw_mii(dev);
212 * Asix "high level" commands
214 static int asix_sw_reset(struct ueth_data *dev, u8 flags)
218 ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
220 debug("Failed to send software reset: %02x\n", ret);
227 static inline int asix_get_phy_addr(struct ueth_data *dev)
229 ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2);
231 int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
233 debug("asix_get_phy_addr()\n");
236 debug("Error reading PHYID register: %02x\n", ret);
239 debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]);
246 static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
250 debug("asix_write_medium_mode() - mode = 0x%04x\n", mode);
251 ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode,
254 debug("Failed to write Medium Mode mode to 0x%04x: %02x\n",
260 static u16 asix_read_rx_ctl(struct ueth_data *dev)
262 ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1);
264 int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v);
267 debug("Error reading RX_CTL register: %02x\n", ret);
269 ret = le16_to_cpu(*v);
273 static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode)
277 debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode);
278 ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
280 debug("Failed to write RX_CTL mode to 0x%04x: %02x\n",
286 static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep)
290 debug("asix_write_gpio() - value = 0x%04x\n", value);
291 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
293 debug("Failed to write GPIO value 0x%04x: %02x\n",
297 udelay(sleep * 1000);
302 static int asix_write_hwaddr(struct eth_device *eth)
304 struct ueth_data *dev = (struct ueth_data *)eth->priv;
306 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
308 memcpy(buf, eth->enetaddr, ETH_ALEN);
310 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, buf);
312 debug("Failed to set MAC address: %02x\n", ret);
322 * mii_nway_restart - restart NWay (autonegotiation) for this interface
324 * Returns 0 on success, negative on error.
326 static int mii_nway_restart(struct ueth_data *dev)
331 /* if autoneg is off, it's an error */
332 bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR);
334 if (bmcr & BMCR_ANENABLE) {
335 bmcr |= BMCR_ANRESTART;
336 asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
343 static int asix_read_mac(struct eth_device *eth)
345 struct ueth_data *dev = (struct ueth_data *)eth->priv;
346 struct asix_private *priv = (struct asix_private *)dev->dev_priv;
348 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
350 if (priv->flags & FLAG_EEPROM_MAC) {
351 for (i = 0; i < (ETH_ALEN >> 1); i++) {
352 if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
353 0x04 + i, 0, 2, buf) < 0) {
354 debug("Failed to read SROM address 04h.\n");
357 memcpy((eth->enetaddr + i * 2), buf, 2);
360 if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf)
362 debug("Failed to read MAC address.\n");
365 memcpy(eth->enetaddr, buf, ETH_ALEN);
371 static int asix_basic_reset(struct ueth_data *dev)
376 if (asix_write_gpio(dev,
377 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0)
380 /* 0x10 is the phy id of the embedded 10/100 ethernet phy */
381 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
382 if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
383 embd_phy, 0, 0, NULL) < 0) {
384 debug("Select PHY #1 failed\n");
388 if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0)
391 if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0)
395 if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0)
398 if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0)
402 rx_ctl = asix_read_rx_ctl(dev);
403 debug("RX_CTL is 0x%04x after software reset\n", rx_ctl);
404 if (asix_write_rx_ctl(dev, 0x0000) < 0)
407 rx_ctl = asix_read_rx_ctl(dev);
408 debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
410 dev->phy_id = asix_get_phy_addr(dev);
412 debug("Failed to read phy id\n");
414 asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
415 asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
416 ADVERTISE_ALL | ADVERTISE_CSMA);
417 mii_nway_restart(dev);
419 if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
422 if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
423 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
424 AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
425 debug("Write IPG,IPG1,IPG2 failed\n");
435 static int asix_init(struct eth_device *eth, bd_t *bd)
437 struct ueth_data *dev = (struct ueth_data *)eth->priv;
439 #define TIMEOUT_RESOLUTION 50 /* ms */
442 debug("** %s()\n", __func__);
444 if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
448 link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) &
450 if (!link_detected) {
452 printf("Waiting for Ethernet connection... ");
453 udelay(TIMEOUT_RESOLUTION * 1000);
454 timeout += TIMEOUT_RESOLUTION;
456 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
461 printf("unable to connect.\n");
470 static int asix_send(struct eth_device *eth, void *packet, int length)
472 struct ueth_data *dev = (struct ueth_data *)eth->priv;
476 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
477 PKTSIZE + sizeof(packet_len));
479 debug("** %s(), len %d\n", __func__, length);
481 packet_len = (((length) ^ 0x0000ffff) << 16) + (length);
482 cpu_to_le32s(&packet_len);
484 memcpy(msg, &packet_len, sizeof(packet_len));
485 memcpy(msg + sizeof(packet_len), (void *)packet, length);
489 err = usb_bulk_msg(dev->pusb_dev,
490 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
492 length + sizeof(packet_len),
494 USB_BULK_SEND_TIMEOUT);
495 debug("Tx: len = %u, actual = %u, err = %d\n",
496 length + sizeof(packet_len), actual_len, err);
501 static int asix_recv(struct eth_device *eth)
503 struct ueth_data *dev = (struct ueth_data *)eth->priv;
504 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
505 unsigned char *buf_ptr;
510 debug("** %s()\n", __func__);
512 err = usb_bulk_msg(dev->pusb_dev,
513 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
517 USB_BULK_RECV_TIMEOUT);
518 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
521 debug("Rx: failed to receive\n");
524 if (actual_len > AX_RX_URB_SIZE) {
525 debug("Rx: received too many bytes %d\n", actual_len);
530 while (actual_len > 0) {
532 * 1st 4 bytes contain the length of the actual data as two
533 * complementary 16-bit words. Extract the length of the data.
535 if (actual_len < sizeof(packet_len)) {
536 debug("Rx: incomplete packet length\n");
539 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
540 le32_to_cpus(&packet_len);
541 if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
542 debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
543 packet_len, (~packet_len >> 16) & 0x7ff,
547 packet_len = packet_len & 0x7ff;
548 if (packet_len > actual_len - sizeof(packet_len)) {
549 debug("Rx: too large packet: %d\n", packet_len);
553 /* Notify net stack */
554 NetReceive(buf_ptr + sizeof(packet_len), packet_len);
556 /* Adjust for next iteration. Packets are padded to 16-bits */
559 actual_len -= sizeof(packet_len) + packet_len;
560 buf_ptr += sizeof(packet_len) + packet_len;
566 static void asix_halt(struct eth_device *eth)
568 debug("** %s()\n", __func__);
572 * Asix probing functions
574 void asix_eth_before_probe(void)
580 unsigned short vendor;
581 unsigned short product;
585 static const struct asix_dongle const asix_dongles[] = {
586 { 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */
587 { 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */
588 /* Cables-to-Go USB Ethernet Adapter */
589 { 0x0b95, 0x772a, FLAG_TYPE_AX88772 },
590 { 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */
591 { 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */
592 { 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */
593 { 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */
594 { 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */
595 /* DLink DUB-E100 H/W Ver B1 Alternate */
596 { 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
598 { 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
599 { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
602 /* Probe to see if a new device is actually an asix device */
603 int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
604 struct ueth_data *ss)
606 struct usb_interface *iface;
607 struct usb_interface_descriptor *iface_desc;
608 int ep_in_found = 0, ep_out_found = 0;
611 /* let's examine the device now */
612 iface = &dev->config.if_desc[ifnum];
613 iface_desc = &dev->config.if_desc[ifnum].desc;
615 for (i = 0; asix_dongles[i].vendor != 0; i++) {
616 if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
617 dev->descriptor.idProduct == asix_dongles[i].product)
618 /* Found a supported dongle */
622 if (asix_dongles[i].vendor == 0)
625 memset(ss, 0, sizeof(struct ueth_data));
627 /* At this point, we know we've got a live one */
628 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
629 dev->descriptor.idVendor, dev->descriptor.idProduct);
631 /* Initialize the ueth_data structure with some useful info */
634 ss->subclass = iface_desc->bInterfaceSubClass;
635 ss->protocol = iface_desc->bInterfaceProtocol;
637 /* alloc driver private */
638 ss->dev_priv = calloc(1, sizeof(struct asix_private));
642 ((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags;
645 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
646 * int. We will ignore any others.
648 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
649 /* is it an BULK endpoint? */
650 if ((iface->ep_desc[i].bmAttributes &
651 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
652 u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
653 if (ep_addr & USB_DIR_IN) {
655 ss->ep_in = ep_addr &
656 USB_ENDPOINT_NUMBER_MASK;
661 ss->ep_out = ep_addr &
662 USB_ENDPOINT_NUMBER_MASK;
668 /* is it an interrupt endpoint? */
669 if ((iface->ep_desc[i].bmAttributes &
670 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
671 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
672 USB_ENDPOINT_NUMBER_MASK;
673 ss->irqinterval = iface->ep_desc[i].bInterval;
676 debug("Endpoints In %d Out %d Int %d\n",
677 ss->ep_in, ss->ep_out, ss->ep_int);
679 /* Do some basic sanity checks, and bail if we find a problem */
680 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
681 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
682 debug("Problems with device\n");
685 dev->privptr = (void *)ss;
689 int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
690 struct eth_device *eth)
692 struct asix_private *priv = (struct asix_private *)ss->dev_priv;
695 debug("%s: missing parameter.\n", __func__);
698 sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
699 eth->init = asix_init;
700 eth->send = asix_send;
701 eth->recv = asix_recv;
702 eth->halt = asix_halt;
703 if (!(priv->flags & FLAG_TYPE_AX88172))
704 eth->write_hwaddr = asix_write_hwaddr;
707 if (asix_basic_reset(ss))
710 /* Get the MAC address */
711 if (asix_read_mac(eth))
713 debug("MAC %pM\n", eth->enetaddr);