drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/io.h>
  46 #include <linux/list.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <linux/usb/ch9.h>
  50 #include <linux/usb/gadget.h>
  51
  52 #include "core.h"
  53 #include "gadget.h"
  54 #include "io.h"
  55
  56 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
  57                 const struct dwc3_event_depevt *event);
  58
  59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  60 {
  61         switch (state) {
  62         case EP0_UNCONNECTED:
  63                 return "Unconnected";
  64         case EP0_SETUP_PHASE:
  65                 return "Setup Phase";
  66         case EP0_DATA_PHASE:
  67                 return "Data Phase";
  68         case EP0_STATUS_PHASE:
  69                 return "Status Phase";
  70         default:
  71                 return "UNKNOWN";
  72         }
  73 }
  74
  75 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  76                 u32 len, u32 type)
  77 {
  78         struct dwc3_gadget_ep_cmd_params params;
  79         struct dwc3_trb_hw              *trb_hw;
  80         struct dwc3_trb                 trb;
  81         struct dwc3_ep                  *dep;
  82
  83         int                             ret;
  84
  85         dep = dwc->eps[epnum];
  86         if (dep->flags & DWC3_EP_BUSY) {
  87                 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
  88                 return 0;
  89         }
  90
  91         trb_hw = dwc->ep0_trb;
  92         memset(&trb, 0, sizeof(trb));
  93
  94         trb.trbctl = type;
  95         trb.bplh = buf_dma;
  96         trb.length = len;
  97
  98         trb.hwo = 1;
  99         trb.lst = 1;
 100         trb.ioc = 1;
 101         trb.isp_imi = 1;
 102
 103         dwc3_trb_to_hw(&trb, trb_hw);
 104
 105         memset(&params, 0, sizeof(params));
 106         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 107         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 108
 109         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 110                         DWC3_DEPCMD_STARTTRANSFER, &params);
 111         if (ret < 0) {
 112                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 113                 return ret;
 114         }
 115
 116         dep->flags |= DWC3_EP_BUSY;
 117         dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
 118                         dep->number);
 119
 120         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 121
 122         return 0;
 123 }
 124
 125 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 126                 struct dwc3_request *req)
 127 {
 128         int                     ret = 0;
 129
 130         req->request.actual     = 0;
 131         req->request.status     = -EINPROGRESS;
 132         req->epnum              = dep->number;
 133
 134         list_add_tail(&req->list, &dep->request_list);
 135
 136         /*
 137          * Gadget driver might not be quick enough to queue a request
 138          * before we get a Transfer Not Ready event on this endpoint.
 139          *
 140          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 141          * flag is set, it's telling us that as soon as Gadget queues the
 142          * required request, we should kick the transfer here because the
 143          * IRQ we were waiting for is long gone.
 144          */
 145         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 146                 struct dwc3     *dwc = dep->dwc;
 147                 unsigned        direction;
 148                 u32             type;
 149
 150                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 151
 152                 if (dwc->ep0state != EP0_DATA_PHASE) {
 153                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 154                         return 0;
 155                 }
 156
 157                 ret = dwc3_ep0_start_trans(dwc, direction,
 158                                 req->request.dma, req->request.length,
 159                                 DWC3_TRBCTL_CONTROL_DATA);
 160                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 161                                 DWC3_EP0_DIR_IN);
 162         }
 163
 164         return ret;
 165 }
 166
 167 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 168                 gfp_t gfp_flags)
 169 {
 170         struct dwc3_request             *req = to_dwc3_request(request);
 171         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 172         struct dwc3                     *dwc = dep->dwc;
 173
 174         unsigned long                   flags;
 175
 176         int                             ret;
 177
 178         spin_lock_irqsave(&dwc->lock, flags);
 179         if (!dep->desc) {
 180                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
 181                                 request, dep->name);
 182                 ret = -ESHUTDOWN;
 183                 goto out;
 184         }
 185
 186         /* we share one TRB for ep0/1 */
 187         if (!list_empty(&dwc->eps[0]->request_list) ||
 188                         !list_empty(&dwc->eps[1]->request_list) ||
 189                         dwc->ep0_status_pending) {
 190                 ret = -EBUSY;
 191                 goto out;
 192         }
 193
 194         dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
 195                         request, dep->name, request->length,
 196                         dwc3_ep0_state_string(dwc->ep0state));
 197
 198         ret = __dwc3_gadget_ep0_queue(dep, req);
 199
 200 out:
 201         spin_unlock_irqrestore(&dwc->lock, flags);
 202
 203         return ret;
 204 }
 205
 206 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 207 {
 208         struct dwc3_ep          *dep = dwc->eps[0];
 209
 210         /* stall is always issued on EP0 */
 211         __dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
 212         dwc->eps[0]->flags = DWC3_EP_ENABLED;
 213
 214         if (!list_empty(&dep->request_list)) {
 215                 struct dwc3_request     *req;
 216
 217                 req = next_request(&dep->request_list);
 218                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 219         }
 220
 221         dwc->ep0state = EP0_SETUP_PHASE;
 222         dwc3_ep0_out_start(dwc);
 223 }
 224
 225 void dwc3_ep0_out_start(struct dwc3 *dwc)
 226 {
 227         int                             ret;
 228
 229         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 230                         DWC3_TRBCTL_CONTROL_SETUP);
 231         WARN_ON(ret < 0);
 232 }
 233
 234 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 235 {
 236         struct dwc3_ep          *dep;
 237         u32                     windex = le16_to_cpu(wIndex_le);
 238         u32                     epnum;
 239
 240         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 241         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 242                 epnum |= 1;
 243
 244         dep = dwc->eps[epnum];
 245         if (dep->flags & DWC3_EP_ENABLED)
 246                 return dep;
 247
 248         return NULL;
 249 }
 250
 251 static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
 252 {
 253         dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr,
 254                         dwc->ep0_usb_req.length,
 255                         DWC3_TRBCTL_CONTROL_DATA);
 256 }
 257
 258 /*
 259  * ch 9.4.5
 260  */
 261 static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 262 {
 263         struct dwc3_ep          *dep;
 264         u32                     recip;
 265         u16                     usb_status = 0;
 266         __le16                  *response_pkt;
 267
 268         recip = ctrl->bRequestType & USB_RECIP_MASK;
 269         switch (recip) {
 270         case USB_RECIP_DEVICE:
 271                 /*
 272                  * We are self-powered. U1/U2/LTM will be set later
 273                  * once we handle this states. RemoteWakeup is 0 on SS
 274                  */
 275                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 276                 break;
 277
 278         case USB_RECIP_INTERFACE:
 279                 /*
 280                  * Function Remote Wake Capable D0
 281                  * Function Remote Wakeup       D1
 282                  */
 283                 break;
 284
 285         case USB_RECIP_ENDPOINT:
 286                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 287                 if (!dep)
 288                        return -EINVAL;
 289
 290                 if (dep->flags & DWC3_EP_STALL)
 291                         usb_status = 1 << USB_ENDPOINT_HALT;
 292                 break;
 293         default:
 294                 return -EINVAL;
 295         };
 296
 297         response_pkt = (__le16 *) dwc->setup_buf;
 298         *response_pkt = cpu_to_le16(usb_status);
 299         dwc->ep0_usb_req.length = sizeof(*response_pkt);
 300         dwc->ep0_status_pending = 1;
 301
 302         return 0;
 303 }
 304
 305 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 306                 struct usb_ctrlrequest *ctrl, int set)
 307 {
 308         struct dwc3_ep          *dep;
 309         u32                     recip;
 310         u32                     wValue;
 311         u32                     wIndex;
 312         u32                     reg;
 313         int                     ret;
 314         u32                     mode;
 315
 316         wValue = le16_to_cpu(ctrl->wValue);
 317         wIndex = le16_to_cpu(ctrl->wIndex);
 318         recip = ctrl->bRequestType & USB_RECIP_MASK;
 319         switch (recip) {
 320         case USB_RECIP_DEVICE:
 321
 322                 /*
 323                  * 9.4.1 says only only for SS, in AddressState only for
 324                  * default control pipe
 325                  */
 326                 switch (wValue) {
 327                 case USB_DEVICE_U1_ENABLE:
 328                 case USB_DEVICE_U2_ENABLE:
 329                 case USB_DEVICE_LTM_ENABLE:
 330                         if (dwc->dev_state != DWC3_CONFIGURED_STATE)
 331                                 return -EINVAL;
 332                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 333                                 return -EINVAL;
 334                 }
 335
 336                 /* XXX add U[12] & LTM */
 337                 switch (wValue) {
 338                 case USB_DEVICE_REMOTE_WAKEUP:
 339                         break;
 340                 case USB_DEVICE_U1_ENABLE:
 341                         break;
 342                 case USB_DEVICE_U2_ENABLE:
 343                         break;
 344                 case USB_DEVICE_LTM_ENABLE:
 345                         break;
 346
 347                 case USB_DEVICE_TEST_MODE:
 348                         if ((wIndex & 0xff) != 0)
 349                                 return -EINVAL;
 350                         if (!set)
 351                                 return -EINVAL;
 352
 353                         mode = wIndex >> 8;
 354                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 355                         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
 356
 357                         switch (mode) {
 358                         case TEST_J:
 359                         case TEST_K:
 360                         case TEST_SE0_NAK:
 361                         case TEST_PACKET:
 362                         case TEST_FORCE_EN:
 363                                 reg |= mode << 1;
 364                                 break;
 365                         default:
 366                                 return -EINVAL;
 367                         }
 368                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 369                         break;
 370                 default:
 371                         return -EINVAL;
 372                 }
 373                 break;
 374
 375         case USB_RECIP_INTERFACE:
 376                 switch (wValue) {
 377                 case USB_INTRF_FUNC_SUSPEND:
 378                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 379                                 /* XXX enable Low power suspend */
 380                                 ;
 381                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 382                                 /* XXX enable remote wakeup */
 383                                 ;
 384                         break;
 385                 default:
 386                         return -EINVAL;
 387                 }
 388                 break;
 389
 390         case USB_RECIP_ENDPOINT:
 391                 switch (wValue) {
 392                 case USB_ENDPOINT_HALT:
 393
 394                         dep =  dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 395                         if (!dep)
 396                                 return -EINVAL;
 397                         ret = __dwc3_gadget_ep_set_halt(dep, set);
 398                         if (ret)
 399                                 return -EINVAL;
 400                         break;
 401                 default:
 402                         return -EINVAL;
 403                 }
 404                 break;
 405
 406         default:
 407                 return -EINVAL;
 408         };
 409
 410         return 0;
 411 }
 412
 413 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 414 {
 415         u32 addr;
 416         u32 reg;
 417
 418         addr = le16_to_cpu(ctrl->wValue);
 419         if (addr > 127)
 420                 return -EINVAL;
 421
 422         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 423         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 424         reg |= DWC3_DCFG_DEVADDR(addr);
 425         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 426
 427         if (addr)
 428                 dwc->dev_state = DWC3_ADDRESS_STATE;
 429         else
 430                 dwc->dev_state = DWC3_DEFAULT_STATE;
 431
 432         return 0;
 433 }
 434
 435 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 436 {
 437         int ret;
 438
 439         spin_unlock(&dwc->lock);
 440         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 441         spin_lock(&dwc->lock);
 442         return ret;
 443 }
 444
 445 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 446 {
 447         u32 cfg;
 448         int ret;
 449
 450         dwc->start_config_issued = false;
 451         cfg = le16_to_cpu(ctrl->wValue);
 452
 453         switch (dwc->dev_state) {
 454         case DWC3_DEFAULT_STATE:
 455                 return -EINVAL;
 456                 break;
 457
 458         case DWC3_ADDRESS_STATE:
 459                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 460                 /* if the cfg matches and the cfg is non zero */
 461                 if (!ret && cfg)
 462                         dwc->dev_state = DWC3_CONFIGURED_STATE;
 463                 break;
 464
 465         case DWC3_CONFIGURED_STATE:
 466                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 467                 if (!cfg)
 468                         dwc->dev_state = DWC3_ADDRESS_STATE;
 469                 break;
 470         }
 471         return 0;
 472 }
 473
 474 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 475 {
 476         int ret;
 477
 478         switch (ctrl->bRequest) {
 479         case USB_REQ_GET_STATUS:
 480                 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
 481                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 482                 break;
 483         case USB_REQ_CLEAR_FEATURE:
 484                 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
 485                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 486                 break;
 487         case USB_REQ_SET_FEATURE:
 488                 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
 489                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 490                 break;
 491         case USB_REQ_SET_ADDRESS:
 492                 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
 493                 ret = dwc3_ep0_set_address(dwc, ctrl);
 494                 break;
 495         case USB_REQ_SET_CONFIGURATION:
 496                 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
 497                 ret = dwc3_ep0_set_config(dwc, ctrl);
 498                 break;
 499         default:
 500                 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
 501                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 502                 break;
 503         };
 504
 505         return ret;
 506 }
 507
 508 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 509                 const struct dwc3_event_depevt *event)
 510 {
 511         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 512         int ret;
 513         u32 len;
 514
 515         if (!dwc->gadget_driver)
 516                 goto err;
 517
 518         len = le16_to_cpu(ctrl->wLength);
 519         if (!len) {
 520                 dwc->three_stage_setup = false;
 521                 dwc->ep0_expect_in = false;
 522                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 523         } else {
 524                 dwc->three_stage_setup = true;
 525                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 526                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 527         }
 528
 529         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 530                 ret = dwc3_ep0_std_request(dwc, ctrl);
 531         else
 532                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 533
 534         if (ret >= 0)
 535                 return;
 536
 537 err:
 538         dwc3_ep0_stall_and_restart(dwc);
 539 }
 540
 541 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 542                 const struct dwc3_event_depevt *event)
 543 {
 544         struct dwc3_request     *r = NULL;
 545         struct usb_request      *ur;
 546         struct dwc3_trb         trb;
 547         struct dwc3_ep          *dep;
 548         u32                     transferred;
 549         u8                      epnum;
 550
 551         epnum = event->endpoint_number;
 552         dep = dwc->eps[epnum];
 553
 554         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 555
 556         if (!dwc->ep0_status_pending) {
 557                 r = next_request(&dwc->eps[0]->request_list);
 558                 ur = &r->request;
 559         } else {
 560                 ur = &dwc->ep0_usb_req;
 561                 dwc->ep0_status_pending = 0;
 562         }
 563
 564         dwc3_trb_to_nat(dwc->ep0_trb, &trb);
 565
 566         if (dwc->ep0_bounced) {
 567                 struct dwc3_ep  *ep0 = dwc->eps[0];
 568
 569                 transferred = min_t(u32, ur->length,
 570                                 ep0->endpoint.maxpacket - trb.length);
 571                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 572                 dwc->ep0_bounced = false;
 573         } else {
 574                 transferred = ur->length - trb.length;
 575         }
 576
 577         ur->actual += transferred;
 578
 579         if ((epnum & 1) && ur->actual < ur->length) {
 580                 /* for some reason we did not get everything out */
 581
 582                 dwc3_ep0_stall_and_restart(dwc);
 583         } else {
 584                 /*
 585                  * handle the case where we have to send a zero packet. This
 586                  * seems to be case when req.length > maxpacket. Could it be?
 587                  */
 588                 if (r)
 589                         dwc3_gadget_giveback(dep, r, 0);
 590         }
 591 }
 592
 593 static void dwc3_ep0_complete_req(struct dwc3 *dwc,
 594                 const struct dwc3_event_depevt *event)
 595 {
 596         struct dwc3_request     *r;
 597         struct dwc3_ep          *dep;
 598
 599         dep = dwc->eps[0];
 600
 601         if (!list_empty(&dep->request_list)) {
 602                 r = next_request(&dep->request_list);
 603
 604                 dwc3_gadget_giveback(dep, r, 0);
 605         }
 606
 607         dwc->ep0state = EP0_SETUP_PHASE;
 608         dwc3_ep0_out_start(dwc);
 609 }
 610
 611 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 612                         const struct dwc3_event_depevt *event)
 613 {
 614         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 615
 616         dep->flags &= ~DWC3_EP_BUSY;
 617
 618         switch (dwc->ep0state) {
 619         case EP0_SETUP_PHASE:
 620                 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
 621                 dwc3_ep0_inspect_setup(dwc, event);
 622                 break;
 623
 624         case EP0_DATA_PHASE:
 625                 dev_vdbg(dwc->dev, "Data Phase\n");
 626                 dwc3_ep0_complete_data(dwc, event);
 627                 break;
 628
 629         case EP0_STATUS_PHASE:
 630                 dev_vdbg(dwc->dev, "Status Phase\n");
 631                 dwc3_ep0_complete_req(dwc, event);
 632                 break;
 633         default:
 634                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 635         }
 636 }
 637
 638 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
 639                 const struct dwc3_event_depevt *event)
 640 {
 641         dwc->ep0state = EP0_SETUP_PHASE;
 642         dwc3_ep0_out_start(dwc);
 643 }
 644
 645 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
 646                 const struct dwc3_event_depevt *event)
 647 {
 648         struct dwc3_ep          *dep;
 649         struct dwc3_request     *req;
 650         int                     ret;
 651
 652         dep = dwc->eps[0];
 653         dwc->ep0state = EP0_DATA_PHASE;
 654
 655         if (dwc->ep0_status_pending) {
 656                 dwc3_ep0_send_status_response(dwc);
 657                 return;
 658         }
 659
 660         if (list_empty(&dep->request_list)) {
 661                 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
 662                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 663
 664                 if (event->endpoint_number)
 665                         dep->flags |= DWC3_EP0_DIR_IN;
 666                 return;
 667         }
 668
 669         req = next_request(&dep->request_list);
 670         req->direction = !!event->endpoint_number;
 671
 672         dwc->ep0state = EP0_DATA_PHASE;
 673         if (req->request.length == 0) {
 674                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 675                                 dwc->ctrl_req_addr, 0,
 676                                 DWC3_TRBCTL_CONTROL_DATA);
 677         } else if ((req->request.length % dep->endpoint.maxpacket)
 678                         && (event->endpoint_number == 0)) {
 679                 dwc3_map_buffer_to_dma(req);
 680
 681                 WARN_ON(req->request.length > dep->endpoint.maxpacket);
 682
 683                 dwc->ep0_bounced = true;
 684
 685                 /*
 686                  * REVISIT in case request length is bigger than EP0
 687                  * wMaxPacketSize, we will need two chained TRBs to handle
 688                  * the transfer.
 689                  */
 690                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 691                                 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
 692                                 DWC3_TRBCTL_CONTROL_DATA);
 693         } else {
 694                 dwc3_map_buffer_to_dma(req);
 695
 696                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 697                                 req->request.dma, req->request.length,
 698                                 DWC3_TRBCTL_CONTROL_DATA);
 699         }
 700
 701         WARN_ON(ret < 0);
 702 }
 703
 704 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
 705                 const struct dwc3_event_depevt *event)
 706 {
 707         u32                     type;
 708         int                     ret;
 709
 710         dwc->ep0state = EP0_STATUS_PHASE;
 711
 712         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 713                 : DWC3_TRBCTL_CONTROL_STATUS2;
 714
 715         ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 716                         dwc->ctrl_req_addr, 0, type);
 717
 718         WARN_ON(ret < 0);
 719 }
 720
 721 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
 722                 const struct dwc3_event_depevt *event)
 723 {
 724         switch (event->status) {
 725         case DEPEVT_STATUS_CONTROL_SETUP:
 726                 dev_vdbg(dwc->dev, "Control Setup\n");
 727                 dwc3_ep0_do_control_setup(dwc, event);
 728                 break;
 729
 730         case DEPEVT_STATUS_CONTROL_DATA:
 731                 dev_vdbg(dwc->dev, "Control Data\n");
 732
 733                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
 734                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 735                                         dwc->ep0_next_event,
 736                                         DWC3_EP0_NRDY_DATA);
 737
 738                         dwc3_ep0_stall_and_restart(dwc);
 739                         return;
 740                 }
 741
 742                 /*
 743                  * One of the possible error cases is when Host _does_
 744                  * request for Data Phase, but it does so on the wrong
 745                  * direction.
 746                  *
 747                  * Here, we already know ep0_next_event is DATA (see above),
 748                  * so we only need to check for direction.
 749                  */
 750                 if (dwc->ep0_expect_in != event->endpoint_number) {
 751                         dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
 752                         dwc3_ep0_stall_and_restart(dwc);
 753                         return;
 754                 }
 755
 756                 dwc3_ep0_do_control_data(dwc, event);
 757                 break;
 758
 759         case DEPEVT_STATUS_CONTROL_STATUS:
 760                 dev_vdbg(dwc->dev, "Control Status\n");
 761
 762                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
 763                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 764                                         dwc->ep0_next_event,
 765                                         DWC3_EP0_NRDY_STATUS);
 766
 767                         dwc3_ep0_stall_and_restart(dwc);
 768                         return;
 769                 }
 770                 dwc3_ep0_do_control_status(dwc, event);
 771         }
 772 }
 773
 774 void dwc3_ep0_interrupt(struct dwc3 *dwc,
 775                 const const struct dwc3_event_depevt *event)
 776 {
 777         u8                      epnum = event->endpoint_number;
 778
 779         dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
 780                         dwc3_ep_event_string(event->endpoint_event),
 781                         epnum >> 1, (epnum & 1) ? "in" : "out",
 782                         dwc3_ep0_state_string(dwc->ep0state));
 783
 784         switch (event->endpoint_event) {
 785         case DWC3_DEPEVT_XFERCOMPLETE:
 786                 dwc3_ep0_xfer_complete(dwc, event);
 787                 break;
 788
 789         case DWC3_DEPEVT_XFERNOTREADY:
 790                 dwc3_ep0_xfernotready(dwc, event);
 791                 break;
 792
 793         case DWC3_DEPEVT_XFERINPROGRESS:
 794         case DWC3_DEPEVT_RXTXFIFOEVT:
 795         case DWC3_DEPEVT_STREAMEVT:
 796         case DWC3_DEPEVT_EPCMDCMPLT:
 797                 break;
 798         }
 799 }