2 * core.h - DesignWare USB3 DRD Core Header
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #ifndef __DRIVERS_USB_DWC3_CORE_H
40 #define __DRIVERS_USB_DWC3_CORE_H
42 #include <linux/device.h>
43 #include <linux/spinlock.h>
44 #include <linux/list.h>
45 #include <linux/dma-mapping.h>
47 #include <linux/debugfs.h>
49 #include <linux/usb/ch9.h>
50 #include <linux/usb/gadget.h>
52 /* Global constants */
53 #define DWC3_ENDPOINTS_NUM 32
55 #define DWC3_EVENT_BUFFERS_NUM 2
56 #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
57 #define DWC3_EVENT_TYPE_MASK 0xfe
59 #define DWC3_EVENT_TYPE_DEV 0
60 #define DWC3_EVENT_TYPE_CARKIT 3
61 #define DWC3_EVENT_TYPE_I2C 4
63 #define DWC3_DEVICE_EVENT_DISCONNECT 0
64 #define DWC3_DEVICE_EVENT_RESET 1
65 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
66 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
67 #define DWC3_DEVICE_EVENT_WAKEUP 4
68 #define DWC3_DEVICE_EVENT_EOPF 6
69 #define DWC3_DEVICE_EVENT_SOF 7
70 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
71 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
72 #define DWC3_DEVICE_EVENT_OVERFLOW 11
74 #define DWC3_GEVNTCOUNT_MASK 0xfffc
75 #define DWC3_GSNPSID_MASK 0xffff0000
76 #define DWC3_GSNPSREV_MASK 0xffff
78 /* Global Registers */
79 #define DWC3_GSBUSCFG0 0xc100
80 #define DWC3_GSBUSCFG1 0xc104
81 #define DWC3_GTXTHRCFG 0xc108
82 #define DWC3_GRXTHRCFG 0xc10c
83 #define DWC3_GCTL 0xc110
84 #define DWC3_GEVTEN 0xc114
85 #define DWC3_GSTS 0xc118
86 #define DWC3_GSNPSID 0xc120
87 #define DWC3_GGPIO 0xc124
88 #define DWC3_GUID 0xc128
89 #define DWC3_GUCTL 0xc12c
90 #define DWC3_GBUSERRADDR0 0xc130
91 #define DWC3_GBUSERRADDR1 0xc134
92 #define DWC3_GPRTBIMAP0 0xc138
93 #define DWC3_GPRTBIMAP1 0xc13c
94 #define DWC3_GHWPARAMS0 0xc140
95 #define DWC3_GHWPARAMS1 0xc144
96 #define DWC3_GHWPARAMS2 0xc148
97 #define DWC3_GHWPARAMS3 0xc14c
98 #define DWC3_GHWPARAMS4 0xc150
99 #define DWC3_GHWPARAMS5 0xc154
100 #define DWC3_GHWPARAMS6 0xc158
101 #define DWC3_GHWPARAMS7 0xc15c
102 #define DWC3_GDBGFIFOSPACE 0xc160
103 #define DWC3_GDBGLTSSM 0xc164
104 #define DWC3_GPRTBIMAP_HS0 0xc180
105 #define DWC3_GPRTBIMAP_HS1 0xc184
106 #define DWC3_GPRTBIMAP_FS0 0xc188
107 #define DWC3_GPRTBIMAP_FS1 0xc18c
109 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
110 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
112 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
114 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
116 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
117 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
119 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
120 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
121 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
122 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
124 #define DWC3_GHWPARAMS8 0xc600
126 /* Device Registers */
127 #define DWC3_DCFG 0xc700
128 #define DWC3_DCTL 0xc704
129 #define DWC3_DEVTEN 0xc708
130 #define DWC3_DSTS 0xc70c
131 #define DWC3_DGCMDPAR 0xc710
132 #define DWC3_DGCMD 0xc714
133 #define DWC3_DALEPENA 0xc720
134 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
135 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
136 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
137 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
140 #define DWC3_OCFG 0xcc00
141 #define DWC3_OCTL 0xcc04
142 #define DWC3_OEVTEN 0xcc08
143 #define DWC3_OSTS 0xcc0C
147 /* Global Configuration Register */
148 #define DWC3_GCTL_PWRDNSCALE(n) (n << 19)
149 #define DWC3_GCTL_U2RSTECN (1 << 16)
150 #define DWC3_GCTL_RAMCLKSEL(x) ((x & DWC3_GCTL_CLK_MASK) << 6)
151 #define DWC3_GCTL_CLK_BUS (0)
152 #define DWC3_GCTL_CLK_PIPE (1)
153 #define DWC3_GCTL_CLK_PIPEHALF (2)
154 #define DWC3_GCTL_CLK_MASK (3)
156 #define DWC3_GCTL_PRTCAPDIR(n) (n << 12)
157 #define DWC3_GCTL_PRTCAP_HOST 1
158 #define DWC3_GCTL_PRTCAP_DEVICE 2
159 #define DWC3_GCTL_PRTCAP_OTG 3
161 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
162 #define DWC3_GCTL_SCALEDOWN(n) (n << 4)
163 #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
165 /* Global USB2 PHY Configuration Register */
166 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
167 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
169 /* Global USB3 PIPE Control Register */
170 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
171 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
173 /* Device Configuration Register */
174 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
175 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
177 #define DWC3_DCFG_SPEED_MASK (7 << 0)
178 #define DWC3_DCFG_SUPERSPEED (4 << 0)
179 #define DWC3_DCFG_HIGHSPEED (0 << 0)
180 #define DWC3_DCFG_FULLSPEED2 (1 << 0)
181 #define DWC3_DCFG_LOWSPEED (2 << 0)
182 #define DWC3_DCFG_FULLSPEED1 (3 << 0)
184 /* Device Control Register */
185 #define DWC3_DCTL_RUN_STOP (1 << 31)
186 #define DWC3_DCTL_CSFTRST (1 << 30)
187 #define DWC3_DCTL_LSFTRST (1 << 29)
189 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
190 #define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24)
192 #define DWC3_DCTL_APPL1RES (1 << 23)
194 #define DWC3_DCTL_INITU2ENA (1 << 12)
195 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
196 #define DWC3_DCTL_INITU1ENA (1 << 10)
197 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
198 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
200 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
201 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
203 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
204 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
205 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
206 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
207 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
208 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
209 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
211 /* Device Event Enable Register */
212 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
213 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
214 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
215 #define DWC3_DEVTEN_ERRTICERREN (1 << 9)
216 #define DWC3_DEVTEN_SOFEN (1 << 7)
217 #define DWC3_DEVTEN_EOPFEN (1 << 6)
218 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
219 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
220 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
221 #define DWC3_DEVTEN_USBRSTEN (1 << 1)
222 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
224 /* Device Status Register */
225 #define DWC3_DSTS_PWRUPREQ (1 << 24)
226 #define DWC3_DSTS_COREIDLE (1 << 23)
227 #define DWC3_DSTS_DEVCTRLHLT (1 << 22)
229 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
230 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
232 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
234 #define DWC3_DSTS_SOFFN_MASK (0x3ff << 3)
235 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
237 #define DWC3_DSTS_CONNECTSPD (7 << 0)
239 #define DWC3_DSTS_SUPERSPEED (4 << 0)
240 #define DWC3_DSTS_HIGHSPEED (0 << 0)
241 #define DWC3_DSTS_FULLSPEED2 (1 << 0)
242 #define DWC3_DSTS_LOWSPEED (2 << 0)
243 #define DWC3_DSTS_FULLSPEED1 (3 << 0)
245 /* Device Generic Command Register */
246 #define DWC3_DGCMD_SET_LMP 0x01
247 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
248 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
249 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
250 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
251 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
252 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
254 /* Device Endpoint Command Register */
255 #define DWC3_DEPCMD_PARAM_SHIFT 16
256 #define DWC3_DEPCMD_PARAM(x) (x << DWC3_DEPCMD_PARAM_SHIFT)
257 #define DWC3_DEPCMD_GET_RSC_IDX(x) ((x >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
258 #define DWC3_DEPCMD_STATUS_MASK (0x0f << 12)
259 #define DWC3_DEPCMD_STATUS(x) ((x & DWC3_DEPCMD_STATUS_MASK) >> 12)
260 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
261 #define DWC3_DEPCMD_CMDACT (1 << 10)
262 #define DWC3_DEPCMD_CMDIOC (1 << 8)
264 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
265 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
266 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
267 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
268 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
269 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
270 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
271 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
272 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
274 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
275 #define DWC3_DALEPENA_EP(n) (1 << n)
277 #define DWC3_DEPCMD_TYPE_CONTROL 0
278 #define DWC3_DEPCMD_TYPE_ISOC 1
279 #define DWC3_DEPCMD_TYPE_BULK 2
280 #define DWC3_DEPCMD_TYPE_INTR 3
287 * struct dwc3_event_buffer - Software event buffer representation
288 * @list: a list of event buffers
290 * @length: size of this buffer
292 * @dwc: pointer to DWC controller
294 struct dwc3_event_buffer {
304 #define DWC3_EP_FLAG_STALLED (1 << 0)
305 #define DWC3_EP_FLAG_WEDGED (1 << 1)
307 #define DWC3_EP_DIRECTION_TX true
308 #define DWC3_EP_DIRECTION_RX false
310 #define DWC3_TRB_NUM 32
311 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
314 * struct dwc3_ep - device side endpoint representation
315 * @endpoint: usb endpoint
316 * @request_list: list of requests for this endpoint
317 * @req_queued: list of requests on this ep which have TRBs setup
318 * @trb_pool: array of transaction buffers
319 * @trb_pool_dma: dma address of @trb_pool
320 * @free_slot: next slot which is going to be used
321 * @busy_slot: first slot which is owned by HW
322 * @desc: usb_endpoint_descriptor pointer
323 * @dwc: pointer to DWC controller
324 * @flags: endpoint flags (wedged, stalled, ...)
325 * @current_trb: index of current used trb
326 * @number: endpoint number (1 - 15)
327 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
328 * @res_trans_idx: Resource transfer index
329 * @interval: the intervall on which the ISOC transfer is started
330 * @name: a human readable name e.g. ep1out-bulk
331 * @direction: true for TX, false for RX
332 * @stream_capable: true when streams are enabled
335 struct usb_ep endpoint;
336 struct list_head request_list;
337 struct list_head req_queued;
339 struct dwc3_trb_hw *trb_pool;
340 dma_addr_t trb_pool_dma;
343 const struct usb_endpoint_descriptor *desc;
347 #define DWC3_EP_ENABLED (1 << 0)
348 #define DWC3_EP_STALL (1 << 1)
349 #define DWC3_EP_WEDGE (1 << 2)
350 #define DWC3_EP_BUSY (1 << 4)
351 #define DWC3_EP_PENDING_REQUEST (1 << 5)
353 /* This last one is specific to EP0 */
354 #define DWC3_EP0_DIR_IN (1 << 31)
356 unsigned current_trb;
365 unsigned direction:1;
366 unsigned stream_capable:1;
370 DWC3_PHY_UNKNOWN = 0,
376 DWC3_EP0_UNKNOWN = 0,
380 DWC3_EP0_NRDY_STATUS,
383 enum dwc3_ep0_state {
390 enum dwc3_link_state {
392 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
393 DWC3_LINK_STATE_U1 = 0x01,
394 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
395 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
396 DWC3_LINK_STATE_SS_DIS = 0x04,
397 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
398 DWC3_LINK_STATE_SS_INACT = 0x06,
399 DWC3_LINK_STATE_POLL = 0x07,
400 DWC3_LINK_STATE_RECOV = 0x08,
401 DWC3_LINK_STATE_HRESET = 0x09,
402 DWC3_LINK_STATE_CMPLY = 0x0a,
403 DWC3_LINK_STATE_LPBK = 0x0b,
404 DWC3_LINK_STATE_MASK = 0x0f,
407 enum dwc3_device_state {
410 DWC3_CONFIGURED_STATE,
414 * struct dwc3_trb - transfer request block
415 * @bpl: lower 32bit of the buffer
416 * @bph: higher 32bit of the buffer
417 * @length: buffer size (up to 16mb - 1)
418 * @pcm1: packet count m1
419 * @trbsts: trb status
423 * @hwo: hardware owner of descriptor
425 * @chn: chain buffers
426 * @csp: continue on short packets (only supported on isoc eps)
427 * @trbctl: trb control
430 * 3 = control-status-2
431 * 4 = control-status-3
432 * 5 = control-data (first trb of data stage)
433 * 6 = isochronous-first (first trb of service interval)
437 * @isp_imi: interrupt on short packet / interrupt on missed isoc
438 * @ioc: interrupt on complete
439 * @sid_sofn: Stream ID / SOF Number
450 #define DWC3_TRB_STS_OKAY 0
451 #define DWC3_TRB_STS_MISSED_ISOC 1
452 #define DWC3_TRB_STS_SETUP_PENDING 2
475 * struct dwc3_trb_hw - transfer request block (hw format)
488 static inline void dwc3_trb_to_hw(struct dwc3_trb *nat, struct dwc3_trb_hw *hw)
490 hw->bpl = cpu_to_le32(lower_32_bits(nat->bplh));
491 hw->bph = cpu_to_le32(upper_32_bits(nat->bplh));
492 hw->size = cpu_to_le32p(&nat->len_pcm);
493 /* HWO is written last */
494 hw->ctrl = cpu_to_le32p(&nat->control);
497 static inline void dwc3_trb_to_nat(struct dwc3_trb_hw *hw, struct dwc3_trb *nat)
501 bplh = le32_to_cpup(&hw->bpl);
502 bplh |= (u64) le32_to_cpup(&hw->bph) << 32;
505 nat->len_pcm = le32_to_cpup(&hw->size);
506 nat->control = le32_to_cpup(&hw->ctrl);
510 * dwc3_hwparams - copy of HWPARAMS registers
511 * @hwparams0 - GHWPARAMS0
512 * @hwparams1 - GHWPARAMS1
513 * @hwparams2 - GHWPARAMS2
514 * @hwparams3 - GHWPARAMS3
515 * @hwparams4 - GHWPARAMS4
516 * @hwparams5 - GHWPARAMS5
517 * @hwparams6 - GHWPARAMS6
518 * @hwparams7 - GHWPARAMS7
519 * @hwparams8 - GHWPARAMS8
521 struct dwc3_hwparams {
534 * struct dwc3 - representation of our controller
535 * @ctrl_req: usb control request which is used for ep0
536 * @ep0_trb: trb which is used for the ctrl_req
537 * @ep0_bounce: bounce buffer for ep0
538 * @setup_buf: used while precessing STD USB requests
539 * @ctrl_req_addr: dma address of ctrl_req
540 * @ep0_trb: dma address of ep0_trb
541 * @ep0_usb_req: dummy req used while handling STD USB requests
542 * @setup_buf_addr: dma address of setup_buf
543 * @ep0_bounce_addr: dma address of ep0_bounce
544 * @lock: for synchronizing
545 * @dev: pointer to our struct device
546 * @event_buffer_list: a list of event buffers
547 * @gadget: device side representation of the peripheral controller
548 * @gadget_driver: pointer to the gadget driver
549 * @regs: base address for our registers
550 * @regs_size: address space size
552 * @revision: revision register contents
553 * @is_selfpowered: true when we are selfpowered
554 * @three_stage_setup: set if we perform a three phase setup
555 * @ep0_status_pending: ep0 status response without a req is pending
556 * @ep0_bounced: true when we used bounce buffer
557 * @ep0_expect_in: true when we expect a DATA IN transfer
558 * @start_config_issued: true when StartConfig command has been issued
559 * @ep0_next_event: hold the next expected event
560 * @ep0state: state of endpoint zero
561 * @link_state: link state
562 * @speed: device speed (super, high, full, low)
563 * @mem: points to start of memory which is used for this struct.
564 * @hwparams: copy of hwparams registers
565 * @root: debugfs root folder pointer
568 struct usb_ctrlrequest *ctrl_req;
569 struct dwc3_trb_hw *ep0_trb;
572 dma_addr_t ctrl_req_addr;
573 dma_addr_t ep0_trb_addr;
574 dma_addr_t setup_buf_addr;
575 dma_addr_t ep0_bounce_addr;
576 struct usb_request ep0_usb_req;
581 struct dwc3_event_buffer *ev_buffs[DWC3_EVENT_BUFFERS_NUM];
582 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
584 struct usb_gadget gadget;
585 struct usb_gadget_driver *gadget_driver;
594 #define DWC3_REVISION_173A 0x5533173a
595 #define DWC3_REVISION_175A 0x5533175a
596 #define DWC3_REVISION_180A 0x5533180a
597 #define DWC3_REVISION_183A 0x5533183a
598 #define DWC3_REVISION_185A 0x5533185a
599 #define DWC3_REVISION_188A 0x5533188a
600 #define DWC3_REVISION_190A 0x5533190a
602 unsigned is_selfpowered:1;
603 unsigned three_stage_setup:1;
604 unsigned ep0_status_pending:1;
605 unsigned ep0_bounced:1;
606 unsigned ep0_expect_in:1;
607 unsigned start_config_issued:1;
609 enum dwc3_ep0_next ep0_next_event;
610 enum dwc3_ep0_state ep0state;
611 enum dwc3_link_state link_state;
612 enum dwc3_device_state dev_state;
617 struct dwc3_hwparams hwparams;
621 /* -------------------------------------------------------------------------- */
623 #define DWC3_TRBSTS_OK 0
624 #define DWC3_TRBSTS_MISSED_ISOC 1
625 #define DWC3_TRBSTS_SETUP_PENDING 2
627 #define DWC3_TRBCTL_NORMAL 1
628 #define DWC3_TRBCTL_CONTROL_SETUP 2
629 #define DWC3_TRBCTL_CONTROL_STATUS2 3
630 #define DWC3_TRBCTL_CONTROL_STATUS3 4
631 #define DWC3_TRBCTL_CONTROL_DATA 5
632 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST 6
633 #define DWC3_TRBCTL_ISOCHRONOUS 7
634 #define DWC3_TRBCTL_LINK_TRB 8
636 /* -------------------------------------------------------------------------- */
638 struct dwc3_event_type {
644 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
645 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
646 #define DWC3_DEPEVT_XFERNOTREADY 0x03
647 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
648 #define DWC3_DEPEVT_STREAMEVT 0x06
649 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
652 * struct dwc3_event_depvt - Device Endpoint Events
653 * @one_bit: indicates this is an endpoint event (not used)
654 * @endpoint_number: number of the endpoint
655 * @endpoint_event: The event we have:
657 * 0x01 - XferComplete
658 * 0x02 - XferInProgress
659 * 0x03 - XferNotReady
660 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
664 * @reserved11_10: Reserved, don't use.
665 * @status: Indicates the status of the event. Refer to databook for
667 * @parameters: Parameters of the current event. Refer to databook for
670 struct dwc3_event_depevt {
672 u32 endpoint_number:5;
673 u32 endpoint_event:4;
676 #define DEPEVT_STATUS_BUSERR (1 << 0)
677 #define DEPEVT_STATUS_SHORT (1 << 1)
678 #define DEPEVT_STATUS_IOC (1 << 2)
679 #define DEPEVT_STATUS_LST (1 << 3)
681 /* Stream event only */
682 #define DEPEVT_STREAMEVT_FOUND 1
683 #define DEPEVT_STREAMEVT_NOTFOUND 2
685 /* Control-only Status */
686 #define DEPEVT_STATUS_CONTROL_SETUP 0
687 #define DEPEVT_STATUS_CONTROL_DATA 1
688 #define DEPEVT_STATUS_CONTROL_STATUS 2
694 * struct dwc3_event_devt - Device Events
695 * @one_bit: indicates this is a non-endpoint event (not used)
696 * @device_event: indicates it's a device event. Should read as 0x00
697 * @type: indicates the type of device event.
710 * 12 - VndrDevTstRcved
711 * @reserved15_12: Reserved, not used
712 * @event_info: Information about this event
713 * @reserved31_24: Reserved, not used
715 struct dwc3_event_devt {
725 * struct dwc3_event_gevt - Other Core Events
726 * @one_bit: indicates this is a non-endpoint event (not used)
727 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
728 * @phy_port_number: self-explanatory
729 * @reserved31_12: Reserved, not used.
731 struct dwc3_event_gevt {
734 u32 phy_port_number:4;
735 u32 reserved31_12:20;
739 * union dwc3_event - representation of Event Buffer contents
740 * @raw: raw 32-bit event
741 * @type: the type of the event
742 * @depevt: Device Endpoint Event
743 * @devt: Device Event
744 * @gevt: Global Event
748 struct dwc3_event_type type;
749 struct dwc3_event_depevt depevt;
750 struct dwc3_event_devt devt;
751 struct dwc3_event_gevt gevt;
755 * DWC3 Features to be used as Driver Data
758 #define DWC3_HAS_PERIPHERAL BIT(0)
759 #define DWC3_HAS_XHCI BIT(1)
760 #define DWC3_HAS_OTG BIT(3)
762 #endif /* __DRIVERS_USB_DWC3_CORE_H */