2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
46 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/delay.h>
50 #include <linux/dma-mapping.h>
53 #include <linux/usb/ch9.h>
54 #include <linux/usb/gadget.h>
62 static char *maximum_speed = "super";
63 module_param(maximum_speed, charp, 0);
64 MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
66 /* -------------------------------------------------------------------------- */
68 #define DWC3_DEVS_POSSIBLE 32
70 static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);
72 int dwc3_get_device_id(void)
77 id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
78 if (id < DWC3_DEVS_POSSIBLE) {
81 old = test_and_set_bit(id, dwc3_devs);
85 pr_err("dwc3: no space for new device\n");
91 EXPORT_SYMBOL_GPL(dwc3_get_device_id);
93 void dwc3_put_device_id(int id)
100 ret = test_bit(id, dwc3_devs);
101 WARN(!ret, "dwc3: ID %d not in use\n", id);
102 clear_bit(id, dwc3_devs);
104 EXPORT_SYMBOL_GPL(dwc3_put_device_id);
106 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
110 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
111 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
112 reg |= DWC3_GCTL_PRTCAPDIR(mode);
113 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
117 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
118 * @dwc: pointer to our context structure
120 static void dwc3_core_soft_reset(struct dwc3 *dwc)
124 /* Before Resetting PHY, put Core in Reset */
125 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
126 reg |= DWC3_GCTL_CORESOFTRESET;
127 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
129 /* Assert USB3 PHY reset */
130 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
131 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
132 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
134 /* Assert USB2 PHY reset */
135 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
136 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
137 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
141 /* Clear USB3 PHY reset */
142 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
143 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
144 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
146 /* Clear USB2 PHY reset */
147 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
148 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
149 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
151 /* After PHYs are stable we can take Core out of reset state */
152 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
153 reg &= ~DWC3_GCTL_CORESOFTRESET;
154 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
158 * dwc3_free_one_event_buffer - Frees one event buffer
159 * @dwc: Pointer to our controller context structure
160 * @evt: Pointer to event buffer to be freed
162 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
163 struct dwc3_event_buffer *evt)
165 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
170 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
171 * @dwc: Pointer to our controller context structure
172 * @length: size of the event buffer
174 * Returns a pointer to the allocated event buffer structure on success
175 * otherwise ERR_PTR(errno).
177 static struct dwc3_event_buffer *__devinit
178 dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
180 struct dwc3_event_buffer *evt;
182 evt = kzalloc(sizeof(*evt), GFP_KERNEL);
184 return ERR_PTR(-ENOMEM);
187 evt->length = length;
188 evt->buf = dma_alloc_coherent(dwc->dev, length,
189 &evt->dma, GFP_KERNEL);
192 return ERR_PTR(-ENOMEM);
199 * dwc3_free_event_buffers - frees all allocated event buffers
200 * @dwc: Pointer to our controller context structure
202 static void dwc3_free_event_buffers(struct dwc3 *dwc)
204 struct dwc3_event_buffer *evt;
207 for (i = 0; i < dwc->num_event_buffers; i++) {
208 evt = dwc->ev_buffs[i];
210 dwc3_free_one_event_buffer(dwc, evt);
213 kfree(dwc->ev_buffs);
217 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
218 * @dwc: pointer to our controller context structure
219 * @length: size of event buffer
221 * Returns 0 on success otherwise negative errno. In the error case, dwc
222 * may contain some buffers allocated but not all which were requested.
224 static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
229 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
230 dwc->num_event_buffers = num;
232 dwc->ev_buffs = kzalloc(sizeof(*dwc->ev_buffs) * num, GFP_KERNEL);
233 if (!dwc->ev_buffs) {
234 dev_err(dwc->dev, "can't allocate event buffers array\n");
238 for (i = 0; i < num; i++) {
239 struct dwc3_event_buffer *evt;
241 evt = dwc3_alloc_one_event_buffer(dwc, length);
243 dev_err(dwc->dev, "can't allocate event buffer\n");
246 dwc->ev_buffs[i] = evt;
253 * dwc3_event_buffers_setup - setup our allocated event buffers
254 * @dwc: pointer to our controller context structure
256 * Returns 0 on success otherwise negative errno.
258 static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
260 struct dwc3_event_buffer *evt;
263 for (n = 0; n < dwc->num_event_buffers; n++) {
264 evt = dwc->ev_buffs[n];
265 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
266 evt->buf, (unsigned long long) evt->dma,
269 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
270 lower_32_bits(evt->dma));
271 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
272 upper_32_bits(evt->dma));
273 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
274 evt->length & 0xffff);
275 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
281 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
283 struct dwc3_event_buffer *evt;
286 for (n = 0; n < dwc->num_event_buffers; n++) {
287 evt = dwc->ev_buffs[n];
288 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
289 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
290 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
291 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
295 static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
297 struct dwc3_hwparams *parms = &dwc->hwparams;
299 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
300 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
301 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
302 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
303 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
304 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
305 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
306 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
307 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
311 * dwc3_core_init - Low-level initialization of DWC3 Core
312 * @dwc: Pointer to our controller context structure
314 * Returns 0 on success otherwise negative errno.
316 static int __devinit dwc3_core_init(struct dwc3 *dwc)
318 unsigned long timeout;
322 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
323 /* This should read as U3 followed by revision number */
324 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
325 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
331 dwc3_core_soft_reset(dwc);
333 /* issue device SoftReset too */
334 timeout = jiffies + msecs_to_jiffies(500);
335 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
337 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
338 if (!(reg & DWC3_DCTL_CSFTRST))
341 if (time_after(jiffies, timeout)) {
342 dev_err(dwc->dev, "Reset Timed Out\n");
350 dwc3_cache_hwparams(dwc);
352 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
353 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
354 reg &= ~DWC3_GCTL_DISSCRAMBLE;
356 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
357 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
358 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
361 dev_dbg(dwc->dev, "No power optimization available\n");
365 * WORKAROUND: DWC3 revisions <1.90a have a bug
366 * where the device can fail to connect at SuperSpeed
367 * and falls back to high-speed mode which causes
368 * the device to enter a Connect/Disconnect loop
370 if (dwc->revision < DWC3_REVISION_190A)
371 reg |= DWC3_GCTL_U2RSTECN;
373 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
375 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
377 dev_err(dwc->dev, "failed to allocate event buffers\n");
382 ret = dwc3_event_buffers_setup(dwc);
384 dev_err(dwc->dev, "failed to setup event buffers\n");
391 dwc3_free_event_buffers(dwc);
397 static void dwc3_core_exit(struct dwc3 *dwc)
399 dwc3_event_buffers_cleanup(dwc);
400 dwc3_free_event_buffers(dwc);
403 #define DWC3_ALIGN_MASK (16 - 1)
405 static int __devinit dwc3_probe(struct platform_device *pdev)
407 struct device_node *node = pdev->dev.of_node;
408 struct resource *res;
410 struct device *dev = &pdev->dev;
419 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
421 dev_err(dev, "not enough memory\n");
424 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
427 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
429 dev_err(dev, "missing IRQ\n");
432 dwc->xhci_resources[1] = *res;
434 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
436 dev_err(dev, "missing memory resource\n");
439 dwc->xhci_resources[0] = *res;
440 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
444 * Request memory region but exclude xHCI regs,
445 * since it will be requested by the xhci-plat driver.
447 res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
448 resource_size(res) - DWC3_GLOBALS_REGS_START,
451 dev_err(dev, "can't request mem region\n");
455 regs = devm_ioremap(dev, res->start, resource_size(res));
457 dev_err(dev, "ioremap failed\n");
461 spin_lock_init(&dwc->lock);
462 platform_set_drvdata(pdev, dwc);
465 dwc->regs_size = resource_size(res);
468 if (!strncmp("super", maximum_speed, 5))
469 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
470 else if (!strncmp("high", maximum_speed, 4))
471 dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
472 else if (!strncmp("full", maximum_speed, 4))
473 dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
474 else if (!strncmp("low", maximum_speed, 3))
475 dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
477 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
479 if (of_get_property(node, "tx-fifo-resize", NULL))
480 dwc->needs_fifo_resize = true;
482 pm_runtime_enable(dev);
483 pm_runtime_get_sync(dev);
484 pm_runtime_forbid(dev);
486 ret = dwc3_core_init(dwc);
488 dev_err(dev, "failed to initialize core\n");
492 mode = DWC3_MODE(dwc->hwparams.hwparams0);
495 case DWC3_MODE_DEVICE:
496 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
497 ret = dwc3_gadget_init(dwc);
499 dev_err(dev, "failed to initialize gadget\n");
504 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
505 ret = dwc3_host_init(dwc);
507 dev_err(dev, "failed to initialize host\n");
512 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
513 ret = dwc3_host_init(dwc);
515 dev_err(dev, "failed to initialize host\n");
519 ret = dwc3_gadget_init(dwc);
521 dev_err(dev, "failed to initialize gadget\n");
526 dev_err(dev, "Unsupported mode of operation %d\n", mode);
531 ret = dwc3_debugfs_init(dwc);
533 dev_err(dev, "failed to initialize debugfs\n");
537 pm_runtime_allow(dev);
543 case DWC3_MODE_DEVICE:
544 dwc3_gadget_exit(dwc);
551 dwc3_gadget_exit(dwc);
564 static int __devexit dwc3_remove(struct platform_device *pdev)
566 struct dwc3 *dwc = platform_get_drvdata(pdev);
567 struct resource *res;
569 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
571 pm_runtime_put(&pdev->dev);
572 pm_runtime_disable(&pdev->dev);
574 dwc3_debugfs_exit(dwc);
577 case DWC3_MODE_DEVICE:
578 dwc3_gadget_exit(dwc);
585 dwc3_gadget_exit(dwc);
597 static struct platform_driver dwc3_driver = {
599 .remove = __devexit_p(dwc3_remove),
605 module_platform_driver(dwc3_driver);
607 MODULE_ALIAS("platform:dwc3");
608 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
609 MODULE_LICENSE("Dual BSD/GPL");
610 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");