drivers/tty/serial/sunzilog.c

   1 /* sunzilog.c: Zilog serial driver for Sparc systems.
   2  *
   3  * Driver for Zilog serial chips found on Sun workstations and
   4  * servers.  This driver could actually be made more generic.
   5  *
   6  * This is based on the old drivers/sbus/char/zs.c code.  A lot
   7  * of code has been simply moved over directly from there but
   8  * much has been rewritten.  Credits therefore go out to Eddie
   9  * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
  10  * work there.
  11  *
  12  * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/errno.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/tty_flip.h>
  21 #include <linux/major.h>
  22 #include <linux/string.h>
  23 #include <linux/ptrace.h>
  24 #include <linux/ioport.h>
  25 #include <linux/slab.h>
  26 #include <linux/circ_buf.h>
  27 #include <linux/serial.h>
  28 #include <linux/sysrq.h>
  29 #include <linux/console.h>
  30 #include <linux/spinlock.h>
  31 #ifdef CONFIG_SERIO
  32 #include <linux/serio.h>
  33 #endif
  34 #include <linux/init.h>
  35 #include <linux/of_device.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/prom.h>
  40 #include <asm/setup.h>
  41
  42 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  43 #define SUPPORT_SYSRQ
  44 #endif
  45
  46 #include <linux/serial_core.h>
  47 #include <linux/sunserialcore.h>
  48
  49 #include "sunzilog.h"
  50
  51 /* On 32-bit sparcs we need to delay after register accesses
  52  * to accommodate sun4 systems, but we do not need to flush writes.
  53  * On 64-bit sparc we only need to flush single writes to ensure
  54  * completion.
  55  */
  56 #ifndef CONFIG_SPARC64
  57 #define ZSDELAY()               udelay(5)
  58 #define ZSDELAY_LONG()          udelay(20)
  59 #define ZS_WSYNC(channel)       do { } while (0)
  60 #else
  61 #define ZSDELAY()
  62 #define ZSDELAY_LONG()
  63 #define ZS_WSYNC(__channel) \
  64         readb(&((__channel)->control))
  65 #endif
  66
  67 #define ZS_CLOCK                4915200 /* Zilog input clock rate. */
  68 #define ZS_CLOCK_DIVISOR        16      /* Divisor this driver uses. */
  69
  70 /*
  71  * We wrap our port structure around the generic uart_port.
  72  */
  73 struct uart_sunzilog_port {
  74         struct uart_port                port;
  75
  76         /* IRQ servicing chain.  */
  77         struct uart_sunzilog_port       *next;
  78
  79         /* Current values of Zilog write registers.  */
  80         unsigned char                   curregs[NUM_ZSREGS];
  81
  82         unsigned int                    flags;
  83 #define SUNZILOG_FLAG_CONS_KEYB         0x00000001
  84 #define SUNZILOG_FLAG_CONS_MOUSE        0x00000002
  85 #define SUNZILOG_FLAG_IS_CONS           0x00000004
  86 #define SUNZILOG_FLAG_IS_KGDB           0x00000008
  87 #define SUNZILOG_FLAG_MODEM_STATUS      0x00000010
  88 #define SUNZILOG_FLAG_IS_CHANNEL_A      0x00000020
  89 #define SUNZILOG_FLAG_REGS_HELD         0x00000040
  90 #define SUNZILOG_FLAG_TX_STOPPED        0x00000080
  91 #define SUNZILOG_FLAG_TX_ACTIVE         0x00000100
  92 #define SUNZILOG_FLAG_ESCC              0x00000200
  93 #define SUNZILOG_FLAG_ISR_HANDLER       0x00000400
  94
  95         unsigned int cflag;
  96
  97         unsigned char                   parity_mask;
  98         unsigned char                   prev_status;
  99
 100 #ifdef CONFIG_SERIO
 101         struct serio                    serio;
 102         int                             serio_open;
 103 #endif
 104 };
 105
 106 static void sunzilog_putchar(struct uart_port *port, int ch);
 107
 108 #define ZILOG_CHANNEL_FROM_PORT(PORT)   ((struct zilog_channel __iomem *)((PORT)->membase))
 109 #define UART_ZILOG(PORT)                ((struct uart_sunzilog_port *)(PORT))
 110
 111 #define ZS_IS_KEYB(UP)  ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
 112 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
 113 #define ZS_IS_CONS(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
 114 #define ZS_IS_KGDB(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
 115 #define ZS_WANTS_MODEM_STATUS(UP)       ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
 116 #define ZS_IS_CHANNEL_A(UP)     ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
 117 #define ZS_REGS_HELD(UP)        ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
 118 #define ZS_TX_STOPPED(UP)       ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
 119 #define ZS_TX_ACTIVE(UP)        ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
 120
 121 /* Reading and writing Zilog8530 registers.  The delays are to make this
 122  * driver work on the Sun4 which needs a settling delay after each chip
 123  * register access, other machines handle this in hardware via auxiliary
 124  * flip-flops which implement the settle time we do in software.
 125  *
 126  * The port lock must be held and local IRQs must be disabled
 127  * when {read,write}_zsreg is invoked.
 128  */
 129 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
 130                                 unsigned char reg)
 131 {
 132         unsigned char retval;
 133
 134         writeb(reg, &channel->control);
 135         ZSDELAY();
 136         retval = readb(&channel->control);
 137         ZSDELAY();
 138
 139         return retval;
 140 }
 141
 142 static void write_zsreg(struct zilog_channel __iomem *channel,
 143                         unsigned char reg, unsigned char value)
 144 {
 145         writeb(reg, &channel->control);
 146         ZSDELAY();
 147         writeb(value, &channel->control);
 148         ZSDELAY();
 149 }
 150
 151 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
 152 {
 153         int i;
 154
 155         for (i = 0; i < 32; i++) {
 156                 unsigned char regval;
 157
 158                 regval = readb(&channel->control);
 159                 ZSDELAY();
 160                 if (regval & Rx_CH_AV)
 161                         break;
 162
 163                 regval = read_zsreg(channel, R1);
 164                 readb(&channel->data);
 165                 ZSDELAY();
 166
 167                 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
 168                         writeb(ERR_RES, &channel->control);
 169                         ZSDELAY();
 170                         ZS_WSYNC(channel);
 171                 }
 172         }
 173 }
 174
 175 /* This function must only be called when the TX is not busy.  The UART
 176  * port lock must be held and local interrupts disabled.
 177  */
 178 static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
 179 {
 180         int i;
 181         int escc;
 182         unsigned char r15;
 183
 184         /* Let pending transmits finish.  */
 185         for (i = 0; i < 1000; i++) {
 186                 unsigned char stat = read_zsreg(channel, R1);
 187                 if (stat & ALL_SNT)
 188                         break;
 189                 udelay(100);
 190         }
 191
 192         writeb(ERR_RES, &channel->control);
 193         ZSDELAY();
 194         ZS_WSYNC(channel);
 195
 196         sunzilog_clear_fifo(channel);
 197
 198         /* Disable all interrupts.  */
 199         write_zsreg(channel, R1,
 200                     regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
 201
 202         /* Set parity, sync config, stop bits, and clock divisor.  */
 203         write_zsreg(channel, R4, regs[R4]);
 204
 205         /* Set misc. TX/RX control bits.  */
 206         write_zsreg(channel, R10, regs[R10]);
 207
 208         /* Set TX/RX controls sans the enable bits.  */
 209         write_zsreg(channel, R3, regs[R3] & ~RxENAB);
 210         write_zsreg(channel, R5, regs[R5] & ~TxENAB);
 211
 212         /* Synchronous mode config.  */
 213         write_zsreg(channel, R6, regs[R6]);
 214         write_zsreg(channel, R7, regs[R7]);
 215
 216         /* Don't mess with the interrupt vector (R2, unused by us) and
 217          * master interrupt control (R9).  We make sure this is setup
 218          * properly at probe time then never touch it again.
 219          */
 220
 221         /* Disable baud generator.  */
 222         write_zsreg(channel, R14, regs[R14] & ~BRENAB);
 223
 224         /* Clock mode control.  */
 225         write_zsreg(channel, R11, regs[R11]);
 226
 227         /* Lower and upper byte of baud rate generator divisor.  */
 228         write_zsreg(channel, R12, regs[R12]);
 229         write_zsreg(channel, R13, regs[R13]);
 230
 231         /* Now rewrite R14, with BRENAB (if set).  */
 232         write_zsreg(channel, R14, regs[R14]);
 233
 234         /* External status interrupt control.  */
 235         write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
 236
 237         /* ESCC Extension Register */
 238         r15 = read_zsreg(channel, R15);
 239         if (r15 & 0x01) {
 240                 write_zsreg(channel, R7,  regs[R7p]);
 241
 242                 /* External status interrupt and FIFO control.  */
 243                 write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
 244                 escc = 1;
 245         } else {
 246                  /* Clear FIFO bit case it is an issue */
 247                 regs[R15] &= ~FIFOEN;
 248                 escc = 0;
 249         }
 250
 251         /* Reset external status interrupts.  */
 252         write_zsreg(channel, R0, RES_EXT_INT); /* First Latch  */
 253         write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
 254
 255         /* Rewrite R3/R5, this time without enables masked.  */
 256         write_zsreg(channel, R3, regs[R3]);
 257         write_zsreg(channel, R5, regs[R5]);
 258
 259         /* Rewrite R1, this time without IRQ enabled masked.  */
 260         write_zsreg(channel, R1, regs[R1]);
 261
 262         return escc;
 263 }
 264
 265 /* Reprogram the Zilog channel HW registers with the copies found in the
 266  * software state struct.  If the transmitter is busy, we defer this update
 267  * until the next TX complete interrupt.  Else, we do it right now.
 268  *
 269  * The UART port lock must be held and local interrupts disabled.
 270  */
 271 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
 272                                        struct zilog_channel __iomem *channel)
 273 {
 274         if (!ZS_REGS_HELD(up)) {
 275                 if (ZS_TX_ACTIVE(up)) {
 276                         up->flags |= SUNZILOG_FLAG_REGS_HELD;
 277                 } else {
 278                         __load_zsregs(channel, up->curregs);
 279                 }
 280         }
 281 }
 282
 283 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
 284 {
 285         unsigned int cur_cflag = up->cflag;
 286         int brg, new_baud;
 287
 288         up->cflag &= ~CBAUD;
 289         up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
 290
 291         brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
 292         up->curregs[R12] = (brg & 0xff);
 293         up->curregs[R13] = (brg >> 8) & 0xff;
 294         sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
 295 }
 296
 297 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
 298                                          unsigned char ch, int is_break)
 299 {
 300         if (ZS_IS_KEYB(up)) {
 301                 /* Stop-A is handled by drivers/char/keyboard.c now. */
 302 #ifdef CONFIG_SERIO
 303                 if (up->serio_open)
 304                         serio_interrupt(&up->serio, ch, 0);
 305 #endif
 306         } else if (ZS_IS_MOUSE(up)) {
 307                 int ret = suncore_mouse_baud_detection(ch, is_break);
 308
 309                 switch (ret) {
 310                 case 2:
 311                         sunzilog_change_mouse_baud(up);
 312                         /* fallthru */
 313                 case 1:
 314                         break;
 315
 316                 case 0:
 317 #ifdef CONFIG_SERIO
 318                         if (up->serio_open)
 319                                 serio_interrupt(&up->serio, ch, 0);
 320 #endif
 321                         break;
 322                 };
 323         }
 324 }
 325
 326 static struct tty_struct *
 327 sunzilog_receive_chars(struct uart_sunzilog_port *up,
 328                        struct zilog_channel __iomem *channel)
 329 {
 330         struct tty_struct *tty;
 331         unsigned char ch, r1, flag;
 332
 333         tty = NULL;
 334         if (up->port.state != NULL &&           /* Unopened serial console */
 335             up->port.state->port.tty != NULL)   /* Keyboard || mouse */
 336                 tty = up->port.state->port.tty;
 337
 338         for (;;) {
 339
 340                 r1 = read_zsreg(channel, R1);
 341                 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
 342                         writeb(ERR_RES, &channel->control);
 343                         ZSDELAY();
 344                         ZS_WSYNC(channel);
 345                 }
 346
 347                 ch = readb(&channel->control);
 348                 ZSDELAY();
 349
 350                 /* This funny hack depends upon BRK_ABRT not interfering
 351                  * with the other bits we care about in R1.
 352                  */
 353                 if (ch & BRK_ABRT)
 354                         r1 |= BRK_ABRT;
 355
 356                 if (!(ch & Rx_CH_AV))
 357                         break;
 358
 359                 ch = readb(&channel->data);
 360                 ZSDELAY();
 361
 362                 ch &= up->parity_mask;
 363
 364                 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
 365                         sunzilog_kbdms_receive_chars(up, ch, 0);
 366                         continue;
 367                 }
 368
 369                 if (tty == NULL) {
 370                         uart_handle_sysrq_char(&up->port, ch);
 371                         continue;
 372                 }
 373
 374                 /* A real serial line, record the character and status.  */
 375                 flag = TTY_NORMAL;
 376                 up->port.icount.rx++;
 377                 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
 378                         if (r1 & BRK_ABRT) {
 379                                 r1 &= ~(PAR_ERR | CRC_ERR);
 380                                 up->port.icount.brk++;
 381                                 if (uart_handle_break(&up->port))
 382                                         continue;
 383                         }
 384                         else if (r1 & PAR_ERR)
 385                                 up->port.icount.parity++;
 386                         else if (r1 & CRC_ERR)
 387                                 up->port.icount.frame++;
 388                         if (r1 & Rx_OVR)
 389                                 up->port.icount.overrun++;
 390                         r1 &= up->port.read_status_mask;
 391                         if (r1 & BRK_ABRT)
 392                                 flag = TTY_BREAK;
 393                         else if (r1 & PAR_ERR)
 394                                 flag = TTY_PARITY;
 395                         else if (r1 & CRC_ERR)
 396                                 flag = TTY_FRAME;
 397                 }
 398                 if (uart_handle_sysrq_char(&up->port, ch))
 399                         continue;
 400
 401                 if (up->port.ignore_status_mask == 0xff ||
 402                     (r1 & up->port.ignore_status_mask) == 0) {
 403                         tty_insert_flip_char(tty, ch, flag);
 404                 }
 405                 if (r1 & Rx_OVR)
 406                         tty_insert_flip_char(tty, 0, TTY_OVERRUN);
 407         }
 408
 409         return tty;
 410 }
 411
 412 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
 413                                    struct zilog_channel __iomem *channel)
 414 {
 415         unsigned char status;
 416
 417         status = readb(&channel->control);
 418         ZSDELAY();
 419
 420         writeb(RES_EXT_INT, &channel->control);
 421         ZSDELAY();
 422         ZS_WSYNC(channel);
 423
 424         if (status & BRK_ABRT) {
 425                 if (ZS_IS_MOUSE(up))
 426                         sunzilog_kbdms_receive_chars(up, 0, 1);
 427                 if (ZS_IS_CONS(up)) {
 428                         /* Wait for BREAK to deassert to avoid potentially
 429                          * confusing the PROM.
 430                          */
 431                         while (1) {
 432                                 status = readb(&channel->control);
 433                                 ZSDELAY();
 434                                 if (!(status & BRK_ABRT))
 435                                         break;
 436                         }
 437                         sun_do_break();
 438                         return;
 439                 }
 440         }
 441
 442         if (ZS_WANTS_MODEM_STATUS(up)) {
 443                 if (status & SYNC)
 444                         up->port.icount.dsr++;
 445
 446                 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
 447                  * But it does not tell us which bit has changed, we have to keep
 448                  * track of this ourselves.
 449                  */
 450                 if ((status ^ up->prev_status) ^ DCD)
 451                         uart_handle_dcd_change(&up->port,
 452                                                (status & DCD));
 453                 if ((status ^ up->prev_status) ^ CTS)
 454                         uart_handle_cts_change(&up->port,
 455                                                (status & CTS));
 456
 457                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 458         }
 459
 460         up->prev_status = status;
 461 }
 462
 463 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
 464                                     struct zilog_channel __iomem *channel)
 465 {
 466         struct circ_buf *xmit;
 467
 468         if (ZS_IS_CONS(up)) {
 469                 unsigned char status = readb(&channel->control);
 470                 ZSDELAY();
 471
 472                 /* TX still busy?  Just wait for the next TX done interrupt.
 473                  *
 474                  * It can occur because of how we do serial console writes.  It would
 475                  * be nice to transmit console writes just like we normally would for
 476                  * a TTY line. (ie. buffered and TX interrupt driven).  That is not
 477                  * easy because console writes cannot sleep.  One solution might be
 478                  * to poll on enough port->xmit space becoming free.  -DaveM
 479                  */
 480                 if (!(status & Tx_BUF_EMP))
 481                         return;
 482         }
 483
 484         up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
 485
 486         if (ZS_REGS_HELD(up)) {
 487                 __load_zsregs(channel, up->curregs);
 488                 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
 489         }
 490
 491         if (ZS_TX_STOPPED(up)) {
 492                 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
 493                 goto ack_tx_int;
 494         }
 495
 496         if (up->port.x_char) {
 497                 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 498                 writeb(up->port.x_char, &channel->data);
 499                 ZSDELAY();
 500                 ZS_WSYNC(channel);
 501
 502                 up->port.icount.tx++;
 503                 up->port.x_char = 0;
 504                 return;
 505         }
 506
 507         if (up->port.state == NULL)
 508                 goto ack_tx_int;
 509         xmit = &up->port.state->xmit;
 510         if (uart_circ_empty(xmit))
 511                 goto ack_tx_int;
 512
 513         if (uart_tx_stopped(&up->port))
 514                 goto ack_tx_int;
 515
 516         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 517         writeb(xmit->buf[xmit->tail], &channel->data);
 518         ZSDELAY();
 519         ZS_WSYNC(channel);
 520
 521         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 522         up->port.icount.tx++;
 523
 524         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 525                 uart_write_wakeup(&up->port);
 526
 527         return;
 528
 529 ack_tx_int:
 530         writeb(RES_Tx_P, &channel->control);
 531         ZSDELAY();
 532         ZS_WSYNC(channel);
 533 }
 534
 535 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
 536 {
 537         struct uart_sunzilog_port *up = dev_id;
 538
 539         while (up) {
 540                 struct zilog_channel __iomem *channel
 541                         = ZILOG_CHANNEL_FROM_PORT(&up->port);
 542                 struct tty_struct *tty;
 543                 unsigned char r3;
 544
 545                 spin_lock(&up->port.lock);
 546                 r3 = read_zsreg(channel, R3);
 547
 548                 /* Channel A */
 549                 tty = NULL;
 550                 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
 551                         writeb(RES_H_IUS, &channel->control);
 552                         ZSDELAY();
 553                         ZS_WSYNC(channel);
 554
 555                         if (r3 & CHARxIP)
 556                                 tty = sunzilog_receive_chars(up, channel);
 557                         if (r3 & CHAEXT)
 558                                 sunzilog_status_handle(up, channel);
 559                         if (r3 & CHATxIP)
 560                                 sunzilog_transmit_chars(up, channel);
 561                 }
 562                 spin_unlock(&up->port.lock);
 563
 564                 if (tty)
 565                         tty_flip_buffer_push(tty);
 566
 567                 /* Channel B */
 568                 up = up->next;
 569                 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 570
 571                 spin_lock(&up->port.lock);
 572                 tty = NULL;
 573                 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
 574                         writeb(RES_H_IUS, &channel->control);
 575                         ZSDELAY();
 576                         ZS_WSYNC(channel);
 577
 578                         if (r3 & CHBRxIP)
 579                                 tty = sunzilog_receive_chars(up, channel);
 580                         if (r3 & CHBEXT)
 581                                 sunzilog_status_handle(up, channel);
 582                         if (r3 & CHBTxIP)
 583                                 sunzilog_transmit_chars(up, channel);
 584                 }
 585                 spin_unlock(&up->port.lock);
 586
 587                 if (tty)
 588                         tty_flip_buffer_push(tty);
 589
 590                 up = up->next;
 591         }
 592
 593         return IRQ_HANDLED;
 594 }
 595
 596 /* A convenient way to quickly get R0 status.  The caller must _not_ hold the
 597  * port lock, it is acquired here.
 598  */
 599 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
 600 {
 601         struct zilog_channel __iomem *channel;
 602         unsigned char status;
 603
 604         channel = ZILOG_CHANNEL_FROM_PORT(port);
 605         status = readb(&channel->control);
 606         ZSDELAY();
 607
 608         return status;
 609 }
 610
 611 /* The port lock is not held.  */
 612 static unsigned int sunzilog_tx_empty(struct uart_port *port)
 613 {
 614         unsigned long flags;
 615         unsigned char status;
 616         unsigned int ret;
 617
 618         spin_lock_irqsave(&port->lock, flags);
 619
 620         status = sunzilog_read_channel_status(port);
 621
 622         spin_unlock_irqrestore(&port->lock, flags);
 623
 624         if (status & Tx_BUF_EMP)
 625                 ret = TIOCSER_TEMT;
 626         else
 627                 ret = 0;
 628
 629         return ret;
 630 }
 631
 632 /* The port lock is held and interrupts are disabled.  */
 633 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
 634 {
 635         unsigned char status;
 636         unsigned int ret;
 637
 638         status = sunzilog_read_channel_status(port);
 639
 640         ret = 0;
 641         if (status & DCD)
 642                 ret |= TIOCM_CAR;
 643         if (status & SYNC)
 644                 ret |= TIOCM_DSR;
 645         if (status & CTS)
 646                 ret |= TIOCM_CTS;
 647
 648         return ret;
 649 }
 650
 651 /* The port lock is held and interrupts are disabled.  */
 652 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
 653 {
 654         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 655         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 656         unsigned char set_bits, clear_bits;
 657
 658         set_bits = clear_bits = 0;
 659
 660         if (mctrl & TIOCM_RTS)
 661                 set_bits |= RTS;
 662         else
 663                 clear_bits |= RTS;
 664         if (mctrl & TIOCM_DTR)
 665                 set_bits |= DTR;
 666         else
 667                 clear_bits |= DTR;
 668
 669         /* NOTE: Not subject to 'transmitter active' rule.  */
 670         up->curregs[R5] |= set_bits;
 671         up->curregs[R5] &= ~clear_bits;
 672         write_zsreg(channel, R5, up->curregs[R5]);
 673 }
 674
 675 /* The port lock is held and interrupts are disabled.  */
 676 static void sunzilog_stop_tx(struct uart_port *port)
 677 {
 678         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 679
 680         up->flags |= SUNZILOG_FLAG_TX_STOPPED;
 681 }
 682
 683 /* The port lock is held and interrupts are disabled.  */
 684 static void sunzilog_start_tx(struct uart_port *port)
 685 {
 686         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 687         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 688         unsigned char status;
 689
 690         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 691         up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
 692
 693         status = readb(&channel->control);
 694         ZSDELAY();
 695
 696         /* TX busy?  Just wait for the TX done interrupt.  */
 697         if (!(status & Tx_BUF_EMP))
 698                 return;
 699
 700         /* Send the first character to jump-start the TX done
 701          * IRQ sending engine.
 702          */
 703         if (port->x_char) {
 704                 writeb(port->x_char, &channel->data);
 705                 ZSDELAY();
 706                 ZS_WSYNC(channel);
 707
 708                 port->icount.tx++;
 709                 port->x_char = 0;
 710         } else {
 711                 struct circ_buf *xmit = &port->state->xmit;
 712
 713                 writeb(xmit->buf[xmit->tail], &channel->data);
 714                 ZSDELAY();
 715                 ZS_WSYNC(channel);
 716
 717                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 718                 port->icount.tx++;
 719
 720                 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 721                         uart_write_wakeup(&up->port);
 722         }
 723 }
 724
 725 /* The port lock is held.  */
 726 static void sunzilog_stop_rx(struct uart_port *port)
 727 {
 728         struct uart_sunzilog_port *up = UART_ZILOG(port);
 729         struct zilog_channel __iomem *channel;
 730
 731         if (ZS_IS_CONS(up))
 732                 return;
 733
 734         channel = ZILOG_CHANNEL_FROM_PORT(port);
 735
 736         /* Disable all RX interrupts.  */
 737         up->curregs[R1] &= ~RxINT_MASK;
 738         sunzilog_maybe_update_regs(up, channel);
 739 }
 740
 741 /* The port lock is held.  */
 742 static void sunzilog_enable_ms(struct uart_port *port)
 743 {
 744         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 745         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 746         unsigned char new_reg;
 747
 748         new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
 749         if (new_reg != up->curregs[R15]) {
 750                 up->curregs[R15] = new_reg;
 751
 752                 /* NOTE: Not subject to 'transmitter active' rule.  */
 753                 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
 754         }
 755 }
 756
 757 /* The port lock is not held.  */
 758 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
 759 {
 760         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 761         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 762         unsigned char set_bits, clear_bits, new_reg;
 763         unsigned long flags;
 764
 765         set_bits = clear_bits = 0;
 766
 767         if (break_state)
 768                 set_bits |= SND_BRK;
 769         else
 770                 clear_bits |= SND_BRK;
 771
 772         spin_lock_irqsave(&port->lock, flags);
 773
 774         new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
 775         if (new_reg != up->curregs[R5]) {
 776                 up->curregs[R5] = new_reg;
 777
 778                 /* NOTE: Not subject to 'transmitter active' rule.  */
 779                 write_zsreg(channel, R5, up->curregs[R5]);
 780         }
 781
 782         spin_unlock_irqrestore(&port->lock, flags);
 783 }
 784
 785 static void __sunzilog_startup(struct uart_sunzilog_port *up)
 786 {
 787         struct zilog_channel __iomem *channel;
 788
 789         channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 790         up->prev_status = readb(&channel->control);
 791
 792         /* Enable receiver and transmitter.  */
 793         up->curregs[R3] |= RxENAB;
 794         up->curregs[R5] |= TxENAB;
 795
 796         up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
 797         sunzilog_maybe_update_regs(up, channel);
 798 }
 799
 800 static int sunzilog_startup(struct uart_port *port)
 801 {
 802         struct uart_sunzilog_port *up = UART_ZILOG(port);
 803         unsigned long flags;
 804
 805         if (ZS_IS_CONS(up))
 806                 return 0;
 807
 808         spin_lock_irqsave(&port->lock, flags);
 809         __sunzilog_startup(up);
 810         spin_unlock_irqrestore(&port->lock, flags);
 811         return 0;
 812 }
 813
 814 /*
 815  * The test for ZS_IS_CONS is explained by the following e-mail:
 816  *****
 817  * From: Russell King <rmk@arm.linux.org.uk>
 818  * Date: Sun, 8 Dec 2002 10:18:38 +0000
 819  *
 820  * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
 821  * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
 822  * > and I noticed that something is not right with reference
 823  * > counting in this case. It seems that when the console
 824  * > is open by kernel initially, this is not accounted
 825  * > as an open, and uart_startup is not called.
 826  *
 827  * That is correct.  We are unable to call uart_startup when the serial
 828  * console is initialised because it may need to allocate memory (as
 829  * request_irq does) and the memory allocators may not have been
 830  * initialised.
 831  *
 832  * 1. initialise the port into a state where it can send characters in the
 833  *    console write method.
 834  *
 835  * 2. don't do the actual hardware shutdown in your shutdown() method (but
 836  *    do the normal software shutdown - ie, free irqs etc)
 837  *****
 838  */
 839 static void sunzilog_shutdown(struct uart_port *port)
 840 {
 841         struct uart_sunzilog_port *up = UART_ZILOG(port);
 842         struct zilog_channel __iomem *channel;
 843         unsigned long flags;
 844
 845         if (ZS_IS_CONS(up))
 846                 return;
 847
 848         spin_lock_irqsave(&port->lock, flags);
 849
 850         channel = ZILOG_CHANNEL_FROM_PORT(port);
 851
 852         /* Disable receiver and transmitter.  */
 853         up->curregs[R3] &= ~RxENAB;
 854         up->curregs[R5] &= ~TxENAB;
 855
 856         /* Disable all interrupts and BRK assertion.  */
 857         up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
 858         up->curregs[R5] &= ~SND_BRK;
 859         sunzilog_maybe_update_regs(up, channel);
 860
 861         spin_unlock_irqrestore(&port->lock, flags);
 862 }
 863
 864 /* Shared by TTY driver and serial console setup.  The port lock is held
 865  * and local interrupts are disabled.
 866  */
 867 static void
 868 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
 869                        unsigned int iflag, int brg)
 870 {
 871
 872         up->curregs[R10] = NRZ;
 873         up->curregs[R11] = TCBR | RCBR;
 874
 875         /* Program BAUD and clock source. */
 876         up->curregs[R4] &= ~XCLK_MASK;
 877         up->curregs[R4] |= X16CLK;
 878         up->curregs[R12] = brg & 0xff;
 879         up->curregs[R13] = (brg >> 8) & 0xff;
 880         up->curregs[R14] = BRSRC | BRENAB;
 881
 882         /* Character size, stop bits, and parity. */
 883         up->curregs[R3] &= ~RxN_MASK;
 884         up->curregs[R5] &= ~TxN_MASK;
 885         switch (cflag & CSIZE) {
 886         case CS5:
 887                 up->curregs[R3] |= Rx5;
 888                 up->curregs[R5] |= Tx5;
 889                 up->parity_mask = 0x1f;
 890                 break;
 891         case CS6:
 892                 up->curregs[R3] |= Rx6;
 893                 up->curregs[R5] |= Tx6;
 894                 up->parity_mask = 0x3f;
 895                 break;
 896         case CS7:
 897                 up->curregs[R3] |= Rx7;
 898                 up->curregs[R5] |= Tx7;
 899                 up->parity_mask = 0x7f;
 900                 break;
 901         case CS8:
 902         default:
 903                 up->curregs[R3] |= Rx8;
 904                 up->curregs[R5] |= Tx8;
 905                 up->parity_mask = 0xff;
 906                 break;
 907         };
 908         up->curregs[R4] &= ~0x0c;
 909         if (cflag & CSTOPB)
 910                 up->curregs[R4] |= SB2;
 911         else
 912                 up->curregs[R4] |= SB1;
 913         if (cflag & PARENB)
 914                 up->curregs[R4] |= PAR_ENAB;
 915         else
 916                 up->curregs[R4] &= ~PAR_ENAB;
 917         if (!(cflag & PARODD))
 918                 up->curregs[R4] |= PAR_EVEN;
 919         else
 920                 up->curregs[R4] &= ~PAR_EVEN;
 921
 922         up->port.read_status_mask = Rx_OVR;
 923         if (iflag & INPCK)
 924                 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
 925         if (iflag & (BRKINT | PARMRK))
 926                 up->port.read_status_mask |= BRK_ABRT;
 927
 928         up->port.ignore_status_mask = 0;
 929         if (iflag & IGNPAR)
 930                 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
 931         if (iflag & IGNBRK) {
 932                 up->port.ignore_status_mask |= BRK_ABRT;
 933                 if (iflag & IGNPAR)
 934                         up->port.ignore_status_mask |= Rx_OVR;
 935         }
 936
 937         if ((cflag & CREAD) == 0)
 938                 up->port.ignore_status_mask = 0xff;
 939 }
 940
 941 /* The port lock is not held.  */
 942 static void
 943 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
 944                      struct ktermios *old)
 945 {
 946         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 947         unsigned long flags;
 948         int baud, brg;
 949
 950         baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
 951
 952         spin_lock_irqsave(&up->port.lock, flags);
 953
 954         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
 955
 956         sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
 957
 958         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 959                 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
 960         else
 961                 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
 962
 963         up->cflag = termios->c_cflag;
 964
 965         sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
 966
 967         uart_update_timeout(port, termios->c_cflag, baud);
 968
 969         spin_unlock_irqrestore(&up->port.lock, flags);
 970 }
 971
 972 static const char *sunzilog_type(struct uart_port *port)
 973 {
 974         struct uart_sunzilog_port *up = UART_ZILOG(port);
 975
 976         return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
 977 }
 978
 979 /* We do not request/release mappings of the registers here, this
 980  * happens at early serial probe time.
 981  */
 982 static void sunzilog_release_port(struct uart_port *port)
 983 {
 984 }
 985
 986 static int sunzilog_request_port(struct uart_port *port)
 987 {
 988         return 0;
 989 }
 990
 991 /* These do not need to do anything interesting either.  */
 992 static void sunzilog_config_port(struct uart_port *port, int flags)
 993 {
 994 }
 995
 996 /* We do not support letting the user mess with the divisor, IRQ, etc. */
 997 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
 998 {
 999         return -EINVAL;
1000 }
1001
1002 #ifdef CONFIG_CONSOLE_POLL
1003 static int sunzilog_get_poll_char(struct uart_port *port)
1004 {
1005         unsigned char ch, r1;
1006         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
1007         struct zilog_channel __iomem *channel
1008                 = ZILOG_CHANNEL_FROM_PORT(&up->port);
1009
1010
1011         r1 = read_zsreg(channel, R1);
1012         if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
1013                 writeb(ERR_RES, &channel->control);
1014                 ZSDELAY();
1015                 ZS_WSYNC(channel);
1016         }
1017
1018         ch = readb(&channel->control);
1019         ZSDELAY();
1020
1021         /* This funny hack depends upon BRK_ABRT not interfering
1022          * with the other bits we care about in R1.
1023          */
1024         if (ch & BRK_ABRT)
1025                 r1 |= BRK_ABRT;
1026
1027         if (!(ch & Rx_CH_AV))
1028                 return NO_POLL_CHAR;
1029
1030         ch = readb(&channel->data);
1031         ZSDELAY();
1032
1033         ch &= up->parity_mask;
1034         return ch;
1035 }
1036
1037 static void sunzilog_put_poll_char(struct uart_port *port,
1038                         unsigned char ch)
1039 {
1040         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *)port;
1041
1042         sunzilog_putchar(&up->port, ch);
1043 }
1044 #endif /* CONFIG_CONSOLE_POLL */
1045
1046 static struct uart_ops sunzilog_pops = {
1047         .tx_empty       =       sunzilog_tx_empty,
1048         .set_mctrl      =       sunzilog_set_mctrl,
1049         .get_mctrl      =       sunzilog_get_mctrl,
1050         .stop_tx        =       sunzilog_stop_tx,
1051         .start_tx       =       sunzilog_start_tx,
1052         .stop_rx        =       sunzilog_stop_rx,
1053         .enable_ms      =       sunzilog_enable_ms,
1054         .break_ctl      =       sunzilog_break_ctl,
1055         .startup        =       sunzilog_startup,
1056         .shutdown       =       sunzilog_shutdown,
1057         .set_termios    =       sunzilog_set_termios,
1058         .type           =       sunzilog_type,
1059         .release_port   =       sunzilog_release_port,
1060         .request_port   =       sunzilog_request_port,
1061         .config_port    =       sunzilog_config_port,
1062         .verify_port    =       sunzilog_verify_port,
1063 #ifdef CONFIG_CONSOLE_POLL
1064         .poll_get_char  =       sunzilog_get_poll_char,
1065         .poll_put_char  =       sunzilog_put_poll_char,
1066 #endif
1067 };
1068
1069 static int uart_chip_count;
1070 static struct uart_sunzilog_port *sunzilog_port_table;
1071 static struct zilog_layout __iomem **sunzilog_chip_regs;
1072
1073 static struct uart_sunzilog_port *sunzilog_irq_chain;
1074
1075 static struct uart_driver sunzilog_reg = {
1076         .owner          =       THIS_MODULE,
1077         .driver_name    =       "sunzilog",
1078         .dev_name       =       "ttyS",
1079         .major          =       TTY_MAJOR,
1080 };
1081
1082 static int __init sunzilog_alloc_tables(int num_sunzilog)
1083 {
1084         struct uart_sunzilog_port *up;
1085         unsigned long size;
1086         int num_channels = num_sunzilog * 2;
1087         int i;
1088
1089         size = num_channels * sizeof(struct uart_sunzilog_port);
1090         sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1091         if (!sunzilog_port_table)
1092                 return -ENOMEM;
1093
1094         for (i = 0; i < num_channels; i++) {
1095                 up = &sunzilog_port_table[i];
1096
1097                 spin_lock_init(&up->port.lock);
1098
1099                 if (i == 0)
1100                         sunzilog_irq_chain = up;
1101
1102                 if (i < num_channels - 1)
1103                         up->next = up + 1;
1104                 else
1105                         up->next = NULL;
1106         }
1107
1108         size = num_sunzilog * sizeof(struct zilog_layout __iomem *);
1109         sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1110         if (!sunzilog_chip_regs) {
1111                 kfree(sunzilog_port_table);
1112                 sunzilog_irq_chain = NULL;
1113                 return -ENOMEM;
1114         }
1115
1116         return 0;
1117 }
1118
1119 static void sunzilog_free_tables(void)
1120 {
1121         kfree(sunzilog_port_table);
1122         sunzilog_irq_chain = NULL;
1123         kfree(sunzilog_chip_regs);
1124 }
1125
1126 #define ZS_PUT_CHAR_MAX_DELAY   2000    /* 10 ms */
1127
1128 static void sunzilog_putchar(struct uart_port *port, int ch)
1129 {
1130         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1131         int loops = ZS_PUT_CHAR_MAX_DELAY;
1132
1133         /* This is a timed polling loop so do not switch the explicit
1134          * udelay with ZSDELAY as that is a NOP on some platforms.  -DaveM
1135          */
1136         do {
1137                 unsigned char val = readb(&channel->control);
1138                 if (val & Tx_BUF_EMP) {
1139                         ZSDELAY();
1140                         break;
1141                 }
1142                 udelay(5);
1143         } while (--loops);
1144
1145         writeb(ch, &channel->data);
1146         ZSDELAY();
1147         ZS_WSYNC(channel);
1148 }
1149
1150 #ifdef CONFIG_SERIO
1151
1152 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1153
1154 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1155 {
1156         struct uart_sunzilog_port *up = serio->port_data;
1157         unsigned long flags;
1158
1159         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1160
1161         sunzilog_putchar(&up->port, ch);
1162
1163         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1164
1165         return 0;
1166 }
1167
1168 static int sunzilog_serio_open(struct serio *serio)
1169 {
1170         struct uart_sunzilog_port *up = serio->port_data;
1171         unsigned long flags;
1172         int ret;
1173
1174         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1175         if (!up->serio_open) {
1176                 up->serio_open = 1;
1177                 ret = 0;
1178         } else
1179                 ret = -EBUSY;
1180         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1181
1182         return ret;
1183 }
1184
1185 static void sunzilog_serio_close(struct serio *serio)
1186 {
1187         struct uart_sunzilog_port *up = serio->port_data;
1188         unsigned long flags;
1189
1190         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1191         up->serio_open = 0;
1192         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1193 }
1194
1195 #endif /* CONFIG_SERIO */
1196
1197 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1198 static void
1199 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1200 {
1201         struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1202         unsigned long flags;
1203         int locked = 1;
1204
1205         local_irq_save(flags);
1206         if (up->port.sysrq) {
1207                 locked = 0;
1208         } else if (oops_in_progress) {
1209                 locked = spin_trylock(&up->port.lock);
1210         } else
1211                 spin_lock(&up->port.lock);
1212
1213         uart_console_write(&up->port, s, count, sunzilog_putchar);
1214         udelay(2);
1215
1216         if (locked)
1217                 spin_unlock(&up->port.lock);
1218         local_irq_restore(flags);
1219 }
1220
1221 static int __init sunzilog_console_setup(struct console *con, char *options)
1222 {
1223         struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1224         unsigned long flags;
1225         int baud, brg;
1226
1227         if (up->port.type != PORT_SUNZILOG)
1228                 return -1;
1229
1230         printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1231                (sunzilog_reg.minor - 64) + con->index, con->index);
1232
1233         /* Get firmware console settings.  */
1234         sunserial_console_termios(con, up->port.dev->of_node);
1235
1236         /* Firmware console speed is limited to 150-->38400 baud so
1237          * this hackish cflag thing is OK.
1238          */
1239         switch (con->cflag & CBAUD) {
1240         case B150: baud = 150; break;
1241         case B300: baud = 300; break;
1242         case B600: baud = 600; break;
1243         case B1200: baud = 1200; break;
1244         case B2400: baud = 2400; break;
1245         case B4800: baud = 4800; break;
1246         default: case B9600: baud = 9600; break;
1247         case B19200: baud = 19200; break;
1248         case B38400: baud = 38400; break;
1249         };
1250
1251         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1252
1253         spin_lock_irqsave(&up->port.lock, flags);
1254
1255         up->curregs[R15] |= BRKIE;
1256         sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1257
1258         sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1259         __sunzilog_startup(up);
1260
1261         spin_unlock_irqrestore(&up->port.lock, flags);
1262
1263         return 0;
1264 }
1265
1266 static struct console sunzilog_console_ops = {
1267         .name   =       "ttyS",
1268         .write  =       sunzilog_console_write,
1269         .device =       uart_console_device,
1270         .setup  =       sunzilog_console_setup,
1271         .flags  =       CON_PRINTBUFFER,
1272         .index  =       -1,
1273         .data   =       &sunzilog_reg,
1274 };
1275
1276 static inline struct console *SUNZILOG_CONSOLE(void)
1277 {
1278         return &sunzilog_console_ops;
1279 }
1280
1281 #else
1282 #define SUNZILOG_CONSOLE()      (NULL)
1283 #endif
1284
1285 static void __devinit sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1286 {
1287         int baud, brg;
1288
1289         if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1290                 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1291                 baud = 1200;
1292         } else {
1293                 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1294                 baud = 4800;
1295         }
1296
1297         up->curregs[R15] |= BRKIE;
1298         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1299         sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1300         sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1301         __sunzilog_startup(up);
1302 }
1303
1304 #ifdef CONFIG_SERIO
1305 static void __devinit sunzilog_register_serio(struct uart_sunzilog_port *up)
1306 {
1307         struct serio *serio = &up->serio;
1308
1309         serio->port_data = up;
1310
1311         serio->id.type = SERIO_RS232;
1312         if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1313                 serio->id.proto = SERIO_SUNKBD;
1314                 strlcpy(serio->name, "zskbd", sizeof(serio->name));
1315         } else {
1316                 serio->id.proto = SERIO_SUN;
1317                 serio->id.extra = 1;
1318                 strlcpy(serio->name, "zsms", sizeof(serio->name));
1319         }
1320         strlcpy(serio->phys,
1321                 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1322                  "zs/serio0" : "zs/serio1"),
1323                 sizeof(serio->phys));
1324
1325         serio->write = sunzilog_serio_write;
1326         serio->open = sunzilog_serio_open;
1327         serio->close = sunzilog_serio_close;
1328         serio->dev.parent = up->port.dev;
1329
1330         serio_register_port(serio);
1331 }
1332 #endif
1333
1334 static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
1335 {
1336         struct zilog_channel __iomem *channel;
1337         unsigned long flags;
1338         int baud, brg;
1339
1340         channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1341
1342         spin_lock_irqsave(&up->port.lock, flags);
1343         if (ZS_IS_CHANNEL_A(up)) {
1344                 write_zsreg(channel, R9, FHWRES);
1345                 ZSDELAY_LONG();
1346                 (void) read_zsreg(channel, R0);
1347         }
1348
1349         if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1350                          SUNZILOG_FLAG_CONS_MOUSE)) {
1351                 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1352                 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1353                 up->curregs[R3] = RxENAB | Rx8;
1354                 up->curregs[R5] = TxENAB | Tx8;
1355                 up->curregs[R6] = 0x00; /* SDLC Address */
1356                 up->curregs[R7] = 0x7E; /* SDLC Flag    */
1357                 up->curregs[R9] = NV;
1358                 up->curregs[R7p] = 0x00;
1359                 sunzilog_init_kbdms(up);
1360                 /* Only enable interrupts if an ISR handler available */
1361                 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1362                         up->curregs[R9] |= MIE;
1363                 write_zsreg(channel, R9, up->curregs[R9]);
1364         } else {
1365                 /* Normal serial TTY. */
1366                 up->parity_mask = 0xff;
1367                 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1368                 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1369                 up->curregs[R3] = RxENAB | Rx8;
1370                 up->curregs[R5] = TxENAB | Tx8;
1371                 up->curregs[R6] = 0x00; /* SDLC Address */
1372                 up->curregs[R7] = 0x7E; /* SDLC Flag    */
1373                 up->curregs[R9] = NV;
1374                 up->curregs[R10] = NRZ;
1375                 up->curregs[R11] = TCBR | RCBR;
1376                 baud = 9600;
1377                 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1378                 up->curregs[R12] = (brg & 0xff);
1379                 up->curregs[R13] = (brg >> 8) & 0xff;
1380                 up->curregs[R14] = BRSRC | BRENAB;
1381                 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1382                 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1383                 if (__load_zsregs(channel, up->curregs)) {
1384                         up->flags |= SUNZILOG_FLAG_ESCC;
1385                 }
1386                 /* Only enable interrupts if an ISR handler available */
1387                 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1388                         up->curregs[R9] |= MIE;
1389                 write_zsreg(channel, R9, up->curregs[R9]);
1390         }
1391
1392         spin_unlock_irqrestore(&up->port.lock, flags);
1393
1394 #ifdef CONFIG_SERIO
1395         if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1396                          SUNZILOG_FLAG_CONS_MOUSE))
1397                 sunzilog_register_serio(up);
1398 #endif
1399 }
1400
1401 static int zilog_irq;
1402
1403 static int __devinit zs_probe(struct platform_device *op)
1404 {
1405         static int kbm_inst, uart_inst;
1406         int inst;
1407         struct uart_sunzilog_port *up;
1408         struct zilog_layout __iomem *rp;
1409         int keyboard_mouse = 0;
1410         int err;
1411
1412         if (of_find_property(op->dev.of_node, "keyboard", NULL))
1413                 keyboard_mouse = 1;
1414
1415         /* uarts must come before keyboards/mice */
1416         if (keyboard_mouse)
1417                 inst = uart_chip_count + kbm_inst;
1418         else
1419                 inst = uart_inst;
1420
1421         sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1422                                               sizeof(struct zilog_layout),
1423                                               "zs");
1424         if (!sunzilog_chip_regs[inst])
1425                 return -ENOMEM;
1426
1427         rp = sunzilog_chip_regs[inst];
1428
1429         if (!zilog_irq)
1430                 zilog_irq = op->archdata.irqs[0];
1431
1432         up = &sunzilog_port_table[inst * 2];
1433
1434         /* Channel A */
1435         up[0].port.mapbase = op->resource[0].start + 0x00;
1436         up[0].port.membase = (void __iomem *) &rp->channelA;
1437         up[0].port.iotype = UPIO_MEM;
1438         up[0].port.irq = op->archdata.irqs[0];
1439         up[0].port.uartclk = ZS_CLOCK;
1440         up[0].port.fifosize = 1;
1441         up[0].port.ops = &sunzilog_pops;
1442         up[0].port.type = PORT_SUNZILOG;
1443         up[0].port.flags = 0;
1444         up[0].port.line = (inst * 2) + 0;
1445         up[0].port.dev = &op->dev;
1446         up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1447         if (keyboard_mouse)
1448                 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1449         sunzilog_init_hw(&up[0]);
1450
1451         /* Channel B */
1452         up[1].port.mapbase = op->resource[0].start + 0x04;
1453         up[1].port.membase = (void __iomem *) &rp->channelB;
1454         up[1].port.iotype = UPIO_MEM;
1455         up[1].port.irq = op->archdata.irqs[0];
1456         up[1].port.uartclk = ZS_CLOCK;
1457         up[1].port.fifosize = 1;
1458         up[1].port.ops = &sunzilog_pops;
1459         up[1].port.type = PORT_SUNZILOG;
1460         up[1].port.flags = 0;
1461         up[1].port.line = (inst * 2) + 1;
1462         up[1].port.dev = &op->dev;
1463         up[1].flags |= 0;
1464         if (keyboard_mouse)
1465                 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1466         sunzilog_init_hw(&up[1]);
1467
1468         if (!keyboard_mouse) {
1469                 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1470                                             &sunzilog_reg, up[0].port.line,
1471                                             false))
1472                         up->flags |= SUNZILOG_FLAG_IS_CONS;
1473                 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1474                 if (err) {
1475                         of_iounmap(&op->resource[0],
1476                                    rp, sizeof(struct zilog_layout));
1477                         return err;
1478                 }
1479                 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1480                                             &sunzilog_reg, up[1].port.line,
1481                                             false))
1482                         up->flags |= SUNZILOG_FLAG_IS_CONS;
1483                 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1484                 if (err) {
1485                         uart_remove_one_port(&sunzilog_reg, &up[0].port);
1486                         of_iounmap(&op->resource[0],
1487                                    rp, sizeof(struct zilog_layout));
1488                         return err;
1489                 }
1490                 uart_inst++;
1491         } else {
1492                 printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "
1493                        "is a %s\n",
1494                        dev_name(&op->dev),
1495                        (unsigned long long) up[0].port.mapbase,
1496                        op->archdata.irqs[0], sunzilog_type(&up[0].port));
1497                 printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "
1498                        "is a %s\n",
1499                        dev_name(&op->dev),
1500                        (unsigned long long) up[1].port.mapbase,
1501                        op->archdata.irqs[0], sunzilog_type(&up[1].port));
1502                 kbm_inst++;
1503         }
1504
1505         dev_set_drvdata(&op->dev, &up[0]);
1506
1507         return 0;
1508 }
1509
1510 static void __devexit zs_remove_one(struct uart_sunzilog_port *up)
1511 {
1512         if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1513 #ifdef CONFIG_SERIO
1514                 serio_unregister_port(&up->serio);
1515 #endif
1516         } else
1517                 uart_remove_one_port(&sunzilog_reg, &up->port);
1518 }
1519
1520 static int __devexit zs_remove(struct platform_device *op)
1521 {
1522         struct uart_sunzilog_port *up = dev_get_drvdata(&op->dev);
1523         struct zilog_layout __iomem *regs;
1524
1525         zs_remove_one(&up[0]);
1526         zs_remove_one(&up[1]);
1527
1528         regs = sunzilog_chip_regs[up[0].port.line / 2];
1529         of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1530
1531         dev_set_drvdata(&op->dev, NULL);
1532
1533         return 0;
1534 }
1535
1536 static const struct of_device_id zs_match[] = {
1537         {
1538                 .name = "zs",
1539         },
1540         {},
1541 };
1542 MODULE_DEVICE_TABLE(of, zs_match);
1543
1544 static struct platform_driver zs_driver = {
1545         .driver = {
1546                 .name = "zs",
1547                 .owner = THIS_MODULE,
1548                 .of_match_table = zs_match,
1549         },
1550         .probe          = zs_probe,
1551         .remove         = __devexit_p(zs_remove),
1552 };
1553
1554 static int __init sunzilog_init(void)
1555 {
1556         struct device_node *dp;
1557         int err;
1558         int num_keybms = 0;
1559         int num_sunzilog = 0;
1560
1561         for_each_node_by_name(dp, "zs") {
1562                 num_sunzilog++;
1563                 if (of_find_property(dp, "keyboard", NULL))
1564                         num_keybms++;
1565         }
1566
1567         if (num_sunzilog) {
1568                 err = sunzilog_alloc_tables(num_sunzilog);
1569                 if (err)
1570                         goto out;
1571
1572                 uart_chip_count = num_sunzilog - num_keybms;
1573
1574                 err = sunserial_register_minors(&sunzilog_reg,
1575                                                 uart_chip_count * 2);
1576                 if (err)
1577                         goto out_free_tables;
1578         }
1579
1580         err = platform_driver_register(&zs_driver);
1581         if (err)
1582                 goto out_unregister_uart;
1583
1584         if (!zilog_irq) {
1585                 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1586                 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1587                                   "zs", sunzilog_irq_chain);
1588                 if (err)
1589                         goto out_unregister_driver;
1590
1591                 /* Enable Interrupts */
1592                 while (up) {
1593                         struct zilog_channel __iomem *channel;
1594
1595                         /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1596                         channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1597                         up->flags       |= SUNZILOG_FLAG_ISR_HANDLER;
1598                         up->curregs[R9] |= MIE;
1599                         write_zsreg(channel, R9, up->curregs[R9]);
1600                         up = up->next;
1601                 }
1602         }
1603
1604 out:
1605         return err;
1606
1607 out_unregister_driver:
1608         platform_driver_unregister(&zs_driver);
1609
1610 out_unregister_uart:
1611         if (num_sunzilog) {
1612                 sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);
1613                 sunzilog_reg.cons = NULL;
1614         }
1615
1616 out_free_tables:
1617         sunzilog_free_tables();
1618         goto out;
1619 }
1620
1621 static void __exit sunzilog_exit(void)
1622 {
1623         platform_driver_unregister(&zs_driver);
1624
1625         if (!zilog_irq) {
1626                 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1627
1628                 /* Disable Interrupts */
1629                 while (up) {
1630                         struct zilog_channel __iomem *channel;
1631
1632                         /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1633                         channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1634                         up->flags       &= ~SUNZILOG_FLAG_ISR_HANDLER;
1635                         up->curregs[R9] &= ~MIE;
1636                         write_zsreg(channel, R9, up->curregs[R9]);
1637                         up = up->next;
1638                 }
1639
1640                 free_irq(zilog_irq, sunzilog_irq_chain);
1641                 zilog_irq = 0;
1642         }
1643
1644         if (sunzilog_reg.nr) {
1645                 sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);
1646                 sunzilog_free_tables();
1647         }
1648 }
1649
1650 module_init(sunzilog_init);
1651 module_exit(sunzilog_exit);
1652
1653 MODULE_AUTHOR("David S. Miller");
1654 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1655 MODULE_VERSION("2.0");
1656 MODULE_LICENSE("GPL");