drivers/tty/serial/sunsab.c

   1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
   2  *
   3  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
   4  * Copyright (C) 2002, 2006  David S. Miller (davem@davemloft.net)
   5  *
   6  * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
   7  *   Maxim Krasnyanskiy <maxk@qualcomm.com>
   8  *
   9  * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
  10  * rates to be programmed into the UART.  Also eliminated a lot of
  11  * duplicated code in the console setup.
  12  *   Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
  13  *
  14  * Ported to new 2.5.x UART layer.
  15  *   David S. Miller <davem@davemloft.net>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/major.h>
  24 #include <linux/string.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/ioport.h>
  27 #include <linux/circ_buf.h>
  28 #include <linux/serial.h>
  29 #include <linux/sysrq.h>
  30 #include <linux/console.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/slab.h>
  33 #include <linux/delay.h>
  34 #include <linux/init.h>
  35 #include <linux/of_device.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/prom.h>
  40
  41 #if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  42 #define SUPPORT_SYSRQ
  43 #endif
  44
  45 #include <linux/serial_core.h>
  46
  47 #include "suncore.h"
  48 #include "sunsab.h"
  49
  50 struct uart_sunsab_port {
  51         struct uart_port                port;           /* Generic UART port    */
  52         union sab82532_async_regs       __iomem *regs;  /* Chip registers       */
  53         unsigned long                   irqflags;       /* IRQ state flags      */
  54         int                             dsr;            /* Current DSR state    */
  55         unsigned int                    cec_timeout;    /* Chip poll timeout... */
  56         unsigned int                    tec_timeout;    /* likewise             */
  57         unsigned char                   interrupt_mask0;/* ISR0 masking         */
  58         unsigned char                   interrupt_mask1;/* ISR1 masking         */
  59         unsigned char                   pvr_dtr_bit;    /* Which PVR bit is DTR */
  60         unsigned char                   pvr_dsr_bit;    /* Which PVR bit is DSR */
  61         unsigned int                    gis_shift;
  62         int                             type;           /* SAB82532 version     */
  63
  64         /* Setting configuration bits while the transmitter is active
  65          * can cause garbage characters to get emitted by the chip.
  66          * Therefore, we cache such writes here and do the real register
  67          * write the next time the transmitter becomes idle.
  68          */
  69         unsigned int                    cached_ebrg;
  70         unsigned char                   cached_mode;
  71         unsigned char                   cached_pvr;
  72         unsigned char                   cached_dafo;
  73 };
  74
  75 /*
  76  * This assumes you have a 29.4912 MHz clock for your UART.
  77  */
  78 #define SAB_BASE_BAUD ( 29491200 / 16 )
  79
  80 static char *sab82532_version[16] = {
  81         "V1.0", "V2.0", "V3.2", "V(0x03)",
  82         "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
  83         "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
  84         "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
  85 };
  86
  87 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
  88 #define SAB82532_MAX_CEC_TIMEOUT  50000 /* 2.5 TX CLKs (at 50 baud) */
  89
  90 #define SAB82532_RECV_FIFO_SIZE 32      /* Standard async fifo sizes */
  91 #define SAB82532_XMIT_FIFO_SIZE 32
  92
  93 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
  94 {
  95         int timeout = up->tec_timeout;
  96
  97         while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
  98                 udelay(1);
  99 }
 100
 101 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
 102 {
 103         int timeout = up->cec_timeout;
 104
 105         while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
 106                 udelay(1);
 107 }
 108
 109 static struct tty_struct *
 110 receive_chars(struct uart_sunsab_port *up,
 111               union sab82532_irq_status *stat)
 112 {
 113         struct tty_struct *tty = NULL;
 114         unsigned char buf[32];
 115         int saw_console_brk = 0;
 116         int free_fifo = 0;
 117         int count = 0;
 118         int i;
 119
 120         if (up->port.state != NULL)             /* Unopened serial console */
 121                 tty = up->port.state->port.tty;
 122
 123         /* Read number of BYTES (Character + Status) available. */
 124         if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
 125                 count = SAB82532_RECV_FIFO_SIZE;
 126                 free_fifo++;
 127         }
 128
 129         if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
 130                 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
 131                 free_fifo++;
 132         }
 133
 134         /* Issue a FIFO read command in case we where idle. */
 135         if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
 136                 sunsab_cec_wait(up);
 137                 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
 138                 return tty;
 139         }
 140
 141         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 142                 free_fifo++;
 143
 144         /* Read the FIFO. */
 145         for (i = 0; i < count; i++)
 146                 buf[i] = readb(&up->regs->r.rfifo[i]);
 147
 148         /* Issue Receive Message Complete command. */
 149         if (free_fifo) {
 150                 sunsab_cec_wait(up);
 151                 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
 152         }
 153
 154         /* Count may be zero for BRK, so we check for it here */
 155         if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
 156             (up->port.line == up->port.cons->index))
 157                 saw_console_brk = 1;
 158
 159         if (count == 0) {
 160                 if (unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
 161                         stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
 162                                              SAB82532_ISR0_FERR);
 163                         up->port.icount.brk++;
 164                         uart_handle_break(&up->port);
 165                 }
 166         }
 167
 168         for (i = 0; i < count; i++) {
 169                 unsigned char ch = buf[i], flag;
 170
 171                 if (tty == NULL) {
 172                         uart_handle_sysrq_char(&up->port, ch);
 173                         continue;
 174                 }
 175
 176                 flag = TTY_NORMAL;
 177                 up->port.icount.rx++;
 178
 179                 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
 180                                                 SAB82532_ISR0_FERR |
 181                                                 SAB82532_ISR0_RFO)) ||
 182                     unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
 183                         /*
 184                          * For statistics only
 185                          */
 186                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 187                                 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
 188                                                      SAB82532_ISR0_FERR);
 189                                 up->port.icount.brk++;
 190                                 /*
 191                                  * We do the SysRQ and SAK checking
 192                                  * here because otherwise the break
 193                                  * may get masked by ignore_status_mask
 194                                  * or read_status_mask.
 195                                  */
 196                                 if (uart_handle_break(&up->port))
 197                                         continue;
 198                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 199                                 up->port.icount.parity++;
 200                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 201                                 up->port.icount.frame++;
 202                         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 203                                 up->port.icount.overrun++;
 204
 205                         /*
 206                          * Mask off conditions which should be ingored.
 207                          */
 208                         stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
 209                         stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
 210
 211                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 212                                 flag = TTY_BREAK;
 213                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 214                                 flag = TTY_PARITY;
 215                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 216                                 flag = TTY_FRAME;
 217                 }
 218
 219                 if (uart_handle_sysrq_char(&up->port, ch))
 220                         continue;
 221
 222                 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
 223                     (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
 224                         tty_insert_flip_char(tty, ch, flag);
 225                 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 226                         tty_insert_flip_char(tty, 0, TTY_OVERRUN);
 227         }
 228
 229         if (saw_console_brk)
 230                 sun_do_break();
 231
 232         return tty;
 233 }
 234
 235 static void sunsab_stop_tx(struct uart_port *);
 236 static void sunsab_tx_idle(struct uart_sunsab_port *);
 237
 238 static void transmit_chars(struct uart_sunsab_port *up,
 239                            union sab82532_irq_status *stat)
 240 {
 241         struct circ_buf *xmit = &up->port.state->xmit;
 242         int i;
 243
 244         if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
 245                 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
 246                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 247                 set_bit(SAB82532_ALLS, &up->irqflags);
 248         }
 249
 250 #if 0 /* bde@nwlink.com says this check causes problems */
 251         if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
 252                 return;
 253 #endif
 254
 255         if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
 256                 return;
 257
 258         set_bit(SAB82532_XPR, &up->irqflags);
 259         sunsab_tx_idle(up);
 260
 261         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 262                 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 263                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 264                 return;
 265         }
 266
 267         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 268         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 269         clear_bit(SAB82532_ALLS, &up->irqflags);
 270
 271         /* Stuff 32 bytes into Transmit FIFO. */
 272         clear_bit(SAB82532_XPR, &up->irqflags);
 273         for (i = 0; i < up->port.fifosize; i++) {
 274                 writeb(xmit->buf[xmit->tail],
 275                        &up->regs->w.xfifo[i]);
 276                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 277                 up->port.icount.tx++;
 278                 if (uart_circ_empty(xmit))
 279                         break;
 280         }
 281
 282         /* Issue a Transmit Frame command. */
 283         sunsab_cec_wait(up);
 284         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 285
 286         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 287                 uart_write_wakeup(&up->port);
 288
 289         if (uart_circ_empty(xmit))
 290                 sunsab_stop_tx(&up->port);
 291 }
 292
 293 static void check_status(struct uart_sunsab_port *up,
 294                          union sab82532_irq_status *stat)
 295 {
 296         if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
 297                 uart_handle_dcd_change(&up->port,
 298                                        !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
 299
 300         if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
 301                 uart_handle_cts_change(&up->port,
 302                                        (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
 303
 304         if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
 305                 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
 306                 up->port.icount.dsr++;
 307         }
 308
 309         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 310 }
 311
 312 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
 313 {
 314         struct uart_sunsab_port *up = dev_id;
 315         struct tty_struct *tty;
 316         union sab82532_irq_status status;
 317         unsigned long flags;
 318         unsigned char gis;
 319
 320         spin_lock_irqsave(&up->port.lock, flags);
 321
 322         status.stat = 0;
 323         gis = readb(&up->regs->r.gis) >> up->gis_shift;
 324         if (gis & 1)
 325                 status.sreg.isr0 = readb(&up->regs->r.isr0);
 326         if (gis & 2)
 327                 status.sreg.isr1 = readb(&up->regs->r.isr1);
 328
 329         tty = NULL;
 330         if (status.stat) {
 331                 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 332                                          SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
 333                     (status.sreg.isr1 & SAB82532_ISR1_BRK))
 334                         tty = receive_chars(up, &status);
 335                 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
 336                     (status.sreg.isr1 & SAB82532_ISR1_CSC))
 337                         check_status(up, &status);
 338                 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
 339                         transmit_chars(up, &status);
 340         }
 341
 342         spin_unlock_irqrestore(&up->port.lock, flags);
 343
 344         if (tty)
 345                 tty_flip_buffer_push(tty);
 346
 347         return IRQ_HANDLED;
 348 }
 349
 350 /* port->lock is not held.  */
 351 static unsigned int sunsab_tx_empty(struct uart_port *port)
 352 {
 353         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 354         int ret;
 355
 356         /* Do not need a lock for a state test like this.  */
 357         if (test_bit(SAB82532_ALLS, &up->irqflags))
 358                 ret = TIOCSER_TEMT;
 359         else
 360                 ret = 0;
 361
 362         return ret;
 363 }
 364
 365 /* port->lock held by caller.  */
 366 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
 367 {
 368         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 369
 370         if (mctrl & TIOCM_RTS) {
 371                 up->cached_mode &= ~SAB82532_MODE_FRTS;
 372                 up->cached_mode |= SAB82532_MODE_RTS;
 373         } else {
 374                 up->cached_mode |= (SAB82532_MODE_FRTS |
 375                                     SAB82532_MODE_RTS);
 376         }
 377         if (mctrl & TIOCM_DTR) {
 378                 up->cached_pvr &= ~(up->pvr_dtr_bit);
 379         } else {
 380                 up->cached_pvr |= up->pvr_dtr_bit;
 381         }
 382
 383         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 384         if (test_bit(SAB82532_XPR, &up->irqflags))
 385                 sunsab_tx_idle(up);
 386 }
 387
 388 /* port->lock is held by caller and interrupts are disabled.  */
 389 static unsigned int sunsab_get_mctrl(struct uart_port *port)
 390 {
 391         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 392         unsigned char val;
 393         unsigned int result;
 394
 395         result = 0;
 396
 397         val = readb(&up->regs->r.pvr);
 398         result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
 399
 400         val = readb(&up->regs->r.vstr);
 401         result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
 402
 403         val = readb(&up->regs->r.star);
 404         result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
 405
 406         return result;
 407 }
 408
 409 /* port->lock held by caller.  */
 410 static void sunsab_stop_tx(struct uart_port *port)
 411 {
 412         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 413
 414         up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 415         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 416 }
 417
 418 /* port->lock held by caller.  */
 419 static void sunsab_tx_idle(struct uart_sunsab_port *up)
 420 {
 421         if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
 422                 u8 tmp;
 423
 424                 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
 425                 writeb(up->cached_mode, &up->regs->rw.mode);
 426                 writeb(up->cached_pvr, &up->regs->rw.pvr);
 427                 writeb(up->cached_dafo, &up->regs->w.dafo);
 428
 429                 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
 430                 tmp = readb(&up->regs->rw.ccr2);
 431                 tmp &= ~0xc0;
 432                 tmp |= (up->cached_ebrg >> 2) & 0xc0;
 433                 writeb(tmp, &up->regs->rw.ccr2);
 434         }
 435 }
 436
 437 /* port->lock held by caller.  */
 438 static void sunsab_start_tx(struct uart_port *port)
 439 {
 440         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 441         struct circ_buf *xmit = &up->port.state->xmit;
 442         int i;
 443
 444         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 445         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 446
 447         if (!test_bit(SAB82532_XPR, &up->irqflags))
 448                 return;
 449
 450         clear_bit(SAB82532_ALLS, &up->irqflags);
 451         clear_bit(SAB82532_XPR, &up->irqflags);
 452
 453         for (i = 0; i < up->port.fifosize; i++) {
 454                 writeb(xmit->buf[xmit->tail],
 455                        &up->regs->w.xfifo[i]);
 456                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 457                 up->port.icount.tx++;
 458                 if (uart_circ_empty(xmit))
 459                         break;
 460         }
 461
 462         /* Issue a Transmit Frame command.  */
 463         sunsab_cec_wait(up);
 464         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 465 }
 466
 467 /* port->lock is not held.  */
 468 static void sunsab_send_xchar(struct uart_port *port, char ch)
 469 {
 470         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 471         unsigned long flags;
 472
 473         spin_lock_irqsave(&up->port.lock, flags);
 474
 475         sunsab_tec_wait(up);
 476         writeb(ch, &up->regs->w.tic);
 477
 478         spin_unlock_irqrestore(&up->port.lock, flags);
 479 }
 480
 481 /* port->lock held by caller.  */
 482 static void sunsab_stop_rx(struct uart_port *port)
 483 {
 484         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 485
 486         up->interrupt_mask0 |= SAB82532_IMR0_TCD;
 487         writeb(up->interrupt_mask1, &up->regs->w.imr0);
 488 }
 489
 490 /* port->lock held by caller.  */
 491 static void sunsab_enable_ms(struct uart_port *port)
 492 {
 493         /* For now we always receive these interrupts.  */
 494 }
 495
 496 /* port->lock is not held.  */
 497 static void sunsab_break_ctl(struct uart_port *port, int break_state)
 498 {
 499         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 500         unsigned long flags;
 501         unsigned char val;
 502
 503         spin_lock_irqsave(&up->port.lock, flags);
 504
 505         val = up->cached_dafo;
 506         if (break_state)
 507                 val |= SAB82532_DAFO_XBRK;
 508         else
 509                 val &= ~SAB82532_DAFO_XBRK;
 510         up->cached_dafo = val;
 511
 512         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 513         if (test_bit(SAB82532_XPR, &up->irqflags))
 514                 sunsab_tx_idle(up);
 515
 516         spin_unlock_irqrestore(&up->port.lock, flags);
 517 }
 518
 519 /* port->lock is not held.  */
 520 static int sunsab_startup(struct uart_port *port)
 521 {
 522         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 523         unsigned long flags;
 524         unsigned char tmp;
 525         int err = request_irq(up->port.irq, sunsab_interrupt,
 526                               IRQF_SHARED, "sab", up);
 527         if (err)
 528                 return err;
 529
 530         spin_lock_irqsave(&up->port.lock, flags);
 531
 532         /*
 533          * Wait for any commands or immediate characters
 534          */
 535         sunsab_cec_wait(up);
 536         sunsab_tec_wait(up);
 537
 538         /*
 539          * Clear the FIFO buffers.
 540          */
 541         writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
 542         sunsab_cec_wait(up);
 543         writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
 544
 545         /*
 546          * Clear the interrupt registers.
 547          */
 548         (void) readb(&up->regs->r.isr0);
 549         (void) readb(&up->regs->r.isr1);
 550
 551         /*
 552          * Now, initialize the UART
 553          */
 554         writeb(0, &up->regs->w.ccr0);                           /* power-down */
 555         writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
 556                SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
 557         writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
 558         writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
 559                SAB82532_CCR2_TOE, &up->regs->w.ccr2);
 560         writeb(0, &up->regs->w.ccr3);
 561         writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
 562         up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
 563                            SAB82532_MODE_RAC);
 564         writeb(up->cached_mode, &up->regs->w.mode);
 565         writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
 566
 567         tmp = readb(&up->regs->rw.ccr0);
 568         tmp |= SAB82532_CCR0_PU;        /* power-up */
 569         writeb(tmp, &up->regs->rw.ccr0);
 570
 571         /*
 572          * Finally, enable interrupts
 573          */
 574         up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 575                                SAB82532_IMR0_PLLA);
 576         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 577         up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 578                                SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 579                                SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 580                                SAB82532_IMR1_XPR);
 581         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 582         set_bit(SAB82532_ALLS, &up->irqflags);
 583         set_bit(SAB82532_XPR, &up->irqflags);
 584
 585         spin_unlock_irqrestore(&up->port.lock, flags);
 586
 587         return 0;
 588 }
 589
 590 /* port->lock is not held.  */
 591 static void sunsab_shutdown(struct uart_port *port)
 592 {
 593         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 594         unsigned long flags;
 595
 596         spin_lock_irqsave(&up->port.lock, flags);
 597
 598         /* Disable Interrupts */
 599         up->interrupt_mask0 = 0xff;
 600         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 601         up->interrupt_mask1 = 0xff;
 602         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 603
 604         /* Disable break condition */
 605         up->cached_dafo = readb(&up->regs->rw.dafo);
 606         up->cached_dafo &= ~SAB82532_DAFO_XBRK;
 607         writeb(up->cached_dafo, &up->regs->rw.dafo);
 608
 609         /* Disable Receiver */
 610         up->cached_mode &= ~SAB82532_MODE_RAC;
 611         writeb(up->cached_mode, &up->regs->rw.mode);
 612
 613         /*
 614          * XXX FIXME
 615          *
 616          * If the chip is powered down here the system hangs/crashes during
 617          * reboot or shutdown.  This needs to be investigated further,
 618          * similar behaviour occurs in 2.4 when the driver is configured
 619          * as a module only.  One hint may be that data is sometimes
 620          * transmitted at 9600 baud during shutdown (regardless of the
 621          * speed the chip was configured for when the port was open).
 622          */
 623 #if 0
 624         /* Power Down */
 625         tmp = readb(&up->regs->rw.ccr0);
 626         tmp &= ~SAB82532_CCR0_PU;
 627         writeb(tmp, &up->regs->rw.ccr0);
 628 #endif
 629
 630         spin_unlock_irqrestore(&up->port.lock, flags);
 631         free_irq(up->port.irq, up);
 632 }
 633
 634 /*
 635  * This is used to figure out the divisor speeds.
 636  *
 637  * The formula is:    Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
 638  *
 639  * with               0 <= N < 64 and 0 <= M < 16
 640  */
 641
 642 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
 643 {
 644         int     n, m;
 645
 646         if (baud == 0) {
 647                 *n_ret = 0;
 648                 *m_ret = 0;
 649                 return;
 650         }
 651
 652         /*
 653          * We scale numbers by 10 so that we get better accuracy
 654          * without having to use floating point.  Here we increment m
 655          * until n is within the valid range.
 656          */
 657         n = (SAB_BASE_BAUD * 10) / baud;
 658         m = 0;
 659         while (n >= 640) {
 660                 n = n / 2;
 661                 m++;
 662         }
 663         n = (n+5) / 10;
 664         /*
 665          * We try very hard to avoid speeds with M == 0 since they may
 666          * not work correctly for XTAL frequences above 10 MHz.
 667          */
 668         if ((m == 0) && ((n & 1) == 0)) {
 669                 n = n / 2;
 670                 m++;
 671         }
 672         *n_ret = n - 1;
 673         *m_ret = m;
 674 }
 675
 676 /* Internal routine, port->lock is held and local interrupts are disabled.  */
 677 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
 678                                   unsigned int iflag, unsigned int baud,
 679                                   unsigned int quot)
 680 {
 681         unsigned char dafo;
 682         int bits, n, m;
 683
 684         /* Byte size and parity */
 685         switch (cflag & CSIZE) {
 686               case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 687               case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
 688               case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
 689               case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
 690               /* Never happens, but GCC is too dumb to figure it out */
 691               default:  dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 692         }
 693
 694         if (cflag & CSTOPB) {
 695                 dafo |= SAB82532_DAFO_STOP;
 696                 bits++;
 697         }
 698
 699         if (cflag & PARENB) {
 700                 dafo |= SAB82532_DAFO_PARE;
 701                 bits++;
 702         }
 703
 704         if (cflag & PARODD) {
 705                 dafo |= SAB82532_DAFO_PAR_ODD;
 706         } else {
 707                 dafo |= SAB82532_DAFO_PAR_EVEN;
 708         }
 709         up->cached_dafo = dafo;
 710
 711         calc_ebrg(baud, &n, &m);
 712
 713         up->cached_ebrg = n | (m << 6);
 714
 715         up->tec_timeout = (10 * 1000000) / baud;
 716         up->cec_timeout = up->tec_timeout >> 2;
 717
 718         /* CTS flow control flags */
 719         /* We encode read_status_mask and ignore_status_mask like so:
 720          *
 721          * ---------------------
 722          * | ... | ISR1 | ISR0 |
 723          * ---------------------
 724          *  ..    15   8 7    0
 725          */
 726
 727         up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 728                                      SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
 729                                      SAB82532_ISR0_CDSC);
 730         up->port.read_status_mask |= (SAB82532_ISR1_CSC |
 731                                       SAB82532_ISR1_ALLS |
 732                                       SAB82532_ISR1_XPR) << 8;
 733         if (iflag & INPCK)
 734                 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
 735                                               SAB82532_ISR0_FERR);
 736         if (iflag & (BRKINT | PARMRK))
 737                 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
 738
 739         /*
 740          * Characteres to ignore
 741          */
 742         up->port.ignore_status_mask = 0;
 743         if (iflag & IGNPAR)
 744                 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
 745                                                 SAB82532_ISR0_FERR);
 746         if (iflag & IGNBRK) {
 747                 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
 748                 /*
 749                  * If we're ignoring parity and break indicators,
 750                  * ignore overruns too (for real raw support).
 751                  */
 752                 if (iflag & IGNPAR)
 753                         up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
 754         }
 755
 756         /*
 757          * ignore all characters if CREAD is not set
 758          */
 759         if ((cflag & CREAD) == 0)
 760                 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
 761                                                 SAB82532_ISR0_TCD);
 762
 763         uart_update_timeout(&up->port, cflag,
 764                             (up->port.uartclk / (16 * quot)));
 765
 766         /* Now schedule a register update when the chip's
 767          * transmitter is idle.
 768          */
 769         up->cached_mode |= SAB82532_MODE_RAC;
 770         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 771         if (test_bit(SAB82532_XPR, &up->irqflags))
 772                 sunsab_tx_idle(up);
 773 }
 774
 775 /* port->lock is not held.  */
 776 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
 777                                struct ktermios *old)
 778 {
 779         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 780         unsigned long flags;
 781         unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 782         unsigned int quot = uart_get_divisor(port, baud);
 783
 784         spin_lock_irqsave(&up->port.lock, flags);
 785         sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
 786         spin_unlock_irqrestore(&up->port.lock, flags);
 787 }
 788
 789 static const char *sunsab_type(struct uart_port *port)
 790 {
 791         struct uart_sunsab_port *up = (void *)port;
 792         static char buf[36];
 793
 794         sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
 795         return buf;
 796 }
 797
 798 static void sunsab_release_port(struct uart_port *port)
 799 {
 800 }
 801
 802 static int sunsab_request_port(struct uart_port *port)
 803 {
 804         return 0;
 805 }
 806
 807 static void sunsab_config_port(struct uart_port *port, int flags)
 808 {
 809 }
 810
 811 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
 812 {
 813         return -EINVAL;
 814 }
 815
 816 static struct uart_ops sunsab_pops = {
 817         .tx_empty       = sunsab_tx_empty,
 818         .set_mctrl      = sunsab_set_mctrl,
 819         .get_mctrl      = sunsab_get_mctrl,
 820         .stop_tx        = sunsab_stop_tx,
 821         .start_tx       = sunsab_start_tx,
 822         .send_xchar     = sunsab_send_xchar,
 823         .stop_rx        = sunsab_stop_rx,
 824         .enable_ms      = sunsab_enable_ms,
 825         .break_ctl      = sunsab_break_ctl,
 826         .startup        = sunsab_startup,
 827         .shutdown       = sunsab_shutdown,
 828         .set_termios    = sunsab_set_termios,
 829         .type           = sunsab_type,
 830         .release_port   = sunsab_release_port,
 831         .request_port   = sunsab_request_port,
 832         .config_port    = sunsab_config_port,
 833         .verify_port    = sunsab_verify_port,
 834 };
 835
 836 static struct uart_driver sunsab_reg = {
 837         .owner                  = THIS_MODULE,
 838         .driver_name            = "sunsab",
 839         .dev_name               = "ttyS",
 840         .major                  = TTY_MAJOR,
 841 };
 842
 843 static struct uart_sunsab_port *sunsab_ports;
 844
 845 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
 846
 847 static void sunsab_console_putchar(struct uart_port *port, int c)
 848 {
 849         struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
 850
 851         sunsab_tec_wait(up);
 852         writeb(c, &up->regs->w.tic);
 853 }
 854
 855 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
 856 {
 857         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 858         unsigned long flags;
 859         int locked = 1;
 860
 861         local_irq_save(flags);
 862         if (up->port.sysrq) {
 863                 locked = 0;
 864         } else if (oops_in_progress) {
 865                 locked = spin_trylock(&up->port.lock);
 866         } else
 867                 spin_lock(&up->port.lock);
 868
 869         uart_console_write(&up->port, s, n, sunsab_console_putchar);
 870         sunsab_tec_wait(up);
 871
 872         if (locked)
 873                 spin_unlock(&up->port.lock);
 874         local_irq_restore(flags);
 875 }
 876
 877 static int sunsab_console_setup(struct console *con, char *options)
 878 {
 879         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 880         unsigned long flags;
 881         unsigned int baud, quot;
 882
 883         /*
 884          * The console framework calls us for each and every port
 885          * registered. Defer the console setup until the requested
 886          * port has been properly discovered. A bit of a hack,
 887          * though...
 888          */
 889         if (up->port.type != PORT_SUNSAB)
 890                 return -1;
 891
 892         printk("Console: ttyS%d (SAB82532)\n",
 893                (sunsab_reg.minor - 64) + con->index);
 894
 895         sunserial_console_termios(con, up->port.dev->of_node);
 896
 897         switch (con->cflag & CBAUD) {
 898         case B150: baud = 150; break;
 899         case B300: baud = 300; break;
 900         case B600: baud = 600; break;
 901         case B1200: baud = 1200; break;
 902         case B2400: baud = 2400; break;
 903         case B4800: baud = 4800; break;
 904         default: case B9600: baud = 9600; break;
 905         case B19200: baud = 19200; break;
 906         case B38400: baud = 38400; break;
 907         case B57600: baud = 57600; break;
 908         case B115200: baud = 115200; break;
 909         case B230400: baud = 230400; break;
 910         case B460800: baud = 460800; break;
 911         };
 912
 913         /*
 914          * Temporary fix.
 915          */
 916         spin_lock_init(&up->port.lock);
 917
 918         /*
 919          * Initialize the hardware
 920          */
 921         sunsab_startup(&up->port);
 922
 923         spin_lock_irqsave(&up->port.lock, flags);
 924
 925         /*
 926          * Finally, enable interrupts
 927          */
 928         up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 929                                 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
 930         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 931         up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 932                                 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 933                                 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 934                                 SAB82532_IMR1_XPR;
 935         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 936
 937         quot = uart_get_divisor(&up->port, baud);
 938         sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
 939         sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
 940
 941         spin_unlock_irqrestore(&up->port.lock, flags);
 942
 943         return 0;
 944 }
 945
 946 static struct console sunsab_console = {
 947         .name   =       "ttyS",
 948         .write  =       sunsab_console_write,
 949         .device =       uart_console_device,
 950         .setup  =       sunsab_console_setup,
 951         .flags  =       CON_PRINTBUFFER,
 952         .index  =       -1,
 953         .data   =       &sunsab_reg,
 954 };
 955
 956 static inline struct console *SUNSAB_CONSOLE(void)
 957 {
 958         return &sunsab_console;
 959 }
 960 #else
 961 #define SUNSAB_CONSOLE()        (NULL)
 962 #define sunsab_console_init()   do { } while (0)
 963 #endif
 964
 965 static int __devinit sunsab_init_one(struct uart_sunsab_port *up,
 966                                      struct platform_device *op,
 967                                      unsigned long offset,
 968                                      int line)
 969 {
 970         up->port.line = line;
 971         up->port.dev = &op->dev;
 972
 973         up->port.mapbase = op->resource[0].start + offset;
 974         up->port.membase = of_ioremap(&op->resource[0], offset,
 975                                       sizeof(union sab82532_async_regs),
 976                                       "sab");
 977         if (!up->port.membase)
 978                 return -ENOMEM;
 979         up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
 980
 981         up->port.irq = op->archdata.irqs[0];
 982
 983         up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
 984         up->port.iotype = UPIO_MEM;
 985
 986         writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
 987
 988         up->port.ops = &sunsab_pops;
 989         up->port.type = PORT_SUNSAB;
 990         up->port.uartclk = SAB_BASE_BAUD;
 991
 992         up->type = readb(&up->regs->r.vstr) & 0x0f;
 993         writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
 994         writeb(0xff, &up->regs->w.pim);
 995         if ((up->port.line & 0x1) == 0) {
 996                 up->pvr_dsr_bit = (1 << 0);
 997                 up->pvr_dtr_bit = (1 << 1);
 998                 up->gis_shift = 2;
 999         } else {
1000                 up->pvr_dsr_bit = (1 << 3);
1001                 up->pvr_dtr_bit = (1 << 2);
1002                 up->gis_shift = 0;
1003         }
1004         up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1005         writeb(up->cached_pvr, &up->regs->w.pvr);
1006         up->cached_mode = readb(&up->regs->rw.mode);
1007         up->cached_mode |= SAB82532_MODE_FRTS;
1008         writeb(up->cached_mode, &up->regs->rw.mode);
1009         up->cached_mode |= SAB82532_MODE_RTS;
1010         writeb(up->cached_mode, &up->regs->rw.mode);
1011
1012         up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1013         up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1014
1015         return 0;
1016 }
1017
1018 static int __devinit sab_probe(struct platform_device *op)
1019 {
1020         static int inst;
1021         struct uart_sunsab_port *up;
1022         int err;
1023
1024         up = &sunsab_ports[inst * 2];
1025
1026         err = sunsab_init_one(&up[0], op,
1027                               0,
1028                               (inst * 2) + 0);
1029         if (err)
1030                 goto out;
1031
1032         err = sunsab_init_one(&up[1], op,
1033                               sizeof(union sab82532_async_regs),
1034                               (inst * 2) + 1);
1035         if (err)
1036                 goto out1;
1037
1038         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1039                                 &sunsab_reg, up[0].port.line,
1040                                 false);
1041
1042         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1043                                 &sunsab_reg, up[1].port.line,
1044                                 false);
1045
1046         err = uart_add_one_port(&sunsab_reg, &up[0].port);
1047         if (err)
1048                 goto out2;
1049
1050         err = uart_add_one_port(&sunsab_reg, &up[1].port);
1051         if (err)
1052                 goto out3;
1053
1054         dev_set_drvdata(&op->dev, &up[0]);
1055
1056         inst++;
1057
1058         return 0;
1059
1060 out3:
1061         uart_remove_one_port(&sunsab_reg, &up[0].port);
1062 out2:
1063         of_iounmap(&op->resource[0],
1064                    up[1].port.membase,
1065                    sizeof(union sab82532_async_regs));
1066 out1:
1067         of_iounmap(&op->resource[0],
1068                    up[0].port.membase,
1069                    sizeof(union sab82532_async_regs));
1070 out:
1071         return err;
1072 }
1073
1074 static int __devexit sab_remove(struct platform_device *op)
1075 {
1076         struct uart_sunsab_port *up = dev_get_drvdata(&op->dev);
1077
1078         uart_remove_one_port(&sunsab_reg, &up[1].port);
1079         uart_remove_one_port(&sunsab_reg, &up[0].port);
1080         of_iounmap(&op->resource[0],
1081                    up[1].port.membase,
1082                    sizeof(union sab82532_async_regs));
1083         of_iounmap(&op->resource[0],
1084                    up[0].port.membase,
1085                    sizeof(union sab82532_async_regs));
1086
1087         dev_set_drvdata(&op->dev, NULL);
1088
1089         return 0;
1090 }
1091
1092 static const struct of_device_id sab_match[] = {
1093         {
1094                 .name = "se",
1095         },
1096         {
1097                 .name = "serial",
1098                 .compatible = "sab82532",
1099         },
1100         {},
1101 };
1102 MODULE_DEVICE_TABLE(of, sab_match);
1103
1104 static struct platform_driver sab_driver = {
1105         .driver = {
1106                 .name = "sab",
1107                 .owner = THIS_MODULE,
1108                 .of_match_table = sab_match,
1109         },
1110         .probe          = sab_probe,
1111         .remove         = __devexit_p(sab_remove),
1112 };
1113
1114 static int __init sunsab_init(void)
1115 {
1116         struct device_node *dp;
1117         int err;
1118         int num_channels = 0;
1119
1120         for_each_node_by_name(dp, "se")
1121                 num_channels += 2;
1122         for_each_node_by_name(dp, "serial") {
1123                 if (of_device_is_compatible(dp, "sab82532"))
1124                         num_channels += 2;
1125         }
1126
1127         if (num_channels) {
1128                 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1129                                        num_channels, GFP_KERNEL);
1130                 if (!sunsab_ports)
1131                         return -ENOMEM;
1132
1133                 err = sunserial_register_minors(&sunsab_reg, num_channels);
1134                 if (err) {
1135                         kfree(sunsab_ports);
1136                         sunsab_ports = NULL;
1137
1138                         return err;
1139                 }
1140         }
1141
1142         return platform_driver_register(&sab_driver);
1143 }
1144
1145 static void __exit sunsab_exit(void)
1146 {
1147         platform_driver_unregister(&sab_driver);
1148         if (sunsab_reg.nr) {
1149                 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1150         }
1151
1152         kfree(sunsab_ports);
1153         sunsab_ports = NULL;
1154 }
1155
1156 module_init(sunsab_init);
1157 module_exit(sunsab_exit);
1158
1159 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1160 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1161 MODULE_LICENSE("GPL");