2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/sysrq.h>
36 #include <linux/ioport.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/console.h>
41 #include <linux/platform_device.h>
42 #include <linux/serial_sci.h>
43 #include <linux/notifier.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/cpufreq.h>
46 #include <linux/clk.h>
47 #include <linux/ctype.h>
48 #include <linux/err.h>
49 #include <linux/dmaengine.h>
50 #include <linux/scatterlist.h>
51 #include <linux/slab.h>
54 #include <asm/sh_bios.h>
60 struct uart_port port;
62 /* Platform configuration */
63 struct plat_sci_port *cfg;
65 /* Port enable callback */
66 void (*enable)(struct uart_port *port);
68 /* Port disable callback */
69 void (*disable)(struct uart_port *port);
72 struct timer_list break_timer;
80 struct dma_chan *chan_tx;
81 struct dma_chan *chan_rx;
83 #ifdef CONFIG_SERIAL_SH_SCI_DMA
84 struct dma_async_tx_descriptor *desc_tx;
85 struct dma_async_tx_descriptor *desc_rx[2];
86 dma_cookie_t cookie_tx;
87 dma_cookie_t cookie_rx[2];
88 dma_cookie_t active_rx;
89 struct scatterlist sg_tx;
90 unsigned int sg_len_tx;
91 struct scatterlist sg_rx[2];
93 struct sh_dmae_slave param_tx;
94 struct sh_dmae_slave param_rx;
95 struct work_struct work_tx;
96 struct work_struct work_rx;
97 struct timer_list rx_timer;
98 unsigned int rx_timeout;
101 struct notifier_block freq_transition;
104 /* Function prototypes */
105 static void sci_start_tx(struct uart_port *port);
106 static void sci_stop_tx(struct uart_port *port);
107 static void sci_start_rx(struct uart_port *port);
109 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
111 static struct sci_port sci_ports[SCI_NPORTS];
112 static struct uart_driver sci_uart_driver;
114 static inline struct sci_port *
115 to_sci_port(struct uart_port *uart)
117 return container_of(uart, struct sci_port, port);
120 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
122 #ifdef CONFIG_CONSOLE_POLL
123 static int sci_poll_get_char(struct uart_port *port)
125 unsigned short status;
129 status = sci_in(port, SCxSR);
130 if (status & SCxSR_ERRORS(port)) {
131 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
137 if (!(status & SCxSR_RDxF(port)))
140 c = sci_in(port, SCxRDR);
144 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
150 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
152 unsigned short status;
155 status = sci_in(port, SCxSR);
156 } while (!(status & SCxSR_TDxE(port)));
158 sci_out(port, SCxTDR, c);
159 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
161 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
163 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
164 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
166 if (port->mapbase == 0xA4400000) {
167 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
168 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
169 } else if (port->mapbase == 0xA4410000)
170 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
172 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
173 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
177 if (cflag & CRTSCTS) {
179 if (port->mapbase == 0xa4430000) { /* SCIF0 */
180 /* Clear PTCR bit 9-2; enable all scif pins but sck */
181 data = __raw_readw(PORT_PTCR);
182 __raw_writew((data & 0xfc03), PORT_PTCR);
183 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
184 /* Clear PVCR bit 9-2 */
185 data = __raw_readw(PORT_PVCR);
186 __raw_writew((data & 0xfc03), PORT_PVCR);
189 if (port->mapbase == 0xa4430000) { /* SCIF0 */
190 /* Clear PTCR bit 5-2; enable only tx and rx */
191 data = __raw_readw(PORT_PTCR);
192 __raw_writew((data & 0xffc3), PORT_PTCR);
193 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
194 /* Clear PVCR bit 5-2 */
195 data = __raw_readw(PORT_PVCR);
196 __raw_writew((data & 0xffc3), PORT_PVCR);
200 #elif defined(CONFIG_CPU_SH3)
201 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
202 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
206 /* We need to set SCPCR to enable RTS/CTS */
207 data = __raw_readw(SCPCR);
208 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
209 __raw_writew(data & 0x0fcf, SCPCR);
211 if (!(cflag & CRTSCTS)) {
212 /* We need to set SCPCR to enable RTS/CTS */
213 data = __raw_readw(SCPCR);
214 /* Clear out SCP7MD1,0, SCP4MD1,0,
215 Set SCP6MD1,0 = {01} (output) */
216 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
218 data = __raw_readb(SCPDR);
219 /* Set /RTS2 (bit6) = 0 */
220 __raw_writeb(data & 0xbf, SCPDR);
223 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
224 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
228 if (port->mapbase == 0xffe00000) {
229 data = __raw_readw(PSCR);
231 if (!(cflag & CRTSCTS))
234 __raw_writew(data, PSCR);
237 #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
238 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
239 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
240 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
241 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
242 defined(CONFIG_CPU_SUBTYPE_SHX3)
243 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
245 if (!(cflag & CRTSCTS))
246 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
248 #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
249 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
251 if (!(cflag & CRTSCTS))
252 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
255 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
261 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
262 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
263 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7786)
265 static int scif_txfill(struct uart_port *port)
267 return sci_in(port, SCTFDR) & 0xff;
270 static int scif_txroom(struct uart_port *port)
272 return SCIF_TXROOM_MAX - scif_txfill(port);
275 static int scif_rxfill(struct uart_port *port)
277 return sci_in(port, SCRFDR) & 0xff;
279 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
280 static int scif_txfill(struct uart_port *port)
282 if (port->mapbase == 0xffe00000 ||
283 port->mapbase == 0xffe08000)
285 return sci_in(port, SCTFDR) & 0xff;
288 return sci_in(port, SCFDR) >> 8;
291 static int scif_txroom(struct uart_port *port)
293 if (port->mapbase == 0xffe00000 ||
294 port->mapbase == 0xffe08000)
296 return SCIF_TXROOM_MAX - scif_txfill(port);
299 return SCIF2_TXROOM_MAX - scif_txfill(port);
302 static int scif_rxfill(struct uart_port *port)
304 if ((port->mapbase == 0xffe00000) ||
305 (port->mapbase == 0xffe08000)) {
307 return sci_in(port, SCRFDR) & 0xff;
310 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
313 #elif defined(CONFIG_ARCH_SH7372)
314 static int scif_txfill(struct uart_port *port)
316 if (port->type == PORT_SCIFA)
317 return sci_in(port, SCFDR) >> 8;
319 return sci_in(port, SCTFDR);
322 static int scif_txroom(struct uart_port *port)
324 return port->fifosize - scif_txfill(port);
327 static int scif_rxfill(struct uart_port *port)
329 if (port->type == PORT_SCIFA)
330 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
332 return sci_in(port, SCRFDR);
335 static int scif_txfill(struct uart_port *port)
337 return sci_in(port, SCFDR) >> 8;
340 static int scif_txroom(struct uart_port *port)
342 return SCIF_TXROOM_MAX - scif_txfill(port);
345 static int scif_rxfill(struct uart_port *port)
347 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
351 static int sci_txfill(struct uart_port *port)
353 return !(sci_in(port, SCxSR) & SCI_TDRE);
356 static int sci_txroom(struct uart_port *port)
358 return !sci_txfill(port);
361 static int sci_rxfill(struct uart_port *port)
363 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
366 /* ********************************************************************** *
367 * the interrupt related routines *
368 * ********************************************************************** */
370 static void sci_transmit_chars(struct uart_port *port)
372 struct circ_buf *xmit = &port->state->xmit;
373 unsigned int stopped = uart_tx_stopped(port);
374 unsigned short status;
378 status = sci_in(port, SCxSR);
379 if (!(status & SCxSR_TDxE(port))) {
380 ctrl = sci_in(port, SCSCR);
381 if (uart_circ_empty(xmit))
385 sci_out(port, SCSCR, ctrl);
389 if (port->type == PORT_SCI)
390 count = sci_txroom(port);
392 count = scif_txroom(port);
400 } else if (!uart_circ_empty(xmit) && !stopped) {
401 c = xmit->buf[xmit->tail];
402 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
407 sci_out(port, SCxTDR, c);
410 } while (--count > 0);
412 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
414 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
415 uart_write_wakeup(port);
416 if (uart_circ_empty(xmit)) {
419 ctrl = sci_in(port, SCSCR);
421 if (port->type != PORT_SCI) {
422 sci_in(port, SCxSR); /* Dummy read */
423 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
427 sci_out(port, SCSCR, ctrl);
431 /* On SH3, SCIF may read end-of-break as a space->mark char */
432 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
434 static void sci_receive_chars(struct uart_port *port)
436 struct sci_port *sci_port = to_sci_port(port);
437 struct tty_struct *tty = port->state->port.tty;
438 int i, count, copied = 0;
439 unsigned short status;
442 status = sci_in(port, SCxSR);
443 if (!(status & SCxSR_RDxF(port)))
447 if (port->type == PORT_SCI)
448 count = sci_rxfill(port);
450 count = scif_rxfill(port);
452 /* Don't copy more bytes than there is room for in the buffer */
453 count = tty_buffer_request_room(tty, count);
455 /* If for any reason we can't copy more data, we're done! */
459 if (port->type == PORT_SCI) {
460 char c = sci_in(port, SCxRDR);
461 if (uart_handle_sysrq_char(port, c) ||
462 sci_port->break_flag)
465 tty_insert_flip_char(tty, c, TTY_NORMAL);
467 for (i = 0; i < count; i++) {
468 char c = sci_in(port, SCxRDR);
469 status = sci_in(port, SCxSR);
470 #if defined(CONFIG_CPU_SH3)
471 /* Skip "chars" during break */
472 if (sci_port->break_flag) {
474 (status & SCxSR_FER(port))) {
479 /* Nonzero => end-of-break */
480 dev_dbg(port->dev, "debounce<%02x>\n", c);
481 sci_port->break_flag = 0;
488 #endif /* CONFIG_CPU_SH3 */
489 if (uart_handle_sysrq_char(port, c)) {
494 /* Store data and status */
495 if (status & SCxSR_FER(port)) {
497 dev_notice(port->dev, "frame error\n");
498 } else if (status & SCxSR_PER(port)) {
500 dev_notice(port->dev, "parity error\n");
504 tty_insert_flip_char(tty, c, flag);
508 sci_in(port, SCxSR); /* dummy read */
509 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
512 port->icount.rx += count;
516 /* Tell the rest of the system the news. New characters! */
517 tty_flip_buffer_push(tty);
519 sci_in(port, SCxSR); /* dummy read */
520 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
524 #define SCI_BREAK_JIFFIES (HZ/20)
527 * The sci generates interrupts during the break,
528 * 1 per millisecond or so during the break period, for 9600 baud.
529 * So dont bother disabling interrupts.
530 * But dont want more than 1 break event.
531 * Use a kernel timer to periodically poll the rx line until
532 * the break is finished.
534 static inline void sci_schedule_break_timer(struct sci_port *port)
536 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
539 /* Ensure that two consecutive samples find the break over. */
540 static void sci_break_timer(unsigned long data)
542 struct sci_port *port = (struct sci_port *)data;
545 port->enable(&port->port);
547 if (sci_rxd_in(&port->port) == 0) {
548 port->break_flag = 1;
549 sci_schedule_break_timer(port);
550 } else if (port->break_flag == 1) {
552 port->break_flag = 2;
553 sci_schedule_break_timer(port);
555 port->break_flag = 0;
558 port->disable(&port->port);
561 static int sci_handle_errors(struct uart_port *port)
564 unsigned short status = sci_in(port, SCxSR);
565 struct tty_struct *tty = port->state->port.tty;
566 struct sci_port *s = to_sci_port(port);
569 * Handle overruns, if supported.
571 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
572 if (status & (1 << s->cfg->overrun_bit)) {
574 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
577 dev_notice(port->dev, "overrun error");
581 if (status & SCxSR_FER(port)) {
582 if (sci_rxd_in(port) == 0) {
583 /* Notify of BREAK */
584 struct sci_port *sci_port = to_sci_port(port);
586 if (!sci_port->break_flag) {
587 sci_port->break_flag = 1;
588 sci_schedule_break_timer(sci_port);
590 /* Do sysrq handling. */
591 if (uart_handle_break(port))
594 dev_dbg(port->dev, "BREAK detected\n");
596 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
602 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
605 dev_notice(port->dev, "frame error\n");
609 if (status & SCxSR_PER(port)) {
611 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
614 dev_notice(port->dev, "parity error");
618 tty_flip_buffer_push(tty);
623 static int sci_handle_fifo_overrun(struct uart_port *port)
625 struct tty_struct *tty = port->state->port.tty;
626 struct sci_port *s = to_sci_port(port);
630 * XXX: Technically not limited to non-SCIFs, it's simply the
631 * SCLSR check that is for the moment SCIF-specific. This
632 * probably wants to be revisited for SCIFA/B as well as for
633 * factoring in SCI overrun detection.
635 if (port->type != PORT_SCIF)
638 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
639 sci_out(port, SCLSR, 0);
641 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
642 tty_flip_buffer_push(tty);
644 dev_notice(port->dev, "overrun error\n");
651 static int sci_handle_breaks(struct uart_port *port)
654 unsigned short status = sci_in(port, SCxSR);
655 struct tty_struct *tty = port->state->port.tty;
656 struct sci_port *s = to_sci_port(port);
658 if (uart_handle_break(port))
661 if (!s->break_flag && status & SCxSR_BRK(port)) {
662 #if defined(CONFIG_CPU_SH3)
666 /* Notify of BREAK */
667 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
670 dev_dbg(port->dev, "BREAK detected\n");
674 tty_flip_buffer_push(tty);
676 copied += sci_handle_fifo_overrun(port);
681 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
683 #ifdef CONFIG_SERIAL_SH_SCI_DMA
684 struct uart_port *port = ptr;
685 struct sci_port *s = to_sci_port(port);
688 u16 scr = sci_in(port, SCSCR);
689 u16 ssr = sci_in(port, SCxSR);
691 /* Disable future Rx interrupts */
692 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
693 disable_irq_nosync(irq);
698 sci_out(port, SCSCR, scr);
699 /* Clear current interrupt */
700 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
701 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
702 jiffies, s->rx_timeout);
703 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
709 /* I think sci_receive_chars has to be called irrespective
710 * of whether the I_IXOFF is set, otherwise, how is the interrupt
713 sci_receive_chars(ptr);
718 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
720 struct uart_port *port = ptr;
723 spin_lock_irqsave(&port->lock, flags);
724 sci_transmit_chars(port);
725 spin_unlock_irqrestore(&port->lock, flags);
730 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
732 struct uart_port *port = ptr;
735 if (port->type == PORT_SCI) {
736 if (sci_handle_errors(port)) {
737 /* discard character in rx buffer */
739 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
742 sci_handle_fifo_overrun(port);
743 sci_rx_interrupt(irq, ptr);
746 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
748 /* Kick the transmission */
749 sci_tx_interrupt(irq, ptr);
754 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
756 struct uart_port *port = ptr;
759 sci_handle_breaks(port);
760 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
765 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
768 * Not all ports (such as SCIFA) will support REIE. Rather than
769 * special-casing the port type, we check the port initialization
770 * IRQ enable mask to see whether the IRQ is desired at all. If
771 * it's unset, it's logically inferred that there's no point in
774 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
777 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
779 unsigned short ssr_status, scr_status, err_enabled;
780 struct uart_port *port = ptr;
781 struct sci_port *s = to_sci_port(port);
782 irqreturn_t ret = IRQ_NONE;
784 ssr_status = sci_in(port, SCxSR);
785 scr_status = sci_in(port, SCSCR);
786 err_enabled = scr_status & port_rx_irq_mask(port);
789 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
791 ret = sci_tx_interrupt(irq, ptr);
794 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
797 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
798 (scr_status & SCSCR_RIE))
799 ret = sci_rx_interrupt(irq, ptr);
801 /* Error Interrupt */
802 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
803 ret = sci_er_interrupt(irq, ptr);
805 /* Break Interrupt */
806 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
807 ret = sci_br_interrupt(irq, ptr);
813 * Here we define a transition notifier so that we can update all of our
814 * ports' baud rate when the peripheral clock changes.
816 static int sci_notifier(struct notifier_block *self,
817 unsigned long phase, void *p)
819 struct sci_port *sci_port;
822 sci_port = container_of(self, struct sci_port, freq_transition);
824 if ((phase == CPUFREQ_POSTCHANGE) ||
825 (phase == CPUFREQ_RESUMECHANGE)) {
826 struct uart_port *port = &sci_port->port;
828 spin_lock_irqsave(&port->lock, flags);
829 port->uartclk = clk_get_rate(sci_port->iclk);
830 spin_unlock_irqrestore(&port->lock, flags);
836 static void sci_clk_enable(struct uart_port *port)
838 struct sci_port *sci_port = to_sci_port(port);
840 pm_runtime_get_sync(port->dev);
842 clk_enable(sci_port->iclk);
843 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
844 clk_enable(sci_port->fclk);
847 static void sci_clk_disable(struct uart_port *port)
849 struct sci_port *sci_port = to_sci_port(port);
851 clk_disable(sci_port->fclk);
852 clk_disable(sci_port->iclk);
854 pm_runtime_put_sync(port->dev);
857 static int sci_request_irq(struct sci_port *port)
860 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
861 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
864 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
865 "SCI Transmit Data Empty", "SCI Break" };
867 if (port->cfg->irqs[0] == port->cfg->irqs[1]) {
868 if (unlikely(!port->cfg->irqs[0]))
871 if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt,
872 IRQF_DISABLED, "sci", port)) {
873 dev_err(port->port.dev, "Can't allocate IRQ\n");
877 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
878 if (unlikely(!port->cfg->irqs[i]))
881 if (request_irq(port->cfg->irqs[i], handlers[i],
882 IRQF_DISABLED, desc[i], port)) {
883 dev_err(port->port.dev, "Can't allocate IRQ\n");
892 static void sci_free_irq(struct sci_port *port)
896 if (port->cfg->irqs[0] == port->cfg->irqs[1])
897 free_irq(port->cfg->irqs[0], port);
899 for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) {
900 if (!port->cfg->irqs[i])
903 free_irq(port->cfg->irqs[i], port);
908 static unsigned int sci_tx_empty(struct uart_port *port)
910 unsigned short status = sci_in(port, SCxSR);
911 unsigned short in_tx_fifo = scif_txfill(port);
913 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
916 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
918 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
919 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
920 /* If you have signals for DTR and DCD, please implement here. */
923 static unsigned int sci_get_mctrl(struct uart_port *port)
925 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
928 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
931 #ifdef CONFIG_SERIAL_SH_SCI_DMA
932 static void sci_dma_tx_complete(void *arg)
934 struct sci_port *s = arg;
935 struct uart_port *port = &s->port;
936 struct circ_buf *xmit = &port->state->xmit;
939 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
941 spin_lock_irqsave(&port->lock, flags);
943 xmit->tail += sg_dma_len(&s->sg_tx);
944 xmit->tail &= UART_XMIT_SIZE - 1;
946 port->icount.tx += sg_dma_len(&s->sg_tx);
948 async_tx_ack(s->desc_tx);
949 s->cookie_tx = -EINVAL;
952 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
953 uart_write_wakeup(port);
955 if (!uart_circ_empty(xmit)) {
956 schedule_work(&s->work_tx);
957 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
958 u16 ctrl = sci_in(port, SCSCR);
959 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
962 spin_unlock_irqrestore(&port->lock, flags);
965 /* Locking: called with port lock held */
966 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
969 struct uart_port *port = &s->port;
972 room = tty_buffer_request_room(tty, count);
974 if (s->active_rx == s->cookie_rx[0]) {
976 } else if (s->active_rx == s->cookie_rx[1]) {
979 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
984 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
989 for (i = 0; i < room; i++)
990 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
993 port->icount.rx += room;
998 static void sci_dma_rx_complete(void *arg)
1000 struct sci_port *s = arg;
1001 struct uart_port *port = &s->port;
1002 struct tty_struct *tty = port->state->port.tty;
1003 unsigned long flags;
1006 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1008 spin_lock_irqsave(&port->lock, flags);
1010 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1012 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1014 spin_unlock_irqrestore(&port->lock, flags);
1017 tty_flip_buffer_push(tty);
1019 schedule_work(&s->work_rx);
1022 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1024 struct dma_chan *chan = s->chan_rx;
1025 struct uart_port *port = &s->port;
1028 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1029 dma_release_channel(chan);
1030 if (sg_dma_address(&s->sg_rx[0]))
1031 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1032 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1037 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1039 struct dma_chan *chan = s->chan_tx;
1040 struct uart_port *port = &s->port;
1043 s->cookie_tx = -EINVAL;
1044 dma_release_channel(chan);
1049 static void sci_submit_rx(struct sci_port *s)
1051 struct dma_chan *chan = s->chan_rx;
1054 for (i = 0; i < 2; i++) {
1055 struct scatterlist *sg = &s->sg_rx[i];
1056 struct dma_async_tx_descriptor *desc;
1058 desc = chan->device->device_prep_slave_sg(chan,
1059 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1062 s->desc_rx[i] = desc;
1063 desc->callback = sci_dma_rx_complete;
1064 desc->callback_param = s;
1065 s->cookie_rx[i] = desc->tx_submit(desc);
1068 if (!desc || s->cookie_rx[i] < 0) {
1070 async_tx_ack(s->desc_rx[0]);
1071 s->cookie_rx[0] = -EINVAL;
1075 s->cookie_rx[i] = -EINVAL;
1077 dev_warn(s->port.dev,
1078 "failed to re-start DMA, using PIO\n");
1079 sci_rx_dma_release(s, true);
1082 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1083 s->cookie_rx[i], i);
1086 s->active_rx = s->cookie_rx[0];
1088 dma_async_issue_pending(chan);
1091 static void work_fn_rx(struct work_struct *work)
1093 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1094 struct uart_port *port = &s->port;
1095 struct dma_async_tx_descriptor *desc;
1098 if (s->active_rx == s->cookie_rx[0]) {
1100 } else if (s->active_rx == s->cookie_rx[1]) {
1103 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1106 desc = s->desc_rx[new];
1108 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1110 /* Handle incomplete DMA receive */
1111 struct tty_struct *tty = port->state->port.tty;
1112 struct dma_chan *chan = s->chan_rx;
1113 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1115 unsigned long flags;
1118 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1119 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1120 sh_desc->partial, sh_desc->cookie);
1122 spin_lock_irqsave(&port->lock, flags);
1123 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1124 spin_unlock_irqrestore(&port->lock, flags);
1127 tty_flip_buffer_push(tty);
1134 s->cookie_rx[new] = desc->tx_submit(desc);
1135 if (s->cookie_rx[new] < 0) {
1136 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1137 sci_rx_dma_release(s, true);
1141 s->active_rx = s->cookie_rx[!new];
1143 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1144 s->cookie_rx[new], new, s->active_rx);
1147 static void work_fn_tx(struct work_struct *work)
1149 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1150 struct dma_async_tx_descriptor *desc;
1151 struct dma_chan *chan = s->chan_tx;
1152 struct uart_port *port = &s->port;
1153 struct circ_buf *xmit = &port->state->xmit;
1154 struct scatterlist *sg = &s->sg_tx;
1158 * Port xmit buffer is already mapped, and it is one page... Just adjust
1159 * offsets and lengths. Since it is a circular buffer, we have to
1160 * transmit till the end, and then the rest. Take the port lock to get a
1161 * consistent xmit buffer state.
1163 spin_lock_irq(&port->lock);
1164 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1165 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1167 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1168 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1169 spin_unlock_irq(&port->lock);
1171 BUG_ON(!sg_dma_len(sg));
1173 desc = chan->device->device_prep_slave_sg(chan,
1174 sg, s->sg_len_tx, DMA_TO_DEVICE,
1175 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1178 sci_tx_dma_release(s, true);
1182 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1184 spin_lock_irq(&port->lock);
1186 desc->callback = sci_dma_tx_complete;
1187 desc->callback_param = s;
1188 spin_unlock_irq(&port->lock);
1189 s->cookie_tx = desc->tx_submit(desc);
1190 if (s->cookie_tx < 0) {
1191 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1193 sci_tx_dma_release(s, true);
1197 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1198 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1200 dma_async_issue_pending(chan);
1204 static void sci_start_tx(struct uart_port *port)
1206 struct sci_port *s = to_sci_port(port);
1207 unsigned short ctrl;
1209 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1210 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1211 u16 new, scr = sci_in(port, SCSCR);
1215 new = scr & ~0x8000;
1217 sci_out(port, SCSCR, new);
1220 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1222 schedule_work(&s->work_tx);
1225 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1226 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1227 ctrl = sci_in(port, SCSCR);
1228 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
1232 static void sci_stop_tx(struct uart_port *port)
1234 unsigned short ctrl;
1236 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1237 ctrl = sci_in(port, SCSCR);
1239 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1244 sci_out(port, SCSCR, ctrl);
1247 static void sci_start_rx(struct uart_port *port)
1249 unsigned short ctrl;
1251 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1253 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1256 sci_out(port, SCSCR, ctrl);
1259 static void sci_stop_rx(struct uart_port *port)
1261 unsigned short ctrl;
1263 ctrl = sci_in(port, SCSCR);
1265 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1268 ctrl &= ~port_rx_irq_mask(port);
1270 sci_out(port, SCSCR, ctrl);
1273 static void sci_enable_ms(struct uart_port *port)
1275 /* Nothing here yet .. */
1278 static void sci_break_ctl(struct uart_port *port, int break_state)
1280 /* Nothing here yet .. */
1283 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1284 static bool filter(struct dma_chan *chan, void *slave)
1286 struct sh_dmae_slave *param = slave;
1288 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1291 if (param->dma_dev == chan->device->dev) {
1292 chan->private = param;
1299 static void rx_timer_fn(unsigned long arg)
1301 struct sci_port *s = (struct sci_port *)arg;
1302 struct uart_port *port = &s->port;
1303 u16 scr = sci_in(port, SCSCR);
1305 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1307 enable_irq(s->cfg->irqs[1]);
1309 sci_out(port, SCSCR, scr | SCSCR_RIE);
1310 dev_dbg(port->dev, "DMA Rx timed out\n");
1311 schedule_work(&s->work_rx);
1314 static void sci_request_dma(struct uart_port *port)
1316 struct sci_port *s = to_sci_port(port);
1317 struct sh_dmae_slave *param;
1318 struct dma_chan *chan;
1319 dma_cap_mask_t mask;
1322 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1323 port->line, s->cfg->dma_dev);
1325 if (!s->cfg->dma_dev)
1329 dma_cap_set(DMA_SLAVE, mask);
1331 param = &s->param_tx;
1333 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1334 param->slave_id = s->cfg->dma_slave_tx;
1335 param->dma_dev = s->cfg->dma_dev;
1337 s->cookie_tx = -EINVAL;
1338 chan = dma_request_channel(mask, filter, param);
1339 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1342 sg_init_table(&s->sg_tx, 1);
1343 /* UART circular tx buffer is an aligned page. */
1344 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1345 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1346 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1347 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1349 sci_tx_dma_release(s, false);
1351 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1352 sg_dma_len(&s->sg_tx),
1353 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1355 s->sg_len_tx = nent;
1357 INIT_WORK(&s->work_tx, work_fn_tx);
1360 param = &s->param_rx;
1362 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1363 param->slave_id = s->cfg->dma_slave_rx;
1364 param->dma_dev = s->cfg->dma_dev;
1366 chan = dma_request_channel(mask, filter, param);
1367 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1375 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1376 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1377 &dma[0], GFP_KERNEL);
1381 "failed to allocate dma buffer, using PIO\n");
1382 sci_rx_dma_release(s, true);
1386 buf[1] = buf[0] + s->buf_len_rx;
1387 dma[1] = dma[0] + s->buf_len_rx;
1389 for (i = 0; i < 2; i++) {
1390 struct scatterlist *sg = &s->sg_rx[i];
1392 sg_init_table(sg, 1);
1393 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1394 (int)buf[i] & ~PAGE_MASK);
1395 sg_dma_address(sg) = dma[i];
1398 INIT_WORK(&s->work_rx, work_fn_rx);
1399 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1405 static void sci_free_dma(struct uart_port *port)
1407 struct sci_port *s = to_sci_port(port);
1409 if (!s->cfg->dma_dev)
1413 sci_tx_dma_release(s, false);
1415 sci_rx_dma_release(s, false);
1418 static inline void sci_request_dma(struct uart_port *port)
1422 static inline void sci_free_dma(struct uart_port *port)
1427 static int sci_startup(struct uart_port *port)
1429 struct sci_port *s = to_sci_port(port);
1432 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1437 ret = sci_request_irq(s);
1438 if (unlikely(ret < 0))
1441 sci_request_dma(port);
1449 static void sci_shutdown(struct uart_port *port)
1451 struct sci_port *s = to_sci_port(port);
1453 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1465 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1470 return ((freq + 16 * bps) / (16 * bps) - 1);
1472 return ((freq + 16 * bps) / (32 * bps) - 1);
1474 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1476 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1478 return (((freq * 1000 / 32) / bps) - 1);
1481 /* Warn, but use a safe default */
1484 return ((freq + 16 * bps) / (32 * bps) - 1);
1487 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1488 struct ktermios *old)
1490 struct sci_port *s = to_sci_port(port);
1491 unsigned int status, baud, smr_val, max_baud;
1496 * earlyprintk comes here early on with port->uartclk set to zero.
1497 * the clock framework is not up and running at this point so here
1498 * we assume that 115200 is the maximum baud rate. please note that
1499 * the baud rate is not programmed during earlyprintk - it is assumed
1500 * that the previous boot loader has enabled required clocks and
1501 * setup the baud rate generator hardware for us already.
1503 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1505 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1506 if (likely(baud && port->uartclk))
1507 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
1513 status = sci_in(port, SCxSR);
1514 } while (!(status & SCxSR_TEND(port)));
1516 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1518 if (port->type != PORT_SCI)
1519 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1521 smr_val = sci_in(port, SCSMR) & 3;
1523 if ((termios->c_cflag & CSIZE) == CS7)
1525 if (termios->c_cflag & PARENB)
1527 if (termios->c_cflag & PARODD)
1529 if (termios->c_cflag & CSTOPB)
1532 uart_update_timeout(port, termios->c_cflag, baud);
1534 sci_out(port, SCSMR, smr_val);
1536 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1541 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1544 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1546 sci_out(port, SCBRR, t);
1547 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1550 sci_init_pins(port, termios->c_cflag);
1551 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
1553 sci_out(port, SCSCR, s->cfg->scscr);
1555 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1557 * Calculate delay for 1.5 DMA buffers: see
1558 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1559 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1560 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1561 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1562 * sizes), but it has been found out experimentally, that this is not
1563 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1564 * as a minimum seem to work perfectly.
1567 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1570 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1571 s->rx_timeout * 1000 / HZ, port->timeout);
1572 if (s->rx_timeout < msecs_to_jiffies(20))
1573 s->rx_timeout = msecs_to_jiffies(20);
1577 if ((termios->c_cflag & CREAD) != 0)
1584 static const char *sci_type(struct uart_port *port)
1586 switch (port->type) {
1602 static inline unsigned long sci_port_size(struct uart_port *port)
1605 * Pick an arbitrary size that encapsulates all of the base
1606 * registers by default. This can be optimized later, or derived
1607 * from platform resource data at such a time that ports begin to
1608 * behave more erratically.
1613 static int sci_remap_port(struct uart_port *port)
1615 unsigned long size = sci_port_size(port);
1618 * Nothing to do if there's already an established membase.
1623 if (port->flags & UPF_IOREMAP) {
1624 port->membase = ioremap_nocache(port->mapbase, size);
1625 if (unlikely(!port->membase)) {
1626 dev_err(port->dev, "can't remap port#%d\n", port->line);
1631 * For the simple (and majority of) cases where we don't
1632 * need to do any remapping, just cast the cookie
1635 port->membase = (void __iomem *)port->mapbase;
1641 static void sci_release_port(struct uart_port *port)
1643 if (port->flags & UPF_IOREMAP) {
1644 iounmap(port->membase);
1645 port->membase = NULL;
1648 release_mem_region(port->mapbase, sci_port_size(port));
1651 static int sci_request_port(struct uart_port *port)
1653 unsigned long size = sci_port_size(port);
1654 struct resource *res;
1657 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
1658 if (unlikely(res == NULL))
1661 ret = sci_remap_port(port);
1662 if (unlikely(ret != 0)) {
1663 release_resource(res);
1670 static void sci_config_port(struct uart_port *port, int flags)
1672 if (flags & UART_CONFIG_TYPE) {
1673 struct sci_port *sport = to_sci_port(port);
1675 port->type = sport->cfg->type;
1676 sci_request_port(port);
1680 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1682 struct sci_port *s = to_sci_port(port);
1684 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1686 if (ser->baud_base < 2400)
1687 /* No paper tape reader for Mitch.. */
1693 static struct uart_ops sci_uart_ops = {
1694 .tx_empty = sci_tx_empty,
1695 .set_mctrl = sci_set_mctrl,
1696 .get_mctrl = sci_get_mctrl,
1697 .start_tx = sci_start_tx,
1698 .stop_tx = sci_stop_tx,
1699 .stop_rx = sci_stop_rx,
1700 .enable_ms = sci_enable_ms,
1701 .break_ctl = sci_break_ctl,
1702 .startup = sci_startup,
1703 .shutdown = sci_shutdown,
1704 .set_termios = sci_set_termios,
1706 .release_port = sci_release_port,
1707 .request_port = sci_request_port,
1708 .config_port = sci_config_port,
1709 .verify_port = sci_verify_port,
1710 #ifdef CONFIG_CONSOLE_POLL
1711 .poll_get_char = sci_poll_get_char,
1712 .poll_put_char = sci_poll_put_char,
1716 static int __devinit sci_init_single(struct platform_device *dev,
1717 struct sci_port *sci_port,
1719 struct plat_sci_port *p)
1721 struct uart_port *port = &sci_port->port;
1723 port->ops = &sci_uart_ops;
1724 port->iotype = UPIO_MEM;
1729 port->fifosize = 256;
1732 port->fifosize = 64;
1735 port->fifosize = 16;
1743 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1744 if (IS_ERR(sci_port->iclk)) {
1745 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1746 if (IS_ERR(sci_port->iclk)) {
1747 dev_err(&dev->dev, "can't get iclk\n");
1748 return PTR_ERR(sci_port->iclk);
1753 * The function clock is optional, ignore it if we can't
1756 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1757 if (IS_ERR(sci_port->fclk))
1758 sci_port->fclk = NULL;
1760 sci_port->enable = sci_clk_enable;
1761 sci_port->disable = sci_clk_disable;
1762 port->dev = &dev->dev;
1764 pm_runtime_enable(&dev->dev);
1767 sci_port->break_timer.data = (unsigned long)sci_port;
1768 sci_port->break_timer.function = sci_break_timer;
1769 init_timer(&sci_port->break_timer);
1772 * Establish some sensible defaults for the error detection.
1775 p->error_mask = (p->type == PORT_SCI) ?
1776 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
1779 * Establish sensible defaults for the overrun detection, unless
1780 * the part has explicitly disabled support for it.
1782 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
1783 if (p->type == PORT_SCI)
1785 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
1791 * Make the error mask inclusive of overrun detection, if
1794 p->error_mask |= (1 << p->overrun_bit);
1799 port->mapbase = p->mapbase;
1800 port->type = p->type;
1801 port->flags = p->flags;
1804 * The UART port needs an IRQ value, so we peg this to the TX IRQ
1805 * for the multi-IRQ ports, which is where we are primarily
1806 * concerned with the shutdown path synchronization.
1808 * For the muxed case there's nothing more to do.
1810 port->irq = p->irqs[SCIx_RXI_IRQ];
1813 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
1814 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1819 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1820 static void serial_console_putchar(struct uart_port *port, int ch)
1822 sci_poll_put_char(port, ch);
1826 * Print a string to the serial port trying not to disturb
1827 * any possible real use of the port...
1829 static void serial_console_write(struct console *co, const char *s,
1832 struct sci_port *sci_port = &sci_ports[co->index];
1833 struct uart_port *port = &sci_port->port;
1834 unsigned short bits;
1836 if (sci_port->enable)
1837 sci_port->enable(port);
1839 uart_console_write(port, s, count, serial_console_putchar);
1841 /* wait until fifo is empty and last bit has been transmitted */
1842 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1843 while ((sci_in(port, SCxSR) & bits) != bits)
1846 if (sci_port->disable)
1847 sci_port->disable(port);
1850 static int __devinit serial_console_setup(struct console *co, char *options)
1852 struct sci_port *sci_port;
1853 struct uart_port *port;
1861 * Refuse to handle any bogus ports.
1863 if (co->index < 0 || co->index >= SCI_NPORTS)
1866 sci_port = &sci_ports[co->index];
1867 port = &sci_port->port;
1870 * Refuse to handle uninitialized ports.
1875 ret = sci_remap_port(port);
1876 if (unlikely(ret != 0))
1879 if (sci_port->enable)
1880 sci_port->enable(port);
1883 uart_parse_options(options, &baud, &parity, &bits, &flow);
1885 /* TODO: disable clock */
1886 return uart_set_options(port, co, baud, parity, bits, flow);
1889 static struct console serial_console = {
1891 .device = uart_console_device,
1892 .write = serial_console_write,
1893 .setup = serial_console_setup,
1894 .flags = CON_PRINTBUFFER,
1896 .data = &sci_uart_driver,
1899 static struct console early_serial_console = {
1900 .name = "early_ttySC",
1901 .write = serial_console_write,
1902 .flags = CON_PRINTBUFFER,
1906 static char early_serial_buf[32];
1908 static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
1910 struct plat_sci_port *cfg = pdev->dev.platform_data;
1912 if (early_serial_console.data)
1915 early_serial_console.index = pdev->id;
1917 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
1919 serial_console_setup(&early_serial_console, early_serial_buf);
1921 if (!strstr(early_serial_buf, "keep"))
1922 early_serial_console.flags |= CON_BOOT;
1924 register_console(&early_serial_console);
1928 #define SCI_CONSOLE (&serial_console)
1931 static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
1936 #define SCI_CONSOLE NULL
1938 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1940 static char banner[] __initdata =
1941 KERN_INFO "SuperH SCI(F) driver initialized\n";
1943 static struct uart_driver sci_uart_driver = {
1944 .owner = THIS_MODULE,
1945 .driver_name = "sci",
1946 .dev_name = "ttySC",
1948 .minor = SCI_MINOR_START,
1950 .cons = SCI_CONSOLE,
1953 static int sci_remove(struct platform_device *dev)
1955 struct sci_port *port = platform_get_drvdata(dev);
1957 cpufreq_unregister_notifier(&port->freq_transition,
1958 CPUFREQ_TRANSITION_NOTIFIER);
1960 uart_remove_one_port(&sci_uart_driver, &port->port);
1962 clk_put(port->iclk);
1963 clk_put(port->fclk);
1965 pm_runtime_disable(&dev->dev);
1969 static int __devinit sci_probe_single(struct platform_device *dev,
1971 struct plat_sci_port *p,
1972 struct sci_port *sciport)
1977 if (unlikely(index >= SCI_NPORTS)) {
1978 dev_notice(&dev->dev, "Attempting to register port "
1979 "%d when only %d are available.\n",
1980 index+1, SCI_NPORTS);
1981 dev_notice(&dev->dev, "Consider bumping "
1982 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1986 ret = sci_init_single(dev, sciport, index, p);
1990 return uart_add_one_port(&sci_uart_driver, &sciport->port);
1993 static int __devinit sci_probe(struct platform_device *dev)
1995 struct plat_sci_port *p = dev->dev.platform_data;
1996 struct sci_port *sp = &sci_ports[dev->id];
2000 * If we've come here via earlyprintk initialization, head off to
2001 * the special early probe. We don't have sufficient device state
2002 * to make it beyond this yet.
2004 if (is_early_platform_device(dev))
2005 return sci_probe_earlyprintk(dev);
2007 platform_set_drvdata(dev, sp);
2009 ret = sci_probe_single(dev, dev->id, p, sp);
2013 sp->freq_transition.notifier_call = sci_notifier;
2015 ret = cpufreq_register_notifier(&sp->freq_transition,
2016 CPUFREQ_TRANSITION_NOTIFIER);
2017 if (unlikely(ret < 0))
2020 #ifdef CONFIG_SH_STANDARD_BIOS
2021 sh_bios_gdb_detach();
2031 static int sci_suspend(struct device *dev)
2033 struct sci_port *sport = dev_get_drvdata(dev);
2036 uart_suspend_port(&sci_uart_driver, &sport->port);
2041 static int sci_resume(struct device *dev)
2043 struct sci_port *sport = dev_get_drvdata(dev);
2046 uart_resume_port(&sci_uart_driver, &sport->port);
2051 static const struct dev_pm_ops sci_dev_pm_ops = {
2052 .suspend = sci_suspend,
2053 .resume = sci_resume,
2056 static struct platform_driver sci_driver = {
2058 .remove = sci_remove,
2061 .owner = THIS_MODULE,
2062 .pm = &sci_dev_pm_ops,
2066 static int __init sci_init(void)
2072 ret = uart_register_driver(&sci_uart_driver);
2073 if (likely(ret == 0)) {
2074 ret = platform_driver_register(&sci_driver);
2076 uart_unregister_driver(&sci_uart_driver);
2082 static void __exit sci_exit(void)
2084 platform_driver_unregister(&sci_driver);
2085 uart_unregister_driver(&sci_uart_driver);
2088 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2089 early_platform_init_buffer("earlyprintk", &sci_driver,
2090 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2092 module_init(sci_init);
2093 module_exit(sci_exit);
2095 MODULE_LICENSE("GPL");
2096 MODULE_ALIAS("platform:sh-sci");