2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/sysrq.h>
36 #include <linux/ioport.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/console.h>
41 #include <linux/platform_device.h>
42 #include <linux/serial_sci.h>
43 #include <linux/notifier.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/cpufreq.h>
46 #include <linux/clk.h>
47 #include <linux/ctype.h>
48 #include <linux/err.h>
49 #include <linux/dmaengine.h>
50 #include <linux/scatterlist.h>
51 #include <linux/slab.h>
54 #include <asm/sh_bios.h>
60 struct uart_port port;
62 /* Platform configuration */
63 struct plat_sci_port *cfg;
65 /* Port enable callback */
66 void (*enable)(struct uart_port *port);
68 /* Port disable callback */
69 void (*disable)(struct uart_port *port);
72 struct timer_list break_timer;
80 struct dma_chan *chan_tx;
81 struct dma_chan *chan_rx;
83 #ifdef CONFIG_SERIAL_SH_SCI_DMA
84 struct dma_async_tx_descriptor *desc_tx;
85 struct dma_async_tx_descriptor *desc_rx[2];
86 dma_cookie_t cookie_tx;
87 dma_cookie_t cookie_rx[2];
88 dma_cookie_t active_rx;
89 struct scatterlist sg_tx;
90 unsigned int sg_len_tx;
91 struct scatterlist sg_rx[2];
93 struct sh_dmae_slave param_tx;
94 struct sh_dmae_slave param_rx;
95 struct work_struct work_tx;
96 struct work_struct work_rx;
97 struct timer_list rx_timer;
98 unsigned int rx_timeout;
101 struct notifier_block freq_transition;
104 /* Function prototypes */
105 static void sci_start_tx(struct uart_port *port);
106 static void sci_stop_tx(struct uart_port *port);
107 static void sci_start_rx(struct uart_port *port);
109 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
111 static struct sci_port sci_ports[SCI_NPORTS];
112 static struct uart_driver sci_uart_driver;
114 static inline struct sci_port *
115 to_sci_port(struct uart_port *uart)
117 return container_of(uart, struct sci_port, port);
120 struct plat_sci_reg {
124 /* Helper for invalidating specific entries of an inherited map. */
125 #define sci_reg_invalid { .offset = 0, .size = 0 }
127 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
128 [SCIx_PROBE_REGTYPE] = {
129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
133 * Common SCI definitions, dependent on the port's regshift
136 [SCIx_SCI_REGTYPE] = {
137 [SCSMR] = { 0x00, 8 },
138 [SCBRR] = { 0x01, 8 },
139 [SCSCR] = { 0x02, 8 },
140 [SCxTDR] = { 0x03, 8 },
141 [SCxSR] = { 0x04, 8 },
142 [SCxRDR] = { 0x05, 8 },
143 [SCFCR] = sci_reg_invalid,
144 [SCFDR] = sci_reg_invalid,
145 [SCTFDR] = sci_reg_invalid,
146 [SCRFDR] = sci_reg_invalid,
147 [SCSPTR] = sci_reg_invalid,
148 [SCLSR] = sci_reg_invalid,
152 * Common definitions for legacy IrDA ports, dependent on
155 [SCIx_IRDA_REGTYPE] = {
156 [SCSMR] = { 0x00, 8 },
157 [SCBRR] = { 0x01, 8 },
158 [SCSCR] = { 0x02, 8 },
159 [SCxTDR] = { 0x03, 8 },
160 [SCxSR] = { 0x04, 8 },
161 [SCxRDR] = { 0x05, 8 },
162 [SCFCR] = { 0x06, 8 },
163 [SCFDR] = { 0x07, 16 },
164 [SCTFDR] = sci_reg_invalid,
165 [SCRFDR] = sci_reg_invalid,
166 [SCSPTR] = sci_reg_invalid,
167 [SCLSR] = sci_reg_invalid,
171 * Common SCIFA definitions.
173 [SCIx_SCIFA_REGTYPE] = {
174 [SCSMR] = { 0x00, 16 },
175 [SCBRR] = { 0x04, 8 },
176 [SCSCR] = { 0x08, 16 },
177 [SCxTDR] = { 0x20, 8 },
178 [SCxSR] = { 0x14, 16 },
179 [SCxRDR] = { 0x24, 8 },
180 [SCFCR] = { 0x18, 16 },
181 [SCFDR] = { 0x1c, 16 },
182 [SCTFDR] = sci_reg_invalid,
183 [SCRFDR] = sci_reg_invalid,
184 [SCSPTR] = sci_reg_invalid,
185 [SCLSR] = sci_reg_invalid,
189 * Common SCIFB definitions.
191 [SCIx_SCIFB_REGTYPE] = {
192 [SCSMR] = { 0x00, 16 },
193 [SCBRR] = { 0x04, 8 },
194 [SCSCR] = { 0x08, 16 },
195 [SCxTDR] = { 0x40, 8 },
196 [SCxSR] = { 0x14, 16 },
197 [SCxRDR] = { 0x60, 8 },
198 [SCFCR] = { 0x18, 16 },
199 [SCFDR] = { 0x1c, 16 },
200 [SCTFDR] = sci_reg_invalid,
201 [SCRFDR] = sci_reg_invalid,
202 [SCSPTR] = sci_reg_invalid,
203 [SCLSR] = sci_reg_invalid,
207 * Common SH-3 SCIF definitions.
209 [SCIx_SH3_SCIF_REGTYPE] = {
210 [SCSMR] = { 0x00, 8 },
211 [SCBRR] = { 0x02, 8 },
212 [SCSCR] = { 0x04, 8 },
213 [SCxTDR] = { 0x06, 8 },
214 [SCxSR] = { 0x08, 16 },
215 [SCxRDR] = { 0x0a, 8 },
216 [SCFCR] = { 0x0c, 8 },
217 [SCFDR] = { 0x0e, 16 },
218 [SCTFDR] = sci_reg_invalid,
219 [SCRFDR] = sci_reg_invalid,
220 [SCSPTR] = sci_reg_invalid,
221 [SCLSR] = sci_reg_invalid,
225 * Common SH-4(A) SCIF(B) definitions.
227 [SCIx_SH4_SCIF_REGTYPE] = {
228 [SCSMR] = { 0x00, 16 },
229 [SCBRR] = { 0x04, 8 },
230 [SCSCR] = { 0x08, 16 },
231 [SCxTDR] = { 0x0c, 8 },
232 [SCxSR] = { 0x10, 16 },
233 [SCxRDR] = { 0x14, 8 },
234 [SCFCR] = { 0x18, 16 },
235 [SCFDR] = { 0x1c, 16 },
236 [SCTFDR] = sci_reg_invalid,
237 [SCRFDR] = sci_reg_invalid,
238 [SCSPTR] = { 0x20, 16 },
239 [SCLSR] = { 0x24, 16 },
243 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
246 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x0c, 8 },
251 [SCxSR] = { 0x10, 16 },
252 [SCxRDR] = { 0x14, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCFDR] = { 0x1c, 16 },
255 [SCTFDR] = sci_reg_invalid,
256 [SCRFDR] = sci_reg_invalid,
257 [SCSPTR] = sci_reg_invalid,
258 [SCLSR] = { 0x24, 16 },
262 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
265 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
266 [SCSMR] = { 0x00, 16 },
267 [SCBRR] = { 0x04, 8 },
268 [SCSCR] = { 0x08, 16 },
269 [SCxTDR] = { 0x0c, 8 },
270 [SCxSR] = { 0x10, 16 },
271 [SCxRDR] = { 0x14, 8 },
272 [SCFCR] = { 0x18, 16 },
273 [SCFDR] = { 0x1c, 16 },
274 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
275 [SCRFDR] = { 0x20, 16 },
276 [SCSPTR] = { 0x24, 16 },
277 [SCLSR] = { 0x28, 16 },
281 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
284 [SCIx_SH7705_SCIF_REGTYPE] = {
285 [SCSMR] = { 0x00, 16 },
286 [SCBRR] = { 0x04, 8 },
287 [SCSCR] = { 0x08, 16 },
288 [SCxTDR] = { 0x20, 8 },
289 [SCxSR] = { 0x14, 16 },
290 [SCxRDR] = { 0x24, 8 },
291 [SCFCR] = { 0x18, 16 },
292 [SCFDR] = { 0x1c, 16 },
293 [SCTFDR] = sci_reg_invalid,
294 [SCRFDR] = sci_reg_invalid,
295 [SCSPTR] = sci_reg_invalid,
296 [SCLSR] = sci_reg_invalid,
300 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
303 * The "offset" here is rather misleading, in that it refers to an enum
304 * value relative to the port mapping rather than the fixed offset
305 * itself, which needs to be manually retrieved from the platform's
306 * register map for the given port.
308 static unsigned int sci_serial_in(struct uart_port *p, int offset)
310 struct plat_sci_reg *reg = sci_getreg(p, offset);
313 return ioread8(p->membase + (reg->offset << p->regshift));
314 else if (reg->size == 16)
315 return ioread16(p->membase + (reg->offset << p->regshift));
317 WARN(1, "Invalid register access\n");
322 static void sci_serial_out(struct uart_port *p, int offset, int value)
324 struct plat_sci_reg *reg = sci_getreg(p, offset);
327 iowrite8(value, p->membase + (reg->offset << p->regshift));
328 else if (reg->size == 16)
329 iowrite16(value, p->membase + (reg->offset << p->regshift));
331 WARN(1, "Invalid register access\n");
334 #define sci_in(up, offset) (up->serial_in(up, offset))
335 #define sci_out(up, offset, value) (up->serial_out(up, offset, value))
337 static int sci_probe_regmap(struct plat_sci_port *cfg)
341 cfg->regtype = SCIx_SCI_REGTYPE;
344 cfg->regtype = SCIx_IRDA_REGTYPE;
347 cfg->regtype = SCIx_SCIFA_REGTYPE;
350 cfg->regtype = SCIx_SCIFB_REGTYPE;
354 * The SH-4 is a bit of a misnomer here, although that's
355 * where this particular port layout originated. This
356 * configuration (or some slight variation thereof)
357 * remains the dominant model for all SCIFs.
359 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
362 printk(KERN_ERR "Can't probe register map for given port\n");
369 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
371 #ifdef CONFIG_CONSOLE_POLL
372 static int sci_poll_get_char(struct uart_port *port)
374 unsigned short status;
378 status = sci_in(port, SCxSR);
379 if (status & SCxSR_ERRORS(port)) {
380 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
386 if (!(status & SCxSR_RDxF(port)))
389 c = sci_in(port, SCxRDR);
393 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
399 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
401 unsigned short status;
404 status = sci_in(port, SCxSR);
405 } while (!(status & SCxSR_TDxE(port)));
407 sci_out(port, SCxTDR, c);
408 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
410 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
412 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
414 struct sci_port *s = to_sci_port(port);
415 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
418 * Use port-specific handler if provided.
420 if (s->cfg->ops && s->cfg->ops->init_pins) {
421 s->cfg->ops->init_pins(port, cflag);
426 * For the generic path SCSPTR is necessary. Bail out if that's
432 if (!(cflag & CRTSCTS))
433 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */
436 static int sci_txfill(struct uart_port *port)
438 struct plat_sci_reg *reg;
440 reg = sci_getreg(port, SCTFDR);
442 return sci_in(port, SCTFDR) & 0xff;
444 reg = sci_getreg(port, SCFDR);
446 return sci_in(port, SCFDR) >> 8;
448 return !(sci_in(port, SCxSR) & SCI_TDRE);
451 static int sci_txroom(struct uart_port *port)
453 return port->fifosize - sci_txfill(port);
456 static int sci_rxfill(struct uart_port *port)
458 struct plat_sci_reg *reg;
460 reg = sci_getreg(port, SCRFDR);
462 return sci_in(port, SCRFDR) & 0xff;
464 reg = sci_getreg(port, SCFDR);
466 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1);
468 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
472 * SCI helper for checking the state of the muxed port/RXD pins.
474 static inline int sci_rxd_in(struct uart_port *port)
476 struct sci_port *s = to_sci_port(port);
478 if (s->cfg->port_reg <= 0)
481 return !!__raw_readb(s->cfg->port_reg);
484 /* ********************************************************************** *
485 * the interrupt related routines *
486 * ********************************************************************** */
488 static void sci_transmit_chars(struct uart_port *port)
490 struct circ_buf *xmit = &port->state->xmit;
491 unsigned int stopped = uart_tx_stopped(port);
492 unsigned short status;
496 status = sci_in(port, SCxSR);
497 if (!(status & SCxSR_TDxE(port))) {
498 ctrl = sci_in(port, SCSCR);
499 if (uart_circ_empty(xmit))
503 sci_out(port, SCSCR, ctrl);
507 count = sci_txroom(port);
515 } else if (!uart_circ_empty(xmit) && !stopped) {
516 c = xmit->buf[xmit->tail];
517 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
522 sci_out(port, SCxTDR, c);
525 } while (--count > 0);
527 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
529 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
530 uart_write_wakeup(port);
531 if (uart_circ_empty(xmit)) {
534 ctrl = sci_in(port, SCSCR);
536 if (port->type != PORT_SCI) {
537 sci_in(port, SCxSR); /* Dummy read */
538 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
542 sci_out(port, SCSCR, ctrl);
546 /* On SH3, SCIF may read end-of-break as a space->mark char */
547 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
549 static void sci_receive_chars(struct uart_port *port)
551 struct sci_port *sci_port = to_sci_port(port);
552 struct tty_struct *tty = port->state->port.tty;
553 int i, count, copied = 0;
554 unsigned short status;
557 status = sci_in(port, SCxSR);
558 if (!(status & SCxSR_RDxF(port)))
562 /* Don't copy more bytes than there is room for in the buffer */
563 count = tty_buffer_request_room(tty, sci_rxfill(port));
565 /* If for any reason we can't copy more data, we're done! */
569 if (port->type == PORT_SCI) {
570 char c = sci_in(port, SCxRDR);
571 if (uart_handle_sysrq_char(port, c) ||
572 sci_port->break_flag)
575 tty_insert_flip_char(tty, c, TTY_NORMAL);
577 for (i = 0; i < count; i++) {
578 char c = sci_in(port, SCxRDR);
579 status = sci_in(port, SCxSR);
580 #if defined(CONFIG_CPU_SH3)
581 /* Skip "chars" during break */
582 if (sci_port->break_flag) {
584 (status & SCxSR_FER(port))) {
589 /* Nonzero => end-of-break */
590 dev_dbg(port->dev, "debounce<%02x>\n", c);
591 sci_port->break_flag = 0;
598 #endif /* CONFIG_CPU_SH3 */
599 if (uart_handle_sysrq_char(port, c)) {
604 /* Store data and status */
605 if (status & SCxSR_FER(port)) {
607 dev_notice(port->dev, "frame error\n");
608 } else if (status & SCxSR_PER(port)) {
610 dev_notice(port->dev, "parity error\n");
614 tty_insert_flip_char(tty, c, flag);
618 sci_in(port, SCxSR); /* dummy read */
619 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
622 port->icount.rx += count;
626 /* Tell the rest of the system the news. New characters! */
627 tty_flip_buffer_push(tty);
629 sci_in(port, SCxSR); /* dummy read */
630 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
634 #define SCI_BREAK_JIFFIES (HZ/20)
637 * The sci generates interrupts during the break,
638 * 1 per millisecond or so during the break period, for 9600 baud.
639 * So dont bother disabling interrupts.
640 * But dont want more than 1 break event.
641 * Use a kernel timer to periodically poll the rx line until
642 * the break is finished.
644 static inline void sci_schedule_break_timer(struct sci_port *port)
646 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
649 /* Ensure that two consecutive samples find the break over. */
650 static void sci_break_timer(unsigned long data)
652 struct sci_port *port = (struct sci_port *)data;
655 port->enable(&port->port);
657 if (sci_rxd_in(&port->port) == 0) {
658 port->break_flag = 1;
659 sci_schedule_break_timer(port);
660 } else if (port->break_flag == 1) {
662 port->break_flag = 2;
663 sci_schedule_break_timer(port);
665 port->break_flag = 0;
668 port->disable(&port->port);
671 static int sci_handle_errors(struct uart_port *port)
674 unsigned short status = sci_in(port, SCxSR);
675 struct tty_struct *tty = port->state->port.tty;
676 struct sci_port *s = to_sci_port(port);
679 * Handle overruns, if supported.
681 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
682 if (status & (1 << s->cfg->overrun_bit)) {
684 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
687 dev_notice(port->dev, "overrun error");
691 if (status & SCxSR_FER(port)) {
692 if (sci_rxd_in(port) == 0) {
693 /* Notify of BREAK */
694 struct sci_port *sci_port = to_sci_port(port);
696 if (!sci_port->break_flag) {
697 sci_port->break_flag = 1;
698 sci_schedule_break_timer(sci_port);
700 /* Do sysrq handling. */
701 if (uart_handle_break(port))
704 dev_dbg(port->dev, "BREAK detected\n");
706 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
712 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
715 dev_notice(port->dev, "frame error\n");
719 if (status & SCxSR_PER(port)) {
721 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
724 dev_notice(port->dev, "parity error");
728 tty_flip_buffer_push(tty);
733 static int sci_handle_fifo_overrun(struct uart_port *port)
735 struct tty_struct *tty = port->state->port.tty;
736 struct sci_port *s = to_sci_port(port);
737 struct plat_sci_reg *reg;
740 reg = sci_getreg(port, SCLSR);
744 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
745 sci_out(port, SCLSR, 0);
747 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
748 tty_flip_buffer_push(tty);
750 dev_notice(port->dev, "overrun error\n");
757 static int sci_handle_breaks(struct uart_port *port)
760 unsigned short status = sci_in(port, SCxSR);
761 struct tty_struct *tty = port->state->port.tty;
762 struct sci_port *s = to_sci_port(port);
764 if (uart_handle_break(port))
767 if (!s->break_flag && status & SCxSR_BRK(port)) {
768 #if defined(CONFIG_CPU_SH3)
772 /* Notify of BREAK */
773 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
776 dev_dbg(port->dev, "BREAK detected\n");
780 tty_flip_buffer_push(tty);
782 copied += sci_handle_fifo_overrun(port);
787 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
789 #ifdef CONFIG_SERIAL_SH_SCI_DMA
790 struct uart_port *port = ptr;
791 struct sci_port *s = to_sci_port(port);
794 u16 scr = sci_in(port, SCSCR);
795 u16 ssr = sci_in(port, SCxSR);
797 /* Disable future Rx interrupts */
798 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
799 disable_irq_nosync(irq);
804 sci_out(port, SCSCR, scr);
805 /* Clear current interrupt */
806 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
807 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
808 jiffies, s->rx_timeout);
809 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
815 /* I think sci_receive_chars has to be called irrespective
816 * of whether the I_IXOFF is set, otherwise, how is the interrupt
819 sci_receive_chars(ptr);
824 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
826 struct uart_port *port = ptr;
829 spin_lock_irqsave(&port->lock, flags);
830 sci_transmit_chars(port);
831 spin_unlock_irqrestore(&port->lock, flags);
836 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
838 struct uart_port *port = ptr;
841 if (port->type == PORT_SCI) {
842 if (sci_handle_errors(port)) {
843 /* discard character in rx buffer */
845 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
848 sci_handle_fifo_overrun(port);
849 sci_rx_interrupt(irq, ptr);
852 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
854 /* Kick the transmission */
855 sci_tx_interrupt(irq, ptr);
860 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
862 struct uart_port *port = ptr;
865 sci_handle_breaks(port);
866 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
871 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
874 * Not all ports (such as SCIFA) will support REIE. Rather than
875 * special-casing the port type, we check the port initialization
876 * IRQ enable mask to see whether the IRQ is desired at all. If
877 * it's unset, it's logically inferred that there's no point in
880 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
883 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
885 unsigned short ssr_status, scr_status, err_enabled;
886 struct uart_port *port = ptr;
887 struct sci_port *s = to_sci_port(port);
888 irqreturn_t ret = IRQ_NONE;
890 ssr_status = sci_in(port, SCxSR);
891 scr_status = sci_in(port, SCSCR);
892 err_enabled = scr_status & port_rx_irq_mask(port);
895 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
897 ret = sci_tx_interrupt(irq, ptr);
900 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
903 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
904 (scr_status & SCSCR_RIE))
905 ret = sci_rx_interrupt(irq, ptr);
907 /* Error Interrupt */
908 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
909 ret = sci_er_interrupt(irq, ptr);
911 /* Break Interrupt */
912 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
913 ret = sci_br_interrupt(irq, ptr);
919 * Here we define a transition notifier so that we can update all of our
920 * ports' baud rate when the peripheral clock changes.
922 static int sci_notifier(struct notifier_block *self,
923 unsigned long phase, void *p)
925 struct sci_port *sci_port;
928 sci_port = container_of(self, struct sci_port, freq_transition);
930 if ((phase == CPUFREQ_POSTCHANGE) ||
931 (phase == CPUFREQ_RESUMECHANGE)) {
932 struct uart_port *port = &sci_port->port;
934 spin_lock_irqsave(&port->lock, flags);
935 port->uartclk = clk_get_rate(sci_port->iclk);
936 spin_unlock_irqrestore(&port->lock, flags);
942 static void sci_clk_enable(struct uart_port *port)
944 struct sci_port *sci_port = to_sci_port(port);
946 pm_runtime_get_sync(port->dev);
948 clk_enable(sci_port->iclk);
949 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
950 clk_enable(sci_port->fclk);
953 static void sci_clk_disable(struct uart_port *port)
955 struct sci_port *sci_port = to_sci_port(port);
957 clk_disable(sci_port->fclk);
958 clk_disable(sci_port->iclk);
960 pm_runtime_put_sync(port->dev);
963 static int sci_request_irq(struct sci_port *port)
966 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
967 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
970 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
971 "SCI Transmit Data Empty", "SCI Break" };
973 if (port->cfg->irqs[0] == port->cfg->irqs[1]) {
974 if (unlikely(!port->cfg->irqs[0]))
977 if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt,
978 IRQF_DISABLED, "sci", port)) {
979 dev_err(port->port.dev, "Can't allocate IRQ\n");
983 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
984 if (unlikely(!port->cfg->irqs[i]))
987 if (request_irq(port->cfg->irqs[i], handlers[i],
988 IRQF_DISABLED, desc[i], port)) {
989 dev_err(port->port.dev, "Can't allocate IRQ\n");
998 static void sci_free_irq(struct sci_port *port)
1002 if (port->cfg->irqs[0] == port->cfg->irqs[1])
1003 free_irq(port->cfg->irqs[0], port);
1005 for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) {
1006 if (!port->cfg->irqs[i])
1009 free_irq(port->cfg->irqs[i], port);
1014 static unsigned int sci_tx_empty(struct uart_port *port)
1016 unsigned short status = sci_in(port, SCxSR);
1017 unsigned short in_tx_fifo = sci_txfill(port);
1019 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1022 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1024 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
1025 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
1026 /* If you have signals for DTR and DCD, please implement here. */
1029 static unsigned int sci_get_mctrl(struct uart_port *port)
1031 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1034 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
1037 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1038 static void sci_dma_tx_complete(void *arg)
1040 struct sci_port *s = arg;
1041 struct uart_port *port = &s->port;
1042 struct circ_buf *xmit = &port->state->xmit;
1043 unsigned long flags;
1045 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1047 spin_lock_irqsave(&port->lock, flags);
1049 xmit->tail += sg_dma_len(&s->sg_tx);
1050 xmit->tail &= UART_XMIT_SIZE - 1;
1052 port->icount.tx += sg_dma_len(&s->sg_tx);
1054 async_tx_ack(s->desc_tx);
1055 s->cookie_tx = -EINVAL;
1058 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1059 uart_write_wakeup(port);
1061 if (!uart_circ_empty(xmit)) {
1062 schedule_work(&s->work_tx);
1063 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1064 u16 ctrl = sci_in(port, SCSCR);
1065 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1068 spin_unlock_irqrestore(&port->lock, flags);
1071 /* Locking: called with port lock held */
1072 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1075 struct uart_port *port = &s->port;
1076 int i, active, room;
1078 room = tty_buffer_request_room(tty, count);
1080 if (s->active_rx == s->cookie_rx[0]) {
1082 } else if (s->active_rx == s->cookie_rx[1]) {
1085 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1090 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1095 for (i = 0; i < room; i++)
1096 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1099 port->icount.rx += room;
1104 static void sci_dma_rx_complete(void *arg)
1106 struct sci_port *s = arg;
1107 struct uart_port *port = &s->port;
1108 struct tty_struct *tty = port->state->port.tty;
1109 unsigned long flags;
1112 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1114 spin_lock_irqsave(&port->lock, flags);
1116 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1118 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1120 spin_unlock_irqrestore(&port->lock, flags);
1123 tty_flip_buffer_push(tty);
1125 schedule_work(&s->work_rx);
1128 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1130 struct dma_chan *chan = s->chan_rx;
1131 struct uart_port *port = &s->port;
1134 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1135 dma_release_channel(chan);
1136 if (sg_dma_address(&s->sg_rx[0]))
1137 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1138 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1143 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1145 struct dma_chan *chan = s->chan_tx;
1146 struct uart_port *port = &s->port;
1149 s->cookie_tx = -EINVAL;
1150 dma_release_channel(chan);
1155 static void sci_submit_rx(struct sci_port *s)
1157 struct dma_chan *chan = s->chan_rx;
1160 for (i = 0; i < 2; i++) {
1161 struct scatterlist *sg = &s->sg_rx[i];
1162 struct dma_async_tx_descriptor *desc;
1164 desc = chan->device->device_prep_slave_sg(chan,
1165 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1168 s->desc_rx[i] = desc;
1169 desc->callback = sci_dma_rx_complete;
1170 desc->callback_param = s;
1171 s->cookie_rx[i] = desc->tx_submit(desc);
1174 if (!desc || s->cookie_rx[i] < 0) {
1176 async_tx_ack(s->desc_rx[0]);
1177 s->cookie_rx[0] = -EINVAL;
1181 s->cookie_rx[i] = -EINVAL;
1183 dev_warn(s->port.dev,
1184 "failed to re-start DMA, using PIO\n");
1185 sci_rx_dma_release(s, true);
1188 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1189 s->cookie_rx[i], i);
1192 s->active_rx = s->cookie_rx[0];
1194 dma_async_issue_pending(chan);
1197 static void work_fn_rx(struct work_struct *work)
1199 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1200 struct uart_port *port = &s->port;
1201 struct dma_async_tx_descriptor *desc;
1204 if (s->active_rx == s->cookie_rx[0]) {
1206 } else if (s->active_rx == s->cookie_rx[1]) {
1209 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1212 desc = s->desc_rx[new];
1214 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1216 /* Handle incomplete DMA receive */
1217 struct tty_struct *tty = port->state->port.tty;
1218 struct dma_chan *chan = s->chan_rx;
1219 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1221 unsigned long flags;
1224 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1225 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1226 sh_desc->partial, sh_desc->cookie);
1228 spin_lock_irqsave(&port->lock, flags);
1229 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1230 spin_unlock_irqrestore(&port->lock, flags);
1233 tty_flip_buffer_push(tty);
1240 s->cookie_rx[new] = desc->tx_submit(desc);
1241 if (s->cookie_rx[new] < 0) {
1242 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1243 sci_rx_dma_release(s, true);
1247 s->active_rx = s->cookie_rx[!new];
1249 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1250 s->cookie_rx[new], new, s->active_rx);
1253 static void work_fn_tx(struct work_struct *work)
1255 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1256 struct dma_async_tx_descriptor *desc;
1257 struct dma_chan *chan = s->chan_tx;
1258 struct uart_port *port = &s->port;
1259 struct circ_buf *xmit = &port->state->xmit;
1260 struct scatterlist *sg = &s->sg_tx;
1264 * Port xmit buffer is already mapped, and it is one page... Just adjust
1265 * offsets and lengths. Since it is a circular buffer, we have to
1266 * transmit till the end, and then the rest. Take the port lock to get a
1267 * consistent xmit buffer state.
1269 spin_lock_irq(&port->lock);
1270 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1271 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1273 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1274 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1275 spin_unlock_irq(&port->lock);
1277 BUG_ON(!sg_dma_len(sg));
1279 desc = chan->device->device_prep_slave_sg(chan,
1280 sg, s->sg_len_tx, DMA_TO_DEVICE,
1281 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1284 sci_tx_dma_release(s, true);
1288 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1290 spin_lock_irq(&port->lock);
1292 desc->callback = sci_dma_tx_complete;
1293 desc->callback_param = s;
1294 spin_unlock_irq(&port->lock);
1295 s->cookie_tx = desc->tx_submit(desc);
1296 if (s->cookie_tx < 0) {
1297 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1299 sci_tx_dma_release(s, true);
1303 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1304 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1306 dma_async_issue_pending(chan);
1310 static void sci_start_tx(struct uart_port *port)
1312 struct sci_port *s = to_sci_port(port);
1313 unsigned short ctrl;
1315 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1316 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1317 u16 new, scr = sci_in(port, SCSCR);
1321 new = scr & ~0x8000;
1323 sci_out(port, SCSCR, new);
1326 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1328 schedule_work(&s->work_tx);
1331 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1332 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1333 ctrl = sci_in(port, SCSCR);
1334 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
1338 static void sci_stop_tx(struct uart_port *port)
1340 unsigned short ctrl;
1342 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1343 ctrl = sci_in(port, SCSCR);
1345 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1350 sci_out(port, SCSCR, ctrl);
1353 static void sci_start_rx(struct uart_port *port)
1355 unsigned short ctrl;
1357 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1359 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1362 sci_out(port, SCSCR, ctrl);
1365 static void sci_stop_rx(struct uart_port *port)
1367 unsigned short ctrl;
1369 ctrl = sci_in(port, SCSCR);
1371 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1374 ctrl &= ~port_rx_irq_mask(port);
1376 sci_out(port, SCSCR, ctrl);
1379 static void sci_enable_ms(struct uart_port *port)
1381 /* Nothing here yet .. */
1384 static void sci_break_ctl(struct uart_port *port, int break_state)
1386 /* Nothing here yet .. */
1389 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1390 static bool filter(struct dma_chan *chan, void *slave)
1392 struct sh_dmae_slave *param = slave;
1394 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1397 if (param->dma_dev == chan->device->dev) {
1398 chan->private = param;
1405 static void rx_timer_fn(unsigned long arg)
1407 struct sci_port *s = (struct sci_port *)arg;
1408 struct uart_port *port = &s->port;
1409 u16 scr = sci_in(port, SCSCR);
1411 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1413 enable_irq(s->cfg->irqs[1]);
1415 sci_out(port, SCSCR, scr | SCSCR_RIE);
1416 dev_dbg(port->dev, "DMA Rx timed out\n");
1417 schedule_work(&s->work_rx);
1420 static void sci_request_dma(struct uart_port *port)
1422 struct sci_port *s = to_sci_port(port);
1423 struct sh_dmae_slave *param;
1424 struct dma_chan *chan;
1425 dma_cap_mask_t mask;
1428 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1429 port->line, s->cfg->dma_dev);
1431 if (!s->cfg->dma_dev)
1435 dma_cap_set(DMA_SLAVE, mask);
1437 param = &s->param_tx;
1439 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1440 param->slave_id = s->cfg->dma_slave_tx;
1441 param->dma_dev = s->cfg->dma_dev;
1443 s->cookie_tx = -EINVAL;
1444 chan = dma_request_channel(mask, filter, param);
1445 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1448 sg_init_table(&s->sg_tx, 1);
1449 /* UART circular tx buffer is an aligned page. */
1450 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1451 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1452 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1453 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1455 sci_tx_dma_release(s, false);
1457 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1458 sg_dma_len(&s->sg_tx),
1459 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1461 s->sg_len_tx = nent;
1463 INIT_WORK(&s->work_tx, work_fn_tx);
1466 param = &s->param_rx;
1468 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1469 param->slave_id = s->cfg->dma_slave_rx;
1470 param->dma_dev = s->cfg->dma_dev;
1472 chan = dma_request_channel(mask, filter, param);
1473 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1481 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1482 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1483 &dma[0], GFP_KERNEL);
1487 "failed to allocate dma buffer, using PIO\n");
1488 sci_rx_dma_release(s, true);
1492 buf[1] = buf[0] + s->buf_len_rx;
1493 dma[1] = dma[0] + s->buf_len_rx;
1495 for (i = 0; i < 2; i++) {
1496 struct scatterlist *sg = &s->sg_rx[i];
1498 sg_init_table(sg, 1);
1499 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1500 (int)buf[i] & ~PAGE_MASK);
1501 sg_dma_address(sg) = dma[i];
1504 INIT_WORK(&s->work_rx, work_fn_rx);
1505 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1511 static void sci_free_dma(struct uart_port *port)
1513 struct sci_port *s = to_sci_port(port);
1515 if (!s->cfg->dma_dev)
1519 sci_tx_dma_release(s, false);
1521 sci_rx_dma_release(s, false);
1524 static inline void sci_request_dma(struct uart_port *port)
1528 static inline void sci_free_dma(struct uart_port *port)
1533 static int sci_startup(struct uart_port *port)
1535 struct sci_port *s = to_sci_port(port);
1538 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1543 ret = sci_request_irq(s);
1544 if (unlikely(ret < 0))
1547 sci_request_dma(port);
1555 static void sci_shutdown(struct uart_port *port)
1557 struct sci_port *s = to_sci_port(port);
1559 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1571 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1576 return ((freq + 16 * bps) / (16 * bps) - 1);
1578 return ((freq + 16 * bps) / (32 * bps) - 1);
1580 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1582 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1584 return (((freq * 1000 / 32) / bps) - 1);
1587 /* Warn, but use a safe default */
1590 return ((freq + 16 * bps) / (32 * bps) - 1);
1593 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1594 struct ktermios *old)
1596 struct sci_port *s = to_sci_port(port);
1597 unsigned int status, baud, smr_val, max_baud;
1602 * earlyprintk comes here early on with port->uartclk set to zero.
1603 * the clock framework is not up and running at this point so here
1604 * we assume that 115200 is the maximum baud rate. please note that
1605 * the baud rate is not programmed during earlyprintk - it is assumed
1606 * that the previous boot loader has enabled required clocks and
1607 * setup the baud rate generator hardware for us already.
1609 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1611 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1612 if (likely(baud && port->uartclk))
1613 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
1619 status = sci_in(port, SCxSR);
1620 } while (!(status & SCxSR_TEND(port)));
1622 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1624 if (port->type != PORT_SCI)
1625 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1627 smr_val = sci_in(port, SCSMR) & 3;
1629 if ((termios->c_cflag & CSIZE) == CS7)
1631 if (termios->c_cflag & PARENB)
1633 if (termios->c_cflag & PARODD)
1635 if (termios->c_cflag & CSTOPB)
1638 uart_update_timeout(port, termios->c_cflag, baud);
1640 sci_out(port, SCSMR, smr_val);
1642 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1647 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1650 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1652 sci_out(port, SCBRR, t);
1653 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1656 sci_init_pins(port, termios->c_cflag);
1657 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
1659 sci_out(port, SCSCR, s->cfg->scscr);
1661 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1663 * Calculate delay for 1.5 DMA buffers: see
1664 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1665 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1666 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1667 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1668 * sizes), but it has been found out experimentally, that this is not
1669 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1670 * as a minimum seem to work perfectly.
1673 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1676 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1677 s->rx_timeout * 1000 / HZ, port->timeout);
1678 if (s->rx_timeout < msecs_to_jiffies(20))
1679 s->rx_timeout = msecs_to_jiffies(20);
1683 if ((termios->c_cflag & CREAD) != 0)
1690 static const char *sci_type(struct uart_port *port)
1692 switch (port->type) {
1708 static inline unsigned long sci_port_size(struct uart_port *port)
1711 * Pick an arbitrary size that encapsulates all of the base
1712 * registers by default. This can be optimized later, or derived
1713 * from platform resource data at such a time that ports begin to
1714 * behave more erratically.
1719 static int sci_remap_port(struct uart_port *port)
1721 unsigned long size = sci_port_size(port);
1724 * Nothing to do if there's already an established membase.
1729 if (port->flags & UPF_IOREMAP) {
1730 port->membase = ioremap_nocache(port->mapbase, size);
1731 if (unlikely(!port->membase)) {
1732 dev_err(port->dev, "can't remap port#%d\n", port->line);
1737 * For the simple (and majority of) cases where we don't
1738 * need to do any remapping, just cast the cookie
1741 port->membase = (void __iomem *)port->mapbase;
1747 static void sci_release_port(struct uart_port *port)
1749 if (port->flags & UPF_IOREMAP) {
1750 iounmap(port->membase);
1751 port->membase = NULL;
1754 release_mem_region(port->mapbase, sci_port_size(port));
1757 static int sci_request_port(struct uart_port *port)
1759 unsigned long size = sci_port_size(port);
1760 struct resource *res;
1763 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
1764 if (unlikely(res == NULL))
1767 ret = sci_remap_port(port);
1768 if (unlikely(ret != 0)) {
1769 release_resource(res);
1776 static void sci_config_port(struct uart_port *port, int flags)
1778 if (flags & UART_CONFIG_TYPE) {
1779 struct sci_port *sport = to_sci_port(port);
1781 port->type = sport->cfg->type;
1782 sci_request_port(port);
1786 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1788 struct sci_port *s = to_sci_port(port);
1790 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1792 if (ser->baud_base < 2400)
1793 /* No paper tape reader for Mitch.. */
1799 static struct uart_ops sci_uart_ops = {
1800 .tx_empty = sci_tx_empty,
1801 .set_mctrl = sci_set_mctrl,
1802 .get_mctrl = sci_get_mctrl,
1803 .start_tx = sci_start_tx,
1804 .stop_tx = sci_stop_tx,
1805 .stop_rx = sci_stop_rx,
1806 .enable_ms = sci_enable_ms,
1807 .break_ctl = sci_break_ctl,
1808 .startup = sci_startup,
1809 .shutdown = sci_shutdown,
1810 .set_termios = sci_set_termios,
1812 .release_port = sci_release_port,
1813 .request_port = sci_request_port,
1814 .config_port = sci_config_port,
1815 .verify_port = sci_verify_port,
1816 #ifdef CONFIG_CONSOLE_POLL
1817 .poll_get_char = sci_poll_get_char,
1818 .poll_put_char = sci_poll_put_char,
1822 static int __devinit sci_init_single(struct platform_device *dev,
1823 struct sci_port *sci_port,
1825 struct plat_sci_port *p)
1827 struct uart_port *port = &sci_port->port;
1829 port->ops = &sci_uart_ops;
1830 port->iotype = UPIO_MEM;
1835 port->fifosize = 256;
1838 port->fifosize = 64;
1841 port->fifosize = 16;
1848 if (p->regtype == SCIx_PROBE_REGTYPE)
1849 BUG_ON(sci_probe_regmap(p) != 0);
1852 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1853 if (IS_ERR(sci_port->iclk)) {
1854 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1855 if (IS_ERR(sci_port->iclk)) {
1856 dev_err(&dev->dev, "can't get iclk\n");
1857 return PTR_ERR(sci_port->iclk);
1862 * The function clock is optional, ignore it if we can't
1865 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1866 if (IS_ERR(sci_port->fclk))
1867 sci_port->fclk = NULL;
1869 sci_port->enable = sci_clk_enable;
1870 sci_port->disable = sci_clk_disable;
1871 port->dev = &dev->dev;
1873 pm_runtime_enable(&dev->dev);
1876 sci_port->break_timer.data = (unsigned long)sci_port;
1877 sci_port->break_timer.function = sci_break_timer;
1878 init_timer(&sci_port->break_timer);
1881 * Establish some sensible defaults for the error detection.
1884 p->error_mask = (p->type == PORT_SCI) ?
1885 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
1888 * Establish sensible defaults for the overrun detection, unless
1889 * the part has explicitly disabled support for it.
1891 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
1892 if (p->type == PORT_SCI)
1894 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
1900 * Make the error mask inclusive of overrun detection, if
1903 p->error_mask |= (1 << p->overrun_bit);
1908 port->mapbase = p->mapbase;
1909 port->type = p->type;
1910 port->flags = p->flags;
1911 port->regshift = p->regshift;
1914 * The UART port needs an IRQ value, so we peg this to the RX IRQ
1915 * for the multi-IRQ ports, which is where we are primarily
1916 * concerned with the shutdown path synchronization.
1918 * For the muxed case there's nothing more to do.
1920 port->irq = p->irqs[SCIx_RXI_IRQ];
1922 port->serial_in = sci_serial_in;
1923 port->serial_out = sci_serial_out;
1926 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
1927 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1932 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1933 static void serial_console_putchar(struct uart_port *port, int ch)
1935 sci_poll_put_char(port, ch);
1939 * Print a string to the serial port trying not to disturb
1940 * any possible real use of the port...
1942 static void serial_console_write(struct console *co, const char *s,
1945 struct sci_port *sci_port = &sci_ports[co->index];
1946 struct uart_port *port = &sci_port->port;
1947 unsigned short bits;
1949 if (sci_port->enable)
1950 sci_port->enable(port);
1952 uart_console_write(port, s, count, serial_console_putchar);
1954 /* wait until fifo is empty and last bit has been transmitted */
1955 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1956 while ((sci_in(port, SCxSR) & bits) != bits)
1959 if (sci_port->disable)
1960 sci_port->disable(port);
1963 static int __devinit serial_console_setup(struct console *co, char *options)
1965 struct sci_port *sci_port;
1966 struct uart_port *port;
1974 * Refuse to handle any bogus ports.
1976 if (co->index < 0 || co->index >= SCI_NPORTS)
1979 sci_port = &sci_ports[co->index];
1980 port = &sci_port->port;
1983 * Refuse to handle uninitialized ports.
1988 ret = sci_remap_port(port);
1989 if (unlikely(ret != 0))
1992 if (sci_port->enable)
1993 sci_port->enable(port);
1996 uart_parse_options(options, &baud, &parity, &bits, &flow);
1998 /* TODO: disable clock */
1999 return uart_set_options(port, co, baud, parity, bits, flow);
2002 static struct console serial_console = {
2004 .device = uart_console_device,
2005 .write = serial_console_write,
2006 .setup = serial_console_setup,
2007 .flags = CON_PRINTBUFFER,
2009 .data = &sci_uart_driver,
2012 static struct console early_serial_console = {
2013 .name = "early_ttySC",
2014 .write = serial_console_write,
2015 .flags = CON_PRINTBUFFER,
2019 static char early_serial_buf[32];
2021 static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2023 struct plat_sci_port *cfg = pdev->dev.platform_data;
2025 if (early_serial_console.data)
2028 early_serial_console.index = pdev->id;
2030 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
2032 serial_console_setup(&early_serial_console, early_serial_buf);
2034 if (!strstr(early_serial_buf, "keep"))
2035 early_serial_console.flags |= CON_BOOT;
2037 register_console(&early_serial_console);
2041 #define SCI_CONSOLE (&serial_console)
2044 static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2049 #define SCI_CONSOLE NULL
2051 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2053 static char banner[] __initdata =
2054 KERN_INFO "SuperH SCI(F) driver initialized\n";
2056 static struct uart_driver sci_uart_driver = {
2057 .owner = THIS_MODULE,
2058 .driver_name = "sci",
2059 .dev_name = "ttySC",
2061 .minor = SCI_MINOR_START,
2063 .cons = SCI_CONSOLE,
2066 static int sci_remove(struct platform_device *dev)
2068 struct sci_port *port = platform_get_drvdata(dev);
2070 cpufreq_unregister_notifier(&port->freq_transition,
2071 CPUFREQ_TRANSITION_NOTIFIER);
2073 uart_remove_one_port(&sci_uart_driver, &port->port);
2075 clk_put(port->iclk);
2076 clk_put(port->fclk);
2078 pm_runtime_disable(&dev->dev);
2082 static int __devinit sci_probe_single(struct platform_device *dev,
2084 struct plat_sci_port *p,
2085 struct sci_port *sciport)
2090 if (unlikely(index >= SCI_NPORTS)) {
2091 dev_notice(&dev->dev, "Attempting to register port "
2092 "%d when only %d are available.\n",
2093 index+1, SCI_NPORTS);
2094 dev_notice(&dev->dev, "Consider bumping "
2095 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2099 ret = sci_init_single(dev, sciport, index, p);
2103 return uart_add_one_port(&sci_uart_driver, &sciport->port);
2106 static int __devinit sci_probe(struct platform_device *dev)
2108 struct plat_sci_port *p = dev->dev.platform_data;
2109 struct sci_port *sp = &sci_ports[dev->id];
2113 * If we've come here via earlyprintk initialization, head off to
2114 * the special early probe. We don't have sufficient device state
2115 * to make it beyond this yet.
2117 if (is_early_platform_device(dev))
2118 return sci_probe_earlyprintk(dev);
2120 platform_set_drvdata(dev, sp);
2122 ret = sci_probe_single(dev, dev->id, p, sp);
2126 sp->freq_transition.notifier_call = sci_notifier;
2128 ret = cpufreq_register_notifier(&sp->freq_transition,
2129 CPUFREQ_TRANSITION_NOTIFIER);
2130 if (unlikely(ret < 0))
2133 #ifdef CONFIG_SH_STANDARD_BIOS
2134 sh_bios_gdb_detach();
2144 static int sci_suspend(struct device *dev)
2146 struct sci_port *sport = dev_get_drvdata(dev);
2149 uart_suspend_port(&sci_uart_driver, &sport->port);
2154 static int sci_resume(struct device *dev)
2156 struct sci_port *sport = dev_get_drvdata(dev);
2159 uart_resume_port(&sci_uart_driver, &sport->port);
2164 static const struct dev_pm_ops sci_dev_pm_ops = {
2165 .suspend = sci_suspend,
2166 .resume = sci_resume,
2169 static struct platform_driver sci_driver = {
2171 .remove = sci_remove,
2174 .owner = THIS_MODULE,
2175 .pm = &sci_dev_pm_ops,
2179 static int __init sci_init(void)
2185 ret = uart_register_driver(&sci_uart_driver);
2186 if (likely(ret == 0)) {
2187 ret = platform_driver_register(&sci_driver);
2189 uart_unregister_driver(&sci_uart_driver);
2195 static void __exit sci_exit(void)
2197 platform_driver_unregister(&sci_driver);
2198 uart_unregister_driver(&sci_uart_driver);
2201 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2202 early_platform_init_buffer("earlyprintk", &sci_driver,
2203 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2205 module_init(sci_init);
2206 module_exit(sci_exit);
2208 MODULE_LICENSE("GPL");
2209 MODULE_ALIAS("platform:sh-sci");