2 * Driver core for Samsung SoC onboard UARTs.
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 /* Hote on 2410 error handling
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/module.h>
32 #include <linux/ioport.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/delay.h>
43 #include <linux/clk.h>
44 #include <linux/cpufreq.h>
48 #include <mach/hardware.h>
51 #include <plat/regs-serial.h>
55 /* UART name and device definitions */
57 #define S3C24XX_SERIAL_NAME "ttySAC"
58 #define S3C24XX_SERIAL_MAJOR 204
59 #define S3C24XX_SERIAL_MINOR 64
61 /* macros to change one thing to another */
63 #define tx_enabled(port) ((port)->unused[0])
64 #define rx_enabled(port) ((port)->unused[1])
66 /* flag to ignore all characters coming in */
67 #define RXSTAT_DUMMY_READ (0x10000000)
69 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
71 return container_of(port, struct s3c24xx_uart_port, port);
74 /* translate a port to the device name */
76 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
78 return to_platform_device(port->dev)->name;
81 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
83 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
87 * s3c64xx and later SoC's include the interrupt mask and status registers in
88 * the controller itself, unlike the s3c24xx SoC's which have these registers
89 * in the interrupt controller. Check if the port type is s3c64xx or higher.
91 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
93 return to_ourport(port)->info->type == PORT_S3C6400;
96 static void s3c24xx_serial_rx_enable(struct uart_port *port)
99 unsigned int ucon, ufcon;
102 spin_lock_irqsave(&port->lock, flags);
104 while (--count && !s3c24xx_serial_txempty_nofifo(port))
107 ufcon = rd_regl(port, S3C2410_UFCON);
108 ufcon |= S3C2410_UFCON_RESETRX;
109 wr_regl(port, S3C2410_UFCON, ufcon);
111 ucon = rd_regl(port, S3C2410_UCON);
112 ucon |= S3C2410_UCON_RXIRQMODE;
113 wr_regl(port, S3C2410_UCON, ucon);
115 rx_enabled(port) = 1;
116 spin_unlock_irqrestore(&port->lock, flags);
119 static void s3c24xx_serial_rx_disable(struct uart_port *port)
124 spin_lock_irqsave(&port->lock, flags);
126 ucon = rd_regl(port, S3C2410_UCON);
127 ucon &= ~S3C2410_UCON_RXIRQMODE;
128 wr_regl(port, S3C2410_UCON, ucon);
130 rx_enabled(port) = 0;
131 spin_unlock_irqrestore(&port->lock, flags);
134 static void s3c24xx_serial_stop_tx(struct uart_port *port)
136 struct s3c24xx_uart_port *ourport = to_ourport(port);
138 if (tx_enabled(port)) {
139 if (s3c24xx_serial_has_interrupt_mask(port))
140 __set_bit(S3C64XX_UINTM_TXD,
141 portaddrl(port, S3C64XX_UINTM));
143 disable_irq_nosync(ourport->tx_irq);
144 tx_enabled(port) = 0;
145 if (port->flags & UPF_CONS_FLOW)
146 s3c24xx_serial_rx_enable(port);
150 static void s3c24xx_serial_start_tx(struct uart_port *port)
152 struct s3c24xx_uart_port *ourport = to_ourport(port);
154 if (!tx_enabled(port)) {
155 if (port->flags & UPF_CONS_FLOW)
156 s3c24xx_serial_rx_disable(port);
158 if (s3c24xx_serial_has_interrupt_mask(port))
159 __clear_bit(S3C64XX_UINTM_TXD,
160 portaddrl(port, S3C64XX_UINTM));
162 enable_irq(ourport->tx_irq);
163 tx_enabled(port) = 1;
167 static void s3c24xx_serial_stop_rx(struct uart_port *port)
169 struct s3c24xx_uart_port *ourport = to_ourport(port);
171 if (rx_enabled(port)) {
172 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
173 if (s3c24xx_serial_has_interrupt_mask(port))
174 __set_bit(S3C64XX_UINTM_RXD,
175 portaddrl(port, S3C64XX_UINTM));
177 disable_irq_nosync(ourport->rx_irq);
178 rx_enabled(port) = 0;
182 static void s3c24xx_serial_enable_ms(struct uart_port *port)
186 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
188 return to_ourport(port)->info;
191 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
193 if (port->dev == NULL)
196 return (struct s3c2410_uartcfg *)port->dev->platform_data;
199 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
200 unsigned long ufstat)
202 struct s3c24xx_uart_info *info = ourport->info;
204 if (ufstat & info->rx_fifofull)
205 return info->fifosize;
207 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
211 /* ? - where has parity gone?? */
212 #define S3C2410_UERSTAT_PARITY (0x1000)
215 s3c24xx_serial_rx_chars(int irq, void *dev_id)
217 struct s3c24xx_uart_port *ourport = dev_id;
218 struct uart_port *port = &ourport->port;
219 struct tty_struct *tty = port->state->port.tty;
220 unsigned int ufcon, ch, flag, ufstat, uerstat;
223 while (max_count-- > 0) {
224 ufcon = rd_regl(port, S3C2410_UFCON);
225 ufstat = rd_regl(port, S3C2410_UFSTAT);
227 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
230 uerstat = rd_regl(port, S3C2410_UERSTAT);
231 ch = rd_regb(port, S3C2410_URXH);
233 if (port->flags & UPF_CONS_FLOW) {
234 int txe = s3c24xx_serial_txempty_nofifo(port);
236 if (rx_enabled(port)) {
238 rx_enabled(port) = 0;
243 ufcon |= S3C2410_UFCON_RESETRX;
244 wr_regl(port, S3C2410_UFCON, ufcon);
245 rx_enabled(port) = 1;
252 /* insert the character into the buffer */
257 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
258 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
261 /* check for break */
262 if (uerstat & S3C2410_UERSTAT_BREAK) {
265 if (uart_handle_break(port))
269 if (uerstat & S3C2410_UERSTAT_FRAME)
270 port->icount.frame++;
271 if (uerstat & S3C2410_UERSTAT_OVERRUN)
272 port->icount.overrun++;
274 uerstat &= port->read_status_mask;
276 if (uerstat & S3C2410_UERSTAT_BREAK)
278 else if (uerstat & S3C2410_UERSTAT_PARITY)
280 else if (uerstat & (S3C2410_UERSTAT_FRAME |
281 S3C2410_UERSTAT_OVERRUN))
285 if (uart_handle_sysrq_char(port, ch))
288 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
294 tty_flip_buffer_push(tty);
300 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
302 struct s3c24xx_uart_port *ourport = id;
303 struct uart_port *port = &ourport->port;
304 struct circ_buf *xmit = &port->state->xmit;
308 wr_regb(port, S3C2410_UTXH, port->x_char);
314 /* if there isn't anything more to transmit, or the uart is now
315 * stopped, disable the uart and exit
318 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
319 s3c24xx_serial_stop_tx(port);
323 /* try and drain the buffer... */
325 while (!uart_circ_empty(xmit) && count-- > 0) {
326 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
329 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
330 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
334 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
335 uart_write_wakeup(port);
337 if (uart_circ_empty(xmit))
338 s3c24xx_serial_stop_tx(port);
344 /* interrupt handler for s3c64xx and later SoC's.*/
345 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
347 struct s3c24xx_uart_port *ourport = id;
348 struct uart_port *port = &ourport->port;
349 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
351 irqreturn_t ret = IRQ_HANDLED;
353 spin_lock_irqsave(&port->lock, flags);
354 if (pend & S3C64XX_UINTM_RXD_MSK) {
355 ret = s3c24xx_serial_rx_chars(irq, id);
356 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
358 if (pend & S3C64XX_UINTM_TXD_MSK) {
359 ret = s3c24xx_serial_tx_chars(irq, id);
360 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
362 spin_unlock_irqrestore(&port->lock, flags);
366 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
368 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
369 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
370 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
372 if (ufcon & S3C2410_UFCON_FIFOMODE) {
373 if ((ufstat & info->tx_fifomask) != 0 ||
374 (ufstat & info->tx_fifofull))
380 return s3c24xx_serial_txempty_nofifo(port);
383 /* no modem control lines */
384 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
386 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
388 if (umstat & S3C2410_UMSTAT_CTS)
389 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
391 return TIOCM_CAR | TIOCM_DSR;
394 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
396 /* todo - possibly remove AFC and do manual CTS */
399 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
404 spin_lock_irqsave(&port->lock, flags);
406 ucon = rd_regl(port, S3C2410_UCON);
409 ucon |= S3C2410_UCON_SBREAK;
411 ucon &= ~S3C2410_UCON_SBREAK;
413 wr_regl(port, S3C2410_UCON, ucon);
415 spin_unlock_irqrestore(&port->lock, flags);
418 static void s3c24xx_serial_shutdown(struct uart_port *port)
420 struct s3c24xx_uart_port *ourport = to_ourport(port);
422 if (ourport->tx_claimed) {
423 if (!s3c24xx_serial_has_interrupt_mask(port))
424 free_irq(ourport->tx_irq, ourport);
425 tx_enabled(port) = 0;
426 ourport->tx_claimed = 0;
429 if (ourport->rx_claimed) {
430 if (!s3c24xx_serial_has_interrupt_mask(port))
431 free_irq(ourport->rx_irq, ourport);
432 ourport->rx_claimed = 0;
433 rx_enabled(port) = 0;
436 /* Clear pending interrupts and mask all interrupts */
437 if (s3c24xx_serial_has_interrupt_mask(port)) {
438 wr_regl(port, S3C64XX_UINTP, 0xf);
439 wr_regl(port, S3C64XX_UINTM, 0xf);
443 static int s3c24xx_serial_startup(struct uart_port *port)
445 struct s3c24xx_uart_port *ourport = to_ourport(port);
448 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
449 port->mapbase, port->membase);
451 rx_enabled(port) = 1;
453 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
454 s3c24xx_serial_portname(port), ourport);
457 printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
461 ourport->rx_claimed = 1;
463 dbg("requesting tx irq...\n");
465 tx_enabled(port) = 1;
467 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
468 s3c24xx_serial_portname(port), ourport);
471 printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
475 ourport->tx_claimed = 1;
477 dbg("s3c24xx_serial_startup ok\n");
479 /* the port reset code should have done the correct
480 * register setup for the port controls */
485 s3c24xx_serial_shutdown(port);
489 static int s3c64xx_serial_startup(struct uart_port *port)
491 struct s3c24xx_uart_port *ourport = to_ourport(port);
494 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
495 port->mapbase, port->membase);
497 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
498 s3c24xx_serial_portname(port), ourport);
500 printk(KERN_ERR "cannot get irq %d\n", port->irq);
504 /* For compatibility with s3c24xx Soc's */
505 rx_enabled(port) = 1;
506 ourport->rx_claimed = 1;
507 tx_enabled(port) = 0;
508 ourport->tx_claimed = 1;
510 /* Enable Rx Interrupt */
511 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
512 dbg("s3c64xx_serial_startup ok\n");
516 /* power power management control */
518 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
521 struct s3c24xx_uart_port *ourport = to_ourport(port);
523 ourport->pm_level = level;
527 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
528 clk_disable(ourport->baudclk);
530 clk_disable(ourport->clk);
534 clk_enable(ourport->clk);
536 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
537 clk_enable(ourport->baudclk);
541 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
545 /* baud rate calculation
547 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
548 * of different sources, including the peripheral clock ("pclk") and an
549 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
550 * with a programmable extra divisor.
552 * The following code goes through the clock sources, and calculates the
553 * baud clocks (and the resultant actual baud rates) and then tries to
554 * pick the closest one and select that.
561 static struct s3c24xx_uart_clksrc tmp_clksrc = {
569 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
571 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
573 return (info->get_clksrc)(port, c);
577 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
579 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
581 return (info->set_clksrc)(port, c);
585 struct s3c24xx_uart_clksrc *clksrc;
587 unsigned int divslot;
592 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
593 struct uart_port *port,
594 struct s3c24xx_uart_clksrc *clksrc,
597 struct s3c24xx_uart_port *ourport = to_ourport(port);
600 calc->src = clk_get(port->dev, clksrc->name);
601 if (calc->src == NULL || IS_ERR(calc->src))
604 rate = clk_get_rate(calc->src);
605 rate /= clksrc->divisor;
607 calc->clksrc = clksrc;
609 if (ourport->info->has_divslot) {
610 unsigned long div = rate / baud;
612 /* The UDIVSLOT register on the newer UARTs allows us to
613 * get a divisor adjustment of 1/16th on the baud clock.
615 * We don't keep the UDIVSLOT value (the 16ths we calculated
616 * by not multiplying the baud by 16) as it is easy enough
620 calc->quot = div / 16;
621 calc->calc = rate / div;
623 calc->quot = (rate + (8 * baud)) / (16 * baud);
624 calc->calc = (rate / (calc->quot * 16));
631 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
632 struct s3c24xx_uart_clksrc **clksrc,
636 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
637 struct s3c24xx_uart_clksrc *clkp;
638 struct baud_calc res[MAX_CLKS];
639 struct baud_calc *resptr, *best, *sptr;
645 if (cfg->clocks_size < 2) {
646 if (cfg->clocks_size == 0)
649 /* check to see if we're sourcing fclk, and if so we're
650 * going to have to update the clock source
653 if (strcmp(clkp->name, "fclk") == 0) {
654 struct s3c24xx_uart_clksrc src;
656 s3c24xx_serial_getsource(port, &src);
658 /* check that the port already using fclk, and if
659 * not, then re-select fclk
662 if (strcmp(src.name, clkp->name) == 0) {
663 s3c24xx_serial_setsource(port, clkp);
664 s3c24xx_serial_getsource(port, &src);
667 clkp->divisor = src.divisor;
670 s3c24xx_serial_calcbaud(res, port, clkp, baud);
676 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
677 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
682 /* ok, we now need to select the best clock we found */
685 unsigned int deviation = (1<<30)|((1<<30)-1);
688 for (sptr = res; sptr < resptr; sptr++) {
689 calc_deviation = baud - sptr->calc;
690 if (calc_deviation < 0)
691 calc_deviation = -calc_deviation;
693 if (calc_deviation < deviation) {
695 deviation = calc_deviation;
700 /* store results to pass back */
702 *clksrc = best->clksrc;
710 * This table takes the fractional value of the baud divisor and gives
711 * the recommended setting for the UDIVSLOT register.
713 static u16 udivslot_table[16] = {
732 static void s3c24xx_serial_set_termios(struct uart_port *port,
733 struct ktermios *termios,
734 struct ktermios *old)
736 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
737 struct s3c24xx_uart_port *ourport = to_ourport(port);
738 struct s3c24xx_uart_clksrc *clksrc = NULL;
739 struct clk *clk = NULL;
741 unsigned int baud, quot;
744 unsigned int udivslot = 0;
747 * We don't support modem control lines.
749 termios->c_cflag &= ~(HUPCL | CMSPAR);
750 termios->c_cflag |= CLOCAL;
753 * Ask the core to calculate the divisor for us.
756 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
758 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
759 quot = port->custom_divisor;
761 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
763 /* check to see if we need to change clock source */
765 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
766 dbg("selecting clock %p\n", clk);
767 s3c24xx_serial_setsource(port, clksrc);
769 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
770 clk_disable(ourport->baudclk);
771 ourport->baudclk = NULL;
776 ourport->clksrc = clksrc;
777 ourport->baudclk = clk;
778 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
781 if (ourport->info->has_divslot) {
782 unsigned int div = ourport->baudclk_rate / baud;
784 if (cfg->has_fracval) {
785 udivslot = (div & 15);
786 dbg("fracval = %04x\n", udivslot);
788 udivslot = udivslot_table[div & 15];
789 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
793 switch (termios->c_cflag & CSIZE) {
795 dbg("config: 5bits/char\n");
796 ulcon = S3C2410_LCON_CS5;
799 dbg("config: 6bits/char\n");
800 ulcon = S3C2410_LCON_CS6;
803 dbg("config: 7bits/char\n");
804 ulcon = S3C2410_LCON_CS7;
808 dbg("config: 8bits/char\n");
809 ulcon = S3C2410_LCON_CS8;
813 /* preserve original lcon IR settings */
814 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
816 if (termios->c_cflag & CSTOPB)
817 ulcon |= S3C2410_LCON_STOPB;
819 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
821 if (termios->c_cflag & PARENB) {
822 if (termios->c_cflag & PARODD)
823 ulcon |= S3C2410_LCON_PODD;
825 ulcon |= S3C2410_LCON_PEVEN;
827 ulcon |= S3C2410_LCON_PNONE;
830 spin_lock_irqsave(&port->lock, flags);
832 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
833 ulcon, quot, udivslot);
835 wr_regl(port, S3C2410_ULCON, ulcon);
836 wr_regl(port, S3C2410_UBRDIV, quot);
837 wr_regl(port, S3C2410_UMCON, umcon);
839 if (ourport->info->has_divslot)
840 wr_regl(port, S3C2443_DIVSLOT, udivslot);
842 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
843 rd_regl(port, S3C2410_ULCON),
844 rd_regl(port, S3C2410_UCON),
845 rd_regl(port, S3C2410_UFCON));
848 * Update the per-port timeout.
850 uart_update_timeout(port, termios->c_cflag, baud);
853 * Which character status flags are we interested in?
855 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
856 if (termios->c_iflag & INPCK)
857 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
860 * Which character status flags should we ignore?
862 port->ignore_status_mask = 0;
863 if (termios->c_iflag & IGNPAR)
864 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
865 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
866 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
869 * Ignore all characters if CREAD is not set.
871 if ((termios->c_cflag & CREAD) == 0)
872 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
874 spin_unlock_irqrestore(&port->lock, flags);
877 static const char *s3c24xx_serial_type(struct uart_port *port)
879 switch (port->type) {
893 #define MAP_SIZE (0x100)
895 static void s3c24xx_serial_release_port(struct uart_port *port)
897 release_mem_region(port->mapbase, MAP_SIZE);
900 static int s3c24xx_serial_request_port(struct uart_port *port)
902 const char *name = s3c24xx_serial_portname(port);
903 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
906 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
908 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
910 if (flags & UART_CONFIG_TYPE &&
911 s3c24xx_serial_request_port(port) == 0)
912 port->type = info->type;
916 * verify the new serial_struct (for TIOCSSERIAL).
919 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
921 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
923 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
930 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
932 static struct console s3c24xx_serial_console;
934 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
936 #define S3C24XX_SERIAL_CONSOLE NULL
939 static struct uart_ops s3c24xx_serial_ops = {
940 .pm = s3c24xx_serial_pm,
941 .tx_empty = s3c24xx_serial_tx_empty,
942 .get_mctrl = s3c24xx_serial_get_mctrl,
943 .set_mctrl = s3c24xx_serial_set_mctrl,
944 .stop_tx = s3c24xx_serial_stop_tx,
945 .start_tx = s3c24xx_serial_start_tx,
946 .stop_rx = s3c24xx_serial_stop_rx,
947 .enable_ms = s3c24xx_serial_enable_ms,
948 .break_ctl = s3c24xx_serial_break_ctl,
949 .startup = s3c24xx_serial_startup,
950 .shutdown = s3c24xx_serial_shutdown,
951 .set_termios = s3c24xx_serial_set_termios,
952 .type = s3c24xx_serial_type,
953 .release_port = s3c24xx_serial_release_port,
954 .request_port = s3c24xx_serial_request_port,
955 .config_port = s3c24xx_serial_config_port,
956 .verify_port = s3c24xx_serial_verify_port,
959 static struct uart_driver s3c24xx_uart_drv = {
960 .owner = THIS_MODULE,
961 .driver_name = "s3c2410_serial",
962 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
963 .cons = S3C24XX_SERIAL_CONSOLE,
964 .dev_name = S3C24XX_SERIAL_NAME,
965 .major = S3C24XX_SERIAL_MAJOR,
966 .minor = S3C24XX_SERIAL_MINOR,
969 static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
972 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
976 .ops = &s3c24xx_serial_ops,
977 .flags = UPF_BOOT_AUTOCONF,
983 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
987 .ops = &s3c24xx_serial_ops,
988 .flags = UPF_BOOT_AUTOCONF,
992 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
996 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
1000 .ops = &s3c24xx_serial_ops,
1001 .flags = UPF_BOOT_AUTOCONF,
1006 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1009 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
1013 .ops = &s3c24xx_serial_ops,
1014 .flags = UPF_BOOT_AUTOCONF,
1021 /* s3c24xx_serial_resetport
1023 * wrapper to call the specific reset for this port (reset the fifos
1027 static inline int s3c24xx_serial_resetport(struct uart_port *port,
1028 struct s3c2410_uartcfg *cfg)
1030 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1032 return (info->reset_port)(port, cfg);
1036 #ifdef CONFIG_CPU_FREQ
1038 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1039 unsigned long val, void *data)
1041 struct s3c24xx_uart_port *port;
1042 struct uart_port *uport;
1044 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1045 uport = &port->port;
1047 /* check to see if port is enabled */
1049 if (port->pm_level != 0)
1052 /* try and work out if the baudrate is changing, we can detect
1053 * a change in rate, but we do not have support for detecting
1054 * a disturbance in the clock-rate over the change.
1057 if (IS_ERR(port->clk))
1060 if (port->baudclk_rate == clk_get_rate(port->clk))
1063 if (val == CPUFREQ_PRECHANGE) {
1064 /* we should really shut the port down whilst the
1065 * frequency change is in progress. */
1067 } else if (val == CPUFREQ_POSTCHANGE) {
1068 struct ktermios *termios;
1069 struct tty_struct *tty;
1071 if (uport->state == NULL)
1074 tty = uport->state->port.tty;
1079 termios = tty->termios;
1081 if (termios == NULL) {
1082 printk(KERN_WARNING "%s: no termios?\n", __func__);
1086 s3c24xx_serial_set_termios(uport, termios, NULL);
1093 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1095 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1097 return cpufreq_register_notifier(&port->freq_transition,
1098 CPUFREQ_TRANSITION_NOTIFIER);
1101 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1103 cpufreq_unregister_notifier(&port->freq_transition,
1104 CPUFREQ_TRANSITION_NOTIFIER);
1108 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1113 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1118 /* s3c24xx_serial_init_port
1120 * initialise a single serial port from the platform device given
1123 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1124 struct s3c24xx_uart_info *info,
1125 struct platform_device *platdev)
1127 struct uart_port *port = &ourport->port;
1128 struct s3c2410_uartcfg *cfg;
1129 struct resource *res;
1132 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1134 if (platdev == NULL)
1137 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1139 if (port->mapbase != 0)
1142 if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
1143 printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
1144 cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
1148 /* setup info for port */
1149 port->dev = &platdev->dev;
1150 ourport->info = info;
1152 /* Startup sequence is different for s3c64xx and higher SoC's */
1153 if (s3c24xx_serial_has_interrupt_mask(port))
1154 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1156 /* copy the info in from provided structure */
1157 ourport->port.fifosize = info->fifosize;
1159 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1163 if (cfg->uart_flags & UPF_CONS_FLOW) {
1164 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1165 port->flags |= UPF_CONS_FLOW;
1168 /* sort our the physical and virtual addresses for each UART */
1170 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1172 printk(KERN_ERR "failed to find memory resource for uart\n");
1176 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1178 port->mapbase = res->start;
1179 port->membase = S3C_VA_UART + (res->start & 0xfffff);
1180 ret = platform_get_irq(platdev, 0);
1185 ourport->rx_irq = ret;
1186 ourport->tx_irq = ret + 1;
1189 ret = platform_get_irq(platdev, 1);
1191 ourport->tx_irq = ret;
1193 ourport->clk = clk_get(&platdev->dev, "uart");
1195 /* Keep all interrupts masked and cleared */
1196 if (s3c24xx_serial_has_interrupt_mask(port)) {
1197 wr_regl(port, S3C64XX_UINTM, 0xf);
1198 wr_regl(port, S3C64XX_UINTP, 0xf);
1199 wr_regl(port, S3C64XX_UINTSP, 0xf);
1202 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1203 port->mapbase, port->membase, port->irq,
1204 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1206 /* reset the fifos (and setup the uart) */
1207 s3c24xx_serial_resetport(port, cfg);
1211 static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1212 struct device_attribute *attr,
1215 struct uart_port *port = s3c24xx_dev_to_port(dev);
1216 struct s3c24xx_uart_port *ourport = to_ourport(port);
1218 return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name);
1221 static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1223 /* Device driver serial port probe */
1225 static int probe_index;
1227 int s3c24xx_serial_probe(struct platform_device *dev,
1228 struct s3c24xx_uart_info *info)
1230 struct s3c24xx_uart_port *ourport;
1233 dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
1235 ourport = &s3c24xx_serial_ports[probe_index];
1238 dbg("%s: initialising port %p...\n", __func__, ourport);
1240 ret = s3c24xx_serial_init_port(ourport, info, dev);
1244 dbg("%s: adding port\n", __func__);
1245 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1246 platform_set_drvdata(dev, &ourport->port);
1248 ret = device_create_file(&dev->dev, &dev_attr_clock_source);
1250 printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
1252 ret = s3c24xx_serial_cpufreq_register(ourport);
1254 dev_err(&dev->dev, "failed to add cpufreq notifier\n");
1262 EXPORT_SYMBOL_GPL(s3c24xx_serial_probe);
1264 int __devexit s3c24xx_serial_remove(struct platform_device *dev)
1266 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1269 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1270 device_remove_file(&dev->dev, &dev_attr_clock_source);
1271 uart_remove_one_port(&s3c24xx_uart_drv, port);
1277 EXPORT_SYMBOL_GPL(s3c24xx_serial_remove);
1279 /* UART power management code */
1280 #ifdef CONFIG_PM_SLEEP
1281 static int s3c24xx_serial_suspend(struct device *dev)
1283 struct uart_port *port = s3c24xx_dev_to_port(dev);
1286 uart_suspend_port(&s3c24xx_uart_drv, port);
1291 static int s3c24xx_serial_resume(struct device *dev)
1293 struct uart_port *port = s3c24xx_dev_to_port(dev);
1294 struct s3c24xx_uart_port *ourport = to_ourport(port);
1297 clk_enable(ourport->clk);
1298 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1299 clk_disable(ourport->clk);
1301 uart_resume_port(&s3c24xx_uart_drv, port);
1307 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1308 .suspend = s3c24xx_serial_suspend,
1309 .resume = s3c24xx_serial_resume,
1311 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1313 #else /* !CONFIG_PM_SLEEP */
1315 #define SERIAL_SAMSUNG_PM_OPS NULL
1316 #endif /* CONFIG_PM_SLEEP */
1318 int s3c24xx_serial_init(struct platform_driver *drv,
1319 struct s3c24xx_uart_info *info)
1321 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1323 drv->driver.pm = SERIAL_SAMSUNG_PM_OPS;
1325 return platform_driver_register(drv);
1328 EXPORT_SYMBOL_GPL(s3c24xx_serial_init);
1330 /* module initialisation code */
1332 static int __init s3c24xx_serial_modinit(void)
1336 ret = uart_register_driver(&s3c24xx_uart_drv);
1338 printk(KERN_ERR "failed to register UART driver\n");
1345 static void __exit s3c24xx_serial_modexit(void)
1347 uart_unregister_driver(&s3c24xx_uart_drv);
1350 module_init(s3c24xx_serial_modinit);
1351 module_exit(s3c24xx_serial_modexit);
1355 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1357 static struct uart_port *cons_uart;
1360 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1362 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1363 unsigned long ufstat, utrstat;
1365 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1366 /* fifo mode - check amount of data in fifo registers... */
1368 ufstat = rd_regl(port, S3C2410_UFSTAT);
1369 return (ufstat & info->tx_fifofull) ? 0 : 1;
1372 /* in non-fifo mode, we go and use the tx buffer empty */
1374 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1375 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1379 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1381 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1382 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1384 wr_regb(cons_uart, S3C2410_UTXH, ch);
1388 s3c24xx_serial_console_write(struct console *co, const char *s,
1391 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1395 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1396 int *parity, int *bits)
1398 struct s3c24xx_uart_clksrc clksrc;
1402 unsigned int ubrdiv;
1405 ulcon = rd_regl(port, S3C2410_ULCON);
1406 ucon = rd_regl(port, S3C2410_UCON);
1407 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1409 dbg("s3c24xx_serial_get_options: port=%p\n"
1410 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1411 port, ulcon, ucon, ubrdiv);
1413 if ((ucon & 0xf) != 0) {
1414 /* consider the serial port configured if the tx/rx mode set */
1416 switch (ulcon & S3C2410_LCON_CSMASK) {
1417 case S3C2410_LCON_CS5:
1420 case S3C2410_LCON_CS6:
1423 case S3C2410_LCON_CS7:
1427 case S3C2410_LCON_CS8:
1432 switch (ulcon & S3C2410_LCON_PMASK) {
1433 case S3C2410_LCON_PEVEN:
1437 case S3C2410_LCON_PODD:
1441 case S3C2410_LCON_PNONE:
1446 /* now calculate the baud rate */
1448 s3c24xx_serial_getsource(port, &clksrc);
1450 clk = clk_get(port->dev, clksrc.name);
1451 if (!IS_ERR(clk) && clk != NULL)
1452 rate = clk_get_rate(clk) / clksrc.divisor;
1457 *baud = rate / (16 * (ubrdiv + 1));
1458 dbg("calculated baud %d\n", *baud);
1463 /* s3c24xx_serial_init_ports
1465 * initialise the serial ports from the machine provided initialisation
1469 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info **info)
1471 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1472 struct platform_device **platdev_ptr;
1475 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1477 platdev_ptr = s3c24xx_uart_devs;
1479 for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) {
1480 s3c24xx_serial_init_port(ptr, info[i], *platdev_ptr);
1487 s3c24xx_serial_console_setup(struct console *co, char *options)
1489 struct uart_port *port;
1495 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1496 co, co->index, options);
1498 /* is this a valid port */
1500 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1503 port = &s3c24xx_serial_ports[co->index].port;
1505 /* is the port configured? */
1507 if (port->mapbase == 0x0)
1512 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1515 * Check whether an invalid uart number has been specified, and
1516 * if so, search for the first available port that does have
1520 uart_parse_options(options, &baud, &parity, &bits, &flow);
1522 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1524 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1526 return uart_set_options(port, co, baud, parity, bits, flow);
1529 /* s3c24xx_serial_initconsole
1531 * initialise the console from one of the uart drivers
1534 static struct console s3c24xx_serial_console = {
1535 .name = S3C24XX_SERIAL_NAME,
1536 .device = uart_console_device,
1537 .flags = CON_PRINTBUFFER,
1539 .write = s3c24xx_serial_console_write,
1540 .setup = s3c24xx_serial_console_setup,
1541 .data = &s3c24xx_uart_drv,
1544 int s3c24xx_serial_initconsole(struct platform_driver *drv,
1545 struct s3c24xx_uart_info **info)
1548 struct platform_device *dev = s3c24xx_uart_devs[0];
1550 dbg("s3c24xx_serial_initconsole\n");
1552 /* select driver based on the cpu */
1555 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1559 if (strcmp(dev->name, drv->driver.name) != 0)
1562 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1563 s3c24xx_serial_init_ports(info);
1565 register_console(&s3c24xx_serial_console);
1569 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1571 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1572 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1573 MODULE_LICENSE("GPL v2");