drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/serial_reg.h>
  19 #include <linux/slab.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/tty.h>
  24 #include <linux/tty_flip.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/dmi.h>
  28
  29 #include <linux/dmaengine.h>
  30 #include <linux/pch_dma.h>
  31
  32 enum {
  33         PCH_UART_HANDLED_RX_INT_SHIFT,
  34         PCH_UART_HANDLED_TX_INT_SHIFT,
  35         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  36         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  37         PCH_UART_HANDLED_MS_INT_SHIFT,
  38 };
  39
  40 enum {
  41         PCH_UART_8LINE,
  42         PCH_UART_2LINE,
  43 };
  44
  45 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  46
  47 /* Set the max number of UART port
  48  * Intel EG20T PCH: 4 port
  49  * LAPIS Semiconductor ML7213 IOH: 3 port
  50  * LAPIS Semiconductor ML7223 IOH: 2 port
  51 */
  52 #define PCH_UART_NR     4
  53
  54 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  55 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  56 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  57                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  58 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  59                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  60 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  61
  62 #define PCH_UART_RBR            0x00
  63 #define PCH_UART_THR            0x00
  64
  65 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  66                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  67 #define PCH_UART_IER_ERBFI      0x00000001
  68 #define PCH_UART_IER_ETBEI      0x00000002
  69 #define PCH_UART_IER_ELSI       0x00000004
  70 #define PCH_UART_IER_EDSSI      0x00000008
  71
  72 #define PCH_UART_IIR_IP                 0x00000001
  73 #define PCH_UART_IIR_IID                0x00000006
  74 #define PCH_UART_IIR_MSI                0x00000000
  75 #define PCH_UART_IIR_TRI                0x00000002
  76 #define PCH_UART_IIR_RRI                0x00000004
  77 #define PCH_UART_IIR_REI                0x00000006
  78 #define PCH_UART_IIR_TOI                0x00000008
  79 #define PCH_UART_IIR_FIFO256            0x00000020
  80 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  81 #define PCH_UART_IIR_FE                 0x000000C0
  82
  83 #define PCH_UART_FCR_FIFOE              0x00000001
  84 #define PCH_UART_FCR_RFR                0x00000002
  85 #define PCH_UART_FCR_TFR                0x00000004
  86 #define PCH_UART_FCR_DMS                0x00000008
  87 #define PCH_UART_FCR_FIFO256            0x00000020
  88 #define PCH_UART_FCR_RFTL               0x000000C0
  89
  90 #define PCH_UART_FCR_RFTL1              0x00000000
  91 #define PCH_UART_FCR_RFTL64             0x00000040
  92 #define PCH_UART_FCR_RFTL128            0x00000080
  93 #define PCH_UART_FCR_RFTL224            0x000000C0
  94 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  95 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  96 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  97 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  98 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  99 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 100 #define PCH_UART_FCR_RFTL_SHIFT         6
 101
 102 #define PCH_UART_LCR_WLS        0x00000003
 103 #define PCH_UART_LCR_STB        0x00000004
 104 #define PCH_UART_LCR_PEN        0x00000008
 105 #define PCH_UART_LCR_EPS        0x00000010
 106 #define PCH_UART_LCR_SP         0x00000020
 107 #define PCH_UART_LCR_SB         0x00000040
 108 #define PCH_UART_LCR_DLAB       0x00000080
 109 #define PCH_UART_LCR_NP         0x00000000
 110 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 111 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 112 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 113 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 114                                 PCH_UART_LCR_SP)
 115
 116 #define PCH_UART_LCR_5BIT       0x00000000
 117 #define PCH_UART_LCR_6BIT       0x00000001
 118 #define PCH_UART_LCR_7BIT       0x00000002
 119 #define PCH_UART_LCR_8BIT       0x00000003
 120
 121 #define PCH_UART_MCR_DTR        0x00000001
 122 #define PCH_UART_MCR_RTS        0x00000002
 123 #define PCH_UART_MCR_OUT        0x0000000C
 124 #define PCH_UART_MCR_LOOP       0x00000010
 125 #define PCH_UART_MCR_AFE        0x00000020
 126
 127 #define PCH_UART_LSR_DR         0x00000001
 128 #define PCH_UART_LSR_ERR        (1<<7)
 129
 130 #define PCH_UART_MSR_DCTS       0x00000001
 131 #define PCH_UART_MSR_DDSR       0x00000002
 132 #define PCH_UART_MSR_TERI       0x00000004
 133 #define PCH_UART_MSR_DDCD       0x00000008
 134 #define PCH_UART_MSR_CTS        0x00000010
 135 #define PCH_UART_MSR_DSR        0x00000020
 136 #define PCH_UART_MSR_RI         0x00000040
 137 #define PCH_UART_MSR_DCD        0x00000080
 138 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 139                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 140
 141 #define PCH_UART_DLL            0x00
 142 #define PCH_UART_DLM            0x01
 143
 144 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 145 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 146 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 147 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 148 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 149
 150 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 151 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 152 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 153 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 154 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 155 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 156 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 157 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 158 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 159 #define PCH_UART_HAL_STB1               0
 160 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 161
 162 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 163 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 164 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 165                                         PCH_UART_HAL_CLR_RX_FIFO)
 166
 167 #define PCH_UART_HAL_DMA_MODE0          0
 168 #define PCH_UART_HAL_FIFO_DIS           0
 169 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 170 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 171                                         PCH_UART_FCR_FIFO256)
 172 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 173 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 174 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 175 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 176 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 177 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 178 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 179 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 180 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 181 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 182 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 183 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 184 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 185 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 186
 187 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 188 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 189 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 190 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 191 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 192
 193 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 194 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 195 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 196 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 197 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 198
 199 #define PCI_VENDOR_ID_ROHM              0x10DB
 200
 201 struct pch_uart_buffer {
 202         unsigned char *buf;
 203         int size;
 204 };
 205
 206 struct eg20t_port {
 207         struct uart_port port;
 208         int port_type;
 209         void __iomem *membase;
 210         resource_size_t mapbase;
 211         unsigned int iobase;
 212         struct pci_dev *pdev;
 213         int fifo_size;
 214         int base_baud;
 215         int start_tx;
 216         int start_rx;
 217         int tx_empty;
 218         int int_dis_flag;
 219         int trigger;
 220         int trigger_level;
 221         struct pch_uart_buffer rxbuf;
 222         unsigned int dmsr;
 223         unsigned int fcr;
 224         unsigned int mcr;
 225         unsigned int use_dma;
 226         unsigned int use_dma_flag;
 227         struct dma_async_tx_descriptor  *desc_tx;
 228         struct dma_async_tx_descriptor  *desc_rx;
 229         struct pch_dma_slave            param_tx;
 230         struct pch_dma_slave            param_rx;
 231         struct dma_chan                 *chan_tx;
 232         struct dma_chan                 *chan_rx;
 233         struct scatterlist              *sg_tx_p;
 234         int                             nent;
 235         struct scatterlist              sg_rx;
 236         int                             tx_dma_use;
 237         void                            *rx_buf_virt;
 238         dma_addr_t                      rx_buf_dma;
 239
 240         /* protect the eg20t_port private structure and io access to membase */
 241         spinlock_t lock;
 242 };
 243
 244 /**
 245  * struct pch_uart_driver_data - private data structure for UART-DMA
 246  * @port_type:                  The number of DMA channel
 247  * @line_no:                    UART port line number (0, 1, 2...)
 248  */
 249 struct pch_uart_driver_data {
 250         int port_type;
 251         int line_no;
 252 };
 253
 254 enum pch_uart_num_t {
 255         pch_et20t_uart0 = 0,
 256         pch_et20t_uart1,
 257         pch_et20t_uart2,
 258         pch_et20t_uart3,
 259         pch_ml7213_uart0,
 260         pch_ml7213_uart1,
 261         pch_ml7213_uart2,
 262         pch_ml7223_uart0,
 263         pch_ml7223_uart1,
 264         pch_ml7831_uart0,
 265         pch_ml7831_uart1,
 266 };
 267
 268 static struct pch_uart_driver_data drv_dat[] = {
 269         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 270         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 271         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 272         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 273         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 274         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 275         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 276         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
 277         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
 278         [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
 279         [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
 280 };
 281
 282 static unsigned int default_baud = 9600;
 283 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 284 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 285 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 286 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 287
 288 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
 289                                  int base_baud)
 290 {
 291         struct eg20t_port *priv = pci_get_drvdata(pdev);
 292
 293         priv->trigger_level = 1;
 294         priv->fcr = 0;
 295 }
 296
 297 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
 298 {
 299         unsigned int msr = ioread8(base + UART_MSR);
 300         priv->dmsr |= msr & PCH_UART_MSR_DELTA;
 301
 302         return msr;
 303 }
 304
 305 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 306                                           unsigned int flag)
 307 {
 308         u8 ier = ioread8(priv->membase + UART_IER);
 309         ier |= flag & PCH_UART_IER_MASK;
 310         iowrite8(ier, priv->membase + UART_IER);
 311 }
 312
 313 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 314                                            unsigned int flag)
 315 {
 316         u8 ier = ioread8(priv->membase + UART_IER);
 317         ier &= ~(flag & PCH_UART_IER_MASK);
 318         iowrite8(ier, priv->membase + UART_IER);
 319 }
 320
 321 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 322                                  unsigned int parity, unsigned int bits,
 323                                  unsigned int stb)
 324 {
 325         unsigned int dll, dlm, lcr;
 326         int div;
 327
 328         div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
 329         if (div < 0 || USHRT_MAX <= div) {
 330                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 331                 return -EINVAL;
 332         }
 333
 334         dll = (unsigned int)div & 0x00FFU;
 335         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 336
 337         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 338                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 339                 return -EINVAL;
 340         }
 341
 342         if (bits & ~PCH_UART_LCR_WLS) {
 343                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 344                 return -EINVAL;
 345         }
 346
 347         if (stb & ~PCH_UART_LCR_STB) {
 348                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 349                 return -EINVAL;
 350         }
 351
 352         lcr = parity;
 353         lcr |= bits;
 354         lcr |= stb;
 355
 356         dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 357                  __func__, baud, div, lcr, jiffies);
 358         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 359         iowrite8(dll, priv->membase + PCH_UART_DLL);
 360         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 361         iowrite8(lcr, priv->membase + UART_LCR);
 362
 363         return 0;
 364 }
 365
 366 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 367                                     unsigned int flag)
 368 {
 369         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 370                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 371                         __func__, flag);
 372                 return -EINVAL;
 373         }
 374
 375         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 376         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 377                  priv->membase + UART_FCR);
 378         iowrite8(priv->fcr, priv->membase + UART_FCR);
 379
 380         return 0;
 381 }
 382
 383 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 384                                  unsigned int dmamode,
 385                                  unsigned int fifo_size, unsigned int trigger)
 386 {
 387         u8 fcr;
 388
 389         if (dmamode & ~PCH_UART_FCR_DMS) {
 390                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 391                         __func__, dmamode);
 392                 return -EINVAL;
 393         }
 394
 395         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 396                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 397                         __func__, fifo_size);
 398                 return -EINVAL;
 399         }
 400
 401         if (trigger & ~PCH_UART_FCR_RFTL) {
 402                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 403                         __func__, trigger);
 404                 return -EINVAL;
 405         }
 406
 407         switch (priv->fifo_size) {
 408         case 256:
 409                 priv->trigger_level =
 410                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 411                 break;
 412         case 64:
 413                 priv->trigger_level =
 414                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 415                 break;
 416         case 16:
 417                 priv->trigger_level =
 418                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 419                 break;
 420         default:
 421                 priv->trigger_level =
 422                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 423                 break;
 424         }
 425         fcr =
 426             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 427         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 428         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 429                  priv->membase + UART_FCR);
 430         iowrite8(fcr, priv->membase + UART_FCR);
 431         priv->fcr = fcr;
 432
 433         return 0;
 434 }
 435
 436 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 437 {
 438         priv->dmsr = 0;
 439         return get_msr(priv, priv->membase);
 440 }
 441
 442 static void pch_uart_hal_write(struct eg20t_port *priv,
 443                               const unsigned char *buf, int tx_size)
 444 {
 445         int i;
 446         unsigned int thr;
 447
 448         for (i = 0; i < tx_size;) {
 449                 thr = buf[i++];
 450                 iowrite8(thr, priv->membase + PCH_UART_THR);
 451         }
 452 }
 453
 454 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 455                              int rx_size)
 456 {
 457         int i;
 458         u8 rbr, lsr;
 459
 460         lsr = ioread8(priv->membase + UART_LSR);
 461         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 462              i < rx_size && lsr & UART_LSR_DR;
 463              lsr = ioread8(priv->membase + UART_LSR)) {
 464                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 465                 buf[i++] = rbr;
 466         }
 467         return i;
 468 }
 469
 470 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
 471 {
 472         unsigned int iir;
 473         int ret;
 474
 475         iir = ioread8(priv->membase + UART_IIR);
 476         ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
 477         return ret;
 478 }
 479
 480 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 481 {
 482         return ioread8(priv->membase + UART_LSR);
 483 }
 484
 485 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 486 {
 487         unsigned int lcr;
 488
 489         lcr = ioread8(priv->membase + UART_LCR);
 490         if (on)
 491                 lcr |= PCH_UART_LCR_SB;
 492         else
 493                 lcr &= ~PCH_UART_LCR_SB;
 494
 495         iowrite8(lcr, priv->membase + UART_LCR);
 496 }
 497
 498 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 499                    int size)
 500 {
 501         struct uart_port *port;
 502         struct tty_struct *tty;
 503
 504         port = &priv->port;
 505         tty = tty_port_tty_get(&port->state->port);
 506         if (!tty) {
 507                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 508                 return -EBUSY;
 509         }
 510
 511         tty_insert_flip_string(tty, buf, size);
 512         tty_flip_buffer_push(tty);
 513         tty_kref_put(tty);
 514
 515         return 0;
 516 }
 517
 518 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 519 {
 520         int ret;
 521         struct uart_port *port = &priv->port;
 522
 523         if (port->x_char) {
 524                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 525                         __func__, port->x_char, jiffies);
 526                 buf[0] = port->x_char;
 527                 port->x_char = 0;
 528                 ret = 1;
 529         } else {
 530                 ret = 0;
 531         }
 532
 533         return ret;
 534 }
 535
 536 static int dma_push_rx(struct eg20t_port *priv, int size)
 537 {
 538         struct tty_struct *tty;
 539         int room;
 540         struct uart_port *port = &priv->port;
 541
 542         port = &priv->port;
 543         tty = tty_port_tty_get(&port->state->port);
 544         if (!tty) {
 545                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 546                 return 0;
 547         }
 548
 549         room = tty_buffer_request_room(tty, size);
 550
 551         if (room < size)
 552                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 553                          size - room);
 554         if (!room)
 555                 goto out;
 556
 557         tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
 558
 559         port->icount.rx += room;
 560 out:
 561         tty_kref_put(tty);
 562
 563         return room;
 564 }
 565
 566 static void pch_free_dma(struct uart_port *port)
 567 {
 568         struct eg20t_port *priv;
 569         priv = container_of(port, struct eg20t_port, port);
 570
 571         if (priv->chan_tx) {
 572                 dma_release_channel(priv->chan_tx);
 573                 priv->chan_tx = NULL;
 574         }
 575         if (priv->chan_rx) {
 576                 dma_release_channel(priv->chan_rx);
 577                 priv->chan_rx = NULL;
 578         }
 579         if (sg_dma_address(&priv->sg_rx))
 580                 dma_free_coherent(port->dev, port->fifosize,
 581                                   sg_virt(&priv->sg_rx),
 582                                   sg_dma_address(&priv->sg_rx));
 583
 584         return;
 585 }
 586
 587 static bool filter(struct dma_chan *chan, void *slave)
 588 {
 589         struct pch_dma_slave *param = slave;
 590
 591         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 592                                                   chan->device->dev)) {
 593                 chan->private = param;
 594                 return true;
 595         } else {
 596                 return false;
 597         }
 598 }
 599
 600 static void pch_request_dma(struct uart_port *port)
 601 {
 602         dma_cap_mask_t mask;
 603         struct dma_chan *chan;
 604         struct pci_dev *dma_dev;
 605         struct pch_dma_slave *param;
 606         struct eg20t_port *priv =
 607                                 container_of(port, struct eg20t_port, port);
 608         dma_cap_zero(mask);
 609         dma_cap_set(DMA_SLAVE, mask);
 610
 611         dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
 612                                        PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 613                                                                 information */
 614         /* Set Tx DMA */
 615         param = &priv->param_tx;
 616         param->dma_dev = &dma_dev->dev;
 617         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 618
 619         param->tx_reg = port->mapbase + UART_TX;
 620         chan = dma_request_channel(mask, filter, param);
 621         if (!chan) {
 622                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 623                         __func__);
 624                 return;
 625         }
 626         priv->chan_tx = chan;
 627
 628         /* Set Rx DMA */
 629         param = &priv->param_rx;
 630         param->dma_dev = &dma_dev->dev;
 631         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 632
 633         param->rx_reg = port->mapbase + UART_RX;
 634         chan = dma_request_channel(mask, filter, param);
 635         if (!chan) {
 636                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 637                         __func__);
 638                 dma_release_channel(priv->chan_tx);
 639                 priv->chan_tx = NULL;
 640                 return;
 641         }
 642
 643         /* Get Consistent memory for DMA */
 644         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 645                                     &priv->rx_buf_dma, GFP_KERNEL);
 646         priv->chan_rx = chan;
 647 }
 648
 649 static void pch_dma_rx_complete(void *arg)
 650 {
 651         struct eg20t_port *priv = arg;
 652         struct uart_port *port = &priv->port;
 653         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 654         int count;
 655
 656         if (!tty) {
 657                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 658                 return;
 659         }
 660
 661         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 662         count = dma_push_rx(priv, priv->trigger_level);
 663         if (count)
 664                 tty_flip_buffer_push(tty);
 665         tty_kref_put(tty);
 666         async_tx_ack(priv->desc_rx);
 667         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 668                                             PCH_UART_HAL_RX_ERR_INT);
 669 }
 670
 671 static void pch_dma_tx_complete(void *arg)
 672 {
 673         struct eg20t_port *priv = arg;
 674         struct uart_port *port = &priv->port;
 675         struct circ_buf *xmit = &port->state->xmit;
 676         struct scatterlist *sg = priv->sg_tx_p;
 677         int i;
 678
 679         for (i = 0; i < priv->nent; i++, sg++) {
 680                 xmit->tail += sg_dma_len(sg);
 681                 port->icount.tx += sg_dma_len(sg);
 682         }
 683         xmit->tail &= UART_XMIT_SIZE - 1;
 684         async_tx_ack(priv->desc_tx);
 685         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 686         priv->tx_dma_use = 0;
 687         priv->nent = 0;
 688         kfree(priv->sg_tx_p);
 689         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 690 }
 691
 692 static int pop_tx(struct eg20t_port *priv, int size)
 693 {
 694         int count = 0;
 695         struct uart_port *port = &priv->port;
 696         struct circ_buf *xmit = &port->state->xmit;
 697
 698         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 699                 goto pop_tx_end;
 700
 701         do {
 702                 int cnt_to_end =
 703                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 704                 int sz = min(size - count, cnt_to_end);
 705                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 706                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 707                 count += sz;
 708         } while (!uart_circ_empty(xmit) && count < size);
 709
 710 pop_tx_end:
 711         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 712                  count, size - count, jiffies);
 713
 714         return count;
 715 }
 716
 717 static int handle_rx_to(struct eg20t_port *priv)
 718 {
 719         struct pch_uart_buffer *buf;
 720         int rx_size;
 721         int ret;
 722         if (!priv->start_rx) {
 723                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 724                                                      PCH_UART_HAL_RX_ERR_INT);
 725                 return 0;
 726         }
 727         buf = &priv->rxbuf;
 728         do {
 729                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 730                 ret = push_rx(priv, buf->buf, rx_size);
 731                 if (ret)
 732                         return 0;
 733         } while (rx_size == buf->size);
 734
 735         return PCH_UART_HANDLED_RX_INT;
 736 }
 737
 738 static int handle_rx(struct eg20t_port *priv)
 739 {
 740         return handle_rx_to(priv);
 741 }
 742
 743 static int dma_handle_rx(struct eg20t_port *priv)
 744 {
 745         struct uart_port *port = &priv->port;
 746         struct dma_async_tx_descriptor *desc;
 747         struct scatterlist *sg;
 748
 749         priv = container_of(port, struct eg20t_port, port);
 750         sg = &priv->sg_rx;
 751
 752         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 753
 754         sg_dma_len(sg) = priv->trigger_level;
 755
 756         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 757                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 758                      ~PAGE_MASK);
 759
 760         sg_dma_address(sg) = priv->rx_buf_dma;
 761
 762         desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
 763                         sg, 1, DMA_FROM_DEVICE,
 764                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 765
 766         if (!desc)
 767                 return 0;
 768
 769         priv->desc_rx = desc;
 770         desc->callback = pch_dma_rx_complete;
 771         desc->callback_param = priv;
 772         desc->tx_submit(desc);
 773         dma_async_issue_pending(priv->chan_rx);
 774
 775         return PCH_UART_HANDLED_RX_INT;
 776 }
 777
 778 static unsigned int handle_tx(struct eg20t_port *priv)
 779 {
 780         struct uart_port *port = &priv->port;
 781         struct circ_buf *xmit = &port->state->xmit;
 782         int fifo_size;
 783         int tx_size;
 784         int size;
 785         int tx_empty;
 786
 787         if (!priv->start_tx) {
 788                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 789                         __func__, jiffies);
 790                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 791                 priv->tx_empty = 1;
 792                 return 0;
 793         }
 794
 795         fifo_size = max(priv->fifo_size, 1);
 796         tx_empty = 1;
 797         if (pop_tx_x(priv, xmit->buf)) {
 798                 pch_uart_hal_write(priv, xmit->buf, 1);
 799                 port->icount.tx++;
 800                 tx_empty = 0;
 801                 fifo_size--;
 802         }
 803         size = min(xmit->head - xmit->tail, fifo_size);
 804         if (size < 0)
 805                 size = fifo_size;
 806
 807         tx_size = pop_tx(priv, size);
 808         if (tx_size > 0) {
 809                 port->icount.tx += tx_size;
 810                 tx_empty = 0;
 811         }
 812
 813         priv->tx_empty = tx_empty;
 814
 815         if (tx_empty) {
 816                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 817                 uart_write_wakeup(port);
 818         }
 819
 820         return PCH_UART_HANDLED_TX_INT;
 821 }
 822
 823 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 824 {
 825         struct uart_port *port = &priv->port;
 826         struct circ_buf *xmit = &port->state->xmit;
 827         struct scatterlist *sg;
 828         int nent;
 829         int fifo_size;
 830         int tx_empty;
 831         struct dma_async_tx_descriptor *desc;
 832         int num;
 833         int i;
 834         int bytes;
 835         int size;
 836         int rem;
 837
 838         if (!priv->start_tx) {
 839                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 840                         __func__, jiffies);
 841                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 842                 priv->tx_empty = 1;
 843                 return 0;
 844         }
 845
 846         if (priv->tx_dma_use) {
 847                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 848                         __func__, jiffies);
 849                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 850                 priv->tx_empty = 1;
 851                 return 0;
 852         }
 853
 854         fifo_size = max(priv->fifo_size, 1);
 855         tx_empty = 1;
 856         if (pop_tx_x(priv, xmit->buf)) {
 857                 pch_uart_hal_write(priv, xmit->buf, 1);
 858                 port->icount.tx++;
 859                 tx_empty = 0;
 860                 fifo_size--;
 861         }
 862
 863         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 864                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 865                              xmit->tail, UART_XMIT_SIZE));
 866         if (!bytes) {
 867                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 868                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 869                 uart_write_wakeup(port);
 870                 return 0;
 871         }
 872
 873         if (bytes > fifo_size) {
 874                 num = bytes / fifo_size + 1;
 875                 size = fifo_size;
 876                 rem = bytes % fifo_size;
 877         } else {
 878                 num = 1;
 879                 size = bytes;
 880                 rem = bytes;
 881         }
 882
 883         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 884                 __func__, num, size, rem);
 885
 886         priv->tx_dma_use = 1;
 887
 888         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 889
 890         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 891         sg = priv->sg_tx_p;
 892
 893         for (i = 0; i < num; i++, sg++) {
 894                 if (i == (num - 1))
 895                         sg_set_page(sg, virt_to_page(xmit->buf),
 896                                     rem, fifo_size * i);
 897                 else
 898                         sg_set_page(sg, virt_to_page(xmit->buf),
 899                                     size, fifo_size * i);
 900         }
 901
 902         sg = priv->sg_tx_p;
 903         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
 904         if (!nent) {
 905                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
 906                 return 0;
 907         }
 908         priv->nent = nent;
 909
 910         for (i = 0; i < nent; i++, sg++) {
 911                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
 912                               fifo_size * i;
 913                 sg_dma_address(sg) = (sg_dma_address(sg) &
 914                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
 915                 if (i == (nent - 1))
 916                         sg_dma_len(sg) = rem;
 917                 else
 918                         sg_dma_len(sg) = size;
 919         }
 920
 921         desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
 922                                         priv->sg_tx_p, nent, DMA_TO_DEVICE,
 923                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 924         if (!desc) {
 925                 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
 926                         __func__);
 927                 return 0;
 928         }
 929         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
 930         priv->desc_tx = desc;
 931         desc->callback = pch_dma_tx_complete;
 932         desc->callback_param = priv;
 933
 934         desc->tx_submit(desc);
 935
 936         dma_async_issue_pending(priv->chan_tx);
 937
 938         return PCH_UART_HANDLED_TX_INT;
 939 }
 940
 941 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
 942 {
 943         u8 fcr = ioread8(priv->membase + UART_FCR);
 944         struct uart_port *port = &priv->port;
 945         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 946         char   *error_msg[5] = {};
 947         int    i = 0;
 948
 949         /* Reset FIFO */
 950         fcr |= UART_FCR_CLEAR_RCVR;
 951         iowrite8(fcr, priv->membase + UART_FCR);
 952
 953         if (lsr & PCH_UART_LSR_ERR)
 954                 error_msg[i++] = "Error data in FIFO\n";
 955
 956         if (lsr & UART_LSR_FE) {
 957                 port->icount.frame++;
 958                 error_msg[i++] = "  Framing Error\n";
 959         }
 960
 961         if (lsr & UART_LSR_PE) {
 962                 port->icount.parity++;
 963                 error_msg[i++] = "  Parity Error\n";
 964         }
 965
 966         if (lsr & UART_LSR_OE) {
 967                 port->icount.overrun++;
 968                 error_msg[i++] = "  Overrun Error\n";
 969         }
 970
 971         if (tty == NULL) {
 972                 for (i = 0; error_msg[i] != NULL; i++)
 973                         dev_err(&priv->pdev->dev, error_msg[i]);
 974         } else {
 975                 tty_kref_put(tty);
 976         }
 977 }
 978
 979 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
 980 {
 981         struct eg20t_port *priv = dev_id;
 982         unsigned int handled;
 983         u8 lsr;
 984         int ret = 0;
 985         unsigned int iid;
 986         unsigned long flags;
 987
 988         spin_lock_irqsave(&priv->lock, flags);
 989         handled = 0;
 990         while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
 991                 switch (iid) {
 992                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
 993                         lsr = pch_uart_hal_get_line_status(priv);
 994                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
 995                                                 UART_LSR_PE | UART_LSR_OE)) {
 996                                 pch_uart_err_ir(priv, lsr);
 997                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
 998                         }
 999                         break;
1000                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1001                         if (priv->use_dma) {
1002                                 pch_uart_hal_disable_interrupt(priv,
1003                                                 PCH_UART_HAL_RX_INT |
1004                                                 PCH_UART_HAL_RX_ERR_INT);
1005                                 ret = dma_handle_rx(priv);
1006                                 if (!ret)
1007                                         pch_uart_hal_enable_interrupt(priv,
1008                                                 PCH_UART_HAL_RX_INT |
1009                                                 PCH_UART_HAL_RX_ERR_INT);
1010                         } else {
1011                                 ret = handle_rx(priv);
1012                         }
1013                         break;
1014                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1015                                                    (FIFO Timeout) */
1016                         ret = handle_rx_to(priv);
1017                         break;
1018                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1019                                                    Empty */
1020                         if (priv->use_dma)
1021                                 ret = dma_handle_tx(priv);
1022                         else
1023                                 ret = handle_tx(priv);
1024                         break;
1025                 case PCH_UART_IID_MS:   /* Modem Status */
1026                         ret = PCH_UART_HANDLED_MS_INT;
1027                         break;
1028                 default:        /* Never junp to this label */
1029                         dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1030                                 iid, jiffies);
1031                         ret = -1;
1032                         break;
1033                 }
1034                 handled |= (unsigned int)ret;
1035         }
1036         if (handled == 0 && iid <= 1) {
1037                 if (priv->int_dis_flag)
1038                         priv->int_dis_flag = 0;
1039         }
1040
1041         spin_unlock_irqrestore(&priv->lock, flags);
1042         return IRQ_RETVAL(handled);
1043 }
1044
1045 /* This function tests whether the transmitter fifo and shifter for the port
1046                                                 described by 'port' is empty. */
1047 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1048 {
1049         struct eg20t_port *priv;
1050         int ret;
1051         priv = container_of(port, struct eg20t_port, port);
1052         if (priv->tx_empty)
1053                 ret = TIOCSER_TEMT;
1054         else
1055                 ret = 0;
1056
1057         return ret;
1058 }
1059
1060 /* Returns the current state of modem control inputs. */
1061 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1062 {
1063         struct eg20t_port *priv;
1064         u8 modem;
1065         unsigned int ret = 0;
1066
1067         priv = container_of(port, struct eg20t_port, port);
1068         modem = pch_uart_hal_get_modem(priv);
1069
1070         if (modem & UART_MSR_DCD)
1071                 ret |= TIOCM_CAR;
1072
1073         if (modem & UART_MSR_RI)
1074                 ret |= TIOCM_RNG;
1075
1076         if (modem & UART_MSR_DSR)
1077                 ret |= TIOCM_DSR;
1078
1079         if (modem & UART_MSR_CTS)
1080                 ret |= TIOCM_CTS;
1081
1082         return ret;
1083 }
1084
1085 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1086 {
1087         u32 mcr = 0;
1088         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1089
1090         if (mctrl & TIOCM_DTR)
1091                 mcr |= UART_MCR_DTR;
1092         if (mctrl & TIOCM_RTS)
1093                 mcr |= UART_MCR_RTS;
1094         if (mctrl & TIOCM_LOOP)
1095                 mcr |= UART_MCR_LOOP;
1096
1097         if (priv->mcr & UART_MCR_AFE)
1098                 mcr |= UART_MCR_AFE;
1099
1100         if (mctrl)
1101                 iowrite8(mcr, priv->membase + UART_MCR);
1102 }
1103
1104 static void pch_uart_stop_tx(struct uart_port *port)
1105 {
1106         struct eg20t_port *priv;
1107         priv = container_of(port, struct eg20t_port, port);
1108         priv->start_tx = 0;
1109         priv->tx_dma_use = 0;
1110 }
1111
1112 static void pch_uart_start_tx(struct uart_port *port)
1113 {
1114         struct eg20t_port *priv;
1115
1116         priv = container_of(port, struct eg20t_port, port);
1117
1118         if (priv->use_dma) {
1119                 if (priv->tx_dma_use) {
1120                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1121                                 __func__);
1122                         return;
1123                 }
1124         }
1125
1126         priv->start_tx = 1;
1127         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1128 }
1129
1130 static void pch_uart_stop_rx(struct uart_port *port)
1131 {
1132         struct eg20t_port *priv;
1133         priv = container_of(port, struct eg20t_port, port);
1134         priv->start_rx = 0;
1135         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1136                                              PCH_UART_HAL_RX_ERR_INT);
1137         priv->int_dis_flag = 1;
1138 }
1139
1140 /* Enable the modem status interrupts. */
1141 static void pch_uart_enable_ms(struct uart_port *port)
1142 {
1143         struct eg20t_port *priv;
1144         priv = container_of(port, struct eg20t_port, port);
1145         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1146 }
1147
1148 /* Control the transmission of a break signal. */
1149 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1150 {
1151         struct eg20t_port *priv;
1152         unsigned long flags;
1153
1154         priv = container_of(port, struct eg20t_port, port);
1155         spin_lock_irqsave(&priv->lock, flags);
1156         pch_uart_hal_set_break(priv, ctl);
1157         spin_unlock_irqrestore(&priv->lock, flags);
1158 }
1159
1160 /* Grab any interrupt resources and initialise any low level driver state. */
1161 static int pch_uart_startup(struct uart_port *port)
1162 {
1163         struct eg20t_port *priv;
1164         int ret;
1165         int fifo_size;
1166         int trigger_level;
1167
1168         priv = container_of(port, struct eg20t_port, port);
1169         priv->tx_empty = 1;
1170
1171         if (port->uartclk)
1172                 priv->base_baud = port->uartclk;
1173         else
1174                 port->uartclk = priv->base_baud;
1175
1176         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1177         ret = pch_uart_hal_set_line(priv, default_baud,
1178                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1179                               PCH_UART_HAL_STB1);
1180         if (ret)
1181                 return ret;
1182
1183         switch (priv->fifo_size) {
1184         case 256:
1185                 fifo_size = PCH_UART_HAL_FIFO256;
1186                 break;
1187         case 64:
1188                 fifo_size = PCH_UART_HAL_FIFO64;
1189                 break;
1190         case 16:
1191                 fifo_size = PCH_UART_HAL_FIFO16;
1192                 break;
1193         case 1:
1194         default:
1195                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1196                 break;
1197         }
1198
1199         switch (priv->trigger) {
1200         case PCH_UART_HAL_TRIGGER1:
1201                 trigger_level = 1;
1202                 break;
1203         case PCH_UART_HAL_TRIGGER_L:
1204                 trigger_level = priv->fifo_size / 4;
1205                 break;
1206         case PCH_UART_HAL_TRIGGER_M:
1207                 trigger_level = priv->fifo_size / 2;
1208                 break;
1209         case PCH_UART_HAL_TRIGGER_H:
1210         default:
1211                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1212                 break;
1213         }
1214
1215         priv->trigger_level = trigger_level;
1216         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1217                                     fifo_size, priv->trigger);
1218         if (ret < 0)
1219                 return ret;
1220
1221         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1222                         KBUILD_MODNAME, priv);
1223         if (ret < 0)
1224                 return ret;
1225
1226         if (priv->use_dma)
1227                 pch_request_dma(port);
1228
1229         priv->start_rx = 1;
1230         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1231                                             PCH_UART_HAL_RX_ERR_INT);
1232         uart_update_timeout(port, CS8, default_baud);
1233
1234         return 0;
1235 }
1236
1237 static void pch_uart_shutdown(struct uart_port *port)
1238 {
1239         struct eg20t_port *priv;
1240         int ret;
1241
1242         priv = container_of(port, struct eg20t_port, port);
1243         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1244         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1245         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1246                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1247         if (ret)
1248                 dev_err(priv->port.dev,
1249                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1250
1251         pch_free_dma(port);
1252
1253         free_irq(priv->port.irq, priv);
1254 }
1255
1256 /* Change the port parameters, including word length, parity, stop
1257  *bits.  Update read_status_mask and ignore_status_mask to indicate
1258  *the types of events we are interested in receiving.  */
1259 static void pch_uart_set_termios(struct uart_port *port,
1260                                  struct ktermios *termios, struct ktermios *old)
1261 {
1262         int baud;
1263         int rtn;
1264         unsigned int parity, bits, stb;
1265         struct eg20t_port *priv;
1266         unsigned long flags;
1267
1268         priv = container_of(port, struct eg20t_port, port);
1269         switch (termios->c_cflag & CSIZE) {
1270         case CS5:
1271                 bits = PCH_UART_HAL_5BIT;
1272                 break;
1273         case CS6:
1274                 bits = PCH_UART_HAL_6BIT;
1275                 break;
1276         case CS7:
1277                 bits = PCH_UART_HAL_7BIT;
1278                 break;
1279         default:                /* CS8 */
1280                 bits = PCH_UART_HAL_8BIT;
1281                 break;
1282         }
1283         if (termios->c_cflag & CSTOPB)
1284                 stb = PCH_UART_HAL_STB2;
1285         else
1286                 stb = PCH_UART_HAL_STB1;
1287
1288         if (termios->c_cflag & PARENB) {
1289                 if (termios->c_cflag & PARODD)
1290                         parity = PCH_UART_HAL_PARITY_ODD;
1291                 else
1292                         parity = PCH_UART_HAL_PARITY_EVEN;
1293
1294         } else {
1295                 parity = PCH_UART_HAL_PARITY_NONE;
1296         }
1297
1298         /* Only UART0 has auto hardware flow function */
1299         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1300                 priv->mcr |= UART_MCR_AFE;
1301         else
1302                 priv->mcr &= ~UART_MCR_AFE;
1303
1304         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1305
1306         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1307
1308         spin_lock_irqsave(&priv->lock, flags);
1309         spin_lock(&port->lock);
1310
1311         uart_update_timeout(port, termios->c_cflag, baud);
1312         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1313         if (rtn)
1314                 goto out;
1315
1316         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1317         /* Don't rewrite B0 */
1318         if (tty_termios_baud_rate(termios))
1319                 tty_termios_encode_baud_rate(termios, baud, baud);
1320
1321 out:
1322         spin_unlock(&port->lock);
1323         spin_unlock_irqrestore(&priv->lock, flags);
1324 }
1325
1326 static const char *pch_uart_type(struct uart_port *port)
1327 {
1328         return KBUILD_MODNAME;
1329 }
1330
1331 static void pch_uart_release_port(struct uart_port *port)
1332 {
1333         struct eg20t_port *priv;
1334
1335         priv = container_of(port, struct eg20t_port, port);
1336         pci_iounmap(priv->pdev, priv->membase);
1337         pci_release_regions(priv->pdev);
1338 }
1339
1340 static int pch_uart_request_port(struct uart_port *port)
1341 {
1342         struct eg20t_port *priv;
1343         int ret;
1344         void __iomem *membase;
1345
1346         priv = container_of(port, struct eg20t_port, port);
1347         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1348         if (ret < 0)
1349                 return -EBUSY;
1350
1351         membase = pci_iomap(priv->pdev, 1, 0);
1352         if (!membase) {
1353                 pci_release_regions(priv->pdev);
1354                 return -EBUSY;
1355         }
1356         priv->membase = port->membase = membase;
1357
1358         return 0;
1359 }
1360
1361 static void pch_uart_config_port(struct uart_port *port, int type)
1362 {
1363         struct eg20t_port *priv;
1364
1365         priv = container_of(port, struct eg20t_port, port);
1366         if (type & UART_CONFIG_TYPE) {
1367                 port->type = priv->port_type;
1368                 pch_uart_request_port(port);
1369         }
1370 }
1371
1372 static int pch_uart_verify_port(struct uart_port *port,
1373                                 struct serial_struct *serinfo)
1374 {
1375         struct eg20t_port *priv;
1376
1377         priv = container_of(port, struct eg20t_port, port);
1378         if (serinfo->flags & UPF_LOW_LATENCY) {
1379                 dev_info(priv->port.dev,
1380                         "PCH UART : Use PIO Mode (without DMA)\n");
1381                 priv->use_dma = 0;
1382                 serinfo->flags &= ~UPF_LOW_LATENCY;
1383         } else {
1384 #ifndef CONFIG_PCH_DMA
1385                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1386                         __func__);
1387                 return -EOPNOTSUPP;
1388 #endif
1389                 priv->use_dma_flag = 1;
1390                 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1391                 if (!priv->use_dma)
1392                         pch_request_dma(port);
1393                 priv->use_dma = 1;
1394         }
1395
1396         return 0;
1397 }
1398
1399 static struct uart_ops pch_uart_ops = {
1400         .tx_empty = pch_uart_tx_empty,
1401         .set_mctrl = pch_uart_set_mctrl,
1402         .get_mctrl = pch_uart_get_mctrl,
1403         .stop_tx = pch_uart_stop_tx,
1404         .start_tx = pch_uart_start_tx,
1405         .stop_rx = pch_uart_stop_rx,
1406         .enable_ms = pch_uart_enable_ms,
1407         .break_ctl = pch_uart_break_ctl,
1408         .startup = pch_uart_startup,
1409         .shutdown = pch_uart_shutdown,
1410         .set_termios = pch_uart_set_termios,
1411 /*      .pm             = pch_uart_pm,          Not supported yet */
1412 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1413         .type = pch_uart_type,
1414         .release_port = pch_uart_release_port,
1415         .request_port = pch_uart_request_port,
1416         .config_port = pch_uart_config_port,
1417         .verify_port = pch_uart_verify_port
1418 };
1419
1420 static struct uart_driver pch_uart_driver = {
1421         .owner = THIS_MODULE,
1422         .driver_name = KBUILD_MODNAME,
1423         .dev_name = PCH_UART_DRIVER_DEVICE,
1424         .major = 0,
1425         .minor = 0,
1426         .nr = PCH_UART_NR,
1427 };
1428
1429 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1430                                              const struct pci_device_id *id)
1431 {
1432         struct eg20t_port *priv;
1433         int ret;
1434         unsigned int iobase;
1435         unsigned int mapbase;
1436         unsigned char *rxbuf;
1437         int fifosize, base_baud;
1438         int port_type;
1439         struct pch_uart_driver_data *board;
1440         const char *board_name;
1441
1442         board = &drv_dat[id->driver_data];
1443         port_type = board->port_type;
1444
1445         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1446         if (priv == NULL)
1447                 goto init_port_alloc_err;
1448
1449         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1450         if (!rxbuf)
1451                 goto init_port_free_txbuf;
1452
1453         base_baud = 1843200; /* 1.8432MHz */
1454
1455         /* quirk for CM-iTC board */
1456         board_name = dmi_get_system_info(DMI_BOARD_NAME);
1457         if (board_name && strstr(board_name, "CM-iTC"))
1458                 base_baud = 192000000; /* 192.0MHz */
1459
1460         switch (port_type) {
1461         case PORT_UNKNOWN:
1462                 fifosize = 256; /* EG20T/ML7213: UART0 */
1463                 break;
1464         case PORT_8250:
1465                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1466                 break;
1467         default:
1468                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1469                 goto init_port_hal_free;
1470         }
1471
1472         pci_enable_msi(pdev);
1473         pci_set_master(pdev);
1474
1475         spin_lock_init(&priv->lock);
1476
1477         iobase = pci_resource_start(pdev, 0);
1478         mapbase = pci_resource_start(pdev, 1);
1479         priv->mapbase = mapbase;
1480         priv->iobase = iobase;
1481         priv->pdev = pdev;
1482         priv->tx_empty = 1;
1483         priv->rxbuf.buf = rxbuf;
1484         priv->rxbuf.size = PAGE_SIZE;
1485
1486         priv->fifo_size = fifosize;
1487         priv->base_baud = base_baud;
1488         priv->port_type = PORT_MAX_8250 + port_type + 1;
1489         priv->port.dev = &pdev->dev;
1490         priv->port.iobase = iobase;
1491         priv->port.membase = NULL;
1492         priv->port.mapbase = mapbase;
1493         priv->port.irq = pdev->irq;
1494         priv->port.iotype = UPIO_PORT;
1495         priv->port.ops = &pch_uart_ops;
1496         priv->port.flags = UPF_BOOT_AUTOCONF;
1497         priv->port.fifosize = fifosize;
1498         priv->port.line = board->line_no;
1499         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1500
1501         spin_lock_init(&priv->port.lock);
1502
1503         pci_set_drvdata(pdev, priv);
1504         pch_uart_hal_request(pdev, fifosize, base_baud);
1505
1506         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1507         if (ret < 0)
1508                 goto init_port_hal_free;
1509
1510         return priv;
1511
1512 init_port_hal_free:
1513         free_page((unsigned long)rxbuf);
1514 init_port_free_txbuf:
1515         kfree(priv);
1516 init_port_alloc_err:
1517
1518         return NULL;
1519 }
1520
1521 static void pch_uart_exit_port(struct eg20t_port *priv)
1522 {
1523         uart_remove_one_port(&pch_uart_driver, &priv->port);
1524         pci_set_drvdata(priv->pdev, NULL);
1525         free_page((unsigned long)priv->rxbuf.buf);
1526 }
1527
1528 static void pch_uart_pci_remove(struct pci_dev *pdev)
1529 {
1530         struct eg20t_port *priv;
1531
1532         priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1533
1534         pci_disable_msi(pdev);
1535         pch_uart_exit_port(priv);
1536         pci_disable_device(pdev);
1537         kfree(priv);
1538         return;
1539 }
1540 #ifdef CONFIG_PM
1541 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1542 {
1543         struct eg20t_port *priv = pci_get_drvdata(pdev);
1544
1545         uart_suspend_port(&pch_uart_driver, &priv->port);
1546
1547         pci_save_state(pdev);
1548         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1549         return 0;
1550 }
1551
1552 static int pch_uart_pci_resume(struct pci_dev *pdev)
1553 {
1554         struct eg20t_port *priv = pci_get_drvdata(pdev);
1555         int ret;
1556
1557         pci_set_power_state(pdev, PCI_D0);
1558         pci_restore_state(pdev);
1559
1560         ret = pci_enable_device(pdev);
1561         if (ret) {
1562                 dev_err(&pdev->dev,
1563                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1564                 return ret;
1565         }
1566
1567         uart_resume_port(&pch_uart_driver, &priv->port);
1568
1569         return 0;
1570 }
1571 #else
1572 #define pch_uart_pci_suspend NULL
1573 #define pch_uart_pci_resume NULL
1574 #endif
1575
1576 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1577         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1578          .driver_data = pch_et20t_uart0},
1579         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1580          .driver_data = pch_et20t_uart1},
1581         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1582          .driver_data = pch_et20t_uart2},
1583         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1584          .driver_data = pch_et20t_uart3},
1585         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1586          .driver_data = pch_ml7213_uart0},
1587         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1588          .driver_data = pch_ml7213_uart1},
1589         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1590          .driver_data = pch_ml7213_uart2},
1591         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1592          .driver_data = pch_ml7223_uart0},
1593         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1594          .driver_data = pch_ml7223_uart1},
1595         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1596          .driver_data = pch_ml7831_uart0},
1597         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1598          .driver_data = pch_ml7831_uart1},
1599         {0,},
1600 };
1601
1602 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1603                                         const struct pci_device_id *id)
1604 {
1605         int ret;
1606         struct eg20t_port *priv;
1607
1608         ret = pci_enable_device(pdev);
1609         if (ret < 0)
1610                 goto probe_error;
1611
1612         priv = pch_uart_init_port(pdev, id);
1613         if (!priv) {
1614                 ret = -EBUSY;
1615                 goto probe_disable_device;
1616         }
1617         pci_set_drvdata(pdev, priv);
1618
1619         return ret;
1620
1621 probe_disable_device:
1622         pci_disable_msi(pdev);
1623         pci_disable_device(pdev);
1624 probe_error:
1625         return ret;
1626 }
1627
1628 static struct pci_driver pch_uart_pci_driver = {
1629         .name = "pch_uart",
1630         .id_table = pch_uart_pci_id,
1631         .probe = pch_uart_pci_probe,
1632         .remove = __devexit_p(pch_uart_pci_remove),
1633         .suspend = pch_uart_pci_suspend,
1634         .resume = pch_uart_pci_resume,
1635 };
1636
1637 static int __init pch_uart_module_init(void)
1638 {
1639         int ret;
1640
1641         /* register as UART driver */
1642         ret = uart_register_driver(&pch_uart_driver);
1643         if (ret < 0)
1644                 return ret;
1645
1646         /* register as PCI driver */
1647         ret = pci_register_driver(&pch_uart_pci_driver);
1648         if (ret < 0)
1649                 uart_unregister_driver(&pch_uart_driver);
1650
1651         return ret;
1652 }
1653 module_init(pch_uart_module_init);
1654
1655 static void __exit pch_uart_module_exit(void)
1656 {
1657         pci_unregister_driver(&pch_uart_pci_driver);
1658         uart_unregister_driver(&pch_uart_driver);
1659 }
1660 module_exit(pch_uart_module_exit);
1661
1662 MODULE_LICENSE("GPL v2");
1663 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1664 module_param(default_baud, uint, S_IRUGO);