2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #include <linux/kernel.h>
18 #include <linux/serial_reg.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/serial_core.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/interrupt.h>
27 #include <linux/dmi.h>
29 #include <linux/dmaengine.h>
30 #include <linux/pch_dma.h>
33 PCH_UART_HANDLED_RX_INT_SHIFT,
34 PCH_UART_HANDLED_TX_INT_SHIFT,
35 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
36 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
37 PCH_UART_HANDLED_MS_INT_SHIFT,
45 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
47 /* Set the max number of UART port
48 * Intel EG20T PCH: 4 port
49 * LAPIS Semiconductor ML7213 IOH: 3 port
50 * LAPIS Semiconductor ML7223 IOH: 2 port
54 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
55 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
56 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
57 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
58 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
59 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
60 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
62 #define PCH_UART_RBR 0x00
63 #define PCH_UART_THR 0x00
65 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
66 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
67 #define PCH_UART_IER_ERBFI 0x00000001
68 #define PCH_UART_IER_ETBEI 0x00000002
69 #define PCH_UART_IER_ELSI 0x00000004
70 #define PCH_UART_IER_EDSSI 0x00000008
72 #define PCH_UART_IIR_IP 0x00000001
73 #define PCH_UART_IIR_IID 0x00000006
74 #define PCH_UART_IIR_MSI 0x00000000
75 #define PCH_UART_IIR_TRI 0x00000002
76 #define PCH_UART_IIR_RRI 0x00000004
77 #define PCH_UART_IIR_REI 0x00000006
78 #define PCH_UART_IIR_TOI 0x00000008
79 #define PCH_UART_IIR_FIFO256 0x00000020
80 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
81 #define PCH_UART_IIR_FE 0x000000C0
83 #define PCH_UART_FCR_FIFOE 0x00000001
84 #define PCH_UART_FCR_RFR 0x00000002
85 #define PCH_UART_FCR_TFR 0x00000004
86 #define PCH_UART_FCR_DMS 0x00000008
87 #define PCH_UART_FCR_FIFO256 0x00000020
88 #define PCH_UART_FCR_RFTL 0x000000C0
90 #define PCH_UART_FCR_RFTL1 0x00000000
91 #define PCH_UART_FCR_RFTL64 0x00000040
92 #define PCH_UART_FCR_RFTL128 0x00000080
93 #define PCH_UART_FCR_RFTL224 0x000000C0
94 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
95 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
96 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
97 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
98 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
99 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
100 #define PCH_UART_FCR_RFTL_SHIFT 6
102 #define PCH_UART_LCR_WLS 0x00000003
103 #define PCH_UART_LCR_STB 0x00000004
104 #define PCH_UART_LCR_PEN 0x00000008
105 #define PCH_UART_LCR_EPS 0x00000010
106 #define PCH_UART_LCR_SP 0x00000020
107 #define PCH_UART_LCR_SB 0x00000040
108 #define PCH_UART_LCR_DLAB 0x00000080
109 #define PCH_UART_LCR_NP 0x00000000
110 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
111 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
112 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
113 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
116 #define PCH_UART_LCR_5BIT 0x00000000
117 #define PCH_UART_LCR_6BIT 0x00000001
118 #define PCH_UART_LCR_7BIT 0x00000002
119 #define PCH_UART_LCR_8BIT 0x00000003
121 #define PCH_UART_MCR_DTR 0x00000001
122 #define PCH_UART_MCR_RTS 0x00000002
123 #define PCH_UART_MCR_OUT 0x0000000C
124 #define PCH_UART_MCR_LOOP 0x00000010
125 #define PCH_UART_MCR_AFE 0x00000020
127 #define PCH_UART_LSR_DR 0x00000001
128 #define PCH_UART_LSR_ERR (1<<7)
130 #define PCH_UART_MSR_DCTS 0x00000001
131 #define PCH_UART_MSR_DDSR 0x00000002
132 #define PCH_UART_MSR_TERI 0x00000004
133 #define PCH_UART_MSR_DDCD 0x00000008
134 #define PCH_UART_MSR_CTS 0x00000010
135 #define PCH_UART_MSR_DSR 0x00000020
136 #define PCH_UART_MSR_RI 0x00000040
137 #define PCH_UART_MSR_DCD 0x00000080
138 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
139 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
141 #define PCH_UART_DLL 0x00
142 #define PCH_UART_DLM 0x01
144 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
145 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
146 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
147 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
148 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
150 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
151 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
152 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
153 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
154 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
155 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
156 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
157 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
158 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
159 #define PCH_UART_HAL_STB1 0
160 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
162 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
163 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
164 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
165 PCH_UART_HAL_CLR_RX_FIFO)
167 #define PCH_UART_HAL_DMA_MODE0 0
168 #define PCH_UART_HAL_FIFO_DIS 0
169 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
170 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
171 PCH_UART_FCR_FIFO256)
172 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
173 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
174 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
175 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
176 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
177 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
178 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
179 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
180 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
181 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
182 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
183 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
184 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
185 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
187 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
188 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
189 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
190 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
191 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
193 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
194 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
195 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
196 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
197 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
199 #define PCI_VENDOR_ID_ROHM 0x10DB
201 struct pch_uart_buffer {
207 struct uart_port port;
209 void __iomem *membase;
210 resource_size_t mapbase;
212 struct pci_dev *pdev;
221 struct pch_uart_buffer rxbuf;
225 unsigned int use_dma;
226 unsigned int use_dma_flag;
227 struct dma_async_tx_descriptor *desc_tx;
228 struct dma_async_tx_descriptor *desc_rx;
229 struct pch_dma_slave param_tx;
230 struct pch_dma_slave param_rx;
231 struct dma_chan *chan_tx;
232 struct dma_chan *chan_rx;
233 struct scatterlist *sg_tx_p;
235 struct scatterlist sg_rx;
238 dma_addr_t rx_buf_dma;
242 * struct pch_uart_driver_data - private data structure for UART-DMA
243 * @port_type: The number of DMA channel
244 * @line_no: UART port line number (0, 1, 2...)
246 struct pch_uart_driver_data {
251 enum pch_uart_num_t {
265 static struct pch_uart_driver_data drv_dat[] = {
266 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
267 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
268 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
269 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
270 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
271 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
272 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
273 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
274 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
275 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
276 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
279 static unsigned int default_baud = 9600;
280 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
281 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
282 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
283 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
285 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
288 struct eg20t_port *priv = pci_get_drvdata(pdev);
290 priv->trigger_level = 1;
294 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
296 unsigned int msr = ioread8(base + UART_MSR);
297 priv->dmsr |= msr & PCH_UART_MSR_DELTA;
302 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
305 u8 ier = ioread8(priv->membase + UART_IER);
306 ier |= flag & PCH_UART_IER_MASK;
307 iowrite8(ier, priv->membase + UART_IER);
310 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
313 u8 ier = ioread8(priv->membase + UART_IER);
314 ier &= ~(flag & PCH_UART_IER_MASK);
315 iowrite8(ier, priv->membase + UART_IER);
318 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
319 unsigned int parity, unsigned int bits,
322 unsigned int dll, dlm, lcr;
325 div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
326 if (div < 0 || USHRT_MAX <= div) {
327 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
331 dll = (unsigned int)div & 0x00FFU;
332 dlm = ((unsigned int)div >> 8) & 0x00FFU;
334 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
335 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
339 if (bits & ~PCH_UART_LCR_WLS) {
340 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
344 if (stb & ~PCH_UART_LCR_STB) {
345 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
353 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
354 __func__, baud, div, lcr, jiffies);
355 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
356 iowrite8(dll, priv->membase + PCH_UART_DLL);
357 iowrite8(dlm, priv->membase + PCH_UART_DLM);
358 iowrite8(lcr, priv->membase + UART_LCR);
363 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
366 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
367 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
372 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
373 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
374 priv->membase + UART_FCR);
375 iowrite8(priv->fcr, priv->membase + UART_FCR);
380 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
381 unsigned int dmamode,
382 unsigned int fifo_size, unsigned int trigger)
386 if (dmamode & ~PCH_UART_FCR_DMS) {
387 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
392 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
393 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
394 __func__, fifo_size);
398 if (trigger & ~PCH_UART_FCR_RFTL) {
399 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
404 switch (priv->fifo_size) {
406 priv->trigger_level =
407 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
410 priv->trigger_level =
411 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
414 priv->trigger_level =
415 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
418 priv->trigger_level =
419 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
423 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
424 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
425 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
426 priv->membase + UART_FCR);
427 iowrite8(fcr, priv->membase + UART_FCR);
433 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
436 return get_msr(priv, priv->membase);
439 static void pch_uart_hal_write(struct eg20t_port *priv,
440 const unsigned char *buf, int tx_size)
445 for (i = 0; i < tx_size;) {
447 iowrite8(thr, priv->membase + PCH_UART_THR);
451 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
457 lsr = ioread8(priv->membase + UART_LSR);
458 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
459 i < rx_size && lsr & UART_LSR_DR;
460 lsr = ioread8(priv->membase + UART_LSR)) {
461 rbr = ioread8(priv->membase + PCH_UART_RBR);
467 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
472 iir = ioread8(priv->membase + UART_IIR);
473 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
477 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
479 return ioread8(priv->membase + UART_LSR);
482 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
486 lcr = ioread8(priv->membase + UART_LCR);
488 lcr |= PCH_UART_LCR_SB;
490 lcr &= ~PCH_UART_LCR_SB;
492 iowrite8(lcr, priv->membase + UART_LCR);
495 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
498 struct uart_port *port;
499 struct tty_struct *tty;
502 tty = tty_port_tty_get(&port->state->port);
504 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
508 tty_insert_flip_string(tty, buf, size);
509 tty_flip_buffer_push(tty);
515 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
518 struct uart_port *port = &priv->port;
521 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
522 __func__, port->x_char, jiffies);
523 buf[0] = port->x_char;
533 static int dma_push_rx(struct eg20t_port *priv, int size)
535 struct tty_struct *tty;
537 struct uart_port *port = &priv->port;
540 tty = tty_port_tty_get(&port->state->port);
542 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
546 room = tty_buffer_request_room(tty, size);
549 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
554 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
556 port->icount.rx += room;
562 static void pch_free_dma(struct uart_port *port)
564 struct eg20t_port *priv;
565 priv = container_of(port, struct eg20t_port, port);
568 dma_release_channel(priv->chan_tx);
569 priv->chan_tx = NULL;
572 dma_release_channel(priv->chan_rx);
573 priv->chan_rx = NULL;
575 if (sg_dma_address(&priv->sg_rx))
576 dma_free_coherent(port->dev, port->fifosize,
577 sg_virt(&priv->sg_rx),
578 sg_dma_address(&priv->sg_rx));
583 static bool filter(struct dma_chan *chan, void *slave)
585 struct pch_dma_slave *param = slave;
587 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
588 chan->device->dev)) {
589 chan->private = param;
596 static void pch_request_dma(struct uart_port *port)
599 struct dma_chan *chan;
600 struct pci_dev *dma_dev;
601 struct pch_dma_slave *param;
602 struct eg20t_port *priv =
603 container_of(port, struct eg20t_port, port);
605 dma_cap_set(DMA_SLAVE, mask);
607 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
608 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
611 param = &priv->param_tx;
612 param->dma_dev = &dma_dev->dev;
613 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
615 param->tx_reg = port->mapbase + UART_TX;
616 chan = dma_request_channel(mask, filter, param);
618 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
622 priv->chan_tx = chan;
625 param = &priv->param_rx;
626 param->dma_dev = &dma_dev->dev;
627 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
629 param->rx_reg = port->mapbase + UART_RX;
630 chan = dma_request_channel(mask, filter, param);
632 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
634 dma_release_channel(priv->chan_tx);
635 priv->chan_tx = NULL;
639 /* Get Consistent memory for DMA */
640 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
641 &priv->rx_buf_dma, GFP_KERNEL);
642 priv->chan_rx = chan;
645 static void pch_dma_rx_complete(void *arg)
647 struct eg20t_port *priv = arg;
648 struct uart_port *port = &priv->port;
649 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
653 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
657 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
658 count = dma_push_rx(priv, priv->trigger_level);
660 tty_flip_buffer_push(tty);
662 async_tx_ack(priv->desc_rx);
663 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
666 static void pch_dma_tx_complete(void *arg)
668 struct eg20t_port *priv = arg;
669 struct uart_port *port = &priv->port;
670 struct circ_buf *xmit = &port->state->xmit;
671 struct scatterlist *sg = priv->sg_tx_p;
674 for (i = 0; i < priv->nent; i++, sg++) {
675 xmit->tail += sg_dma_len(sg);
676 port->icount.tx += sg_dma_len(sg);
678 xmit->tail &= UART_XMIT_SIZE - 1;
679 async_tx_ack(priv->desc_tx);
680 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
681 priv->tx_dma_use = 0;
683 kfree(priv->sg_tx_p);
684 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
687 static int pop_tx(struct eg20t_port *priv, int size)
690 struct uart_port *port = &priv->port;
691 struct circ_buf *xmit = &port->state->xmit;
693 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
698 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
699 int sz = min(size - count, cnt_to_end);
700 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
701 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
703 } while (!uart_circ_empty(xmit) && count < size);
706 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
707 count, size - count, jiffies);
712 static int handle_rx_to(struct eg20t_port *priv)
714 struct pch_uart_buffer *buf;
717 if (!priv->start_rx) {
718 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
723 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
724 ret = push_rx(priv, buf->buf, rx_size);
727 } while (rx_size == buf->size);
729 return PCH_UART_HANDLED_RX_INT;
732 static int handle_rx(struct eg20t_port *priv)
734 return handle_rx_to(priv);
737 static int dma_handle_rx(struct eg20t_port *priv)
739 struct uart_port *port = &priv->port;
740 struct dma_async_tx_descriptor *desc;
741 struct scatterlist *sg;
743 priv = container_of(port, struct eg20t_port, port);
746 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
748 sg_dma_len(sg) = priv->trigger_level;
750 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
751 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
754 sg_dma_address(sg) = priv->rx_buf_dma;
756 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
757 sg, 1, DMA_FROM_DEVICE,
758 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
763 priv->desc_rx = desc;
764 desc->callback = pch_dma_rx_complete;
765 desc->callback_param = priv;
766 desc->tx_submit(desc);
767 dma_async_issue_pending(priv->chan_rx);
769 return PCH_UART_HANDLED_RX_INT;
772 static unsigned int handle_tx(struct eg20t_port *priv)
774 struct uart_port *port = &priv->port;
775 struct circ_buf *xmit = &port->state->xmit;
781 if (!priv->start_tx) {
782 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
784 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
789 fifo_size = max(priv->fifo_size, 1);
791 if (pop_tx_x(priv, xmit->buf)) {
792 pch_uart_hal_write(priv, xmit->buf, 1);
797 size = min(xmit->head - xmit->tail, fifo_size);
801 tx_size = pop_tx(priv, size);
803 port->icount.tx += tx_size;
807 priv->tx_empty = tx_empty;
810 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
811 uart_write_wakeup(port);
814 return PCH_UART_HANDLED_TX_INT;
817 static unsigned int dma_handle_tx(struct eg20t_port *priv)
819 struct uart_port *port = &priv->port;
820 struct circ_buf *xmit = &port->state->xmit;
821 struct scatterlist *sg;
825 struct dma_async_tx_descriptor *desc;
832 if (!priv->start_tx) {
833 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
835 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
840 if (priv->tx_dma_use) {
841 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
843 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
848 fifo_size = max(priv->fifo_size, 1);
850 if (pop_tx_x(priv, xmit->buf)) {
851 pch_uart_hal_write(priv, xmit->buf, 1);
857 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
858 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
859 xmit->tail, UART_XMIT_SIZE));
861 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
862 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
863 uart_write_wakeup(port);
867 if (bytes > fifo_size) {
868 num = bytes / fifo_size + 1;
870 rem = bytes % fifo_size;
877 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
878 __func__, num, size, rem);
880 priv->tx_dma_use = 1;
882 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
884 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
887 for (i = 0; i < num; i++, sg++) {
889 sg_set_page(sg, virt_to_page(xmit->buf),
892 sg_set_page(sg, virt_to_page(xmit->buf),
893 size, fifo_size * i);
897 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
899 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
904 for (i = 0; i < nent; i++, sg++) {
905 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
907 sg_dma_address(sg) = (sg_dma_address(sg) &
908 ~(UART_XMIT_SIZE - 1)) + sg->offset;
910 sg_dma_len(sg) = rem;
912 sg_dma_len(sg) = size;
915 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
916 priv->sg_tx_p, nent, DMA_TO_DEVICE,
917 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
919 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
923 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
924 priv->desc_tx = desc;
925 desc->callback = pch_dma_tx_complete;
926 desc->callback_param = priv;
928 desc->tx_submit(desc);
930 dma_async_issue_pending(priv->chan_tx);
932 return PCH_UART_HANDLED_TX_INT;
935 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
937 u8 fcr = ioread8(priv->membase + UART_FCR);
940 fcr |= UART_FCR_CLEAR_RCVR;
941 iowrite8(fcr, priv->membase + UART_FCR);
943 if (lsr & PCH_UART_LSR_ERR)
944 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
946 if (lsr & UART_LSR_FE)
947 dev_err(&priv->pdev->dev, "Framing Error\n");
949 if (lsr & UART_LSR_PE)
950 dev_err(&priv->pdev->dev, "Parity Error\n");
952 if (lsr & UART_LSR_OE)
953 dev_err(&priv->pdev->dev, "Overrun Error\n");
956 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
958 struct eg20t_port *priv = dev_id;
959 unsigned int handled;
965 spin_lock_irqsave(&priv->port.lock, flags);
967 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
969 case PCH_UART_IID_RLS: /* Receiver Line Status */
970 lsr = pch_uart_hal_get_line_status(priv);
971 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
972 UART_LSR_PE | UART_LSR_OE)) {
973 pch_uart_err_ir(priv, lsr);
974 ret = PCH_UART_HANDLED_RX_ERR_INT;
977 case PCH_UART_IID_RDR: /* Received Data Ready */
979 pch_uart_hal_disable_interrupt(priv,
980 PCH_UART_HAL_RX_INT);
981 ret = dma_handle_rx(priv);
983 pch_uart_hal_enable_interrupt(priv,
984 PCH_UART_HAL_RX_INT);
986 ret = handle_rx(priv);
989 case PCH_UART_IID_RDR_TO: /* Received Data Ready
991 ret = handle_rx_to(priv);
993 case PCH_UART_IID_THRE: /* Transmitter Holding Register
996 ret = dma_handle_tx(priv);
998 ret = handle_tx(priv);
1000 case PCH_UART_IID_MS: /* Modem Status */
1001 ret = PCH_UART_HANDLED_MS_INT;
1003 default: /* Never junp to this label */
1004 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1009 handled |= (unsigned int)ret;
1011 if (handled == 0 && iid <= 1) {
1012 if (priv->int_dis_flag)
1013 priv->int_dis_flag = 0;
1016 spin_unlock_irqrestore(&priv->port.lock, flags);
1017 return IRQ_RETVAL(handled);
1020 /* This function tests whether the transmitter fifo and shifter for the port
1021 described by 'port' is empty. */
1022 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1024 struct eg20t_port *priv;
1026 priv = container_of(port, struct eg20t_port, port);
1035 /* Returns the current state of modem control inputs. */
1036 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1038 struct eg20t_port *priv;
1040 unsigned int ret = 0;
1042 priv = container_of(port, struct eg20t_port, port);
1043 modem = pch_uart_hal_get_modem(priv);
1045 if (modem & UART_MSR_DCD)
1048 if (modem & UART_MSR_RI)
1051 if (modem & UART_MSR_DSR)
1054 if (modem & UART_MSR_CTS)
1060 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1063 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1065 if (mctrl & TIOCM_DTR)
1066 mcr |= UART_MCR_DTR;
1067 if (mctrl & TIOCM_RTS)
1068 mcr |= UART_MCR_RTS;
1069 if (mctrl & TIOCM_LOOP)
1070 mcr |= UART_MCR_LOOP;
1072 if (priv->mcr & UART_MCR_AFE)
1073 mcr |= UART_MCR_AFE;
1076 iowrite8(mcr, priv->membase + UART_MCR);
1079 static void pch_uart_stop_tx(struct uart_port *port)
1081 struct eg20t_port *priv;
1082 priv = container_of(port, struct eg20t_port, port);
1084 priv->tx_dma_use = 0;
1087 static void pch_uart_start_tx(struct uart_port *port)
1089 struct eg20t_port *priv;
1091 priv = container_of(port, struct eg20t_port, port);
1093 if (priv->use_dma) {
1094 if (priv->tx_dma_use) {
1095 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1102 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1105 static void pch_uart_stop_rx(struct uart_port *port)
1107 struct eg20t_port *priv;
1108 priv = container_of(port, struct eg20t_port, port);
1110 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1111 priv->int_dis_flag = 1;
1114 /* Enable the modem status interrupts. */
1115 static void pch_uart_enable_ms(struct uart_port *port)
1117 struct eg20t_port *priv;
1118 priv = container_of(port, struct eg20t_port, port);
1119 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1122 /* Control the transmission of a break signal. */
1123 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1125 struct eg20t_port *priv;
1126 unsigned long flags;
1128 priv = container_of(port, struct eg20t_port, port);
1129 spin_lock_irqsave(&port->lock, flags);
1130 pch_uart_hal_set_break(priv, ctl);
1131 spin_unlock_irqrestore(&port->lock, flags);
1134 /* Grab any interrupt resources and initialise any low level driver state. */
1135 static int pch_uart_startup(struct uart_port *port)
1137 struct eg20t_port *priv;
1142 priv = container_of(port, struct eg20t_port, port);
1146 priv->base_baud = port->uartclk;
1148 port->uartclk = priv->base_baud;
1150 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1151 ret = pch_uart_hal_set_line(priv, default_baud,
1152 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1157 switch (priv->fifo_size) {
1159 fifo_size = PCH_UART_HAL_FIFO256;
1162 fifo_size = PCH_UART_HAL_FIFO64;
1165 fifo_size = PCH_UART_HAL_FIFO16;
1168 fifo_size = PCH_UART_HAL_FIFO_DIS;
1172 switch (priv->trigger) {
1173 case PCH_UART_HAL_TRIGGER1:
1176 case PCH_UART_HAL_TRIGGER_L:
1177 trigger_level = priv->fifo_size / 4;
1179 case PCH_UART_HAL_TRIGGER_M:
1180 trigger_level = priv->fifo_size / 2;
1182 case PCH_UART_HAL_TRIGGER_H:
1184 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1188 priv->trigger_level = trigger_level;
1189 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1190 fifo_size, priv->trigger);
1194 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1195 KBUILD_MODNAME, priv);
1200 pch_request_dma(port);
1203 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1204 uart_update_timeout(port, CS8, default_baud);
1209 static void pch_uart_shutdown(struct uart_port *port)
1211 struct eg20t_port *priv;
1214 priv = container_of(port, struct eg20t_port, port);
1215 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1216 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1217 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1218 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1220 dev_err(priv->port.dev,
1221 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1225 free_irq(priv->port.irq, priv);
1228 /* Change the port parameters, including word length, parity, stop
1229 *bits. Update read_status_mask and ignore_status_mask to indicate
1230 *the types of events we are interested in receiving. */
1231 static void pch_uart_set_termios(struct uart_port *port,
1232 struct ktermios *termios, struct ktermios *old)
1236 unsigned int parity, bits, stb;
1237 struct eg20t_port *priv;
1238 unsigned long flags;
1240 priv = container_of(port, struct eg20t_port, port);
1241 switch (termios->c_cflag & CSIZE) {
1243 bits = PCH_UART_HAL_5BIT;
1246 bits = PCH_UART_HAL_6BIT;
1249 bits = PCH_UART_HAL_7BIT;
1252 bits = PCH_UART_HAL_8BIT;
1255 if (termios->c_cflag & CSTOPB)
1256 stb = PCH_UART_HAL_STB2;
1258 stb = PCH_UART_HAL_STB1;
1260 if (termios->c_cflag & PARENB) {
1261 if (!(termios->c_cflag & PARODD))
1262 parity = PCH_UART_HAL_PARITY_ODD;
1264 parity = PCH_UART_HAL_PARITY_EVEN;
1267 parity = PCH_UART_HAL_PARITY_NONE;
1270 /* Only UART0 has auto hardware flow function */
1271 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1272 priv->mcr |= UART_MCR_AFE;
1274 priv->mcr &= ~UART_MCR_AFE;
1276 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1278 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1280 spin_lock_irqsave(&port->lock, flags);
1282 uart_update_timeout(port, termios->c_cflag, baud);
1283 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1287 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1288 /* Don't rewrite B0 */
1289 if (tty_termios_baud_rate(termios))
1290 tty_termios_encode_baud_rate(termios, baud, baud);
1293 spin_unlock_irqrestore(&port->lock, flags);
1296 static const char *pch_uart_type(struct uart_port *port)
1298 return KBUILD_MODNAME;
1301 static void pch_uart_release_port(struct uart_port *port)
1303 struct eg20t_port *priv;
1305 priv = container_of(port, struct eg20t_port, port);
1306 pci_iounmap(priv->pdev, priv->membase);
1307 pci_release_regions(priv->pdev);
1310 static int pch_uart_request_port(struct uart_port *port)
1312 struct eg20t_port *priv;
1314 void __iomem *membase;
1316 priv = container_of(port, struct eg20t_port, port);
1317 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1321 membase = pci_iomap(priv->pdev, 1, 0);
1323 pci_release_regions(priv->pdev);
1326 priv->membase = port->membase = membase;
1331 static void pch_uart_config_port(struct uart_port *port, int type)
1333 struct eg20t_port *priv;
1335 priv = container_of(port, struct eg20t_port, port);
1336 if (type & UART_CONFIG_TYPE) {
1337 port->type = priv->port_type;
1338 pch_uart_request_port(port);
1342 static int pch_uart_verify_port(struct uart_port *port,
1343 struct serial_struct *serinfo)
1345 struct eg20t_port *priv;
1347 priv = container_of(port, struct eg20t_port, port);
1348 if (serinfo->flags & UPF_LOW_LATENCY) {
1349 dev_info(priv->port.dev,
1350 "PCH UART : Use PIO Mode (without DMA)\n");
1352 serinfo->flags &= ~UPF_LOW_LATENCY;
1354 #ifndef CONFIG_PCH_DMA
1355 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1360 priv->use_dma_flag = 1;
1361 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1367 static struct uart_ops pch_uart_ops = {
1368 .tx_empty = pch_uart_tx_empty,
1369 .set_mctrl = pch_uart_set_mctrl,
1370 .get_mctrl = pch_uart_get_mctrl,
1371 .stop_tx = pch_uart_stop_tx,
1372 .start_tx = pch_uart_start_tx,
1373 .stop_rx = pch_uart_stop_rx,
1374 .enable_ms = pch_uart_enable_ms,
1375 .break_ctl = pch_uart_break_ctl,
1376 .startup = pch_uart_startup,
1377 .shutdown = pch_uart_shutdown,
1378 .set_termios = pch_uart_set_termios,
1379 /* .pm = pch_uart_pm, Not supported yet */
1380 /* .set_wake = pch_uart_set_wake, Not supported yet */
1381 .type = pch_uart_type,
1382 .release_port = pch_uart_release_port,
1383 .request_port = pch_uart_request_port,
1384 .config_port = pch_uart_config_port,
1385 .verify_port = pch_uart_verify_port
1388 static struct uart_driver pch_uart_driver = {
1389 .owner = THIS_MODULE,
1390 .driver_name = KBUILD_MODNAME,
1391 .dev_name = PCH_UART_DRIVER_DEVICE,
1397 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1398 const struct pci_device_id *id)
1400 struct eg20t_port *priv;
1402 unsigned int iobase;
1403 unsigned int mapbase;
1404 unsigned char *rxbuf;
1405 int fifosize, base_baud;
1407 struct pch_uart_driver_data *board;
1408 const char *board_name;
1410 board = &drv_dat[id->driver_data];
1411 port_type = board->port_type;
1413 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1415 goto init_port_alloc_err;
1417 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1419 goto init_port_free_txbuf;
1421 base_baud = 1843200; /* 1.8432MHz */
1423 /* quirk for CM-iTC board */
1424 board_name = dmi_get_system_info(DMI_BOARD_NAME);
1425 if (board_name && strstr(board_name, "CM-iTC"))
1426 base_baud = 192000000; /* 192.0MHz */
1428 switch (port_type) {
1430 fifosize = 256; /* EG20T/ML7213: UART0 */
1433 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1436 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1437 goto init_port_hal_free;
1440 pci_enable_msi(pdev);
1442 iobase = pci_resource_start(pdev, 0);
1443 mapbase = pci_resource_start(pdev, 1);
1444 priv->mapbase = mapbase;
1445 priv->iobase = iobase;
1448 priv->rxbuf.buf = rxbuf;
1449 priv->rxbuf.size = PAGE_SIZE;
1451 priv->fifo_size = fifosize;
1452 priv->base_baud = base_baud;
1453 priv->port_type = PORT_MAX_8250 + port_type + 1;
1454 priv->port.dev = &pdev->dev;
1455 priv->port.iobase = iobase;
1456 priv->port.membase = NULL;
1457 priv->port.mapbase = mapbase;
1458 priv->port.irq = pdev->irq;
1459 priv->port.iotype = UPIO_PORT;
1460 priv->port.ops = &pch_uart_ops;
1461 priv->port.flags = UPF_BOOT_AUTOCONF;
1462 priv->port.fifosize = fifosize;
1463 priv->port.line = board->line_no;
1464 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1466 spin_lock_init(&priv->port.lock);
1468 pci_set_drvdata(pdev, priv);
1469 pch_uart_hal_request(pdev, fifosize, base_baud);
1471 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1473 goto init_port_hal_free;
1478 free_page((unsigned long)rxbuf);
1479 init_port_free_txbuf:
1481 init_port_alloc_err:
1486 static void pch_uart_exit_port(struct eg20t_port *priv)
1488 uart_remove_one_port(&pch_uart_driver, &priv->port);
1489 pci_set_drvdata(priv->pdev, NULL);
1490 free_page((unsigned long)priv->rxbuf.buf);
1493 static void pch_uart_pci_remove(struct pci_dev *pdev)
1495 struct eg20t_port *priv;
1497 priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1499 pci_disable_msi(pdev);
1500 pch_uart_exit_port(priv);
1501 pci_disable_device(pdev);
1506 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1508 struct eg20t_port *priv = pci_get_drvdata(pdev);
1510 uart_suspend_port(&pch_uart_driver, &priv->port);
1512 pci_save_state(pdev);
1513 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1517 static int pch_uart_pci_resume(struct pci_dev *pdev)
1519 struct eg20t_port *priv = pci_get_drvdata(pdev);
1522 pci_set_power_state(pdev, PCI_D0);
1523 pci_restore_state(pdev);
1525 ret = pci_enable_device(pdev);
1528 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1532 uart_resume_port(&pch_uart_driver, &priv->port);
1537 #define pch_uart_pci_suspend NULL
1538 #define pch_uart_pci_resume NULL
1541 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1542 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1543 .driver_data = pch_et20t_uart0},
1544 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1545 .driver_data = pch_et20t_uart1},
1546 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1547 .driver_data = pch_et20t_uart2},
1548 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1549 .driver_data = pch_et20t_uart3},
1550 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1551 .driver_data = pch_ml7213_uart0},
1552 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1553 .driver_data = pch_ml7213_uart1},
1554 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1555 .driver_data = pch_ml7213_uart2},
1556 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1557 .driver_data = pch_ml7223_uart0},
1558 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1559 .driver_data = pch_ml7223_uart1},
1560 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1561 .driver_data = pch_ml7831_uart0},
1562 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1563 .driver_data = pch_ml7831_uart1},
1567 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1568 const struct pci_device_id *id)
1571 struct eg20t_port *priv;
1573 ret = pci_enable_device(pdev);
1577 priv = pch_uart_init_port(pdev, id);
1580 goto probe_disable_device;
1582 pci_set_drvdata(pdev, priv);
1586 probe_disable_device:
1587 pci_disable_msi(pdev);
1588 pci_disable_device(pdev);
1593 static struct pci_driver pch_uart_pci_driver = {
1595 .id_table = pch_uart_pci_id,
1596 .probe = pch_uart_pci_probe,
1597 .remove = __devexit_p(pch_uart_pci_remove),
1598 .suspend = pch_uart_pci_suspend,
1599 .resume = pch_uart_pci_resume,
1602 static int __init pch_uart_module_init(void)
1606 /* register as UART driver */
1607 ret = uart_register_driver(&pch_uart_driver);
1611 /* register as PCI driver */
1612 ret = pci_register_driver(&pch_uart_pci_driver);
1614 uart_unregister_driver(&pch_uart_driver);
1618 module_init(pch_uart_module_init);
1620 static void __exit pch_uart_module_exit(void)
1622 pci_unregister_driver(&pch_uart_pci_driver);
1623 uart_unregister_driver(&pch_uart_driver);
1625 module_exit(pch_uart_module_exit);
1627 MODULE_LICENSE("GPL v2");
1628 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1629 module_param(default_baud, uint, S_IRUGO);