drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/serial_reg.h>
  19 #include <linux/slab.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/tty.h>
  24 #include <linux/tty_flip.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/dmi.h>
  28
  29 #include <linux/dmaengine.h>
  30 #include <linux/pch_dma.h>
  31
  32 enum {
  33         PCH_UART_HANDLED_RX_INT_SHIFT,
  34         PCH_UART_HANDLED_TX_INT_SHIFT,
  35         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  36         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  37         PCH_UART_HANDLED_MS_INT_SHIFT,
  38 };
  39
  40 enum {
  41         PCH_UART_8LINE,
  42         PCH_UART_2LINE,
  43 };
  44
  45 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  46
  47 /* Set the max number of UART port
  48  * Intel EG20T PCH: 4 port
  49  * LAPIS Semiconductor ML7213 IOH: 3 port
  50  * LAPIS Semiconductor ML7223 IOH: 2 port
  51 */
  52 #define PCH_UART_NR     4
  53
  54 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  55 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  56 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  57                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  58 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  59                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  60 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  61
  62 #define PCH_UART_RBR            0x00
  63 #define PCH_UART_THR            0x00
  64
  65 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  66                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  67 #define PCH_UART_IER_ERBFI      0x00000001
  68 #define PCH_UART_IER_ETBEI      0x00000002
  69 #define PCH_UART_IER_ELSI       0x00000004
  70 #define PCH_UART_IER_EDSSI      0x00000008
  71
  72 #define PCH_UART_IIR_IP                 0x00000001
  73 #define PCH_UART_IIR_IID                0x00000006
  74 #define PCH_UART_IIR_MSI                0x00000000
  75 #define PCH_UART_IIR_TRI                0x00000002
  76 #define PCH_UART_IIR_RRI                0x00000004
  77 #define PCH_UART_IIR_REI                0x00000006
  78 #define PCH_UART_IIR_TOI                0x00000008
  79 #define PCH_UART_IIR_FIFO256            0x00000020
  80 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  81 #define PCH_UART_IIR_FE                 0x000000C0
  82
  83 #define PCH_UART_FCR_FIFOE              0x00000001
  84 #define PCH_UART_FCR_RFR                0x00000002
  85 #define PCH_UART_FCR_TFR                0x00000004
  86 #define PCH_UART_FCR_DMS                0x00000008
  87 #define PCH_UART_FCR_FIFO256            0x00000020
  88 #define PCH_UART_FCR_RFTL               0x000000C0
  89
  90 #define PCH_UART_FCR_RFTL1              0x00000000
  91 #define PCH_UART_FCR_RFTL64             0x00000040
  92 #define PCH_UART_FCR_RFTL128            0x00000080
  93 #define PCH_UART_FCR_RFTL224            0x000000C0
  94 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  95 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  96 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  97 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  98 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  99 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 100 #define PCH_UART_FCR_RFTL_SHIFT         6
 101
 102 #define PCH_UART_LCR_WLS        0x00000003
 103 #define PCH_UART_LCR_STB        0x00000004
 104 #define PCH_UART_LCR_PEN        0x00000008
 105 #define PCH_UART_LCR_EPS        0x00000010
 106 #define PCH_UART_LCR_SP         0x00000020
 107 #define PCH_UART_LCR_SB         0x00000040
 108 #define PCH_UART_LCR_DLAB       0x00000080
 109 #define PCH_UART_LCR_NP         0x00000000
 110 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 111 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 112 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 113 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 114                                 PCH_UART_LCR_SP)
 115
 116 #define PCH_UART_LCR_5BIT       0x00000000
 117 #define PCH_UART_LCR_6BIT       0x00000001
 118 #define PCH_UART_LCR_7BIT       0x00000002
 119 #define PCH_UART_LCR_8BIT       0x00000003
 120
 121 #define PCH_UART_MCR_DTR        0x00000001
 122 #define PCH_UART_MCR_RTS        0x00000002
 123 #define PCH_UART_MCR_OUT        0x0000000C
 124 #define PCH_UART_MCR_LOOP       0x00000010
 125 #define PCH_UART_MCR_AFE        0x00000020
 126
 127 #define PCH_UART_LSR_DR         0x00000001
 128 #define PCH_UART_LSR_ERR        (1<<7)
 129
 130 #define PCH_UART_MSR_DCTS       0x00000001
 131 #define PCH_UART_MSR_DDSR       0x00000002
 132 #define PCH_UART_MSR_TERI       0x00000004
 133 #define PCH_UART_MSR_DDCD       0x00000008
 134 #define PCH_UART_MSR_CTS        0x00000010
 135 #define PCH_UART_MSR_DSR        0x00000020
 136 #define PCH_UART_MSR_RI         0x00000040
 137 #define PCH_UART_MSR_DCD        0x00000080
 138 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 139                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 140
 141 #define PCH_UART_DLL            0x00
 142 #define PCH_UART_DLM            0x01
 143
 144 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 145 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 146 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 147 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 148 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 149
 150 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 151 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 152 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 153 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 154 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 155 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 156 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 157 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 158 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 159 #define PCH_UART_HAL_STB1               0
 160 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 161
 162 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 163 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 164 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 165                                         PCH_UART_HAL_CLR_RX_FIFO)
 166
 167 #define PCH_UART_HAL_DMA_MODE0          0
 168 #define PCH_UART_HAL_FIFO_DIS           0
 169 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 170 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 171                                         PCH_UART_FCR_FIFO256)
 172 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 173 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 174 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 175 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 176 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 177 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 178 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 179 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 180 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 181 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 182 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 183 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 184 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 185 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 186
 187 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 188 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 189 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 190 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 191 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 192
 193 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 194 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 195 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 196 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 197 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 198
 199 #define PCI_VENDOR_ID_ROHM              0x10DB
 200
 201 struct pch_uart_buffer {
 202         unsigned char *buf;
 203         int size;
 204 };
 205
 206 struct eg20t_port {
 207         struct uart_port port;
 208         int port_type;
 209         void __iomem *membase;
 210         resource_size_t mapbase;
 211         unsigned int iobase;
 212         struct pci_dev *pdev;
 213         int fifo_size;
 214         int base_baud;
 215         int start_tx;
 216         int start_rx;
 217         int tx_empty;
 218         int int_dis_flag;
 219         int trigger;
 220         int trigger_level;
 221         struct pch_uart_buffer rxbuf;
 222         unsigned int dmsr;
 223         unsigned int fcr;
 224         unsigned int mcr;
 225         unsigned int use_dma;
 226         unsigned int use_dma_flag;
 227         struct dma_async_tx_descriptor  *desc_tx;
 228         struct dma_async_tx_descriptor  *desc_rx;
 229         struct pch_dma_slave            param_tx;
 230         struct pch_dma_slave            param_rx;
 231         struct dma_chan                 *chan_tx;
 232         struct dma_chan                 *chan_rx;
 233         struct scatterlist              *sg_tx_p;
 234         int                             nent;
 235         struct scatterlist              sg_rx;
 236         int                             tx_dma_use;
 237         void                            *rx_buf_virt;
 238         dma_addr_t                      rx_buf_dma;
 239 };
 240
 241 /**
 242  * struct pch_uart_driver_data - private data structure for UART-DMA
 243  * @port_type:                  The number of DMA channel
 244  * @line_no:                    UART port line number (0, 1, 2...)
 245  */
 246 struct pch_uart_driver_data {
 247         int port_type;
 248         int line_no;
 249 };
 250
 251 enum pch_uart_num_t {
 252         pch_et20t_uart0 = 0,
 253         pch_et20t_uart1,
 254         pch_et20t_uart2,
 255         pch_et20t_uart3,
 256         pch_ml7213_uart0,
 257         pch_ml7213_uart1,
 258         pch_ml7213_uart2,
 259         pch_ml7223_uart0,
 260         pch_ml7223_uart1,
 261         pch_ml7831_uart0,
 262         pch_ml7831_uart1,
 263 };
 264
 265 static struct pch_uart_driver_data drv_dat[] = {
 266         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 267         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 268         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 269         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 270         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 271         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 272         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 273         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
 274         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
 275         [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
 276         [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
 277 };
 278
 279 static unsigned int default_baud = 9600;
 280 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 281 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 282 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 283 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 284
 285 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
 286                                  int base_baud)
 287 {
 288         struct eg20t_port *priv = pci_get_drvdata(pdev);
 289
 290         priv->trigger_level = 1;
 291         priv->fcr = 0;
 292 }
 293
 294 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
 295 {
 296         unsigned int msr = ioread8(base + UART_MSR);
 297         priv->dmsr |= msr & PCH_UART_MSR_DELTA;
 298
 299         return msr;
 300 }
 301
 302 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 303                                           unsigned int flag)
 304 {
 305         u8 ier = ioread8(priv->membase + UART_IER);
 306         ier |= flag & PCH_UART_IER_MASK;
 307         iowrite8(ier, priv->membase + UART_IER);
 308 }
 309
 310 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 311                                            unsigned int flag)
 312 {
 313         u8 ier = ioread8(priv->membase + UART_IER);
 314         ier &= ~(flag & PCH_UART_IER_MASK);
 315         iowrite8(ier, priv->membase + UART_IER);
 316 }
 317
 318 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 319                                  unsigned int parity, unsigned int bits,
 320                                  unsigned int stb)
 321 {
 322         unsigned int dll, dlm, lcr;
 323         int div;
 324
 325         div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
 326         if (div < 0 || USHRT_MAX <= div) {
 327                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 328                 return -EINVAL;
 329         }
 330
 331         dll = (unsigned int)div & 0x00FFU;
 332         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 333
 334         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 335                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 336                 return -EINVAL;
 337         }
 338
 339         if (bits & ~PCH_UART_LCR_WLS) {
 340                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 341                 return -EINVAL;
 342         }
 343
 344         if (stb & ~PCH_UART_LCR_STB) {
 345                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 346                 return -EINVAL;
 347         }
 348
 349         lcr = parity;
 350         lcr |= bits;
 351         lcr |= stb;
 352
 353         dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 354                  __func__, baud, div, lcr, jiffies);
 355         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 356         iowrite8(dll, priv->membase + PCH_UART_DLL);
 357         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 358         iowrite8(lcr, priv->membase + UART_LCR);
 359
 360         return 0;
 361 }
 362
 363 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 364                                     unsigned int flag)
 365 {
 366         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 367                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 368                         __func__, flag);
 369                 return -EINVAL;
 370         }
 371
 372         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 373         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 374                  priv->membase + UART_FCR);
 375         iowrite8(priv->fcr, priv->membase + UART_FCR);
 376
 377         return 0;
 378 }
 379
 380 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 381                                  unsigned int dmamode,
 382                                  unsigned int fifo_size, unsigned int trigger)
 383 {
 384         u8 fcr;
 385
 386         if (dmamode & ~PCH_UART_FCR_DMS) {
 387                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 388                         __func__, dmamode);
 389                 return -EINVAL;
 390         }
 391
 392         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 393                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 394                         __func__, fifo_size);
 395                 return -EINVAL;
 396         }
 397
 398         if (trigger & ~PCH_UART_FCR_RFTL) {
 399                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 400                         __func__, trigger);
 401                 return -EINVAL;
 402         }
 403
 404         switch (priv->fifo_size) {
 405         case 256:
 406                 priv->trigger_level =
 407                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 408                 break;
 409         case 64:
 410                 priv->trigger_level =
 411                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 412                 break;
 413         case 16:
 414                 priv->trigger_level =
 415                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 416                 break;
 417         default:
 418                 priv->trigger_level =
 419                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 420                 break;
 421         }
 422         fcr =
 423             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 424         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 425         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 426                  priv->membase + UART_FCR);
 427         iowrite8(fcr, priv->membase + UART_FCR);
 428         priv->fcr = fcr;
 429
 430         return 0;
 431 }
 432
 433 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 434 {
 435         priv->dmsr = 0;
 436         return get_msr(priv, priv->membase);
 437 }
 438
 439 static void pch_uart_hal_write(struct eg20t_port *priv,
 440                               const unsigned char *buf, int tx_size)
 441 {
 442         int i;
 443         unsigned int thr;
 444
 445         for (i = 0; i < tx_size;) {
 446                 thr = buf[i++];
 447                 iowrite8(thr, priv->membase + PCH_UART_THR);
 448         }
 449 }
 450
 451 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 452                              int rx_size)
 453 {
 454         int i;
 455         u8 rbr, lsr;
 456
 457         lsr = ioread8(priv->membase + UART_LSR);
 458         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 459              i < rx_size && lsr & UART_LSR_DR;
 460              lsr = ioread8(priv->membase + UART_LSR)) {
 461                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 462                 buf[i++] = rbr;
 463         }
 464         return i;
 465 }
 466
 467 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
 468 {
 469         unsigned int iir;
 470         int ret;
 471
 472         iir = ioread8(priv->membase + UART_IIR);
 473         ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
 474         return ret;
 475 }
 476
 477 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 478 {
 479         return ioread8(priv->membase + UART_LSR);
 480 }
 481
 482 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 483 {
 484         unsigned int lcr;
 485
 486         lcr = ioread8(priv->membase + UART_LCR);
 487         if (on)
 488                 lcr |= PCH_UART_LCR_SB;
 489         else
 490                 lcr &= ~PCH_UART_LCR_SB;
 491
 492         iowrite8(lcr, priv->membase + UART_LCR);
 493 }
 494
 495 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 496                    int size)
 497 {
 498         struct uart_port *port;
 499         struct tty_struct *tty;
 500
 501         port = &priv->port;
 502         tty = tty_port_tty_get(&port->state->port);
 503         if (!tty) {
 504                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 505                 return -EBUSY;
 506         }
 507
 508         tty_insert_flip_string(tty, buf, size);
 509         tty_flip_buffer_push(tty);
 510         tty_kref_put(tty);
 511
 512         return 0;
 513 }
 514
 515 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 516 {
 517         int ret;
 518         struct uart_port *port = &priv->port;
 519
 520         if (port->x_char) {
 521                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 522                         __func__, port->x_char, jiffies);
 523                 buf[0] = port->x_char;
 524                 port->x_char = 0;
 525                 ret = 1;
 526         } else {
 527                 ret = 0;
 528         }
 529
 530         return ret;
 531 }
 532
 533 static int dma_push_rx(struct eg20t_port *priv, int size)
 534 {
 535         struct tty_struct *tty;
 536         int room;
 537         struct uart_port *port = &priv->port;
 538
 539         port = &priv->port;
 540         tty = tty_port_tty_get(&port->state->port);
 541         if (!tty) {
 542                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 543                 return 0;
 544         }
 545
 546         room = tty_buffer_request_room(tty, size);
 547
 548         if (room < size)
 549                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 550                          size - room);
 551         if (!room)
 552                 return room;
 553
 554         tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
 555
 556         port->icount.rx += room;
 557         tty_kref_put(tty);
 558
 559         return room;
 560 }
 561
 562 static void pch_free_dma(struct uart_port *port)
 563 {
 564         struct eg20t_port *priv;
 565         priv = container_of(port, struct eg20t_port, port);
 566
 567         if (priv->chan_tx) {
 568                 dma_release_channel(priv->chan_tx);
 569                 priv->chan_tx = NULL;
 570         }
 571         if (priv->chan_rx) {
 572                 dma_release_channel(priv->chan_rx);
 573                 priv->chan_rx = NULL;
 574         }
 575         if (sg_dma_address(&priv->sg_rx))
 576                 dma_free_coherent(port->dev, port->fifosize,
 577                                   sg_virt(&priv->sg_rx),
 578                                   sg_dma_address(&priv->sg_rx));
 579
 580         return;
 581 }
 582
 583 static bool filter(struct dma_chan *chan, void *slave)
 584 {
 585         struct pch_dma_slave *param = slave;
 586
 587         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 588                                                   chan->device->dev)) {
 589                 chan->private = param;
 590                 return true;
 591         } else {
 592                 return false;
 593         }
 594 }
 595
 596 static void pch_request_dma(struct uart_port *port)
 597 {
 598         dma_cap_mask_t mask;
 599         struct dma_chan *chan;
 600         struct pci_dev *dma_dev;
 601         struct pch_dma_slave *param;
 602         struct eg20t_port *priv =
 603                                 container_of(port, struct eg20t_port, port);
 604         dma_cap_zero(mask);
 605         dma_cap_set(DMA_SLAVE, mask);
 606
 607         dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
 608                                        PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 609                                                                 information */
 610         /* Set Tx DMA */
 611         param = &priv->param_tx;
 612         param->dma_dev = &dma_dev->dev;
 613         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 614
 615         param->tx_reg = port->mapbase + UART_TX;
 616         chan = dma_request_channel(mask, filter, param);
 617         if (!chan) {
 618                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 619                         __func__);
 620                 return;
 621         }
 622         priv->chan_tx = chan;
 623
 624         /* Set Rx DMA */
 625         param = &priv->param_rx;
 626         param->dma_dev = &dma_dev->dev;
 627         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 628
 629         param->rx_reg = port->mapbase + UART_RX;
 630         chan = dma_request_channel(mask, filter, param);
 631         if (!chan) {
 632                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 633                         __func__);
 634                 dma_release_channel(priv->chan_tx);
 635                 priv->chan_tx = NULL;
 636                 return;
 637         }
 638
 639         /* Get Consistent memory for DMA */
 640         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 641                                     &priv->rx_buf_dma, GFP_KERNEL);
 642         priv->chan_rx = chan;
 643 }
 644
 645 static void pch_dma_rx_complete(void *arg)
 646 {
 647         struct eg20t_port *priv = arg;
 648         struct uart_port *port = &priv->port;
 649         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 650         int count;
 651
 652         if (!tty) {
 653                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 654                 return;
 655         }
 656
 657         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 658         count = dma_push_rx(priv, priv->trigger_level);
 659         if (count)
 660                 tty_flip_buffer_push(tty);
 661         tty_kref_put(tty);
 662         async_tx_ack(priv->desc_rx);
 663         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 664                                             PCH_UART_HAL_RX_ERR_INT);
 665 }
 666
 667 static void pch_dma_tx_complete(void *arg)
 668 {
 669         struct eg20t_port *priv = arg;
 670         struct uart_port *port = &priv->port;
 671         struct circ_buf *xmit = &port->state->xmit;
 672         struct scatterlist *sg = priv->sg_tx_p;
 673         int i;
 674
 675         for (i = 0; i < priv->nent; i++, sg++) {
 676                 xmit->tail += sg_dma_len(sg);
 677                 port->icount.tx += sg_dma_len(sg);
 678         }
 679         xmit->tail &= UART_XMIT_SIZE - 1;
 680         async_tx_ack(priv->desc_tx);
 681         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 682         priv->tx_dma_use = 0;
 683         priv->nent = 0;
 684         kfree(priv->sg_tx_p);
 685         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 686 }
 687
 688 static int pop_tx(struct eg20t_port *priv, int size)
 689 {
 690         int count = 0;
 691         struct uart_port *port = &priv->port;
 692         struct circ_buf *xmit = &port->state->xmit;
 693
 694         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 695                 goto pop_tx_end;
 696
 697         do {
 698                 int cnt_to_end =
 699                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 700                 int sz = min(size - count, cnt_to_end);
 701                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 702                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 703                 count += sz;
 704         } while (!uart_circ_empty(xmit) && count < size);
 705
 706 pop_tx_end:
 707         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 708                  count, size - count, jiffies);
 709
 710         return count;
 711 }
 712
 713 static int handle_rx_to(struct eg20t_port *priv)
 714 {
 715         struct pch_uart_buffer *buf;
 716         int rx_size;
 717         int ret;
 718         if (!priv->start_rx) {
 719                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 720                                                      PCH_UART_HAL_RX_ERR_INT);
 721                 return 0;
 722         }
 723         buf = &priv->rxbuf;
 724         do {
 725                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 726                 ret = push_rx(priv, buf->buf, rx_size);
 727                 if (ret)
 728                         return 0;
 729         } while (rx_size == buf->size);
 730
 731         return PCH_UART_HANDLED_RX_INT;
 732 }
 733
 734 static int handle_rx(struct eg20t_port *priv)
 735 {
 736         return handle_rx_to(priv);
 737 }
 738
 739 static int dma_handle_rx(struct eg20t_port *priv)
 740 {
 741         struct uart_port *port = &priv->port;
 742         struct dma_async_tx_descriptor *desc;
 743         struct scatterlist *sg;
 744
 745         priv = container_of(port, struct eg20t_port, port);
 746         sg = &priv->sg_rx;
 747
 748         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 749
 750         sg_dma_len(sg) = priv->trigger_level;
 751
 752         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 753                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 754                      ~PAGE_MASK);
 755
 756         sg_dma_address(sg) = priv->rx_buf_dma;
 757
 758         desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
 759                         sg, 1, DMA_FROM_DEVICE,
 760                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 761
 762         if (!desc)
 763                 return 0;
 764
 765         priv->desc_rx = desc;
 766         desc->callback = pch_dma_rx_complete;
 767         desc->callback_param = priv;
 768         desc->tx_submit(desc);
 769         dma_async_issue_pending(priv->chan_rx);
 770
 771         return PCH_UART_HANDLED_RX_INT;
 772 }
 773
 774 static unsigned int handle_tx(struct eg20t_port *priv)
 775 {
 776         struct uart_port *port = &priv->port;
 777         struct circ_buf *xmit = &port->state->xmit;
 778         int fifo_size;
 779         int tx_size;
 780         int size;
 781         int tx_empty;
 782
 783         if (!priv->start_tx) {
 784                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 785                         __func__, jiffies);
 786                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 787                 priv->tx_empty = 1;
 788                 return 0;
 789         }
 790
 791         fifo_size = max(priv->fifo_size, 1);
 792         tx_empty = 1;
 793         if (pop_tx_x(priv, xmit->buf)) {
 794                 pch_uart_hal_write(priv, xmit->buf, 1);
 795                 port->icount.tx++;
 796                 tx_empty = 0;
 797                 fifo_size--;
 798         }
 799         size = min(xmit->head - xmit->tail, fifo_size);
 800         if (size < 0)
 801                 size = fifo_size;
 802
 803         tx_size = pop_tx(priv, size);
 804         if (tx_size > 0) {
 805                 port->icount.tx += tx_size;
 806                 tx_empty = 0;
 807         }
 808
 809         priv->tx_empty = tx_empty;
 810
 811         if (tx_empty) {
 812                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 813                 uart_write_wakeup(port);
 814         }
 815
 816         return PCH_UART_HANDLED_TX_INT;
 817 }
 818
 819 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 820 {
 821         struct uart_port *port = &priv->port;
 822         struct circ_buf *xmit = &port->state->xmit;
 823         struct scatterlist *sg;
 824         int nent;
 825         int fifo_size;
 826         int tx_empty;
 827         struct dma_async_tx_descriptor *desc;
 828         int num;
 829         int i;
 830         int bytes;
 831         int size;
 832         int rem;
 833
 834         if (!priv->start_tx) {
 835                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 836                         __func__, jiffies);
 837                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 838                 priv->tx_empty = 1;
 839                 return 0;
 840         }
 841
 842         if (priv->tx_dma_use) {
 843                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 844                         __func__, jiffies);
 845                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 846                 priv->tx_empty = 1;
 847                 return 0;
 848         }
 849
 850         fifo_size = max(priv->fifo_size, 1);
 851         tx_empty = 1;
 852         if (pop_tx_x(priv, xmit->buf)) {
 853                 pch_uart_hal_write(priv, xmit->buf, 1);
 854                 port->icount.tx++;
 855                 tx_empty = 0;
 856                 fifo_size--;
 857         }
 858
 859         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 860                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 861                              xmit->tail, UART_XMIT_SIZE));
 862         if (!bytes) {
 863                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 864                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 865                 uart_write_wakeup(port);
 866                 return 0;
 867         }
 868
 869         if (bytes > fifo_size) {
 870                 num = bytes / fifo_size + 1;
 871                 size = fifo_size;
 872                 rem = bytes % fifo_size;
 873         } else {
 874                 num = 1;
 875                 size = bytes;
 876                 rem = bytes;
 877         }
 878
 879         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 880                 __func__, num, size, rem);
 881
 882         priv->tx_dma_use = 1;
 883
 884         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 885
 886         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 887         sg = priv->sg_tx_p;
 888
 889         for (i = 0; i < num; i++, sg++) {
 890                 if (i == (num - 1))
 891                         sg_set_page(sg, virt_to_page(xmit->buf),
 892                                     rem, fifo_size * i);
 893                 else
 894                         sg_set_page(sg, virt_to_page(xmit->buf),
 895                                     size, fifo_size * i);
 896         }
 897
 898         sg = priv->sg_tx_p;
 899         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
 900         if (!nent) {
 901                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
 902                 return 0;
 903         }
 904         priv->nent = nent;
 905
 906         for (i = 0; i < nent; i++, sg++) {
 907                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
 908                               fifo_size * i;
 909                 sg_dma_address(sg) = (sg_dma_address(sg) &
 910                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
 911                 if (i == (nent - 1))
 912                         sg_dma_len(sg) = rem;
 913                 else
 914                         sg_dma_len(sg) = size;
 915         }
 916
 917         desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
 918                                         priv->sg_tx_p, nent, DMA_TO_DEVICE,
 919                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 920         if (!desc) {
 921                 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
 922                         __func__);
 923                 return 0;
 924         }
 925         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
 926         priv->desc_tx = desc;
 927         desc->callback = pch_dma_tx_complete;
 928         desc->callback_param = priv;
 929
 930         desc->tx_submit(desc);
 931
 932         dma_async_issue_pending(priv->chan_tx);
 933
 934         return PCH_UART_HANDLED_TX_INT;
 935 }
 936
 937 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
 938 {
 939         u8 fcr = ioread8(priv->membase + UART_FCR);
 940
 941         /* Reset FIFO */
 942         fcr |= UART_FCR_CLEAR_RCVR;
 943         iowrite8(fcr, priv->membase + UART_FCR);
 944
 945         if (lsr & PCH_UART_LSR_ERR)
 946                 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
 947
 948         if (lsr & UART_LSR_FE)
 949                 dev_err(&priv->pdev->dev, "Framing Error\n");
 950
 951         if (lsr & UART_LSR_PE)
 952                 dev_err(&priv->pdev->dev, "Parity Error\n");
 953
 954         if (lsr & UART_LSR_OE)
 955                 dev_err(&priv->pdev->dev, "Overrun Error\n");
 956 }
 957
 958 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
 959 {
 960         struct eg20t_port *priv = dev_id;
 961         unsigned int handled;
 962         u8 lsr;
 963         int ret = 0;
 964         unsigned int iid;
 965         unsigned long flags;
 966
 967         spin_lock_irqsave(&priv->port.lock, flags);
 968         handled = 0;
 969         while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
 970                 switch (iid) {
 971                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
 972                         lsr = pch_uart_hal_get_line_status(priv);
 973                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
 974                                                 UART_LSR_PE | UART_LSR_OE)) {
 975                                 pch_uart_err_ir(priv, lsr);
 976                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
 977                         }
 978                         break;
 979                 case PCH_UART_IID_RDR:  /* Received Data Ready */
 980                         if (priv->use_dma) {
 981                                 pch_uart_hal_disable_interrupt(priv,
 982                                                 PCH_UART_HAL_RX_INT |
 983                                                 PCH_UART_HAL_RX_ERR_INT);
 984                                 ret = dma_handle_rx(priv);
 985                                 if (!ret)
 986                                         pch_uart_hal_enable_interrupt(priv,
 987                                                 PCH_UART_HAL_RX_INT |
 988                                                 PCH_UART_HAL_RX_ERR_INT);
 989                         } else {
 990                                 ret = handle_rx(priv);
 991                         }
 992                         break;
 993                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
 994                                                    (FIFO Timeout) */
 995                         ret = handle_rx_to(priv);
 996                         break;
 997                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
 998                                                    Empty */
 999                         if (priv->use_dma)
1000                                 ret = dma_handle_tx(priv);
1001                         else
1002                                 ret = handle_tx(priv);
1003                         break;
1004                 case PCH_UART_IID_MS:   /* Modem Status */
1005                         ret = PCH_UART_HANDLED_MS_INT;
1006                         break;
1007                 default:        /* Never junp to this label */
1008                         dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1009                                 iid, jiffies);
1010                         ret = -1;
1011                         break;
1012                 }
1013                 handled |= (unsigned int)ret;
1014         }
1015         if (handled == 0 && iid <= 1) {
1016                 if (priv->int_dis_flag)
1017                         priv->int_dis_flag = 0;
1018         }
1019
1020         spin_unlock_irqrestore(&priv->port.lock, flags);
1021         return IRQ_RETVAL(handled);
1022 }
1023
1024 /* This function tests whether the transmitter fifo and shifter for the port
1025                                                 described by 'port' is empty. */
1026 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1027 {
1028         struct eg20t_port *priv;
1029         int ret;
1030         priv = container_of(port, struct eg20t_port, port);
1031         if (priv->tx_empty)
1032                 ret = TIOCSER_TEMT;
1033         else
1034                 ret = 0;
1035
1036         return ret;
1037 }
1038
1039 /* Returns the current state of modem control inputs. */
1040 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1041 {
1042         struct eg20t_port *priv;
1043         u8 modem;
1044         unsigned int ret = 0;
1045
1046         priv = container_of(port, struct eg20t_port, port);
1047         modem = pch_uart_hal_get_modem(priv);
1048
1049         if (modem & UART_MSR_DCD)
1050                 ret |= TIOCM_CAR;
1051
1052         if (modem & UART_MSR_RI)
1053                 ret |= TIOCM_RNG;
1054
1055         if (modem & UART_MSR_DSR)
1056                 ret |= TIOCM_DSR;
1057
1058         if (modem & UART_MSR_CTS)
1059                 ret |= TIOCM_CTS;
1060
1061         return ret;
1062 }
1063
1064 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1065 {
1066         u32 mcr = 0;
1067         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1068
1069         if (mctrl & TIOCM_DTR)
1070                 mcr |= UART_MCR_DTR;
1071         if (mctrl & TIOCM_RTS)
1072                 mcr |= UART_MCR_RTS;
1073         if (mctrl & TIOCM_LOOP)
1074                 mcr |= UART_MCR_LOOP;
1075
1076         if (priv->mcr & UART_MCR_AFE)
1077                 mcr |= UART_MCR_AFE;
1078
1079         if (mctrl)
1080                 iowrite8(mcr, priv->membase + UART_MCR);
1081 }
1082
1083 static void pch_uart_stop_tx(struct uart_port *port)
1084 {
1085         struct eg20t_port *priv;
1086         priv = container_of(port, struct eg20t_port, port);
1087         priv->start_tx = 0;
1088         priv->tx_dma_use = 0;
1089 }
1090
1091 static void pch_uart_start_tx(struct uart_port *port)
1092 {
1093         struct eg20t_port *priv;
1094
1095         priv = container_of(port, struct eg20t_port, port);
1096
1097         if (priv->use_dma) {
1098                 if (priv->tx_dma_use) {
1099                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1100                                 __func__);
1101                         return;
1102                 }
1103         }
1104
1105         priv->start_tx = 1;
1106         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1107 }
1108
1109 static void pch_uart_stop_rx(struct uart_port *port)
1110 {
1111         struct eg20t_port *priv;
1112         priv = container_of(port, struct eg20t_port, port);
1113         priv->start_rx = 0;
1114         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1115                                              PCH_UART_HAL_RX_ERR_INT);
1116         priv->int_dis_flag = 1;
1117 }
1118
1119 /* Enable the modem status interrupts. */
1120 static void pch_uart_enable_ms(struct uart_port *port)
1121 {
1122         struct eg20t_port *priv;
1123         priv = container_of(port, struct eg20t_port, port);
1124         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1125 }
1126
1127 /* Control the transmission of a break signal. */
1128 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1129 {
1130         struct eg20t_port *priv;
1131         unsigned long flags;
1132
1133         priv = container_of(port, struct eg20t_port, port);
1134         spin_lock_irqsave(&port->lock, flags);
1135         pch_uart_hal_set_break(priv, ctl);
1136         spin_unlock_irqrestore(&port->lock, flags);
1137 }
1138
1139 /* Grab any interrupt resources and initialise any low level driver state. */
1140 static int pch_uart_startup(struct uart_port *port)
1141 {
1142         struct eg20t_port *priv;
1143         int ret;
1144         int fifo_size;
1145         int trigger_level;
1146
1147         priv = container_of(port, struct eg20t_port, port);
1148         priv->tx_empty = 1;
1149
1150         if (port->uartclk)
1151                 priv->base_baud = port->uartclk;
1152         else
1153                 port->uartclk = priv->base_baud;
1154
1155         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1156         ret = pch_uart_hal_set_line(priv, default_baud,
1157                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1158                               PCH_UART_HAL_STB1);
1159         if (ret)
1160                 return ret;
1161
1162         switch (priv->fifo_size) {
1163         case 256:
1164                 fifo_size = PCH_UART_HAL_FIFO256;
1165                 break;
1166         case 64:
1167                 fifo_size = PCH_UART_HAL_FIFO64;
1168                 break;
1169         case 16:
1170                 fifo_size = PCH_UART_HAL_FIFO16;
1171                 break;
1172         case 1:
1173         default:
1174                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1175                 break;
1176         }
1177
1178         switch (priv->trigger) {
1179         case PCH_UART_HAL_TRIGGER1:
1180                 trigger_level = 1;
1181                 break;
1182         case PCH_UART_HAL_TRIGGER_L:
1183                 trigger_level = priv->fifo_size / 4;
1184                 break;
1185         case PCH_UART_HAL_TRIGGER_M:
1186                 trigger_level = priv->fifo_size / 2;
1187                 break;
1188         case PCH_UART_HAL_TRIGGER_H:
1189         default:
1190                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1191                 break;
1192         }
1193
1194         priv->trigger_level = trigger_level;
1195         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1196                                     fifo_size, priv->trigger);
1197         if (ret < 0)
1198                 return ret;
1199
1200         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1201                         KBUILD_MODNAME, priv);
1202         if (ret < 0)
1203                 return ret;
1204
1205         if (priv->use_dma)
1206                 pch_request_dma(port);
1207
1208         priv->start_rx = 1;
1209         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1210                                             PCH_UART_HAL_RX_ERR_INT);
1211         uart_update_timeout(port, CS8, default_baud);
1212
1213         return 0;
1214 }
1215
1216 static void pch_uart_shutdown(struct uart_port *port)
1217 {
1218         struct eg20t_port *priv;
1219         int ret;
1220
1221         priv = container_of(port, struct eg20t_port, port);
1222         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1223         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1224         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1225                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1226         if (ret)
1227                 dev_err(priv->port.dev,
1228                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1229
1230         pch_free_dma(port);
1231
1232         free_irq(priv->port.irq, priv);
1233 }
1234
1235 /* Change the port parameters, including word length, parity, stop
1236  *bits.  Update read_status_mask and ignore_status_mask to indicate
1237  *the types of events we are interested in receiving.  */
1238 static void pch_uart_set_termios(struct uart_port *port,
1239                                  struct ktermios *termios, struct ktermios *old)
1240 {
1241         int baud;
1242         int rtn;
1243         unsigned int parity, bits, stb;
1244         struct eg20t_port *priv;
1245         unsigned long flags;
1246
1247         priv = container_of(port, struct eg20t_port, port);
1248         switch (termios->c_cflag & CSIZE) {
1249         case CS5:
1250                 bits = PCH_UART_HAL_5BIT;
1251                 break;
1252         case CS6:
1253                 bits = PCH_UART_HAL_6BIT;
1254                 break;
1255         case CS7:
1256                 bits = PCH_UART_HAL_7BIT;
1257                 break;
1258         default:                /* CS8 */
1259                 bits = PCH_UART_HAL_8BIT;
1260                 break;
1261         }
1262         if (termios->c_cflag & CSTOPB)
1263                 stb = PCH_UART_HAL_STB2;
1264         else
1265                 stb = PCH_UART_HAL_STB1;
1266
1267         if (termios->c_cflag & PARENB) {
1268                 if (termios->c_cflag & PARODD)
1269                         parity = PCH_UART_HAL_PARITY_ODD;
1270                 else
1271                         parity = PCH_UART_HAL_PARITY_EVEN;
1272
1273         } else {
1274                 parity = PCH_UART_HAL_PARITY_NONE;
1275         }
1276
1277         /* Only UART0 has auto hardware flow function */
1278         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1279                 priv->mcr |= UART_MCR_AFE;
1280         else
1281                 priv->mcr &= ~UART_MCR_AFE;
1282
1283         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1284
1285         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1286
1287         spin_lock_irqsave(&port->lock, flags);
1288
1289         uart_update_timeout(port, termios->c_cflag, baud);
1290         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1291         if (rtn)
1292                 goto out;
1293
1294         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1295         /* Don't rewrite B0 */
1296         if (tty_termios_baud_rate(termios))
1297                 tty_termios_encode_baud_rate(termios, baud, baud);
1298
1299 out:
1300         spin_unlock_irqrestore(&port->lock, flags);
1301 }
1302
1303 static const char *pch_uart_type(struct uart_port *port)
1304 {
1305         return KBUILD_MODNAME;
1306 }
1307
1308 static void pch_uart_release_port(struct uart_port *port)
1309 {
1310         struct eg20t_port *priv;
1311
1312         priv = container_of(port, struct eg20t_port, port);
1313         pci_iounmap(priv->pdev, priv->membase);
1314         pci_release_regions(priv->pdev);
1315 }
1316
1317 static int pch_uart_request_port(struct uart_port *port)
1318 {
1319         struct eg20t_port *priv;
1320         int ret;
1321         void __iomem *membase;
1322
1323         priv = container_of(port, struct eg20t_port, port);
1324         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1325         if (ret < 0)
1326                 return -EBUSY;
1327
1328         membase = pci_iomap(priv->pdev, 1, 0);
1329         if (!membase) {
1330                 pci_release_regions(priv->pdev);
1331                 return -EBUSY;
1332         }
1333         priv->membase = port->membase = membase;
1334
1335         return 0;
1336 }
1337
1338 static void pch_uart_config_port(struct uart_port *port, int type)
1339 {
1340         struct eg20t_port *priv;
1341
1342         priv = container_of(port, struct eg20t_port, port);
1343         if (type & UART_CONFIG_TYPE) {
1344                 port->type = priv->port_type;
1345                 pch_uart_request_port(port);
1346         }
1347 }
1348
1349 static int pch_uart_verify_port(struct uart_port *port,
1350                                 struct serial_struct *serinfo)
1351 {
1352         struct eg20t_port *priv;
1353
1354         priv = container_of(port, struct eg20t_port, port);
1355         if (serinfo->flags & UPF_LOW_LATENCY) {
1356                 dev_info(priv->port.dev,
1357                         "PCH UART : Use PIO Mode (without DMA)\n");
1358                 priv->use_dma = 0;
1359                 serinfo->flags &= ~UPF_LOW_LATENCY;
1360         } else {
1361 #ifndef CONFIG_PCH_DMA
1362                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1363                         __func__);
1364                 return -EOPNOTSUPP;
1365 #endif
1366                 priv->use_dma_flag = 1;
1367                 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1368                 if (!priv->use_dma)
1369                         pch_request_dma(port);
1370                 priv->use_dma = 1;
1371         }
1372
1373         return 0;
1374 }
1375
1376 static struct uart_ops pch_uart_ops = {
1377         .tx_empty = pch_uart_tx_empty,
1378         .set_mctrl = pch_uart_set_mctrl,
1379         .get_mctrl = pch_uart_get_mctrl,
1380         .stop_tx = pch_uart_stop_tx,
1381         .start_tx = pch_uart_start_tx,
1382         .stop_rx = pch_uart_stop_rx,
1383         .enable_ms = pch_uart_enable_ms,
1384         .break_ctl = pch_uart_break_ctl,
1385         .startup = pch_uart_startup,
1386         .shutdown = pch_uart_shutdown,
1387         .set_termios = pch_uart_set_termios,
1388 /*      .pm             = pch_uart_pm,          Not supported yet */
1389 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1390         .type = pch_uart_type,
1391         .release_port = pch_uart_release_port,
1392         .request_port = pch_uart_request_port,
1393         .config_port = pch_uart_config_port,
1394         .verify_port = pch_uart_verify_port
1395 };
1396
1397 static struct uart_driver pch_uart_driver = {
1398         .owner = THIS_MODULE,
1399         .driver_name = KBUILD_MODNAME,
1400         .dev_name = PCH_UART_DRIVER_DEVICE,
1401         .major = 0,
1402         .minor = 0,
1403         .nr = PCH_UART_NR,
1404 };
1405
1406 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1407                                              const struct pci_device_id *id)
1408 {
1409         struct eg20t_port *priv;
1410         int ret;
1411         unsigned int iobase;
1412         unsigned int mapbase;
1413         unsigned char *rxbuf;
1414         int fifosize, base_baud;
1415         int port_type;
1416         struct pch_uart_driver_data *board;
1417         const char *board_name;
1418
1419         board = &drv_dat[id->driver_data];
1420         port_type = board->port_type;
1421
1422         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1423         if (priv == NULL)
1424                 goto init_port_alloc_err;
1425
1426         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1427         if (!rxbuf)
1428                 goto init_port_free_txbuf;
1429
1430         base_baud = 1843200; /* 1.8432MHz */
1431
1432         /* quirk for CM-iTC board */
1433         board_name = dmi_get_system_info(DMI_BOARD_NAME);
1434         if (board_name && strstr(board_name, "CM-iTC"))
1435                 base_baud = 192000000; /* 192.0MHz */
1436
1437         switch (port_type) {
1438         case PORT_UNKNOWN:
1439                 fifosize = 256; /* EG20T/ML7213: UART0 */
1440                 break;
1441         case PORT_8250:
1442                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1443                 break;
1444         default:
1445                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1446                 goto init_port_hal_free;
1447         }
1448
1449         pci_enable_msi(pdev);
1450         pci_set_master(pdev);
1451
1452         iobase = pci_resource_start(pdev, 0);
1453         mapbase = pci_resource_start(pdev, 1);
1454         priv->mapbase = mapbase;
1455         priv->iobase = iobase;
1456         priv->pdev = pdev;
1457         priv->tx_empty = 1;
1458         priv->rxbuf.buf = rxbuf;
1459         priv->rxbuf.size = PAGE_SIZE;
1460
1461         priv->fifo_size = fifosize;
1462         priv->base_baud = base_baud;
1463         priv->port_type = PORT_MAX_8250 + port_type + 1;
1464         priv->port.dev = &pdev->dev;
1465         priv->port.iobase = iobase;
1466         priv->port.membase = NULL;
1467         priv->port.mapbase = mapbase;
1468         priv->port.irq = pdev->irq;
1469         priv->port.iotype = UPIO_PORT;
1470         priv->port.ops = &pch_uart_ops;
1471         priv->port.flags = UPF_BOOT_AUTOCONF;
1472         priv->port.fifosize = fifosize;
1473         priv->port.line = board->line_no;
1474         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1475
1476         spin_lock_init(&priv->port.lock);
1477
1478         pci_set_drvdata(pdev, priv);
1479         pch_uart_hal_request(pdev, fifosize, base_baud);
1480
1481         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1482         if (ret < 0)
1483                 goto init_port_hal_free;
1484
1485         return priv;
1486
1487 init_port_hal_free:
1488         free_page((unsigned long)rxbuf);
1489 init_port_free_txbuf:
1490         kfree(priv);
1491 init_port_alloc_err:
1492
1493         return NULL;
1494 }
1495
1496 static void pch_uart_exit_port(struct eg20t_port *priv)
1497 {
1498         uart_remove_one_port(&pch_uart_driver, &priv->port);
1499         pci_set_drvdata(priv->pdev, NULL);
1500         free_page((unsigned long)priv->rxbuf.buf);
1501 }
1502
1503 static void pch_uart_pci_remove(struct pci_dev *pdev)
1504 {
1505         struct eg20t_port *priv;
1506
1507         priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1508
1509         pci_disable_msi(pdev);
1510         pch_uart_exit_port(priv);
1511         pci_disable_device(pdev);
1512         kfree(priv);
1513         return;
1514 }
1515 #ifdef CONFIG_PM
1516 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1517 {
1518         struct eg20t_port *priv = pci_get_drvdata(pdev);
1519
1520         uart_suspend_port(&pch_uart_driver, &priv->port);
1521
1522         pci_save_state(pdev);
1523         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1524         return 0;
1525 }
1526
1527 static int pch_uart_pci_resume(struct pci_dev *pdev)
1528 {
1529         struct eg20t_port *priv = pci_get_drvdata(pdev);
1530         int ret;
1531
1532         pci_set_power_state(pdev, PCI_D0);
1533         pci_restore_state(pdev);
1534
1535         ret = pci_enable_device(pdev);
1536         if (ret) {
1537                 dev_err(&pdev->dev,
1538                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1539                 return ret;
1540         }
1541
1542         uart_resume_port(&pch_uart_driver, &priv->port);
1543
1544         return 0;
1545 }
1546 #else
1547 #define pch_uart_pci_suspend NULL
1548 #define pch_uart_pci_resume NULL
1549 #endif
1550
1551 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1552         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1553          .driver_data = pch_et20t_uart0},
1554         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1555          .driver_data = pch_et20t_uart1},
1556         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1557          .driver_data = pch_et20t_uart2},
1558         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1559          .driver_data = pch_et20t_uart3},
1560         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1561          .driver_data = pch_ml7213_uart0},
1562         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1563          .driver_data = pch_ml7213_uart1},
1564         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1565          .driver_data = pch_ml7213_uart2},
1566         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1567          .driver_data = pch_ml7223_uart0},
1568         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1569          .driver_data = pch_ml7223_uart1},
1570         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1571          .driver_data = pch_ml7831_uart0},
1572         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1573          .driver_data = pch_ml7831_uart1},
1574         {0,},
1575 };
1576
1577 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1578                                         const struct pci_device_id *id)
1579 {
1580         int ret;
1581         struct eg20t_port *priv;
1582
1583         ret = pci_enable_device(pdev);
1584         if (ret < 0)
1585                 goto probe_error;
1586
1587         priv = pch_uart_init_port(pdev, id);
1588         if (!priv) {
1589                 ret = -EBUSY;
1590                 goto probe_disable_device;
1591         }
1592         pci_set_drvdata(pdev, priv);
1593
1594         return ret;
1595
1596 probe_disable_device:
1597         pci_disable_msi(pdev);
1598         pci_disable_device(pdev);
1599 probe_error:
1600         return ret;
1601 }
1602
1603 static struct pci_driver pch_uart_pci_driver = {
1604         .name = "pch_uart",
1605         .id_table = pch_uart_pci_id,
1606         .probe = pch_uart_pci_probe,
1607         .remove = __devexit_p(pch_uart_pci_remove),
1608         .suspend = pch_uart_pci_suspend,
1609         .resume = pch_uart_pci_resume,
1610 };
1611
1612 static int __init pch_uart_module_init(void)
1613 {
1614         int ret;
1615
1616         /* register as UART driver */
1617         ret = uart_register_driver(&pch_uart_driver);
1618         if (ret < 0)
1619                 return ret;
1620
1621         /* register as PCI driver */
1622         ret = pci_register_driver(&pch_uart_pci_driver);
1623         if (ret < 0)
1624                 uart_unregister_driver(&pch_uart_driver);
1625
1626         return ret;
1627 }
1628 module_init(pch_uart_module_init);
1629
1630 static void __exit pch_uart_module_exit(void)
1631 {
1632         pci_unregister_driver(&pch_uart_pci_driver);
1633         uart_unregister_driver(&pch_uart_driver);
1634 }
1635 module_exit(pch_uart_module_exit);
1636
1637 MODULE_LICENSE("GPL v2");
1638 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1639 module_param(default_baud, uint, S_IRUGO);